p-GaN Gate Gallium Nitride High Electron Mobility Transistor with Double-Gate Structure

Abstract

An embodiment of the present application provides a p-GaN gate gallium nitride high electron mobility transistor with a double-gate structure, which includes: a heterostructure layer including a channel layer and a barrier layer that forms an electron gas channel with the channel layer, the barrier layer having a first gate region and a second gate region arranged at intervals; a source electrode and a drain electrode electrically connected through the electron gas channel; a p-GaN gate disposed in the first gate region, and the threshold voltage of the p-GaN gate is a positive value; a sub-gate disposed in the second gate region; wherein, the saturation current corresponding to the sub-gate is not greater than the saturation current corresponding to the p-GaN gate; when the saturation voltage corresponding to the p-GaN gate is reached, the drain electrode has a first voltage; when the saturation voltage corresponding to the sub-gate is reached, the drain electrode has a second voltage; the second voltage is not greater than the first voltage. According to the embodiment of the present application, problems such as mis-turn-on or an increase in current in the electron gas channel of the p-GaN gate gallium nitride high electron mobility transistor with a double-gate structure can be avoided.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a p-GaN gate gallium nitride high electron mobility transistor with a dual-gate structure. Background Art

[0002] The p-GaN gate gallium nitride high electron mobility transistor in the prior art has dynamic stability problems such as threshold voltage drift. Positive drift of the threshold voltage will cause the p-GaN gate gallium nitride high electron mobility transistor to fail to fully turn on and increase the on-resistance; negative drift of the threshold voltage will cause the p-GaN gate gallium nitride high electron mobility transistor to be turned on by mistake or the current will be higher than the normal value, and even cause device damage. In addition, the threshold voltage drift also increases the difficulty of designing the gate drive circuit of the p-GaN gate gallium nitride high electron mobility transistor.

[0003] Therefore, a new p-GaN gate gallium nitride high electron mobility transistor is urgently needed. Summary of the invention

[0004] In view of the problems existing in the background technology, an embodiment of the present application provides a p-GaN gate gallium nitride high electron mobility transistor with a dual-gate structure, which regulates the current in the electron gas channel through negative feedback of the sub-gate to avoid problems such as false start-up of the device or increase of current in the electron gas channel.

[0005] An embodiment of the present application provides a p-GaN gate gallium nitride high electron mobility transistor with a dual-gate structure. The p-GaN gate gallium nitride high electron mobility transistor with a dual-gate structure includes: a heterostructure layer, including a channel layer and a barrier layer forming an electron gas channel with the channel layer, the barrier layer having a first gate region and a second gate region arranged at intervals; a source and a drain, electrically connected via the electron gas channel; a p-GaN gate, arranged in the first gate region, and the threshold voltage of the p-GaN gate is a positive value; a sub-gate, arranged in the second gate region; wherein a saturation current corresponding to the sub-gate is not greater than a saturation current corresponding to the p-GaN gate; when the saturation voltage corresponding to the p-GaN gate is reached, the drain has a first voltage; when the saturation voltage corresponding to the sub-gate is reached, the drain has a second voltage; the second voltage is not greater than the first voltage.

[0006] According to an embodiment of the present application, the threshold voltage of the sub-gate is a negative value or a positive value.

[0007] According to any of the aforementioned embodiments of the present application, the sub-gate is a first metal layer that forms a Schottky contact with the barrier layer.

[0008] According to any of the aforementioned embodiments of the present application, the sub-gate includes an insulating layer disposed in the second gate region and a first metal layer disposed on a side of the insulating layer away from the barrier layer.

[0009] According to any of the foregoing embodiments of the present application, a groove is provided in the second gate region, and the auxiliary gate has a filling portion for filling the groove.

[0010] According to any of the foregoing embodiments of the present application, an ion implantation layer extending into the barrier layer is provided in the second gate region.

[0011] According to any of the foregoing embodiments of the present application, the auxiliary gate includes a first semiconductor layer formed by P-type doping provided in the second gate region and a first metal layer provided on a side of the first semiconductor layer facing away from the barrier layer.

[0012] According to any of the foregoing embodiments of the present application, the p-GaN gate gallium nitride high electron mobility transistor having a double gate structure further includes a buffer layer provided on a side of the channel layer facing away from the barrier layer and a substrate provided on a side of the buffer layer facing away from the channel layer.

[0013] According to any of the foregoing embodiments of the present application, the auxiliary gate is located between the p-GaN gate and the source electrode.

[0014] In an embodiment of the present application, a double gate structure is provided. The threshold voltage of the p-GaN gate in the double gate structure is positive, that is, the p-GaN gate is an enhancement type gate. When the threshold voltage of the p-GaN gate drifts negatively, it will cause the device to be misturned on or the current in the electron gas channel to increase. Since the saturation current corresponding to the auxiliary gate is not greater than the saturation current corresponding to the p-GaN gate and the second voltage is not greater than the first voltage, at this time, the auxiliary gate makes the current in the electron gas channel not increase with the negative drift of the threshold voltage of the p-GaN gate, that is, the auxiliary gate plays a negative feedback regulation role on the current in the electron gas channel, thereby avoiding problems such as misturning on of the p-GaN gate gallium nitride high electron mobility transistor having a double gate structure or an increase in the current in the electron gas channel. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required to be used in the embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained according to these drawings without creative efforts. The drawings are not drawn to actual scale.

[0016] Figure 1 FIG. is a schematic structural diagram of a p-GaN gate gallium nitride high electron mobility transistor having a double gate structure provided by an embodiment of the present application;

[0017] Figure 2 FIG. is a schematic structural diagram of a p-GaN gate gallium nitride high electron mobility transistor having a double gate structure provided by another embodiment of the present application;

[0018] Figure 3 Schematic diagram of a p-GaN gate gallium nitride high electron mobility transistor with a double gate structure provided by another embodiment of the present application;

[0019] Figure 4 Schematic diagram of a p-GaN gate gallium nitride high electron mobility transistor with a double gate structure provided by another embodiment of the present application;

[0020] Figure 5 Schematic diagram of a p-GaN gate gallium nitride high electron mobility transistor with a double gate structure provided by another embodiment of the present application;

[0021] Figure 6 Schematic diagram of a p-GaN gate gallium nitride high electron mobility transistor with a double gate structure provided by another embodiment of the present application.

[0022] Label description:

[0023] 1. Heterostructure layer; 11. Channel layer; 13. Barrier layer; 1A. Electron gas channel; 131. First gate region; 133. Second gate region; 135. Groove; 14. Ion implantation layer;

[0024] 2. Source electrode;

[0025] 3. Drain electrode;

[0026] 4. p-GaN gate; 41. Second semiconductor layer; 43. Second metal layer;

[0027] 5. Auxiliary gate; 51. Insulating layer; 53. First semiconductor layer; 55. First metal layer; 5A. Filling part.

[0028] 6. Buffer layer;

[0029] 7. Substrate. Detailed implementation manners

[0030] The features and exemplary embodiments of various aspects of the present application will be described in detail below. To make the objectives, technical solutions, and advantages of the present application clearer and more understandable, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present application and are not configured to limit the present application. For those skilled in the art, the present application can be implemented without some of these specific details. The following description of the embodiments is only intended to provide a better understanding of the present application by showing examples of the present application.

[0031] It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprising", "including" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, the elements defined by the statement "including..." do not exclude the presence of additional identical elements in the process, method, article or device comprising the said elements. Additionally, in this article, "a plurality of" means more than two, and "above" and "below" include the number itself.

[0032] There are dynamic stability problems such as threshold voltage drift in p-GaN gate gallium nitride high electron mobility transistors in the prior art. The forward drift of the threshold voltage will cause problems that the p-GaN gate gallium nitride high electron mobility transistor cannot be fully turned on and the on-resistance increases; the negative drift of the threshold voltage will cause problems that the p-GaN gate gallium nitride high electron mobility transistor is misturned on or the current is higher than the normal value, and even cause device damage. In addition, the threshold voltage drift also increases the design difficulty of the gate drive circuit of the p-GaN gate gallium nitride high electron mobility transistor.

[0033] Related technology 1 (M. Hua et al., “E-mode p-GaN gate HEMT with p-FET bridge for higher V TH and enhanced V TH stability,” 2020 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2020, pp. 23.1.1-23.1.4, doi: 10.1109 / IEDM13553.2020.5341969) discloses a p-GaN gate gallium nitride high electron mobility transistor with a source p-FET bridge. A Schottky contact is used on the p-GaN layer, and a depletion-mode p-FET with one end connected to the source and the other end connected to the gate is fabricated. Before the device is turned on, the charges stored in the p-GaN layer are released through the depletion-mode p-FET to eliminate the threshold voltage drift caused by p-GaN floating. However, due to the high-resistance characteristics of the p-FET, the charges in the p-GaN are difficult to be released in time at high frequencies, and the threshold voltage drift still exists.

[0034] Related technology 2 (C. Zhang et al., “Hybrid gate p-GaN power HEMTs technology for enhanced V th stability,” 2022 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2022, pp. 35.4.1-35.4.4, doi: 10.1109 / IEDM45625.2022.10019437) discloses a hybrid p-GaN gate gallium nitride high electron mobility transistor. Ohmic contact and Schottky contact are simultaneously fabricated on the gate of the device. By adjusting the ratio of the Schottky contact to the Ohmic contact, the gate leakage current can be regulated. Among them, the Ohmic contact region can provide a current discharge channel, and releasing the charge stored in p-GaN can eliminate the threshold voltage drift phenomenon in the device. However, the leakage current of the device gate may increase, and it is difficult to release the charge in p-GaN in a timely manner at high frequencies.

[0035] To solve the above technical problems, the embodiments of the present application provide a p-GaN gate gallium nitride high electron mobility transistor with a dual-gate structure. The p-GaN gate gallium nitride high electron mobility transistor with a dual-gate structure adjusts the current in the electron gas channel through the negative feedback of the secondary gate to avoid problems such as misturn-on of the device or an increase in the current in the electron gas channel.

[0036] Optionally, the gallium nitride material system in the p-GaN gate gallium nitride high electron mobility transistor with a dual-gate structure in the embodiments of the present application includes at least one of GaN, AlN, InN, and their ternary and quaternary compounds.

[0037] Optionally, the shape of the p-GaN gate gallium nitride high electron mobility transistor with a dual-gate structure can be square, rectangular, circular, irregular, etc., and the present application does not limit this.

[0038] To better understand the present application, the following Figures 1 to 6 describes in detail the p-GaN gate gallium nitride high electron mobility transistor with a dual-gate structure in the embodiments of the present application.

[0039] Please refer to Figure 1 , Figure 1 which is a schematic structural diagram of a p-GaN gate gallium nitride high electron mobility transistor with a dual-gate structure provided by an embodiment of the present application.

[0040] As Figure 1As shown, the p-GaN gate gallium nitride high electron mobility transistor with a double-gate structure includes a heterostructure layer 1, a source 2, a drain 3, a p-GaN gate 4, and a secondary gate 5. The heterostructure layer 1 includes a channel layer 11 and a barrier layer 13 that forms an electron gas channel 1A with the channel layer 11. The barrier layer 13 has a first gate region 131 and a second gate region 133 that are spaced apart. The source 2 and the drain 3 are electrically connected via the electron gas channel 1A. The p-GaN gate 4 is disposed in the first gate region 131, and the threshold voltage of the p-GaN gate 4 is positive. The secondary gate 5 is disposed in the second gate region 133. Among them, the saturation current corresponding to the secondary gate 5 is not greater than the saturation current corresponding to the p-GaN gate 4. When the saturation voltage corresponding to the p-GaN gate 4 is reached, the drain 3 has a first voltage. When the saturation voltage corresponding to the secondary gate 5 is reached, the drain 3 has a second voltage. The second voltage is not greater than the first voltage.

[0041] Optionally, the first gate region 131 is the region where the barrier layer 13 contacts the p-GaN gate 4, and the second gate region 133 is the region where the barrier layer 13 contacts the secondary gate 5. That is, the secondary gate 5 and the p-GaN gate 4 are spaced apart.

[0042] Optionally, the saturation voltage corresponding to the p-GaN gate 4 is the saturation voltage corresponding to the p-GaN gate 4 when no threshold voltage drift occurs. After exceeding the saturation voltage corresponding to the p-GaN gate 4, the current in the electron gas channel 1A no longer increases significantly with the increase in the voltage of the drain 3. After exceeding the saturation voltage corresponding to the secondary gate 5, the current in the electron gas channel 1A no longer increases significantly with the increase in the voltage of the drain 3. That is, when the saturation voltage corresponding to the p-GaN gate 4 is reached, the saturation current corresponding to the p-GaN gate 4 is reached; when the saturation voltage corresponding to the secondary gate 5 is reached, the saturation current corresponding to the secondary gate 5 is reached.

[0043] Optionally, when the voltage applied to the p-GaN gate 4 is zero, the p-GaN gate 4 depletes the two-dimensional electron gas below it to turn off the electron gas channel 1A; the threshold voltage of the p-GaN gate 4 is the minimum voltage value applied to the p-GaN gate 4 to turn on the electron gas channel 1A. When the voltage applied to the p-GaN gate 4 is greater than or equal to its threshold voltage, a two-dimensional electron gas is generated to form a conductive channel in the electron gas channel 1A. That is, the p-GaN gate gallium nitride high electron mobility transistor with a double-gate structure is a normally closed enhancement-type device.

[0044] In an embodiment of the present application, a double-gate structure is provided. The threshold voltage of the p-GaN gate 4 in the double-gate structure is positive, that is, the p-GaN gate 4 is an enhancement-mode gate. When the threshold voltage of the p-GaN gate 4 drifts negatively, it may cause the device to turn on erroneously or the current in the electron gas channel 1A to increase. Since the saturation current corresponding to the auxiliary gate 5 is not greater than the saturation current corresponding to the p-GaN gate 4 and the second voltage is not greater than the first voltage, at this time, the auxiliary gate 5 makes the current in the electron gas channel 1A not increase with the negative drift of the threshold voltage of the p-GaN gate 4, that is, the auxiliary gate 5 plays a negative feedback regulation role on the current in the electron gas channel 1A, thereby avoiding problems such as erroneous turn-on of the p-GaN gate gallium nitride high electron mobility transistor with a double-gate structure or an increase in the current in the electron gas channel.

[0045] Optionally, both the channel layer 11 and the barrier layer 13 are group-III nitride semiconductor layers, and the bandgap of the channel layer 11 is smaller than the bandgap of the barrier layer 13. The spontaneous polarization and piezoelectric polarization effects of the group-III nitride will form a two-dimensional electron gas with high concentration and high mobility at the interface between the channel layer 11 and the barrier layer 13. When the electrons in the two-dimensional electron gas move directionally between the source electrode 2 and the drain electrode 3, a current is formed.

[0046] Optionally, the group-III nitride includes at least one of GaN, AlN, InN, and their ternary and quaternary compounds.

[0047] Exemplarily, the channel layer 11 may be a semiconductor layer made of at least one of GaN, InGaN, AlGaN, or InAlGaN.

[0048] Exemplarily, the barrier layer 13 may be a semiconductor layer made of at least one of GaN, AlN, AlGaN, InGaN, or InAlGaN.

[0049] Optionally, the source electrode 2 and the drain electrode 3 are provided on the side of the barrier layer 13 facing away from the channel layer 11. That is, both the source electrode 2 and the drain electrode 3 are electrically connected to the electron gas channel 1A through the barrier layer 13.

[0050] In some other embodiments, at least one of the source electrode 2 and the drain electrode 3 may also be directly electrically connected to the electron gas channel 1A.

[0051] Optionally, the threshold voltage of the auxiliary gate 5 is negative, that is, the auxiliary gate 5 is a depletion-mode gate; or, the threshold voltage of the auxiliary gate 5 is positive, that is, the auxiliary gate 5 is an enhancement-mode gate.

[0052] Optionally, when the auxiliary gate 5 is a depletion-type gate, the threshold voltage of the auxiliary gate 5 refers to the maximum voltage value applied to the auxiliary gate 5 so that the two-dimensional electron gas in the area below it is depleted and the electron gas channel 1A is turned off; when the voltage value applied to the auxiliary gate 5 is greater than the threshold voltage, the two-dimensional electron gas below it is not depleted by the auxiliary gate 5, so that the electron gas channel 1A forms a conductive channel.

[0053] Optionally, when the auxiliary gate 5 is an enhancement gate, when the voltage applied to the auxiliary gate 5 is zero, the auxiliary gate 5 will deplete the two-dimensional electron gas thereunder to turn off the electron gas channel 1A; the threshold voltage of the auxiliary gate 5 is the minimum voltage value applied to the auxiliary gate 5 to turn on the electron gas channel 1A, and when the voltage applied to the auxiliary gate 5 is greater than or equal to its threshold voltage, a two-dimensional electron gas will be generated to allow the electron gas channel 1A to form a conductive channel.

[0054] Exemplarily, the threshold voltage of the auxiliary gate 5 is a negative value, that is, the auxiliary gate 5 is a depletion gate.

[0055] In some embodiments, the sub-gate 5 is a first metal layer that forms a Schottky contact with the barrier layer 13 .

[0056] Optionally, there is a work function difference between the first metal layer and the barrier layer 13. The difference between the work function of the first metal layer and the work function of the barrier layer 13 is different, and the depletion ability of the first metal layer to the two-dimensional electron gas is also different. Therefore, by adjusting the difference between the work function of the sub-gate 5 and the work function of the barrier layer 13, the concentration of the two-dimensional electron gas depleted by the sub-gate 5 can be adjusted, thereby adjusting the threshold voltage of the sub-gate 5.

[0057] See also Figure 2 , Figure 2 A schematic structural diagram of a p-GaN gate gallium nitride high electron mobility transistor with a dual-gate structure provided in another embodiment of the present application.

[0058] like Figure 2 As shown, in some embodiments, the sub-gate 5 includes an insulating layer 51 disposed in the second gate region 133 and a first metal layer 55 disposed on the side of the insulating layer 51 away from the barrier layer 13. That is, the first metal layer 55 forms an MIS contact with the barrier layer 13 via the insulating layer 51. A part of the work function difference between the first metal layer 55 and the barrier layer 13 will fall on the insulating layer 51, which will weaken the depletion effect of the first metal layer 55 on the two-dimensional electron gas.

[0059] Optionally, the material of the insulating layer 51 includes at least one of aluminum oxide, silicon oxide, silicon nitride, aluminum nitride, gallium oxynitride, aluminum oxynitride, silicon oxynitride, hafnium oxide, and yttrium oxide. These oxides, nitrides, and oxynitrides all have an insulating effect of hindering diffusion and preventing current from flowing.

[0060] Please refer to Figure 3 and Figure 4 , Figure 3 , which is a schematic structural diagram of a p-GaN gate gallium nitride high electron mobility transistor with a double-gate structure provided by another embodiment of the present application. Figure 4 , which is a schematic structural diagram of a p-GaN gate gallium nitride high electron mobility transistor with a double-gate structure provided by another embodiment of the present application.

[0061] As Figure 3 and Figure 4 shown, in some embodiments, the second gate region 133 is provided with a groove 135, and the sub-gate 5 has a filling portion 5A that fills the groove 135. Providing the groove 135 in the second gate region 133 can reduce the two-dimensional electron gas concentration below it, thereby increasing the threshold voltage of the sub-gate 5.

[0062] Please refer to Figure 5 , Figure 5 , which is a schematic structural diagram of a p-GaN gate gallium nitride high electron mobility transistor with a double-gate structure provided by another embodiment of the present application.

[0063] As Figure 5 shown, in some embodiments, the second gate region 133 is provided with an ion implantation layer 14 extending into the barrier layer 13. The ions implanted in the ion implantation layer 14 will cause lattice relaxation of the surface material of the barrier layer 13, thereby weakening the polarization effect of the barrier layer 13 in the region where the second gate region 133 is located, and further reducing the two-dimensional electron gas concentration below it.

[0064] Please refer to Figure 6 , Figure 6 , which is a schematic structural diagram of a p-GaN gate gallium nitride high electron mobility transistor with a double-gate structure provided by another embodiment of the present application.

[0065] As Figure 6 shown, in some embodiments, the sub-gate 5 includes a first semiconductor layer 53 formed by P-type doping and provided in the second gate region 133, and a first metal layer 55 provided on the side of the first semiconductor layer 53 facing away from the barrier layer 13.

[0066] Optionally, the first semiconductor layer 53 is a group III nitride semiconductor layer.

[0067] The first semiconductor layer 53 can be a semiconductor layer of at least one material among GaN, InGaN, AlGaN, or InAlGaN.

[0068] As Figures 1 to 6As shown, in some embodiments, the p-GaN gate 4 includes a second semiconductor layer 41 disposed in the first gate region 131 and formed by P-type doping, and a second metal layer 43 disposed on a side of the second semiconductor layer 41 away from the barrier layer 13 .

[0069] Optionally, the second semiconductor layer 41 is a group III nitride semiconductor layer. The barrier layer 13 and the second semiconductor layer 41 are both group III nitride semiconductor layers, so the barrier layer 13 and the second semiconductor layer 41 have a high lattice matching degree, thereby improving the lattice growth quality of the second semiconductor layer 41 during the molding process.

[0070] like Figures 1 to 6 As shown, in some embodiments, the p-GaN gate gallium nitride high electron mobility transistor with a dual-gate structure further includes a buffer layer 6 disposed on a side of the channel layer 11 away from the barrier layer 13 and a substrate 7 disposed on a side of the buffer layer 6 away from the channel layer 11 .

[0071] Optionally, the buffer layer 6 is a group III nitride semiconductor layer. The buffer layer 6 and the channel layer 11 are both group III nitride semiconductor layers, so the lattice matching between the buffer layer 6 and the channel layer 11 is greater than the lattice matching between the channel layer 11 and the substrate 7, thereby improving the lattice growth quality of the channel layer 11 during the molding process.

[0072] Optionally, the buffer layer 6 has weak p-type C doping impurities. The unintentionally doped III-type nitride semiconductor layer is weakly n-type and has leakage channels, so weak p-type C doping is performed in the buffer layer 6 to reduce the off-state leakage of the device and increase the breakdown voltage of the device.

[0073] Optionally, the substrate 7 may be a Si substrate, a SiC substrate, a Sapphire substrate, a group III nitride substrate, or the like.

[0074] like Figures 1 to 6 As shown, in some embodiments, the sub-gate 5 is disposed between the source 2 and the p-GaN gate 4. For a p-GaN gate gallium nitride high electron mobility transistor with a dual-gate structure, the distance between the gate and the drain determines the magnitude of the device breakdown voltage. The greater the distance, the stronger the voltage withstand capability of the device. Therefore, compared with the p-GaN gate gallium nitride high electron mobility transistor in the prior art, the sub-gate 5 is disposed between the source 2 and the p-GaN gate 4, which does not lead to a decrease in the voltage withstand performance of the device.

[0075] In some other embodiments, the sub-gate 5 may also be disposed between the drain 3 and the p-GaN gate 4 .

[0076] As described above, this is only the specific implementation manner of the present application. Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working process of the above-described system can refer to the corresponding connection structure in the foregoing system embodiment, which will not be elaborated herein. It should be understood that the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of various equivalent modifications or substitutions, and these modifications or substitutions should all be covered within the protection scope of the present application.

Claims

1. A p-GaN gate gallium nitride high electron mobility transistor with a dual-gate structure, characterized in that: include: A heterostructure layer, comprising a channel layer and a barrier layer forming an electron gas channel with the channel layer, wherein the barrier layer has a first gate region and a second gate region which are spaced apart; A source electrode and a drain electrode, electrically connected via the electron gas channel; A p-GaN gate is disposed in the first gate region, and a threshold voltage of the p-GaN gate is a positive value; A secondary gate, disposed in the second gate region; Wherein, the saturation current corresponding to the auxiliary gate is not greater than the saturation current corresponding to the p-GaN gate; When the saturation voltage corresponding to the p-GaN gate is reached, the drain has a first voltage; when the saturation voltage corresponding to the auxiliary gate is reached, the drain has a second voltage; The second voltage is not greater than the first voltage.

2. The p-GaN gate gallium nitride high electron mobility transistor with a dual-gate structure according to claim 1, characterized in that: The threshold voltage of the auxiliary gate is negative or positive.

3. The p-GaN gate gallium nitride high electron mobility transistor with a dual-gate structure according to claim 1, characterized in that: The sub-gate is a first metal layer that forms a Schottky contact with the barrier layer.

4. The p-GaN gate gallium nitride high electron mobility transistor with a dual-gate structure according to claim 1, characterized in that: The auxiliary gate includes an insulating layer disposed in the second gate region and a first metal layer disposed on a side of the insulating layer away from the barrier layer.

5. The p-GaN gate gallium nitride high electron mobility transistor with a dual-gate structure according to claim 3 or 4, characterized in that: The second gate region is provided with a groove, and the auxiliary gate has a filling portion filling the groove.

6. The p-GaN gate gallium nitride high electron mobility transistor with a dual-gate structure according to claim 3, characterized in that: The second gate region is provided with an ion implantation layer extending into the barrier layer.

7. The p-GaN gate gallium nitride high electron mobility transistor with a dual-gate structure according to claim 1, characterized in that: The auxiliary gate includes a first semiconductor layer which is disposed in the second gate region and formed by P-type doping, and a first metal layer which is disposed on a side of the first semiconductor layer away from the barrier layer.

8. The p-GaN gate gallium nitride high electron mobility transistor with a dual-gate structure according to claim 1, characterized in that: The p-GaN gate gallium nitride high electron mobility transistor with a dual-gate structure further includes a buffer layer disposed on a side of the channel layer away from the barrier layer and a substrate disposed on a side of the buffer layer away from the channel layer.

9. The p-GaN gate gallium nitride high electron mobility transistor with a dual-gate structure according to claim 1, characterized in that: The sub-gate is located between the p-GaN gate and the source.

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