A gallium nitride electronic device with an n-type buried layer

Abstract

The application discloses a gallium nitride electronic device with an N-type buried layer, and the structure comprises a substrate, a transition layer, a buffer layer, an N-type buried layer, a second buffer layer, a channel layer, a barrier layer, a p-GaN layer, a passivation layer, source metal, drain metal and gate metal; the N-type buried layer is introduced into the buffer layer, so that the increase of the electric field intensity near the drain caused by external particles and charges entering the device is slowed down, the single-particle burnout resistance of the device is effectively increased, the increase of the electric field intensity near the drain under other stress conditions is relieved, and the application is suitable for the application occasions of power electronic systems, in particular, space power electronic systems.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of power semiconductors, and is mainly used for space power systems. BACKGROUND

[0002] Gallium nitride (GaN) material is a typical representative of the third generation of wide band gap semiconductors, with a band gap of 3.4 eV, higher critical breakdown field, higher electron saturation drift speed, higher limit operating temperature, smaller dielectric constant, and good chemical stability, etc. It is an excellent material for power electronic power semiconductor devices. Gallium nitride power devices are attractive for space applications due to their size, weight and power efficiency. These excellent properties make gallium nitride power devices an ideal choice for key components of satellite systems operating at high power and high frequency in space environment.

[0003] In space radiation environment, electronic equipment will suffer serious radiation effects. Many research reports have proved that gallium nitride power devices are sensitive to single event effects.

[0004] When high energy particles penetrate the device, single event effects (SEE) occur: high energy particles lose energy and produce electron-hole pair (EHP) tracks, and charges are recombined or extracted out of the device through drift and / or diffusion processes, causing transient current, called single event transient (SET). This current spike can be destructive when large enough, such as single event burnout (SEB), single event gate rupture (SEGR), single event upset (SEU), etc. The severity depends on many parameters, such as device structure, amount of charge generated, device operating point, impact location and internal defects. Single event burnout (SEB) is one of the most important categories of gallium nitride power transistor single event effect failure. Therefore, single event burnout is a serious challenge for the application of gallium nitride power devices in space environment. SUMMARY

[0005] The purpose of the present application is to provide a gallium nitride electronic device with an N-type buried layer to solve the problem of gallium nitride power devices in space environment. The present application adds an N-type doped buried layer in the buffer layer of the device based on the original gallium nitride power device. The N-type buried layer can solve the problem of excessive drain electric field strength of gallium nitride power devices after single particle injection, thereby greatly improving the single event burnout resistance of gallium nitride power devices.

[0006] To achieve the above-mentioned purpose of the application, the technical scheme of the present application is as follows:

[0007] A gallium nitride electronic device with N-type buried layer, characterized in that, comprising substrate 01, transition layer 02, first buffer layer 03, N-type buried layer 09, second buffer layer 13, channel layer 04, barrier layer 05 which are sequentially stacked; the device has source metal 10 and drain metal 11 at both ends of the upper surface, respectively, the source metal 10 and the drain metal 11 penetrate the barrier layer 05 along the vertical direction of the device and extend into the channel layer 04; the upper surface of the barrier layer 05 has a gate structure composed of p-GaN layer 06 and gate metal 12, the gate metal 12 is located on the upper surface of the p-GaN layer 06; the upper surface of the barrier layer 05 between the source metal 10 and the gate structure has a gate-source side passivation layer 07, and the upper surface of the barrier layer 05 between the drain metal 11 and the gate structure has a gate-drain side passivation layer 08, the lateral width of the gate-drain side passivation layer 08 is greater than the lateral width of the gate-source side passivation layer 07;

[0008] The N-type buried layer 09 is one or a combination of N-type doped gallium nitride, aluminum gallium nitride or aluminum nitride, the doping impurity is Si or Ge, and the impurity distribution is uniform doping or non-uniform doping, the doping concentration is 1×10 15 ~1×10 21 cm -3 , and the thickness is 0.1~3um.

[0009] Specifically, the substrate 01 is one of silicon substrate, silicon carbide substrate, sapphire substrate, gallium nitride substrate, aluminum nitride substrate.

[0010] Specifically, the transition layer 02 uses one or a combination of gallium nitride, aluminum nitride, aluminum gallium nitride.

[0011] Specifically, the first first buffer layer 03 and the second buffer layer 13 use one or a combination of gallium nitride, aluminum nitride, aluminum gallium nitride, and the doping element is carbon or iron, and the thickness is 0~5um.

[0012] Specifically, the channel layer 04 uses gallium nitride or aluminum gallium nitride.

[0013] Specifically, the barrier layer 05 uses one or a combination of gallium nitride, aluminum nitride, aluminum gallium nitride, and the thickness is 5~100nm.

[0014] Specifically, the p-GaN layer 06 uses P-type doped gallium nitride, aluminum nitride or aluminum gallium nitride.

[0015] Specifically, the gate-source side passivation layer 07 and the gate-drain side passivation layer 08 use one or a combination of SiN x , Al2O3, AlN, SiO2, HfO2, ScO2, TiO2, ZrO2.

[0016] The present application discloses the following technical effects:

[0017] When the GaN HEMT is in off-state bias, i.e., the source metal 10 voltage V S = 0V, the gate metal 12 voltage V G = 0V, and the drain metal 11 voltage V D is high. After the heavy ion incidence, electron-hole pairs are generated along the ion track. The electron and hole begin to move along the direction of the electric field, and the concentration distribution changes, causing the internal electric field intensity distribution of the device to change. Due to the huge difference in electron and hole mobility in gallium nitride, a large number of electrons can be injected from the source, while the holes injected from the drain are relatively few, and the electric field intensity at the drain gradually increases, eventually reaches the critical electric field of the material, and finally burns out.

[0018] The present application adds an N-type buried layer in the buffer layer of the original gallium nitride power device, which can solve the problem of excessive drain electric field intensity of the gallium nitride power device after single particle incidence, thereby greatly improving the single particle burnout resistance of the gallium nitride power device. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 is a cross-sectional schematic diagram of a gallium nitride electronic device with an N-type buried layer of Example 1;

[0020] Figure 2 is a cross-sectional schematic diagram of a gallium nitride electronic device with an N-type buried layer of Example 2;

[0021] Figure 3 is a cross-sectional schematic diagram of a gallium nitride electronic device with an N-type buried layer of Example 3;

[0022] Figure 4 is a cross-sectional schematic diagram of a gallium nitride electronic device with an N-type buried layer of Example 4;

[0023] Figure 5 is a cross-sectional schematic diagram of a gallium nitride electronic device with an N-type buried layer of Example 5;

[0024] Figure 6 is a cross-sectional schematic diagram of a gallium nitride electronic device with an N-type buried layer of Example 6;

[0025] BRIEF DESCRIPTION OF DRAWINGS: 01 is a substrate, 02 is a transition layer, 03 is a buffer layer, 09 is an N-type buried layer, 13 is a second buffer layer, 04 is a channel layer, 05 is a barrier layer, 06 is a p-GaN layer, 07 is a gate-source side passivation layer, 08 is a gate-drain side passivation layer, 10 is a source metal, 11 is a drain metal, 12 is a gate metal, 14 is a gate dielectric layer, 15 is a second N-type buried layer, and 16 is a third buffer layer. Detailed Implementation

[0026] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0027] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0028] Example 1

[0029] Reference Figure 1 As shown, this embodiment provides a gallium nitride electronic device with an N-type buried layer, characterized by comprising: a substrate 01, a transition layer 02, a first buffer layer 03, an N-type buried layer 09, a second buffer layer 13, a channel layer 04, a barrier layer 05, a p-GaN layer 06, a gate-source side passivation layer 07, a gate-drain side passivation layer 08, a source metal 10, a drain metal 11, and a gate metal 12.

[0030] The bottom layer of the device is substrate 01; transition layer 02 is located above substrate 01; first buffer layer 03 is located above transition layer 02; N-type buried layer 09 is located above first buffer layer 03; second buffer layer 13 is located above N-type buried layer 09; barrier layer 05 is located above channel layer 04; p-GaN layer 06, gate-source passivation layer 07, and gate-drain passivation layer 08 are located above AlGaN barrier layer 05, in the following order from left to right: gate-source passivation layer 07, p-GaN layer 06, and gate-drain passivation layer 08; source metal 10 is located at the leftmost end of the device, above channel layer 04, and penetrates gate-source passivation layer 07, barrier layer 05, and part of channel layer 04; drain metal 11 is located at the rightmost end of the device, above channel layer 04, and penetrates gate-drain passivation layer 08, barrier layer 05, and part of channel layer 04; gate metal 12 is located above p-GaN layer 06.

[0031] The N-type buried layer 09 is N-type doped gallium nitride (GaN) and aluminum gallium nitride (GaN). x Al 1-x The material is N or a combination of aluminum nitride (AlN), and the doping impurities are Si, Ge, or other impurities that can act as donors in the N-type buried layer 09 material. The impurity distribution is uniform or non-uniform doping, and the doping concentration is 1×10⁻⁶. 15 ~1×10 21 cm -3 Its thickness is 0.1 to 3 μm.

[0032] In some embodiments, the substrate 01 can include a silicon substrate, a silicon carbide (SiC) substrate, a sapphire substrate, a gallium nitride substrate, an aluminum nitride substrate, or a substrate formed of other suitable materials.

[0033] In some embodiments, the material of the transition layer 02 can include gallium nitride, aluminum nitride, aluminum gallium nitride, or a combination thereof, but is not limited thereto.

[0034] In some embodiments, the material of the first buffer layer 03 and the second buffer layer 13 can include gallium nitride, aluminum nitride, aluminum gallium nitride, or a combination thereof, but is not limited thereto, and is doped with carbon or iron, and has a thickness of 0-5 um.

[0035] In some embodiments, the material of the channel layer 04 can include gallium nitride, aluminum gallium nitride, but is not limited thereto.

[0036] In some embodiments, the material of the barrier layer 05 can include gallium nitride, aluminum nitride, aluminum gallium nitride, or a combination thereof, but is not limited thereto.

[0037] In some embodiments, the material of the p-GaN layer 06 can be P-type doped gallium nitride, aluminum nitride, or aluminum gallium nitride, but is not limited thereto, and is doped with magnesium.

[0038] In some embodiments, the material of the gate-source side passivation layer 07 and the gate-drain side passivation layer 08 is SiN x , Al2O3, AlN, SiO2, HfO2, ScO2, TiO2, ZrO2, or a combination thereof, but is not limited thereto.

[0039] Embodiment 2

[0040] Referring to Figure 2 , the difference between this embodiment and Embodiment 1 is that the N-type buried layer 09 is directly grown on the transition layer 02 in this embodiment.

[0041] Embodiment 3

[0042] As shown in Figure 3 , the difference between this embodiment and Embodiment 1 is that the second N-type buried layer 15 and the third buffer layer 16 are introduced in this embodiment.

[0043] Embodiment 4

[0044] As shown in Figure 4 , the difference between this embodiment and Embodiment 1 is that the channel layer 04 is directly grown on the N-type buried layer 09 in this embodiment.

[0045] Embodiment 5

[0046] As shown in Figure 4As shown, the difference between this embodiment and Embodiment 1 is that Embodiment 1 is an enhancement-type structure, while Embodiment 5 is a depletion-type structure, and the material of the gate dielectric layer 13 is HfO2, Al2O3, SiO2, or SiN. x Or a combination of the above, but not limited to this.

[0047] Example 6

[0048] like Figure 6 As shown, the difference between this embodiment and Embodiment 1 is that Embodiment 1 uses a p-GaN gate structure, while Embodiment 5 uses a MIS gate structure, and the material of the gate dielectric layer 13 is HfO2, Al2O3, SiO2, or SiN. x Or a combination of the above, but not limited to this.

[0049] In the description of this invention, it should be understood that the terms "longitudinal", "lateral", "up", "down", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this invention, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.

[0050] The embodiments described above are merely preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Any modifications and variations made to the technical solutions of the present invention by those skilled in the art without departing from the spirit of the present invention should fall within the protection scope defined by the claims of the present invention.

Claims

1. A gallium nitride electronic device with an N-type buried layer, characterized in that, The device includes a substrate (01), a transition layer (02), a first buffer layer (03), an N-type buried layer (09), a second buffer layer (13), a channel layer (04), and a barrier layer (05) stacked sequentially. The device has a source metal (10) and a drain metal (11) at both ends of its upper surface. The source metal (10) and the drain metal (11) penetrate the barrier layer (05) and extend into the channel layer (04) along the vertical direction of the device. The barrier layer (05) has a gate structure composed of a p-GaN layer (06) and a gate metal (12) on its upper surface. The gate metal (12) is located on the upper surface of the p-GaN layer (06). A gate-source passivation layer (07) is provided on the upper surface of the barrier layer (05) between the source metal (10) and the gate structure, and a gate-drain passivation layer (08) is provided on the upper surface of the barrier layer (05) between the drain metal (11) and the gate structure. The lateral width of the gate-drain passivation layer (08) is greater than the lateral width of the gate-source passivation layer (07). The N-type buried layer (09) is one or more combinations of N-type doped gallium nitride, aluminum gallium nitride, or aluminum nitride, with Si or Ge as the doping impurity. The impurity distribution is uniform or non-uniform doping, and the doping concentration is 1×10⁻⁶. 15 ~1×10 21 cm -3 The thickness is 0.1~3um.

2. A gallium nitride electronic device with an N-type buried layer according to claim 1, characterized in that: The substrate (01) is one of silicon substrate, silicon carbide substrate, sapphire substrate, gallium nitride substrate, and aluminum nitride substrate.

3. A gallium nitride electronic device with an N-type buried layer according to claim 1, characterized in that: The transition layer (02) is made of one or more of gallium nitride, aluminum nitride, and aluminum gallium nitride.

4. A gallium nitride electronic device with an N-type buried layer according to claim 1, characterized in that: The first buffer layer (03) and the second buffer layer (13) are made of one or more of gallium nitride, aluminum nitride, and aluminum gallium nitride, and the doping element is carbon or iron.

5. A gallium nitride electronic device with an N-type buried layer according to claim 1, characterized in that: The channel layer (04) is made of gallium nitride or aluminum gallium nitride.

6. A gallium nitride electronic device with an N-type buried layer according to claim 1, characterized in that: The barrier layer (05) is made of one or more of gallium nitride, aluminum nitride, and aluminum gallium nitride, with a thickness of 5 to 100 nm.

7. A gallium nitride electronic device with an N-type buried layer according to claim 1, characterized in that: The p-GaN layer (06) uses p-type doped gallium nitride.

8. A gallium nitride electronic device with an N-type buried layer according to claim 1, characterized in that: The passivation layer (07) on the gate-source side and the passivation layer (08) on the gate-drain side are made of SiN. x One or more combinations of Al2O3, AlN, SiO2, HfO2, ScO2, TiO2, and ZrO2.

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