A normally-off silicon carbide high-voltage JFET device and a method of manufacturing the same

Abstract

A normally-off silicon carbide high-voltage JFET device and a preparation method thereof. The device comprises growing an N-type drift region on an N-type substrate, having a first and a second P-type well doped region and a first N-type well doped region in the N-type drift region, having a first and a second P-type high doped implant region and a second N-type high doped implant region respectively, having a first N-type high doped implant region between the first and the second P-type well doped region and forming back-to-back PN junctions, forming an oxide medium on the N-type drift region to lead out metal source, drain and gate electrodes, and forming a characteristic structure below the first N-type high doped implant region, which contains a first and a second P-type buried layer and forms normally-off characteristic left, middle and right channels with the first and the second P-type well doped region. The method comprises growing an epitaxial layer on an N-type substrate, performing ion implantation in the epitaxial layer to form different types of low doped wells, performing ion implantation in the different types of wells to form high doped regions respectively, performing high-temperature thermal annealing, growing an interlayer medium and etching and depositing to lead out electrodes.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor manufacturing, and in particular to a high-voltage JFET device based on N-epitaxy normally-off silicon carbide, and a preparation method of the high-voltage JFET device based on N-epitaxy normally-off silicon carbide. BACKGROUND

[0002] The requirements for power devices in today's semiconductor industry are increasing day by day. At present, power semiconductor devices are dominated by silicon materials. In the face of the development trend of power electronics technology towards higher blocking voltage, faster switching speed and higher working temperature, the limitations of silicon-based power devices are increasingly apparent. The performance of traditional silicon-based power devices has approached the theoretical limit of the material, and cannot meet the requirements of the new generation of power electronic systems in high-temperature and high-pressure environments. As a wide-bandgap semiconductor material, silicon carbide has advantages such as wide bandgap, high critical breakdown field, high electron saturation drift speed, and high thermal conductivity compared to traditional silicon materials, and is an ideal semiconductor material for high-power, high-temperature, high-frequency and radiation-resistant applications.

[0003] A junction field effect transistor (JFET) is a voltage-controlled device that can realize various analog and digital integrated circuits by integrating lateral JFET devices and passive devices such as resistors. JFET power devices only use PN junctions to control the gate voltage, and do not have the problem of SiO2 / SiC interface state, which has obvious advantages in reliability compared to silicon carbide LDOMS. Moreover, compared to MOS control mode, the opening voltage of the PN junction gate structure changes less with temperature, reducing the possibility of device mis-triggering in high-temperature environments.

[0004] Silicon carbide JFET devices have the characteristics of relatively easy opening, no low-reliability gate oxide layer, high input resistance, and less noise compared to MOSFET. Existing silicon carbide JFET devices are divided into two categories: normally-on and normally-off. Normally-on devices have better current capacity than normally-off devices, but normally-on silicon carbide JFET devices require a negative voltage to be applied to the gate to deplete the conduction channel when turned off, resulting in high energy loss and increasing the difficulty of circuit design. Normally-off devices have stronger voltage resistance than normally-on devices. When normally-off silicon carbide JFET devices are used, only a gate voltage needs to be applied when turned on, and the channel is automatically pinched off without the need for a gate voltage when turned off, resulting in lower energy consumption but relatively weaker current capacity. Therefore, the existing normally-off silicon carbide high-voltage JFET has the defect of weak current capacity. SUMMARY

[0005] In response to the above problems, the present invention proposes a normally-off silicon carbide high-voltage JFET device structure and a preparation method thereof. The normally-off silicon carbide device of the present invention is formed by improving the normally-on silicon carbide high-voltage JFET device. While having the functions of a normally-off silicon carbide high-voltage JFET, it also has the advantage of high current capability.

[0006] The present invention adopts the following technical solutions:

[0007] The normally-off silicon carbide high-voltage JFET device of the present invention comprises: an N-type substrate 001, an N-type drift region 002 provided on the N-type substrate 001, a first P-type well doping region 003, a second P-type well doping region 004, and a first N-type well doping region 005 provided on the N-type drift region 002, a first P-type highly doped injection region 111 provided in the first P-type well doping region 003, a second P-type highly doped injection region 113 provided in the second P-type well doping region 004, a first N-type highly doped injection region 112 provided between the first P-type well doping region 003 and the second P-type well doping region 004, and two ends of the first N-type highly doped injection region 112 respectively extend and touch the first P-type well doping region. Region 003 and the second P-type well doped region 004, a second N-type highly doped injection region 114 is provided in the first N-type well doped region 005, a first oxide layer dielectric 006 and a second oxide layer dielectric 007 are sequentially provided on the N-type epitaxy, a metal electrode is led out from the first N-type highly doped injection region 112 and serves as a source 01S, a metal electrode is led out from the second N-type highly doped injection region 114 and serves as a drain 01D, a metal electrode is led out from the first P-type highly doped injection region 111 and the second P-type highly doped injection region 113 and serves as a gate 01G, the first P-type well doped region 003 and the second P-type well doped region 004 respectively form a back-to-back PN junction with the first N-type highly doped injection region 112,

[0008] A first P buried layer 031 and a second P buried layer 032 are provided in the N-type drift region 002 below the first N-type highly doped implant region 112. The first P buried layer 031 and the second P buried layer 032 are isolated by the N-type drift region 002. The first P buried layer 031 is electrically connected to the first P-type well doping region 003 so that they have the same potential. The second P buried layer 032 is electrically connected to the second P-type well doping region 004 so that they have the same potential.

[0009] In normal state, the device is in off state, the source electrode 01S is connected to zero potential voltage, the first P-type well doped region 003, the second P-type well doped region 004, the first P buried layer 031 and the second P buried layer 032 are at zero potential, the N-type drift region 002 between the first P-type well doped region 003 and the first P buried layer 031, the N-type drift region 002 between the first P buried layer 031 and the second P buried layer 032, and the N-type drift region 002 between the second P buried layer 032 and the second P-type well doped region 004 are in depletion state, so that the conduction channel 021 is in off state;

[0010] When the device is in on state, the source electrode 01S is connected to zero potential voltage, the gate electrode 01G is connected to positive voltage, the drain electrode 01D is connected to high potential voltage, and the N-type drift region 002 between the first P-type well doped region 003 and the first P buried layer 031, the N-type drift region 002 between the first P buried layer 031 and the second P buried layer 032, and the N-type drift region 002 between the second P buried layer 032 and the second P-type well doped region 004 are turned on under the action of the positive voltage of the gate electrode 01G.

[0011] The preparation method of the normally-off silicon carbide high-voltage JFET device comprises the following steps:

[0012] An N-type substrate 001 is formed on a silicon carbide base, and an N-type drift region 002 is epitaxially grown on the N-type substrate 001;

[0013] P-type ion implantation is performed on the N-type drift region 002 to form a first P-type well doped region 003 and a second P-type well doped region 004, and N-type ion implantation is performed on the N-type drift region 002 to form a first N-type well doped region 005;

[0014] P-type ion implantation is performed in the N-type drift region 002 between the first P-type well doped region 003 and the second P-type well doped region 004 to form a first P buried layer 031, a second P buried layer 032, a first P-type doped channel 0311 electrically connecting the first P-type well doped region 003 and the first P buried layer 031, and a second P-type doped channel 0321 electrically connecting the second P buried layer 032 and the second P-type well doped region 004; high-doped P-type ion implantation is performed in the first P-type well doped region 003 and the second P-type well doped region 004 to form a first P-type high-doped implantation region 111 and a second P-type high-doped implantation region 113;

[0015] The N-type drift region 002 between the first P-type well doped region 003 and the second P-type well doped region 004 and above the first P-buried layer 031 and the second P-buried layer 032, the partial region of the first P-type well doped region 003 adjacent to the second P-type well doped region 004, the partial region of the second P-type well doped region 004 adjacent to the first P-type well doped region 003, and the first N-type well doped region 005 are high-doped N-type ion implanted to form the first N-type high-doped implanted region 112 and the second N-type high-doped implanted region 114, respectively;

[0016] After high-temperature thermal annealing treatment at 1300 DEG C to 1700 DEG C, an oxide layer medium is deposited on the surface of the N-type drift region 002, and a via is etched on the oxide layer medium and metal is deposited to lead out the source electrode 01S above the first N-type high-doped implanted region 112, the source electrode 01D above the second N-type high-doped implanted region 114, and the gate electrode 01G above the first P-type high-doped implanted region 111 and the second P-type high-doped implanted region 113.

[0017] Compared with the prior art, the present application has the following advantages:

[0018] The present application is based on a normally open type silicon carbide high-voltage JFET device, and a P-buried layer is added in the conduction channel of the device. The P-buried layer, the P-WELL well and the surrounding N-type drift region are depleted to pinch off the channel, thereby realizing the function of a normally closed high-voltage JFET device. Since the P-buried layer is connected to the P-WELL well, the P-buried layer, the N-type drift region and the P-WELL well form a plurality of characteristic conduction channels in the region, which are opened by applying a gate voltage. The number of channels of the normally closed silicon carbide high-voltage JFET device is increased, the low current capacity problem of the traditional normally closed silicon carbide high-voltage JFET is solved, the current capacity is improved when the characteristic channel is opened by adding the P-buried layer, the reverse withstand voltage capacity is improved by increasing the range of the depletion region when the device is in the off state, and the process manufacturing cost is reduced. Compared with the silicon carbide LDOMS power device, the present application has the advantage of high reliability.

[0019] The present application provides a normally closed silicon carbide high-voltage JFET device and a preparation method thereof. Compared with the traditional silicon-based JFET device, the SiC device breaks through the limit of the traditional silicon-based withstand voltage capacity and the limit of the working temperature, and has more obvious advantages in high-voltage, high-power and high-temperature environments. Since the device does not have a SiC-SiO2 interface, the equivalent mobility of the channel carriers is higher, and the device has obvious advantages in reliability. The opening voltage of the PN junction gate structure changes less with temperature, reducing the possibility of false triggering of the device in a high-temperature environment.

[0020] The normally-off silicon carbide high-voltage JFET device is a lateral device, and the source, drain and gate of the device are located on the same side, which is convenient for integration with other control circuits or devices. BRIEF DESCRIPTION OF DRAWINGS

[0021] For a better description and illustration of the embodiments and / or examples of the inventions disclosed herein, reference can be made to one or more of the accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the presently described embodiments and / or examples, and the presently understood best modes of these inventions.

[0022] Figure 1 is a schematic diagram of a normally-on silicon carbide high-voltage JFET device.

[0023] Figure 2 is a schematic diagram of internal P-type doping 3D of the silicon carbide normally-off high-voltage JFET device of the present application.

[0024] Figure 3 is a schematic diagram of the overall structure of the device along the AA' section in Figure 2

[0025] Figure 4 is a schematic diagram of the overall structure of the device along the BB' section in Figure 2

[0026] Figure 5 is a schematic diagram of the depletion layer structure formed when the device is in the off state. Figure 3

[0027] Figure 6 is a schematic diagram of the current path formed when the device is in the on state. Figure 3

[0028] Figure 7 is a schematic diagram of the depletion layer structure formed when the device is in the off state. Figure 4

[0029] Figure 8 is a schematic diagram of the current path formed when the device is in the on state. Figure 4

[0030] is a schematic diagram of the preparation steps of the silicon carbide normally-off high-voltage JFET device of the present application. Figure 9

[0031] is a schematic diagram of the preparation process of the silicon carbide normally-off high-voltage JFET device, wherein Fig. 10(a)~Fig. 10(e) are schematic diagrams of each step of the preparation process. Figures 10(a) - 10(e) DETAILED DESCRIPTION

[0032] ​​​​​​For the purposes of the present application, the term "about" means ± 10 % of the value being described.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0034] The semiconductor field vocabulary used herein is the technical vocabulary commonly used by those skilled in the art, for example, for P-type and N-type impurities, to distinguish the doping concentration, P+ type represents P-type high-doped injection region, P-well type represents P-type lightly doped region, N+ type represents N-type high-doped injection region, N-well type represents N-type doped region, N-epi is an epitaxial layer, which is a lightly doped region, and N+Sub is a heavily doped substrate; to distinguish the doping position, "first type" and "second type" are used for position distinction. To distinguish the buried layer structure, first P-type buried layer and second P-type buried layer are used for distinction. To distinguish the channel position of the normally-off device, "left", "middle" and "right" are used for distinction. To distinguish the structure in which P-well is connected to the first P-type buried layer and the second P-type buried layer, "left one", "left two", "right one" and "right two" are used for naming the position of the P-type doped channel. Example 1

[0035] Embodiment 1 relates to a device, namely: a normally-off silicon carbide high-voltage JFET device, comprising: an N-type substrate 001, an N-type drift region 002 is provided on the N-type substrate 001, a first P-type well doped region 003, a second P-type well doped region 004, and a first N-type well doped region 005 are provided on the N-type drift region 002, a first P-type high-doped implantation region 111 is provided in the first P-type well doped region 003, a second P-type high-doped implantation region 113 is provided in the second P-type well doped region 004, a first N-type high-doped implantation region 112 is provided between the first P-type well doped region 003 and the second P-type well doped region 004, and both ends of the first N-type high-doped implantation region 112 extend and touch the first P-type well doped region 003 and the second P-type well doped region 004 respectively, a second N-type high-doped implantation region 114 is provided in the first N-type well doped region 005, a first layer of oxide dielectric 006 and a second layer of oxide dielectric 007 are sequentially provided on the N-type epitaxial layer, a metal electrode is led out from the first N-type high-doped implantation region 112 and serves as a source electrode 01S, a metal electrode is led out from the second N-type high-doped implantation region 114 and serves as a drain electrode 01D, a metal electrode is led out from the first P-type high-doped implantation region 111 and the second P-type high-doped implantation region 113 and serves as a gate electrode 01G, the first P-type well doped region 003 and the second P-type well doped region 004 respectively form a back-to-back PN junction with the first N-type high-doped implantation region 112, a first P-buried layer 031 and a second P-buried layer 032 are provided in the N-type drift region 002 region below the first N-type high-doped implantation region 112, and the first P-buried layer 031 and the second P-buried layer 032 are isolated by the N-type drift region 002, the first P-buried layer 031 is electrically connected with the first P-type well doped region 003 to have the same potential, and the second P-buried layer 032 is electrically connected with the second P-type well doped region 004 to have the same potential;

[0036] In a normal state, the device is in an off state, the source electrode 01S and the gate electrode 01G are connected to zero potential voltage, the first P-type well doped region 003, the second P-type well doped region 004, the first P-buried layer 031, and the second P-buried layer 032 have a potential of zero, the N-type drift region 002 located between the first P-type well doped region 003 and the first P-buried layer 031, the N-type drift region 002 located between the first P-buried layer 031 and the second P-buried layer 032, and the N-type drift region 002 located between the second P-buried layer 032 and the second P-type well doped region 004 are in a depletion state, so that the conduction channel 021 is in an off state;

[0037] Specifically, the first P buried layer 031 and the second P buried layer 032 are respectively exhausted with the N-type drift region 002 therebetween, so that the conduction channel 022 is in an off state, and the second P buried layer 032 and the second P-type well doped region 004 are respectively exhausted with the N-type drift region 002 therebetween, so that the conduction channel 023 is in an off state, and the first P-type well doped region 003 and the second P-type well doped region 004 are respectively exhausted with the N-type drift region 002 therebetween, so as to bear the off-state voltage resistance of the device; the greater the voltage applied to the drain 01D, the wider the above-mentioned exhausted region, thereby realizing the off-state process of high-voltage resistance.

[0038] When the device is in an on state, the source 01S is connected to zero potential voltage, the gate 01G is connected to positive voltage, and the drain 01D is connected to high potential voltage. The gate 01G connected to positive voltage makes the N-type drift region 002 between the first P-type well doped region 003 and the first P buried layer 031, the N-type drift region 002 between the first P buried layer 031 and the second P buried layer 032, and the N-type drift region 002 between the second P buried layer 032 and the second P-type well doped region 004 conduct.

[0039] Specifically, the above-mentioned conduction channels 021, 022 and 023 are weakened in exhaustion and realized in conduction. The actual conduction width of the conduction channels 021, 022 and 023 is positively correlated with the voltage applied between the gate 01G terminal regions, and the JFET device current size is jointly controlled by the high potential voltage applied to the drain 01D and the voltage of the gate 01G.

[0040] The embodiment can further adopt the following technical measures:

[0041] The first P buried layer 031 and the first P-type well doped region 003 are connected through a first P-type doped channel 0311, and the second P buried layer 032 and the second P-type well doped region 004 are connected through a second P-type doped channel 0321.

[0042] The first P buried layer 031 and the first P-type well doped region 003 are connected through a third P-type doped channel 0312, and the second P buried layer 032 and the second P-type well doped region 004 are connected through a fourth P-type doped channel 0322.

[0043] The doping concentration of the first P-type well doped region 003, the second P-type well doped region 004, the first P buried layer 031, the second P buried layer 032, the first P-type doped channel 0311, the second P-type doped channel 0321, the third P-type doped channel 0312 and the fourth P-type doped channel 0322 is 1e10~9e10 cm -3 The doping concentration of the first P-type high-doped injection region 111 and the second P-type high-doped injection region 113 is 1e10~9e10 cm -3; the doping concentration of the first N-type well-doped region 005 is 1e10 ~9e10 cm -3 ; the doping concentration of the first N-type high-doped implant region 112 and the second N-type high-doped implant region 114 is 1e10 ~9e10 cm -3 . Embodiment 2

[0044] Embodiment 2 relates to a device preparation method, i.e., a preparation method of a normally-off silicon carbide high-voltage JFET device, including the following steps:

[0045] forming an N-type substrate 001 on a silicon carbide substrate and epitaxially growing an N-type drift region 002 on the N-type substrate 001;

[0046] performing P-type ion implantation on the N-type drift region 002 to form a first P-type well-doped region 003 and a second P-type well-doped region 004, respectively, and performing N-type ion implantation on the N-type drift region 002 to form a first N-type well-doped region 005;

[0047] performing P-type ion implantation in the N-type drift region 002 between the first P-type well-doped region 003 and the second P-type well-doped region 004 to form a first P-type buried layer 031, a second P-type buried layer 032, a first P-type doped channel 0311 electrically connecting the first P-type well-doped region 003 and the first P-type buried layer 031, and a second P-type doped channel 0321 electrically connecting the second P-type buried layer 032 and the second P-type well-doped region 004; and performing high-doped P-type ion implantation in the first P-type well-doped region 003 and the second P-type well-doped region 004 to form a first P-type high-doped implant region 111 and a second P-type high-doped implant region 113;

[0048] performing high-doped N-type ion implantation in the N-type drift region 002 between the first P-type well-doped region 003 and the second P-type well-doped region 004 and above the first P-type buried layer 031 and the second P-type buried layer 032, a partial region of the first P-type well-doped region 003 adjacent to the second P-type well-doped region 004, a partial region of the second P-type well-doped region 004 adjacent to the first P-type well-doped region 003, and the first N-type well-doped region 005 to form a first N-type high-doped implant region 112 and a second N-type high-doped implant region 114, respectively;

[0049] after high-temperature thermal annealing treatment at 1300℃ ~1700℃, depositing an oxide layer medium on the surface of the N-type drift region 002, etching a through hole on the oxide layer medium, and depositing a metal to form a source electrode 01S above the first N-type high-doped implant region 112, a source electrode 01D above the second N-type high-doped implant region 114, and a gate electrode 01G above the first P-type high-doped implant region 111 and the second P-type high-doped implant region 113.

[0050] The embodiment further adopts the following technical measures:

[0051] The depositing of the oxide layer medium, etching of the through hole and depositing of the metal include: depositing a first layer of oxide layer medium 006, etching a through hole on the first layer of oxide layer medium 006 above the first N-type high-doped injection area 112 and on the first layer of oxide layer medium 006 above the second N-type high-doped injection area 114, and depositing a metal to lead out a source electrode 01S on the first N-type high-doped injection area 112 and a source electrode 01D on the second N-type high-doped injection area 114 respectively; depositing a second layer of oxide layer medium 007 on the first layer of oxide layer medium 006, etching a through hole on the first layer of oxide layer medium 006 above the first P-type high-doped injection area 111 and on the first layer of oxide layer medium 006 above the second P-type high-doped injection area 113 and on the second layer of oxide layer medium 007, and depositing a metal to lead out a gate electrode 01G on the first P-type high-doped injection area 111 and on the second P-type high-doped injection area 113.

[0052] The dose of the P-type ion injection is 1e10~9e10 cm -3 , and the energy is 1.2MeV~10MeV; the dose of the high-doped P-type ion injection is 1e12~9e12 cm -3 , and the energy is 10keV~1.2MeV.

[0053] The dose of the N-type ion injection is 1e10~9e10 cm -3 , and the energy is 1.2MeV~10MeV; the dose of the high-doped N-type ion injection is 1e12~9e12 cm -3 , and the energy is 10keV~1.2MeV.

[0054] The annealing temperature of the high-temperature thermal annealing is 1300℃~1700℃.

[0055] The application will be further explained below with reference to Figures 1 - 4 :

[0056] The application proposes a new type of silicon carbide normally-on high-voltage JFET device structure aiming at the problems of poor current capacity and insufficient channel voltage resistance of the traditional silicon carbide normally-off high-voltage JFET device. Figure 1 is a schematic diagram of a silicon carbide normally-on high-voltage JFET device structure, and the application Figure 2 is a schematic diagram of a silicon carbide normally-off high-voltage JFET device structure. Figure 1On the basis of the trench, the first P buried layer 031 and the second P buried layer 032 are designed, and are connected with the first P-type well doped area 003 and the second P-type well doped area 004 through the first P-type doped channel 0311, the second P-type doped channel 0312, the third P-type doped channel 0321 and the fourth P-type doped channel 0322, to form the normally-off left trench 021, the normally-off middle trench 022 and the normally-off right trench 023.

[0057] In the normally-off state of the normally-off silicon carbide high-voltage JFET device, the source 01S and the gate 01G are connected to zero potential voltage, the zero potential gate 01G is connected with the first P-type high-doped injection area 111 and the second P-type high-doped injection area 113, so that the first P-type well doped area 003, the second P-type well doped area 004, the first P buried layer 031 and the second P buried layer 032 are all at zero potential, the first P-type well doped area 003 and the first P buried layer 031 are respectively connected with the N-type drift area 002 therebetween to make the on-trench 021 in the off state, the first P buried layer 031 and the second P buried layer 032 are respectively connected with the N-type drift area 002 therebetween to make the on-trench 022 in the off state, the second P buried layer 032 and the second P-type well doped area 004 are respectively connected with the N-type drift area 002 therebetween to make the on-trench 023 in the off state, and the first P-type well doped area 003 and the second P-type well doped area 004 are respectively connected with the N-type drift area 002 around to bear the off-state voltage of the device, and the wider the above-mentioned depletion region is, the higher the voltage of the drain 01D is, and the higher the voltage of the drain 01D is, the higher the voltage of the drain 01D is.

[0058] In the normally-off state of the normally-off silicon carbide high-voltage JFET device, the source 01S and the gate 01G are connected to zero potential voltage, the zero potential gate 01G is connected with the first P-type high-doped injection area 111 and the second P-type high-doped injection area 113, so that the first P-type well doped area 003, the second P-type well doped area 004, the first P buried layer 031 and the second P buried layer 032 are all at zero potential, the first P-type well doped area 003 and the first P buried layer 031 are respectively connected with the N-type drift area 002 therebetween to make the on-trench 021 in the off state, the first P buried layer 031 and the second P buried layer 032 are respectively connected with the N-type drift area 002 therebetween to make the on-trench 022 in the off state, the second P buried layer 032 and the second P-type well doped area 004 are respectively connected with the N-type drift area 002 therebetween to make the on-trench 023 in the off state, and the first P-type well doped area 003 and the second P-type well doped area 004 are respectively connected with the N-type drift area 002 around to bear the off-state voltage of the device, and the wider the above-mentioned depletion region is, the higher the voltage of the drain 01D is, and the higher the voltage of the drain 01D is, the higher the voltage of the drain 01D is.

[0059] Figure 2 It is the 3D schematic diagram of the P-type doping of the silicon carbide normally-off high-voltage JFET device of the application.

[0060] The present application is a normally-off silicon carbide high-voltage JFET device, which forms a normally-off feature structure below the first N-type high-doped injection region 112, which includes a first P buried layer 031, a second P buried layer 032, a first P-type well-doped region 003, and a second P-type well-doped region 004 to form a normally-off feature left channel 021, a normally-off feature middle channel 022, and a normally-off feature right channel 023.

[0061] In the area to the right of the first P-type high-doped injection region 111, the area to the left of the second P-type high-doped injection region 113, and the position above the prismatic region of the first P-type well-doped region 003 and the prismatic region of the second P-type well-doped region 004, which is the first N-type high-doped injection region 112 in this example. In the area below the first N-type high-doped injection region 112, the remaining area excluding the first P buried layer 031, the second P buried layer 032, the first P-type doped channel 0311, the second P-type doped channel 0312, the third P-type doped channel 0321, the fourth P-type doped channel 0322, the first P-type well-doped region 003, and the second P-type well-doped region 004 is the on-state channel area during device operation, and this area is part of the N-type drift region 002.

[0062] Figure 3 With Figure 4 being different cross-sectional views of the normally-off silicon carbide high-voltage JFET device of the present application, the difference is that Figure 3 along Figure 2 the AA' section, the first P buried layer 031, the second P buried layer 032, the first P-type well-doped region 003, and the second P-type well-doped region 004 are not connected in the front view, Figure 4 along Figure 2 the BB' section, which shows that the first P buried layer 031, the second P buried layer 032, the first P-type well-doped region 003, and the second P-type well-doped region 004 are connected in the device, Figure 2 which is the complete P-type doped connection structure of the device in this example, showing their relative positions.

[0063] Referring to Figure 5 , Figure 5 is a schematic diagram of the preparation steps of the normally-off silicon carbide high-voltage JFET device of the present application, including the following steps:

[0064] S710, obtaining a substrate.

[0065] Obtaining an N-type silicon carbide substrate.

[0066] S720, growing an epitaxial layer on the substrate.

[0067] Growing an N-type epitaxial layer 002 on one side of the N-type silicon carbide substrate 001.

[0068] S730, twice ion implantation in the epitaxial layer to form different types of doped well.

[0069] Twice ion implantation of different types in the N-type epitaxial layer 002 grown above to form a first P-type well doped region 003, a second P-type well doped region 004, and a first N-type well doped region 005.

[0070] P-type ion implantation is performed again in the N-type drift region 002 between the first P-type well doped region 003 and the second P-type well doped region 004 to form a first P-type buried layer 031, a second P-type buried layer 032, a first P-type doped channel 0311, a second P-type doped channel 0312, a first P-type doped channel 0321, a second P-type doped channel 0322, a characteristic left channel 021, a characteristic middle channel 022, a characteristic right channel 023, a characteristic left middle channel 024, a characteristic right middle channel 025, a characteristic left back conduction channel 026, and a characteristic right back conduction channel 027.

[0071] S740, ion implantation of corresponding types in different types of wells to form high doping.

[0072] High doping is performed in the first P-type well doped region 003, the second P-type well doped region 004, and the first N-type well doped region 005 to form a first P-type high-doped implantation region 111, a second P-type high-doped implantation region 113, and a second N-type high-doped implantation region 114.

[0073] S750, growth of a first layer of interlayer dielectric.

[0074] Growth of a first layer of oxide interlayer dielectric on the plane of the N-type epitaxial layer 002.

[0075] S760, etching and etching deposition of metal electrodes to form source and drain.

[0076] Etching and deposition of metal on the oxide above the corresponding first P-type high-doped implantation region 111, second P-type high-doped implantation region 113, first N-type high-doped implantation region 112, and second N-type high-doped implantation region 114 regions, and leading out the first N-type high-doped implantation region 112 as the device source and the second N-type high-doped implantation region 114 as the device drain on the first layer of interlayer dielectric.

[0077] S770, growth of a second layer of interlayer dielectric.

[0078] Depositing metal on the first layer above the first P-type high doped injection region 111 and the second P-type high doped injection region 113, continuing to etch the second layer of interlayer dielectric and depositing metal on the corresponding position, leading out the metal electrode, connecting the metal electrodes above the second layer of interlayer dielectric, as the device gate.

Claims

1. A normally-off silicon carbide high-voltage JFET device, comprising: An N-type substrate (001) is provided with an N-type drift region (002) on the N-type substrate (001); a first P-type well doping region (003), a second P-type well doping region (004), and a first N-type well doping region (005) are provided on the N-type drift region (002); a first P-type high-doping injection region (111) is provided in the first P-type well doping region (003); a second P-type high-doping injection region (113) is provided in the second P-type well doping region (004); A first N-type highly doped injection region (112) is provided between the second P-type well doping region (004), and both ends of the first N-type highly doped injection region (112) extend and touch the first P-type well doping region (003) and the second P-type well doping region (004), a second N-type highly doped injection region (114) is provided in the first N-type well doping region (005), a first oxide layer medium (006) and a second oxide layer medium (007) are provided in sequence on the N-type epitaxy, and a first N-type highly doped injection region (114) is provided in the first N-type well doping region (005), and a second oxide layer medium (006) and a second oxide layer medium (007) are provided in sequence on the first N-type highly doped injection region (112). A metal electrode is drawn out from the region (112) and serves as a source (01S), a metal electrode is drawn out from the second N-type highly doped injection region (114) and serves as a drain (01D), metal electrodes are drawn out from the first P-type highly doped injection region (111) and the second P-type highly doped injection region (113) and serve as a gate (01G), the first P-type well doped region (003) and the second P-type well doped region (004) respectively forming a back-to-back PN junction with the first N-type highly doped injection region (112), characterized in that: A first P buried layer (031) and a second P buried layer (032) are provided in the N-type drift region (002) below the first N-type highly doped injection region (112), and the first P buried layer (031) and the second P buried layer (032) are isolated by the N-type drift region (002); the first P buried layer (031) and the first P-type well doped region (003) are electrically connected so that they have the same potential; and the second P buried layer (032) and the second P-type well doped region (004) are electrically connected so that they have the same potential; Under normal conditions, the device is in an off state, the source (01S) and the gate (01G) are connected to a zero potential voltage, the potentials of the first P-type well doping region (003), the second P-type well doping region (004), the first P buried layer (031) and the second P buried layer (032) are zero, the N-type drift region (002) between the first P-type well doping region (003) and the first P buried layer (031), the N-type drift region (002) between the first P buried layer (031) and the second P buried layer (032), and the N-type drift region (002) between the second P buried layer (032) and the second P-type well doping region (004) are in a depleted state, so that the conducting channel 021 is in an off state; When the device is in an on state, the source (01S) is connected to a zero potential voltage, the gate (01G) is connected to a positive voltage, and the drain (01D) is externally connected to a high potential voltage. The gate (01G) connected to the positive voltage causes the N-type drift region (002) located between the first P-type well doping region (003) and the first P buried layer (031), the N-type drift region (002) located between the first P buried layer (031) and the second P buried layer (032), and the N-type drift region (002) located between the second P buried layer (032) and the second P-type well doping region (004) to be turned on.

2. The normally-off silicon carbide high-voltage JFET device according to claim 1, characterized in that: The first P-buried layer (031) is connected to the first P-type well doping region (003) via a first P-type doping channel (0311), and the second P-buried layer (032) is connected to the second P-type well doping region (004) via a second P-type doping channel (0321).

3. The normally-off silicon carbide high-voltage JFET device according to claim 1 or 2, characterized in that: The first P-buried layer (031) is connected to the first P-type well doping region (003) via a third P-type doping channel (0312), and the second P-buried layer (032) is connected to the second P-type well doping region (004) via a fourth P-type doping channel (0322).

4. The normally-off silicon carbide high-voltage JFET device according to claim 3, wherein: The doping concentration of the first P-type well doping region (003), the second P-type well doping region (004), the first P buried layer (031), the second P buried layer 032, the first P-type doping channel (0311), the second P-type doping channel (0321), the third P-type doping channel (0312) and the fourth P-type doping channel (0322) is 1e10~9e10 cm -3 The doping concentration of the first P-type highly doped injection region 111 and the second P-type highly doped injection region 113 is 1e10 ~ 9e10 cm -3 The doping concentration of the first N-type well doping region (005) is 1e10 ~9e10 cm -3 The doping concentration of the first N-type highly doped injection region (112) and the second N-type highly doped injection region (114) is 1e10~9e10 cm -3 .

5. A method for preparing a normally-off silicon carbide high-voltage JFET device, characterized in that the steps include: forming an N-type substrate (001) on a silicon carbide base, and epitaxially growing an N-type drift region (002) on the N-type substrate (001); Performing P-type ion implantation on the N-type drift region (002) to form a first P-type well doping region (003) and a second P-type well doping region (004), and performing N-type ion implantation on the N-type drift region (002) to form a first N-type well doping region (005); Performing P-type ion implantation in the N-type drift region (002) between the first P-type well doping region (003) and the second P-type well doping region (004) to respectively form a first P-buried layer (031), a second P-buried layer (032), a first P-type doping channel (0311) electrically connecting the first P-type well doping region (003) to the first P-buried layer (031), and a second P-type doping channel (0321) electrically connecting the second P-buried layer (032) to the second P-type well doping region (004); performing highly doped P-type ion implantation in the first P-type well doping region (003) and the second P-type well doping region (004) to form a first P-type highly doped implantation region (111) and a second P-type highly doped implantation region (113); Highly doped N-type ion implantation is performed in an N-type drift region (002) located between the first P-type well doping region (003) and the second P-type well doping region (004) and above the first P buried layer (031) and the second P buried layer (032), a portion of the first P-type well doping region (003) adjacent to the second P-type well doping region (004), a portion of the second P-type well doping region (004) adjacent to the first P-type well doping region (003), and the first N-type well doping region (005) to form a first N-type highly doped implantation region (112) and a second N-type highly doped implantation region (114), respectively. After a high-temperature thermal annealing treatment at 1300°C to 1700°C, an oxide layer dielectric is deposited on the surface of the N-type drift region (002), and then a through hole is etched on the oxide layer dielectric and metal is deposited to respectively lead out a source electrode (01S) above the first N-type highly doped injection region (112), a drain electrode (01D) above the second N-type highly doped injection region (114), and a gate electrode (01G) above the first P-type highly doped injection region (111) and the second P-type highly doped injection region (113).

6. The method for preparing a normally-off silicon carbide high-voltage JFET device according to claim 5, wherein: The deposition of the oxide layer dielectric, etching through holes and depositing metal include first depositing a first oxide layer dielectric (006), etching through holes on the first oxide layer dielectric (006) above the first N-type highly doped injection region (112) and the first oxide layer dielectric (006) above the second N-type highly doped injection region (114), and depositing metal to respectively lead out a source (01S) on the first N-type highly doped injection region (112) and a drain (01D) on the second N-type highly doped injection region (114); then depositing a second oxide layer dielectric (007) on the first oxide layer dielectric (006), etching through holes on the first oxide layer dielectric (006) above the first P-type highly doped injection region (111) and the second P-type highly doped injection region (113), and depositing metal. ) and a through hole is etched on the substrate, and metal is deposited to lead out a gate (01G) on the first P-type highly doped injection region (111) and the second P-type highly doped injection region (113).

7. The method for preparing a normally-off silicon carbide high-voltage JFET device according to claim 5, wherein: The dose of the P-type ion implantation is 1e10~9e10 cm -3 , the energy is 1.2MeV~10MeV; the dosage of the highly doped P-type ion implantation is 1e12~9e12 cm -3 , energy is 10keV~1.2MeV.

8. The method for preparing a normally-off silicon carbide high-voltage JFET device according to claim 5 or 7, wherein: The dose of the N-type ion implantation is 1e10~9e10 cm -3 , the energy is 1.2MeV~10MeV, and the dosage of the highly doped N-type ion implantation is 1e12~9e12 cm -3 , energy is 10keV~1.2MeV.

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