Grid-connected Inverter Phase Sequence Adaptive Control Method, Device, Electronic Equipment and Computer Readable Storage Medium

Abstract

The present disclosure provides a grid-connected inverter phase sequence adaptive control method, including the following steps: obtaining the quadrature-axis current command value and the direct-axis current command value based on the given voltage and the load system feedback voltage; obtaining the phase difference based on the line voltage of the grid-connected inverter and the initial feedforward adaptive value; obtaining the quadrature-axis current feedback value and the direct-axis current feedback value based on the phase current of the grid-connected inverter and the phase difference; obtaining the quadrature-axis voltage command and the direct-axis voltage command based on the quadrature-axis current command value, the quadrature-axis current feedback value, the direct-axis current command value, and the direct-axis current feedback value; obtaining the voltage synthesis vector based on the quadrature-axis voltage command, the direct-axis voltage command, and the phase difference; determining whether the maximum amplitude of the voltage synthesis vector is greater than a preset amplitude: if not, obtaining the target feedforward adaptive value; if so, adjusting the initial feedforward adaptive value until the maximum amplitude of the voltage synthesis vector is not greater than the preset amplitude, achieving a fast response in case of a fault and automatically establishing voltage, with high efficiency.

Description

Technical Field

[0001] The present disclosure relates to the technical field of frequency converter control, and more particularly, to a phase sequence adaptive control method for a grid-connected inverter, a phase sequence adaptive control device, an electronic device, and a computer-readable storage medium. Background Art

[0002] In order to smoothly deliver the unpredictable electric energy generated by distributed energy to the power grid, a grid-connected inverter is usually used as the interface between the renewable energy power generation unit and the power grid. In order to control the power fed by the grid-connected inverter to the power grid, the system usually uses a phase-locked loop to detect the phase of the grid voltage. When there is a wrong wiring on the grid side of the grid-connected inverter, it will cause the phase sequence to be chaotic, the phase-locked loop cannot correctly detect the grid voltage, and the grid-connected inverter cannot correctly identify and generate the correct output, which will further cause the motor to fail to start or operate unstably. In the prior art, the grid-side lines are usually maintained and overhauled regularly. Due to the long distance of the grid-side lines and various types of wiring faults, there are problems of long maintenance time and high labor consumption. Summary of the Invention

[0003] To solve the above technical problems, the present application provides a phase sequence adaptive control method for a grid-connected inverter, a phase sequence adaptive control device, an electronic device, and a computer-readable storage medium, which perform fault detection based on the amplitude of the output voltage synthesis vector in the system, respond quickly when a fault occurs, have a simple detection method, high efficiency, and can realize automatic voltage build-up, saving manpower.

[0004] The first aspect of the present invention provides a phase sequence adaptive control method, including:

[0005] Obtaining a quadrature-axis current command value and a direct-axis current command value based on a given voltage and a load system feedback voltage;

[0006] Obtaining a phase difference based on the line voltage of the grid-connected inverter and an initial feedforward adaptive value;

[0007] Obtaining a quadrature-axis current feedback value and a direct-axis current feedback value based on the phase current of the grid-connected inverter and the phase difference;

[0008] Obtaining a quadrature-axis voltage command and a direct-axis voltage command based on the quadrature-axis current command value, the quadrature-axis current feedback value, the direct-axis current command value, and the direct-axis current feedback value;

[0009] Obtaining a voltage synthesis vector based on the quadrature-axis voltage command, the direct-axis voltage command, and the phase difference;

[0010] Judging whether the maximum amplitude of the voltage synthesis vector is greater than a preset amplitude:

[0011] If not, obtaining a target feedforward adaptive value;

[0012] If so, adjust the initial feedforward adaptive value until the maximum amplitude of the voltage synthesis vector is not greater than the preset amplitude.

[0013] Optionally, obtaining the phase difference based on the line voltage and the feedforward adaptive value includes:

[0014] Obtain the three-phase voltage based on the line voltage of the grid-connected inverter;

[0015] Obtain the quadrature-axis voltage of the phase-locked loop based on the three-phase voltage;

[0016] Obtain the phase difference based on the quadrature-axis voltage of the phase-locked loop and the feedforward adaptive value.

[0017] Optionally, obtaining the voltage synthesis vector based on the quadrature-axis voltage command, the direct-axis voltage command, and the phase difference includes:

[0018] Obtain the voltage command based on the difference between the quadrature-axis current command value and the current feedback value, and obtain the direct-axis voltage command based on the difference between the direct-axis current command value and the direct-axis current feedback value;

[0019] Obtain the α-axis voltage command and the β-axis voltage command based on the quadrature-axis voltage command, the direct-axis voltage command, and the phase difference;

[0020] Obtain the voltage synthesis vector based on the α-axis voltage command and the β-axis voltage command.

[0021] Optionally, the voltage synthesis vector satisfies:

[0022]

[0023] where A represents the voltage synthesis vector, u α represents the α-axis voltage command, u β represents the β-axis voltage command.

[0024] Optionally, the preset amplitude satisfies:

[0025] U T = 1.1U m

[0026] where U T represents the preset amplitude, U m represents the phase voltage of the grid-connected inverter.

[0027] Optionally, the initial feedforward adaptive value satisfies:

[0028] Q0 = 2πf

[0029] where Q0 represents the initial feedforward adaptive value, and f represents the grid-side frequency of the grid-connected inverter.

[0030] Optionally, the target feedforward adaptive value satisfies:

[0031] Q = -2πf

[0032] wherein Q represents the target feedforward adaptive value, f and represents the grid-side frequency of the grid-connected inverter.

[0033] The second aspect of the present invention provides a phase sequence adaptive control device, comprising:

[0034] An instruction calculation module configured to obtain a quadrature-axis current instruction value and a direct-axis current instruction value based on a given voltage and a load system feedback voltage;

[0035] A phase sequence adaptive module, comprising:

[0036] A phase calculation module configured to obtain a phase difference based on the line voltage of the grid-connected inverter and the feedforward adaptive value;

[0037] A feedback calculation module configured to obtain a quadrature-axis current feedback value and a direct-axis current feedback value based on the phase current of the grid-connected inverter and the phase difference;

[0038] The instruction calculation module further includes a voltage instruction calculation module configured to obtain a quadrature-axis voltage instruction and a direct-axis voltage instruction based on the quadrature-axis current instruction value, the quadrature-axis current feedback value, the direct-axis current instruction value, and the direct-axis current feedback value;

[0039] The phase sequence adjustment module further includes an output voltage vector synthesis module configured to obtain a voltage synthesis vector based on the quadrature-axis voltage instruction, the direct-axis voltage instruction, and the phase difference;

[0040] A determination module configured to determine whether the maximum amplitude of the voltage synthesis vector is greater than a preset amplitude:

[0041] If not, obtain the target feedforward adaptive value;

[0042] If so, adjust the initial feedforward adaptive value until the maximum amplitude of the voltage synthesis vector is not greater than the preset amplitude.

[0043] Optionally, the phase calculation module includes:

[0044] A line-to-phase conversion module configured to obtain three-phase voltages based on the line voltage of the grid-connected inverter;

[0045] A first coordinate transformation module configured to obtain a quadrature-axis voltage of a phase-locked loop based on the three-phase voltages;

[0046] A phase difference output module configured to obtain a phase difference based on the quadrature-axis voltage of the phase-locked loop and the feedforward adaptive value.

[0047] Optionally, the voltage vector synthesis module includes:

[0048] A second coordinate transformation module, configured to obtain an α-axis voltage command and a β-axis voltage command based on a quadrature-axis voltage command, a direct-axis voltage command, and a phase difference;

[0049] A vector synthesis module, configured to obtain a voltage synthesis vector based on the α-axis voltage command and the β-axis voltage command.

[0050] A third aspect of the present invention provides an electronic device, including a bus, a transceiver, a memory, a processor, and a computer program stored on the memory and executable on the processor. The transceiver, the memory, and the processor are connected through the bus. When the computer program is executed by the processor, the steps in the grid-connected inverter phase sequence adaptive control method described in any one of the above are implemented.

[0051] A fourth aspect of the present invention further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by the processor, the steps in the grid-connected inverter phase sequence adaptive control method described in any one of the above are implemented.

[0052] According to the grid-connected inverter phase sequence adaptive control method, phase sequence adaptive control device, electronic device, and computer-readable storage medium provided by the embodiments of the present application, based on the grid-connected inverter, using the amplitude of the output voltage synthesis vector in the system as the switching condition, adaptively solve the phase sequence fault caused by wiring errors. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the background art, the following will describe the drawings required to be used in the embodiments of the present application or the background art. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0054] Figure 1 Shows a schematic diagram of the grid-connected inverter grid-side control system in the embodiments of the present application;

[0055] Figure 2 Shows a flowchart of a grid-connected inverter phase sequence adaptive control method provided by the embodiments of the present application;

[0056] Figure 3 Shows a schematic diagram of the principle of a variable grid inverter provided by the embodiments of the present application;

[0057] Figure 4 Shows a schematic diagram of the phase sequence adjustment module and determination module of a variable grid inverter provided by the embodiments of the present application;

[0058] Figure 5 Shows a wiring fault schematic diagram in the embodiments of the present application;

[0059] Figure 6 Shows the voltage build-up effect diagram using the phase sequence adaptive control method in an embodiment of the present application;

[0060] Figure 7 Shows the schematic diagram of the phase sequence adaptive control device provided in an embodiment of the present application;

[0061] Figure 8 Shows the schematic diagram of the instruction calculation module provided in an embodiment of the present application;

[0062] Figure 9 Shows the schematic diagram of the phase sequence adjustment module provided in an embodiment of the present application;

[0063] Figure 10 Shows the schematic diagram of the phase calculation module provided in an embodiment of the present application;

[0064] Figure 11 Shows the schematic diagram of the feedback calculation module provided in an embodiment of the present application;

[0065] Figure 12 Shows the schematic diagram of the output voltage vector synthesis module provided in an embodiment of the present application;

[0066] Figure 13 Shows the schematic diagram of the electronic device provided in an embodiment of the present application.

[0067] List of reference numerals: 100 - instruction calculation module, 110 - current instruction calculation module, 120 - voltage instruction calculation module, 200 - phase sequence adjustment module, 210 - phase calculation module, 211 - line - phase conversion module, 212 - first coordinate transformation module, 213 - phase difference output module, 2131 - PLL phase - locked loop, 220 - feedback calculation module, 221 - second coordinate transformation module, 222 - third coordinate transformation module, 230 - output voltage vector synthesis module, 231 - fourth coordinate transformation module, 232 - vector synthesis module, 240 - determination module, 500 - space voltage vector modulation module, 910 - power grid, 920 - LCL filter, 921 - Hall current sensor, 922 - Hall voltage sensor, 930 - main control board, 940 - inverter module, 950 - load system, 1110 - bus, 1120 - processor, 1130 - transceiver, 1140 - bus interface, 1150 - memory, 1160 - user interface. Detailed implementation manners

[0068] In the description of the embodiments of the present invention, those skilled in the art should know that the embodiments of the present invention can be implemented as a method, an apparatus, an electronic device, and a computer-readable storage medium. Therefore, the embodiments of the present invention can be specifically implemented in the following forms: complete hardware, complete software (including firmware, resident software, microcode, etc.), and a combination of hardware and software. In addition, in some embodiments, the embodiments of the present invention can also be implemented in the form of a computer program product in one or more computer-readable storage media, and the computer-readable storage media contain computer program code.

[0069] The above-mentioned computer-readable storage media can adopt any combination of one or more computer-readable storage media. Computer-readable storage media include: electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or components, or any combination of the above. More specific examples of computer-readable storage media include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), flash memory, optical fibers, compact disc read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any combination of the above. In the embodiments of the present invention, the computer-readable storage media can be any tangible medium that contains or stores a program, and the program can be used by or in combination with an instruction execution system, device, or component.

[0070] The computer program code contained in the above-mentioned computer-readable storage media can be transmitted by any suitable medium, including: wireless, wire, optical cable, radio frequency (RF), or any suitable combination of the above.

[0071] The computer program code for performing the operations of the embodiments of the present invention can be written in assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, status setting data, integrated circuit configuration data, or in one or more programming languages or combinations thereof. The programming languages include object-oriented programming languages, such as: Java, Smalltalk, C++, and also include conventional procedural programming languages, such as: C language or similar programming languages. The computer program code can be executed entirely on the user's computer, partially on the user's computer, executed as an independent software package, partially on the user's computer and partially on a remote computer, and entirely on a remote computer or server. In the case of a remote computer, the remote computer can be connected to the user's computer through any type of network, including: local area network (LAN) or wide area network (WAN), and can also be connected to an external computer.

[0072] Embodiments of the present invention describe the provided methods, apparatuses, and electronic devices through flowcharts and / or block diagrams.

[0073] It should be understood that each box of the flowchart and / or block diagram, as well as the combinations of boxes in the flowchart and / or block diagram, can be implemented by computer-readable program instructions. These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine. These computer-readable program instructions, when executed by a computer or other programmable data processing device, generate an apparatus that implements the functions / operations specified in the boxes of the flowchart and / or block diagram.

[0074] These computer-readable program instructions can also be stored in a computer-readable storage medium that enables a computer or other programmable data processing device to work in a specific manner. In this way, the instructions stored in the computer-readable storage medium produce an instruction device product that includes instructions for implementing the functions / operations specified in the boxes of the flowchart and / or block diagram.

[0075] The computer-readable program instructions can also be loaded onto a computer, other programmable data processing device, or other device, such that a series of operation steps are executed on the computer, other programmable data processing device, or other device to produce a computer-implemented process. Thus, the instructions executed on the computer or other programmable data processing device can provide a process for implementing the functions / operations specified in the boxes of the flowchart and / or block diagram.

[0076] In the related art, the problem of wiring faults is usually eliminated by manual line inspection, which is not only cumbersome to operate but also error-prone. Considering overcoming the above defects, the present application proposes a phase sequence adaptive control method for a grid-connected inverter, which performs fast fault detection based on the amplitude of the output voltage in the system, realizes automatic adaptation to the grid phase sequence while ensuring the stability of the frequency converter system, and improves the intelligence and convenience of the frequency converter.

[0077] Figure 1 The schematic diagram of the grid-side control system of the grid-connected inverter of the present application is shown, where the power grid 910 supplies power to the load system 950 through the LCL filter 920. The main control board 930 provides a pulse width modulation signal to the inverter module 940, converting the AC power of the power grid 910 into an adjustable AC power to supply the load system 950. Specifically, the LCL filter 902 includes a Hall current sensor 921 and a Hall voltage sensor 922. The main control board 930 collects the phase current I sabc through the Hall current sensor 921, and collects the line voltage U mabc through the Hall voltage sensor 922, and collects the DC load voltage of the load system 950 as the load system feedback voltage U dc .

[0078] Figure 2 The figure shows a phase sequence adaptive control method provided by an embodiment of the present application. The method at least includes the following steps:

[0079] Based on the given voltage and the feedback voltage of the load system, obtain the quadrature-axis current command value and the direct-axis current command value. Figure 3 The figure shows a schematic diagram of the principle of a variable network inverter provided by an embodiment of the present application. Specifically, as Figure 3 shown, it is stipulated that the quadrature-axis current command value i qref is 0, and the difference between the given voltage U ref and the feedback voltage U dc of the load system is adjusted by a PID controller to obtain the direct-axis current command value i dref .

[0080] Obtain the phase difference based on the line voltage of the grid-connected inverter and the initial feedforward adaptive value. Figure 4 The figure shows a schematic diagram of a phase sequence adaptive module of a variable network inverter provided by an embodiment of the present application. Specifically, as Figure 4 shown, the line voltage U mabc is subjected to line-to-phase conversion to obtain three-phase voltages U a , U b , U c . Then, the three-phase voltages U a , U b , U c are subjected to coordinate transformation to obtain the quadrature-axis voltage U qfdb of the phase-locked loop in the d-q coordinate system. Taking the initial feedforward adaptive value Q0 as the initial frequency of the PLL phase-locked loop 2131, the difference between the quadrature-axis voltage U qfdb and 0 is used as a reference signal to be input into the PLL phase-locked loop 2131, and the phase difference θ between the quadrature-axis voltage U qfdb of the phase-locked loop and the grid-side frequency is obtained. The phase difference θ is the output phase angle of the PLL phase-locked loop 2131.

[0081] Obtain the quadrature-axis current feedback value and the direct-axis current feedback value based on the phase current of the grid-connected inverter and the phase difference. Specifically, as Figure 4 shown, the phase current I sabc is subjected to coordinate transformation to obtain the currents i α and i β in the α-β coordinate system. The phase difference θ corresponds to the angle between the two-phase stationary coordinate system and the two-phase rotating coordinate system. Combining the phase difference θ, the currents i α and i β in the α-β coordinate system are again subjected to coordinate transformation to be converted into two direct-axis electric energies, and the quadrature-axis current feedback value i qfdb and the direct-axis current feedback value idfdb 。

[0082] Obtain the quadrature-axis voltage command and the direct-axis voltage command based on the quadrature-axis current command value, the quadrature-axis current feedback value, the direct-axis current command value, and the direct-axis current feedback value.

[0083] Specifically, as Figure 3 shown, the quadrature-axis current command value i qref is subtracted from the quadrature-axis current feedback value i qfdb , and after being adjusted by the PID controller, the quadrature-axis voltage command u d is obtained; the direct-axis current command value i dref is subtracted from the direct-axis current feedback value i dfdb , and after being adjusted by the PID controller, the direct-axis voltage command u q is obtained.

[0084] Obtain the voltage synthesis vector based on the quadrature-axis voltage command, the direct-axis voltage command, and the phase difference.

[0085] Specifically, as Figure 4 shown, the quadrature-axis voltage command u d and the direct-axis voltage command u q are coordinate-transformed to obtain the voltage commands u α and u β in the α-β coordinate system, and u α and u β synthesize the output voltage vector.

[0086] Furthermore, as Figure 3 shown, u α and u β are input to the space voltage vector modulation module (SVPWM) 500 to generate the control signals of the switching tubes and drive the inverter module 940 to work.

[0087] In an optional embodiment, the voltage synthesis vector satisfies:

[0088]

[0089] where A represents the voltage synthesis vector, u α represents the α-axis voltage command, and u β represents the β-axis voltage command.

[0090] Judge whether the maximum amplitude of the voltage synthesis vector is greater than the preset amplitude. If not, obtain the target feedforward adaptive value; if so, adjust the initial feedforward adaptive value until the maximum amplitude of the voltage synthesis vector is not greater than the preset amplitude. Specifically, when the output voltage synthesis vector is greater than the preset amplitude U T , refer to Figure 4, adjust the initial feedforward adaptive value, change the phase difference θ, and further change the voltage command u in the α-β coordinate system based on the phase difference θ α and u β , thereby changing the voltage synthesis vector until it is not greater than the preset amplitude U T , and at this time, the target feedforward adaptive value Q is obtained.

[0091] In an alternative embodiment, the preset amplitude satisfies:

[0092] U T = 1.1U m

[0093] wherein, U T represents the preset amplitude, and U m represents the grid phase voltage of the grid-connected inverter.

[0094] In an alternative embodiment, the initial feedforward adaptive value satisfies:

[0095] Q0 = 2πf

[0096] Q0 represents the initial feedforward adaptive value, and f represents the grid-side frequency of the grid-connected inverter. 2πf represents the angular frequency of the grid frequency f. Inputting the angular frequency as the initial value into the phase-locked loop can achieve the function of feedforward, enabling the phase-locked loop to work properly.

[0097] Figure 5 shows the wiring fault schematic diagrams in various embodiments of the present application. As Figure 5 shown, all three cases of two-phase mixed connection will cause the rotation direction of the dq axis to change, and the feedforward compensation becomes a counteraction, resulting in the phase-locked loop being unable to correctly detect the voltage phase. However, the three-phase mixed connection will not change the rotation direction of the dq axis. Therefore, in the embodiments of the present application, there is no need to judge the specific mixed connection situation. When the output voltage synthesis vector is greater than the preset amplitude U r , make the target feedforward adaptive value Q and the initial feedforward adaptive value Q0 satisfy:

[0098] Q = -Q0

[0099] Since the two-phase mixed connection makes the initial feedforward adaptive value produce a counteraction, the feedforward adaptive value is changed to the opposite of the original, replacing the initial feedforward adaptive value and inputting it into the phase-locked loop to achieve automatic voltage build-up.

[0100] Therefore, in the above embodiment, the target feedforward adaptive value satisfies:

[0101] Q = -2πf

[0102] where Q represents the target feedforward adaptive value, and f represents the grid-side frequency of the grid-connected inverter.

[0103] Embodiment

[0104] Figure 6 Shows the voltage build-up result of the phase sequence adaptive control method provided in this embodiment under the grid phase voltage of 700V and the grid frequency f = 50Hz. Refer to Figure 6 , Figure 6 The above figure shows the voltage build-up process without using the phase sequence adaptive control method provided in the embodiment of the present application. Figure 6 The following figure shows the voltage build-up process using the phase sequence adaptive control method provided in the embodiment of the present application. It can be seen that when the phase sequence adaptive control method provided in the embodiment of the present application is not used, the voltage build-up is severely affected by wiring faults, and even surge voltages occur, which easily lead to circuit damage. After using the phase sequence adaptive control method provided in the embodiment of the present application, the system can quickly respond within a short time, automatically complete fault handling, the system performs normal voltage build-up, and the voltage fluctuation is small, ensuring the stability of the system.

[0105] As described above in conjunction with Figures 1 to 6 , the phase sequence adaptive control method provided in the embodiment of the present invention has been described in detail. This method can also be implemented by a corresponding device. Next, the phase sequence adaptive control device provided in the embodiment of the present invention will be described in detail in conjunction with Figures 7 - 12 .

[0106] Figure 7 Shows a schematic diagram of the phase sequence adaptive control device provided in an embodiment of the present application. As Figure 7 shown, the phase sequence adaptive control device includes:

[0107] Instruction calculation module 100. As Figure 8 shown, the instruction calculation module 100 includes: a current instruction calculation module 110, configured to obtain a quadrature axis current instruction value and a direct axis current instruction value based on a given voltage and a load system feedback voltage; a voltage instruction calculation module 120, configured to obtain a quadrature axis voltage instruction and a direct axis voltage instruction based on the quadrature axis current instruction value, the quadrature axis current feedback value, the direct axis current instruction value, and the direct axis current feedback value;

[0108] Phase sequence adjustment module 200. As Figure 9 shown, the phase sequence adjustment module 200 includes: a phase calculation module 210, configured to obtain a phase difference based on the line voltage of the grid-connected inverter and the feedforward adaptive value; a feedback calculation module 220, configured to obtain a quadrature axis current feedback value and a direct axis current feedback value based on the phase current of the grid-connected inverter and the phase difference; an output voltage vector synthesis module 230, configured to obtain a voltage synthesis vector based on the quadrature axis voltage instruction, the direct axis voltage instruction, and the phase difference;

[0109] Determination module 240, configured to determine whether the maximum amplitude of the voltage synthesis vector is greater than a preset amplitude,

[0110] If not, obtain the target feedforward adaptive value;

[0111] If so, adjust the initial feedforward adaptive value until the maximum amplitude of the voltage synthesis vector is not greater than the preset amplitude.

[0112] In an alternative embodiment, as Figure 10 shown, the phase calculation module 210 includes:

[0113] A line-to-phase conversion module 211, configured to obtain three-phase voltages based on the line voltages of the grid-connected inverter;

[0114] A first coordinate transformation module 212, configured to obtain the quadrature-axis voltage of the phase-locked loop based on the three-phase voltages;

[0115] A phase difference output module 213, configured to obtain a phase difference based on the quadrature-axis voltage of the phase-locked loop and the feedforward adaptive value.

[0116] In an alternative embodiment, as Figure 11 shown, the feedback calculation module 220 includes:

[0117] A second coordinate transformation module 221, configured to obtain an α-axis current feedback value and a β-axis current feedback value based on the phase currents;

[0118] A third coordinate transformation module 222, configured to obtain a quadrature-axis current feedback value and a direct-axis current feedback value based on the α-axis current feedback value, the β-axis current feedback value, and the phase difference.

[0119] In an alternative embodiment, as Figure 12 shown, the output voltage vector synthesis module 230 includes:

[0120] A fourth coordinate transformation module 231, configured to obtain an α-axis voltage command and a β-axis voltage command based on the quadrature-axis voltage command, the direct-axis voltage command, and the phase difference;

[0121] A vector synthesis module 232, configured to obtain a voltage synthesis vector based on the α-axis voltage command and the β-axis voltage command.

[0122] In addition, an embodiment of the present invention further provides an electronic device, including a bus, a transceiver, a memory, a processor, and a computer program stored in the memory and executable on the processor. The transceiver, the memory, and the processor are respectively connected through the bus. When the computer program is executed by the processor, it implements each process of the above-mentioned embodiment of the grid-connected inverter phase sequence adaptive control method and can achieve the same technical effect. To avoid repetition, it will not be elaborated here.

[0123] Specifically, refer to Figure 13As shown in the figure, an embodiment of the present invention further provides an electronic device, which includes a bus 1110, a processor 1120, a transceiver 1130, a bus interface 1140, a memory 1150, and a user interface 1160.

[0124] In an embodiment of the present invention, the electronic device further includes: a computer program stored on the memory 1150 and executable on the processor 1120. When the computer program is executed by the processor 1120, the following steps are implemented:

[0125] Obtain a quadrature-axis current command value and a direct-axis current command value based on a given voltage and a load system feedback voltage;

[0126] Obtain a phase difference based on the line voltage of the grid-connected inverter and an initial feedforward adaptive value;

[0127] Obtain a quadrature-axis current feedback value and a direct-axis current feedback value based on the phase current of the grid-connected inverter and the phase difference;

[0128] Obtain a quadrature-axis voltage command and a direct-axis voltage command based on the quadrature-axis current command value, the quadrature-axis current feedback value, the direct-axis current command value, and the direct-axis current feedback value;

[0129] Obtain a voltage synthesis vector based on the quadrature-axis voltage command, the direct-axis voltage command, and the phase difference;

[0130] Judge whether the maximum amplitude of the voltage synthesis vector is greater than a preset amplitude:

[0131] If not, obtain a target feedforward adaptive value;

[0132] If so, adjust the initial feedforward adaptive value until the maximum amplitude of the voltage synthesis vector is not greater than the preset amplitude.

[0133] Optionally, when the computer program is executed by the processor 1120, the processor further specifically implements the following steps: Obtaining a phase difference based on the line voltage and the feedforward adaptive value includes:

[0134] Obtain three-phase voltages based on the line voltage of the grid-connected inverter;

[0135] Obtain a quadrature-axis voltage of the phase-locked loop based on the three-phase voltages;

[0136] Obtain a phase difference based on the quadrature-axis voltage of the phase-locked loop and the feedforward adaptive value.

[0137] Optionally, when the computer program is executed by the processor 1120, the processor further specifically implements the following steps: Obtaining a voltage synthesis vector based on the quadrature-axis voltage command, the direct-axis voltage command, and the phase difference includes:

[0138] Obtain an α-axis voltage command and a β-axis voltage command based on the quadrature-axis voltage command, the direct-axis voltage command, and the phase difference;

[0139] Obtain a voltage synthesis vector based on the axis voltage command and the β-axis voltage command.

[0140] A transceiver 1130, configured to receive and send data under the control of the processor 1120.

[0141] In an embodiment of the present invention, a bus architecture (represented by bus 1110), the bus 1110 may include any number of interconnected buses and bridges, and the bus 1110 connects various circuits including one or more processors represented by the processor 1120 and a memory represented by the memory 1150 together.

[0142] The bus 1110 represents one or more of any of several types of bus structures, including a memory bus and a memory controller, a peripheral bus, an Accelerate Graphical Port (AGP), a processor, or a local bus using any bus structure in various bus architectures. By way of example and not limitation, such architectures include: Industry Standard Architecture (ISA) bus, Micro Channel Architecture (MCA) bus, Extended ISA (EISA) bus, Video Electronics Standards Association (VESA), Peripheral Component Interconnect (PCI) bus.

[0143] The processor 1120 may be an integrated circuit chip with signal processing capabilities. In implementation, the steps of the above method embodiments may be completed by the integrated logic circuit in hardware or instructions in software form in the processor. The above-mentioned processor includes: general-purpose processor, central processing unit (CPU), network processor (NP), digital signal processor (DSP), application specific integrated circuit (ASIC), field programmable gate array (FPGA), complex programmable logic device (CPLD), programmable logic array (PLA), microcontroller unit (MCU), or other programmable logic devices, discrete gates, transistor logic devices, discrete hardware components. It can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of the present invention. For example, the processor may be a single-core processor or a multi-core processor, and the processor may be integrated on a single chip or located on multiple different chips.

[0144] The processor 1120 may be a microprocessor or any conventional processor. The method steps disclosed in combination with the embodiments of the present invention may be directly executed and completed by a hardware decoding processor, or executed and completed by a combination of hardware and software modules in the decoding processor. The software module may be located in a readable storage medium well known in the art such as random access memory (RAM), flash memory, read-only memory (ROM), programmable ROM (PROM), erasable programmable ROM (EPROM), registers, etc. The readable storage medium is located in the memory, and the processor reads the information in the memory and combines its hardware to complete the steps of the above method.

[0145] A memory or other memory technology, a compact disc read-only memory (CD-ROM), a digital versatile disc (DVD) or other optical storage, a magnetic cassette tape storage, a magnetic disk storage or other magnetic storage device, a memory stick, a mechanical encoding device (such as a punched card or a raised structure in a groove on which instructions are recorded), or any other non-transmission medium can be used to store information that can be accessed by a computing device. As defined in the embodiments of the present invention, a computer-readable storage medium does not include transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (such as light pulses passing through an optical fiber cable), or electrical signals transmitted through wires.

[0146] In several embodiments provided in this application, it should be understood that the disclosed devices, electronic devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of modules or units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Additionally, the shown or discussed couplings or direct couplings or communication connections to each other can be indirect couplings or communication connections through some interfaces, devices, or units, and can also be in the form of electrical, mechanical, or other connections.

[0147] The units described as separate components may or may not be physically separated. The components shown as units may or may not be physical units. They can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to solve the problems to be solved by the solution of the embodiments of the present invention.

[0148] In addition, in each embodiment of the present invention, the functional units can be integrated in one processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. The above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.

[0149] When the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiments of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (including a personal computer, a server, a data center, or other network devices) to execute all or part of the steps of the methods described in the various embodiments of the present invention. And the above storage medium includes various media that can store program codes as enumerated above.

[0150] The bus 1110 can also connect together various other circuits, such as peripheral devices, voltage regulators, or power management circuits. The bus interface 1140 provides an interface between the bus 1110 and the transceiver 1130, which are all well known in the art. Therefore, the embodiments of the present invention will not further describe them.

[0151] The transceiver 1130 can be a component or multiple components, such as multiple receivers and transmitters, providing a unit for communicating with various other devices on the transmission medium. For example: the transceiver 1130 receives external data from other devices, and the transceiver 1130 is used to send the data processed by the processor 1120 to other devices. Depending on the nature of the computer system, a user interface 1160 can also be provided, such as: a touch screen, a physical keyboard, a display, a mouse, a speaker, a microphone, a trackball, a joystick, a stylus.

[0152] It should be understood that in the embodiments of the present invention, the memory 1150 may further include a memory remotely disposed relative to the processor 1120, and these remotely disposed memories can be connected to the server through a network. One or more parts of the above-mentioned network can be an ad hoc network, an intranet, an extranet, a virtual private network (VPN), a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a wireless wide area network (WWAN), a metropolitan area network (MAN), the Internet, a public switched telephone network (PSTN), a plain old telephone service network (POTS), a cellular telephone network, a wireless network, a wireless fidelity (Wi-Fi) network, and a combination of two or more of the above networks. For example, the cellular telephone network and the wireless network can be a Global System for Mobile Communications (GSM) system, a Code Division Multiple Access (CDMA) system, a Worldwide Interoperability for Microwave Access (WiMAX) system, a General Packet Radio Service (GPRS) system, a Wideband Code Division Multiple Access (WCDMA) system, a Long Term Evolution (LTE) system, an LTE Frequency Division Duplex (FDD) system, an LTE Time Division Duplex (TDD) system, an Advanced Long Term Evolution (LTE-A) system, a Universal Mobile Telecommunications System (UMTS) system, an Enhance Mobile Broadband (eMBB) system, a massive Machine Type of Communication (mMTC) system, an UltraReliable Low Latency Communications (uRLLC) system, etc.

[0153] It should be understood that the memory 1150 in the embodiments of the present invention can be a volatile memory or a non-volatile memory, or can include both a volatile memory and a non-volatile memory. Among them, the non-volatile memory includes: Read-Only Memory (ROM), Programmable ROM (PROM), Erasable PROM (EPROM), Electrically Erasable PROM (EEPROM), or Flash Memory.

[0154] The volatile memory includes: a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as: static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchlink dynamic random access memory (SLDRAM), and direct rambus random access memory (DRRAM). The memory 1150 of the electronic device described in the embodiments of the present invention includes but is not limited to the above and any other suitable types of memory.

[0155] In the embodiments of the present invention, the memory 1150 stores the following elements of the operating system 1151 and the application program 1152: executable modules, data structures, or subsets or extended sets thereof.

[0156] Specifically, the operating system 1151 includes various system programs, such as: a framework layer, a core library layer, a driver layer, etc., for implementing various basic services and processing hardware-based tasks. The application program 1152 includes various application programs, such as: a media player and a browser, for implementing various application services. The program for implementing the method of the embodiments of the present invention may be included in the application program 1152. The application program 1152 includes: applets, objects, components, logics, data structures, and other computer system executable instructions for performing specific tasks or implementing specific abstract data types.

[0157] In addition, the embodiments of the present invention also provide a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it implements each process of the above-described embodiment of the grid-connected inverter phase sequence adaptive control method and can achieve the same technical effect. To avoid repetition, it will not be elaborated here.

[0158] A computer-readable storage medium includes: permanent and non-permanent, removable and non-removable media, which are tangible devices that can retain and store instructions for use by an instruction execution device. The computer-readable storage medium includes: electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, and any suitable combination thereof. The computer-readable storage medium includes: phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), non-volatile random access memory (NVRAM), electrically erasable programmable read-only memory (EEPROM), flash memory

[0159] As described above, the above is only the specific implementation manner of the embodiments of the present invention, but the protection scope of the embodiments of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the embodiments of the present invention can easily think of changes or substitutions, which should all be covered within the protection scope of the embodiments of the present invention. Therefore, the protection scope of the embodiments of the present invention should be subject to the protection scope of the claims.

Claims

1. A grid-connected inverter phase sequence adaptive control method, characterized in that: The following steps are involved: Acquire a quadrature-axis current command value and a direct-axis current command value based on a given voltage and a load system feedback voltage; Acquiring a three-phase voltage based on a line voltage of the grid-connected inverter; Acquire a phase-locked loop quadrature-axis voltage based on the three-phase voltage; Acquire a phase difference based on the phase-locked loop quadrature-axis voltage and a feedforward adaptive value; Acquire a quadrature-axis current feedback value and a direct-axis current feedback value based on the phase current of the grid-connected inverter and the phase difference; Acquire a quadrature-axis voltage command and a direct-axis voltage command based on the quadrature-axis current command value, the quadrature-axis current feedback value, the direct-axis current command value, and the direct-axis current feedback value; Acquire a voltage synthesis vector based on the quadrature-axis voltage command, the direct-axis voltage command and the phase difference; Determine whether the maximum amplitude of the voltage synthesis vector is greater than a preset amplitude: If not, the target feedforward adaptive value is obtained; If so, the initial feedforward adaptive value is adjusted until the maximum amplitude of the voltage synthesis vector is no greater than the preset amplitude.

2. The grid-connected inverter phase sequence adaptive control method according to claim 1, characterized in that: The acquiring of a voltage synthesis vector based on the quadrature-axis voltage command, the direct-axis voltage command and the phase difference comprises: acquiring an α-axis voltage command and a β-axis voltage command based on the quadrature-axis voltage command, the direct-axis voltage command, and the phase difference; The voltage synthesis vector is obtained based on the α-axis voltage command and the β-axis voltage command.

3. The grid-connected inverter phase sequence adaptive control method according to claim 2, characterized in that: The voltage synthesis vector satisfies: Wherein, A represents the voltage synthesis vector, u α represents the α-axis voltage command, u β represents the β-axis voltage command.

4. The grid-connected inverter phase sequence adaptive control method according to claim 1, characterized in that: The preset amplitude satisfies: U T =1.1U m Among them, U T represents the preset amplitude, U m Represents the grid phase voltage of the grid-connected inverter.

5. The grid-connected inverter phase sequence adaptive control method according to claim 1, characterized in that: The initial feedforward adaptive value satisfies: Q0=2πf Wherein, Q0 represents the initial feedforward adaptive value, and f represents the grid-side frequency of the grid-connected inverter.

6. The grid-connected inverter phase sequence adaptive control method according to claim 5, characterized in that: The target feedforward adaptive value satisfies: Q=-2πf Wherein, Q represents the target feedforward adaptive value, and f represents the grid-side frequency of the grid-connected inverter.

7. A phase sequence adaptive control device, characterized in that: The method for adaptively controlling phase sequence of a grid-connected inverter applied to any one of claims 1 to 6, the device comprising: The command calculation module (100) includes a current command calculation module (110) configured to obtain a quadrature-axis current command value and a direct-axis current command value based on a given voltage and a load system feedback voltage; The phase sequence adjustment module (200) comprises: The phase calculation module (210) comprises: A line-phase conversion module (211) is configured to obtain a three-phase voltage based on a line voltage of the grid-connected inverter; A first coordinate transformation module (212) is configured to obtain a phase-locked loop quadrature-axis voltage based on the three-phase voltage; A phase difference output module (213) is configured to obtain a phase difference based on the phase-locked loop quadrature-axis voltage and a feedforward adaptive value; A feedback calculation module (220) is configured to obtain a quadrature-axis current feedback value and a direct-axis current feedback value based on the phase current of the grid-connected inverter and the phase difference; The command calculation module (100) further comprises a voltage command calculation module (120) configured to obtain a quadrature-axis voltage command and a direct-axis voltage command based on the quadrature-axis current command value, the quadrature-axis current feedback value, the direct-axis current command value, and the direct-axis current feedback value; The phase sequence adjustment module (200) further comprises an output voltage vector synthesis module (230) configured to obtain a voltage synthesis vector based on the quadrature-axis voltage command, the direct-axis voltage command and the phase difference; A determination module (240) is configured to determine whether the maximum amplitude of the voltage synthesis vector is greater than a preset amplitude, If not, the target feedforward adaptive value is obtained; If so, the initial feedforward adaptive value is adjusted until the maximum amplitude of the voltage synthesis vector is no greater than the preset amplitude.

8. The phase sequence adaptive control device according to claim 7, characterized in that: The feedback calculation module (220) comprises: A second coordinate transformation module (221) is configured to obtain an α-axis current feedback value and a β-axis current feedback value based on the phase current; The third coordinate transformation module (222) is configured to obtain a quadrature-axis current feedback value and a direct-axis current feedback value based on the α-axis current feedback value, the β-axis current feedback value and the phase difference.

9. The phase sequence adaptive control device according to claim 7, characterized in that: The output voltage vector synthesis module (230) comprises: A fourth coordinate transformation module (231) is configured to obtain an α-axis voltage command and a β-axis voltage command based on the quadrature-axis voltage command, the direct-axis voltage command and the phase difference; A vector synthesis module (232) is configured to obtain the voltage synthesis vector based on the α-axis voltage command and the β-axis voltage command.

10. An electronic device, comprising a bus, a transceiver, a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the transceiver, the memory, and the processor are connected via the bus, and when the computer program is executed by the processor, the grid-connected inverter phase sequence adaptive control method according to any one of claims 1 to 6 is implemented.

11. A computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the grid-connected inverter phase sequence adaptive control method according to any one of claims 1 to 6.

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