Voltage conversion circuit

Abstract

The present invention provides a voltage conversion circuit. The voltage conversion circuit includes a plurality of voltage converters, a feedback circuit, and a interleaving controller. The voltage converters are connected in parallel with each other and respectively generate an output voltage according to a plurality of control signals. The feedback circuit is coupled to the voltage converters. The feedback circuit generates a plurality of feedback signals according to a switching voltage on a power switch of each of the voltage converters and an error voltage between the output voltage and a first reference voltage. The interleaving controller is coupled between the feedback circuit and the voltage converters. The interleaving controller includes a plurality of phase-locked loops respectively corresponding to the voltage converters. The interleaving controller generates a plurality of control signals by a phase-locking mechanism respectively according to the feedback signals and a zero-crossing detection state of the power switches of the voltage converters.

Description

Technical Field

[0001] The present invention relates to a voltage conversion circuit, and more particularly to a voltage conversion circuit with a quasi-interleave mechanism that can operate in a multi-phase discontinuous conduction mode (DCM). Background Art

[0002] In the existing technical field, a voltage conversion circuit can be implemented through a pulse distribution architecture or a phase-locked loop architecture. The voltage conversion circuit implemented through the pulse distribution architecture has a high noise sensitivity and a relatively low response rate. The voltage conversion circuit implemented through the phase-locked loop architecture of the prior art has a relatively low noise sensitivity and a relatively fast response rate, but has a relatively complex circuit architecture. Moreover, the voltage conversion circuit implemented with the phase-locked loop architecture can only achieve the interleaving function in the continuous conduction mode (CCM), which cannot meet the application requirements. Summary of the Invention

[0003] The present invention is directed to a voltage conversion circuit that can operate in a quasi-interleave state based on a phase-locking mechanism.

[0004] According to an embodiment of the present invention, a voltage conversion circuit includes a plurality of voltage converters, a feedback circuit, and an interleaving controller. The voltage converters are connected in parallel and respectively generate an output voltage according to a plurality of control signals. The feedback circuit is coupled to the voltage converters. The feedback circuit generates a plurality of feedback signals according to the switching voltage on the power switch of each of the voltage converters and the error voltage between the output voltage and a first reference voltage. The interleaving controller is coupled between the feedback circuit and the voltage converters. The interleaving controller includes a plurality of phase-locked loops respectively corresponding to the plurality of voltage converters. The interleaving controller turns on or off the phase-locking mechanism according to the zero-crossing detection state of the power switch, and respectively generates a plurality of control signals according to the plurality of feedback signals and the zero-crossing detection state. Brief Description of the Drawings

[0005] Figure 1 It is a schematic diagram of the voltage conversion circuit according to an embodiment of the present invention.

[0006] Figure 2 It is a schematic diagram of an implementation manner of the feedback circuit in the voltage conversion circuit according to an embodiment of the present invention.

[0007] Figure 3 It is a schematic diagram of an implementation manner of the interleaving controller in the voltage conversion circuit according to an embodiment of the present invention.

[0008] Figure 4 Schematic diagram of the implementation of the core circuit according to an embodiment of the present invention.

[0009] Figure 5 Waveform diagram of the core circuit according to an embodiment of the present invention.

[0010] Figure 6A And Figure 6B Waveform diagrams of the switching voltage, inductor current, and output voltage of the voltage conversion circuit according to an embodiment of the present invention under different loads. Detailed implementation

[0011] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0012] Please refer to Figure 1 , Figure 1 Schematic diagram of a voltage conversion circuit according to an embodiment of the present invention. The voltage conversion circuit 100 includes a plurality of voltage converters 111, 112, a feedback circuit 120, and an interleaving controller 130. The voltage converters 111 and 112 are coupled in parallel between the input and output terminals of the voltage conversion circuit. Among them, the output terminals of the voltage converter 111 and the voltage converter 112 are coupled to each other. The voltage converters 111 and 112 both receive the input voltage VINA and perform voltage conversion operations on the input voltage VINA according to the control signals PWMA and PWMB respectively, and jointly generate the output voltage Vout at their mutually coupled output terminals.

[0013] In this embodiment, the voltage converter 111 includes power switches T1 and T2. The first ends of the power switches T1 and T2 are both coupled to the inductor LA. The second end of the power switch T1 receives the input voltage VINA, and the second end of the power switch T2 is grounded. The control ends of the power switches T1 and T2 are both coupled to the driver 1111, and are switched on / off by receiving the driving signals provided by the driver 1111 to generate a switching voltage SWA at the end coupled to the inductor LA. The power switches T1 and T2 are alternately turned on and off under the control of the driving signals to perform voltage conversion on the input voltage VINA, and a first part of the output voltage Vout is generated at the output terminal of the voltage converter 111 through the inductor LA as an energy storage component. Here, the driver 1111 receives the control signal PWMA from the interleaving controller 130 and provides driving signals to the power switches T1 and T2 according to the control signal PWMA.

[0014] Similarly, the voltage converter 112 includes power switches T3 and T4. The first ends of the power switches T3 and T4 are both coupled to the inductor LB. The second end of the power switch T3 receives the input voltage VINA, and the second end of the power switch T4 is grounded. The control ends of the power switches T3 and T4 are both coupled to the driver 1121, and are switched on / off by receiving the driving signals provided by the driver 1121 to generate a switching voltage SWB at the end point coupled to the inductor LB. Through an operation similar to that of the voltage converter 111, the voltage converter 112 can generate a second part of the output voltage Vout at the output end. Here, the driver 1121 receives the control signal PWMB from the interleaved controller 130 and provides driving signals to the power switches T3 and T4 according to the control signal PWMB.

[0015] It is worth mentioning that the control signals PWMA and PWMB are both Pulse Width Modulation (PWM) signals, and there may be a certain phase difference between the two. Through the control signals PWMA and PWMB with a phase difference, the voltage converters 111 and 112 can operate in a quasi-interleaved mechanism.

[0016] In this embodiment, the voltage converters 111 and 112 can be buck converters.

[0017] In this embodiment, the voltage conversion circuit 100 further includes current sensors CS1 and CS2. The current sensor CS1 can be coupled to the first end of the power switch T2 and is used to sense the current on the power switch T2 and generate current information CSA. Further, the current sensor CS1 can obtain the zero-crossing detection state at the first end of the power switch T2 according to the current information CSA, and further obtain the mode information DCMA about the DCM mode of the voltage converter 111. Similarly, the current sensor CS2 can be coupled to the first end of the power switch T4 and is used to sense the current on the power switch T4 and generate current information CSB. Further, the current sensor CS2 can obtain the zero-crossing detection state at the first end of the power switch T4 according to the current information CSB, and obtain the mode information DCMB about the DCM mode of the voltage converter 112. Among them, the mode information DCMA and DCMB can be digital signals, and the presence or absence of the zero-crossing detection state of the power switches T2 and T4 can be represented by their logical values.

[0018] The feedback circuit 120 is coupled to the voltage converters 111, 112 and the interleaved controller 130. The feedback circuit 120 can receive the output voltage Vout and the switching voltages SWA and SWB. The feedback circuit 120 detects the error between the output voltage Vout and a reference voltage Vref and generates an error voltage. The feedback circuit 120 generates a feedback signal FBA based on the error voltage and the switching voltage SWA, and generates a feedback signal FBB based on the error voltage and the switching voltage SWB.

[0019] The interleaved controller 130 is coupled to the feedback circuit 120 and the voltage converters 111, 112. The interleaved controller 120 includes two phase-locked loops ( Figure 1 not shown in the figure) corresponding to the voltage converters 111, 112 respectively. The interleaved controller 130 can determine whether to activate the phase-locking mechanism of the phase-locked loop according to the mode information DCMA and DCMB. Among them, in the discontinuous conduction mode, the phase-locking mechanism of the phase-locked loop is turned off. At this time, the interleaved controller 130 can generate control signals PWMA and PWMB according to the feedback signals FBA, FBB and the mode information DCMA and DCMB, and use them to control the voltage conversion of the voltage converters 111, 112. In this embodiment, the interleaved controller 130 can ensure that the voltage converters 111, 112 can stably operate in the discontinuous conduction state by expanding the width of the positive pulse wave of the control signals PWMA and PWMB based on the hysteresis mechanism.

[0020] On the other hand, if in the continuous conduction mode (CCM), the interleaved controller 120 can activate the phase-locked loop therein. In this way, the interleaved controller 130 can generate control signals PWMA and PWMB based on the phase-locking mechanism of the phase-locked loop.

[0021] Please refer to Figure 2 , Figure 2 which is a schematic diagram of an implementation manner of the feedback circuit in the voltage conversion circuit according to an embodiment of the present invention. The feedback circuit 200 can be used to implement Figure 1Feedback circuit 120. Feedback circuit 200 includes an error voltage generator 210, signal processing circuits 221, 222, signal adders 231, 232, and comparators 241, 242. The error voltage generator 210 includes an error amplifier EA, resistors R3, R4, and a capacitor C3. The positive input terminal of the error amplifier EA receives a reference voltage VREF, and the negative input terminal of the error amplifier EA receives the output voltage Vout of the voltage conversion circuit. The resistor R3 and the capacitor C3 are serially coupled between the output terminal of the error amplifier EA and the reference ground terminal GND, wherein an error voltage VEA- is generated at the output terminal of the error amplifier EA. In addition, one end of the resistor R3 is coupled to the output terminal of the error amplifier EA, and an error voltage VEA+ is generated at the other end of the resistor R3. Among them, the error voltage VEA- is provided to the first positive input terminal of the signal adder 231 and the first positive input terminal of the signal adder 232, and the error voltage VEA+ is provided to the first negative input terminal of the signal adder 231 and the first negative input terminal of the signal adder 232.

[0022] The signal processing circuit 221 includes a resistor R1, a capacitor C1, a DC signal extractor (RC extractor) 2211, and a signal amplifier 2212. One end of the resistor R1 receives a switching voltage SWA on the voltage converter 111, and the other end of the resistor R1 is coupled to the first end of the capacitor C1, the DC signal extractor 2211, and the signal amplifier 2212. The second end of the capacitor C1 is coupled to the reference ground terminal GND. The DC signal extractor 2211 is coupled between the resistor R1 and the signal amplifier 2212, and the DC signal extractor 2211 is used to extract the DC component VP_DC1 of the switching voltage SWA. The signal amplifier 2212 receives the AC component VP_AC1 of the switching voltage SWA through the resistor R1 and receives the DC component VP_DC1 of the switching voltage SWA output by the signal extractor 2211. The signal amplifier 2212 amplifies the above DC component VP_DC1 and AC component VP_AC1 according to a gain K to respectively generate a ramp voltage VRMP1+ and a ramp voltage VRMP1-. The signal processing circuit 221 respectively outputs the ramp voltage VRMP1+ and the ramp voltage VRMP1- to the second negative input terminal and the second positive input terminal of the signal adder 231.

[0023] Similar to the signal processing circuit 221, the signal processing circuit 222 includes a resistor R2, a capacitor C2, a DC signal extractor 2221, and a signal amplifier 2222. One end of the resistor R2 receives the switching voltage SWB on the voltage converter 112, and the other end of the resistor R2 is coupled to the first end of the capacitor C2. The second end of the capacitor C2 is coupled to the reference ground terminal GND. The DC signal extractor 2221 is used to extract the DC component VP_DC2 of the switching voltage SWB. The signal amplifier 2212 receives the AC component VP_AC2 and the DC component VP_DC2 of the switching voltage SWB. The signal amplifier 2222 amplifies the DC component VP_DC2 and the AC component VP_AC2 according to the gain K to generate a ramp voltage VRMP2+ and a ramp voltage VRMP2- respectively. The signal processing circuit 222 outputs the ramp voltage VRMP2+ and the ramp voltage VRMP2- to the second negative input terminal and the second positive input terminal of the signal adder 232 respectively.

[0024] The signal adders 231 and 232 further include a third positive input terminal for receiving a reference voltage VREF and a third negative input terminal for receiving the output voltage Vout of the voltage conversion circuit. The signal adder 231 adds the signals received at its first, second, and third positive input terminals, and generates a comparison voltage VCP1 at its positive output terminal according to the added result. The signal adder 231 also adds the signals received at its first, second, and third negative input terminals, and generates a comparison voltage VCP2 at its negative output terminal according to the added result. The signal adder 232 adds the signals received at its first, second, and third positive input terminals, and generates a comparison voltage VCP3 at its positive output terminal according to the added result. The signal adder 232 also adds the signals received at its first, second, and third negative input terminals, and generates a comparison voltage VCP4 at its negative output terminal according to the added result.

[0025] The comparator 241 receives the comparison voltages VCP1 and VCP2, and generates a feedback signal FBA by comparing the comparison voltage VCP1 with the VCP2. The comparator 242 receives the comparison voltages VCP3 and VCP4, and generates a feedback signal FBB by comparing the comparison voltage VCP3 with the VCP4. In this embodiment, the comparators 241 and 242 can be hysteresis comparators.

[0026] In this embodiment, the circuit architectures of the DC signal extractors 2211 and 2221, the signal amplifiers 2212 and 2222, the signal adders 231 and 232, and the comparators 241 and 242 can all be implemented by using relevant circuits well-known to those of ordinary skill in the art, without specific limitations.

[0027] Please refer to Figure 3 , Figure 3Schematic diagram of an embodiment of the interleaved controller 300 in the voltage conversion circuit according to an embodiment of the present invention. Among them Figure 1 The interleaved controller 130 in the embodiment can be implemented by applying the interleaved controller 300. The interleaved controller 300 includes a core circuit 310, logic circuits 321, 322, phase-locked loops (PLLs) 331, 332, and pulse generators PG1 to PG4. The core circuit 310 receives control signals PWMA, PWMB, and mode information DCMA, DCMB, and generates a channel enable signal ONCH1 according to the control signal PWMA and the mode information DCMA, and generates a channel enable signal ONCH2 according to the control signal PWMB and the mode information DCMB. The channel enable signals ONCH1, ONCH2 are respectively provided to the logic circuits 321, 322.

[0028] The logic circuits 321, 322 also respectively receive feedback signals FBA, FBB generated by the feedback circuit 200. The logic circuit 321 includes a NAND gate ND1, a NOR gate NO1, and a latch LA1. The NAND gate ND1 receives the channel enable signal ONCH1 and the feedback signal FBA, and the NOR gate NO1 receives the output signal of the NAND gate ND1 and the pulse wave PS2 generated by the pulse generator PG2. The output of the NOR gate NO1 is coupled to the set terminal S of the latch LA1. In addition, the reset terminal R of the latch LA1 receives the pulse wave PS1 generated by the pulse generator PG1. The output terminal Q of the latch LA1 generates a control signal PWMA, and outputs the control signal PWMA to the pulse generators PG1, PG2, and the phase-locked loop 331.

[0029] In addition, the phase-locked loop 331 receives the mode information DCMA, the control signal PWMA, and the clock signal CK1. Among them, the mode information DCMA is used to control the start or stop of the phase-locked loop 311. When the mode information DCMA indicates that the voltage conversion circuit operates in the DCM mode, the phase-locked loop 331 can be turned off; correspondingly, when the mode information DCMA indicates that the voltage conversion circuit operates in the CCM mode, the phase-locked loop 331 can be started. The phase-locked loop 331 outputs an adjustment signal ADJ1 to the pulse generator PG1. The pulse generator PG1 can generate the pulse wave PS1 according to the mode information DCMA, the control signal PWMA, and the adjustment signal ADJ1, and the pulse generator PG2 can generate the corresponding pulse wave PS2 according to the control signal PWMA.

[0030] In this embodiment, the pulse generator PG1 is a delay unit. When the control signal PWMA is at a logic value of 1, the pulse generator PG1 can start timing and pull down the pulse wave PS1. When the pulse generator PG1 finishes timing, it pulls up the pulse wave PS1 and sets the control signal PWMA to a logic value of 0. For the pulse generator PG2, when the control signal PWMA is at a logic value of 1, the pulse generator PG2 starts timing and pulls up the pulse wave PS2. When the pulse generator PG2 finishes timing, it pulls down the pulse wave PS2 to form a minimum off-time control. Meanwhile, the control signal PWMA can be sent to the phase-locked loop 331. The phase-locked loop 331 compares the phase difference between the control signal PWMA and the clock signal CK1 and adjusts the delay of PG1 to achieve the stability of the voltage conversion frequency in the CCM mode.

[0031] The logic circuit 322 includes a NAND gate ND2, a NOR gate NO2, and a latch LA2. The NAND gate ND2 receives the channel enable signal ONCH2 and the feedback signal FBB. The NOR gate NO2 receives the output signal generated by the NAND gate ND2 and the pulse wave PS4 generated by the pulse generator PG4. The output terminal of the NOR gate NO2 is coupled to the set terminal S of the latch LA2. In addition, the reset terminal R of the latch LA2 receives the pulse wave PS3 generated by the pulse generator PG3. The output terminal Q of the latch LA2 generates the control signal PWMB and outputs the control signal PWMB to the pulse generators PG3, PG4, and the phase-locked loop 332. The phase-locked loop 332 receives the mode information DCMB, the control signal PWMB, and the clock signal CK3, and outputs an adjustment signal ADJ3 to the pulse generator PG3. The mode information DCMB is used to control the startup or shutdown of the phase-locked loop 332. The operation modes of the logic circuit 322, the phase-locked loop 332, the pulse generators PG3, PG4 are similar to those of the aforementioned logic circuit 321, the phase-locked loop 331, the pulse generators PG1, PG2, and will not be elaborated here. Through the phase-locked loops 331, 332, in the CCM mode, the control signals PWMA and PWMB respectively generated by the latches LA1 and LA2 can be interleaved with each other.

[0032] Incidentally, the latches LA1 and LA2 are both SR-type latches.

[0033] Figure 4 Shows Figure 3 a schematic diagram of an embodiment of the core circuit in Figure 4Among them, the core circuit includes signal delayers 411 and 412, single-shot circuits 421 and 422, latch LA4, and logic circuit 430. The signal delayer 411 receives the control signal PWMA to adjust the width of the signal SG1 according to the set delay time. The above-mentioned set delay time can be greater than half of the operating cycle of the voltage conversion circuit. The signal delayer 411 includes latch LA31, switch SW41, capacitor C41, current source I1, operational amplifier OP41, and inverter IV41. The set terminal S of the latch LA31 receives the control signal PWMA, and the reset terminal R of the latch LA31 receives the signal output by the inverter IV41. The inverted output terminal QB of the latch LA31 generates the signal SG1. The switch SW41 is connected in parallel with the capacitor C41. The parallel-connected switch SW41 and capacitor C41 are then connected in series with the current source I1 between the power supply voltage Vdd and the reference ground terminal GND. The end point where the capacitor C41 is coupled to the current source I1 is coupled to the negative input terminal of the operational amplifier OP41. The positive input terminal of the operational amplifier OP41 receives the reference voltage VR1. The output terminal of the operational amplifier OP41 is coupled to the input terminal of the inverter IV41.

[0034] The operational amplifier OP41 can generate an output voltage with a high voltage value in the initial state. During the period when the switch SW41 is turned off, the current source I1 can charge the capacitor C41. At this time, the negative input terminal of the operational amplifier OP41 receives a ramp voltage. When the ramp voltage rises above the reference voltage VR1, the output voltage generated by the operational amplifier OP41 can change to a low voltage value. During the period when the switch SW41 is turned on, the current source I1 does not charge the capacitor C41, and the capacitor C41 can be discharged through the switch SW41, causing the ramp voltage on the negative input terminal of the operational amplifier OP41 to drop rapidly. When the ramp voltage drops below the reference voltage VR1, the output voltage generated by the operational amplifier OP41 can return to a high voltage value.

[0035] By controlling the charging and discharging speed of the capacitor C41, the above-mentioned set time delay can be provided.

[0036] The signal delay 412 includes a latch LA32, a switch SW42, a capacitor C42, a current source I2, an operational amplifier OP42, and an inverter IV42. The set terminal S of the latch LA32 receives the control signal PWMB, and the reset terminal R of the latch LA32 receives the signal output by the inverter IV42. The inverted output terminal QB of the latch LA32 generates the signal SG2. The switch SW42 is coupled in parallel with the capacitor C42. The parallel-connected switch SW42 and capacitor C42 are then coupled in series with the current source I2 between the power supply voltage Vdd and the reference ground terminal GND. The terminal where the capacitor C42 is coupled to the current source I2 is coupled to the negative input terminal of the operational amplifier OP42. The positive input terminal of the operational amplifier OP42 receives the reference voltage VR2. The output terminal of the operational amplifier OP42 is then coupled to the input terminal of the inverter IV42.

[0037] The operation mode of the signal delay 412 is similar to that of the signal delay 411, which will not be elaborated here.

[0038] The single-shot circuit 421 receives the signal SG1 and generates a pulse wave PS41 according to the edge transition of the signal SG1. The single-shot circuit 422 receives the signal SG2 and generates a pulse wave PS42 according to the edge transition of the signal SG2. The set terminal of the latch LA4 receives the pulse wave PS41, and its reset terminal R receives the pulse wave PS42. The latch LA4 generates a latch signal LS at its output terminal Q and an inverted latch signal LSB at its inverted output terminal QB. The logic circuit 430 receives the latch signal LS, the inverted latch signal LSB, and the mode information DCMA, DCMB, and performs a logic operation on the latch signal LS, the inverted latch signal LSB, and the mode information DCMA, DCMB to generate the channel enable signals ONCH1, ONCH2. Only when the mode information DCMA, DCMB are both 1, the channel enable signals ONCH1 and the channel enable signal ONCH2 are controlled by the aforementioned logic. Otherwise, ONCH1 and OCHN2 are set to 1 to ensure that when the load jumps, the interleaved control mode switch does not affect the fast transient response.

[0039] The single trigger circuit 421 includes a NAND gate ND3 and inverters IV1 and IV3. One input terminal of the NAND gate ND3 is coupled to the input terminal of the inverter IV1 to receive the signal SG1, and the other input terminal of the NAND gate ND3 is coupled to the output terminal of the inverter IV1. The output terminal of the NAND gate ND3 is coupled to the input terminal of the inverter IV3, and the output terminal of the inverter IV3 generates a pulse wave PS41. The single trigger circuit 422 includes a NAND gate ND4 and inverters IV2 and IV4. One input terminal of the NAND gate ND4 is coupled to the input terminal of the inverter IV2 to receive the signal SG2, and the other input terminal of the NAND gate ND4 is coupled to the output terminal of the inverter IV2. The output terminal of the NAND gate ND4 is coupled to the input terminal of the inverter IV4, and the output terminal of the inverter IV4 generates a pulse wave PS42.

[0040] The logic circuit 430 includes inverters IV5 and IV6, an AND gate AD1, and NAND gates ND5 and ND6. The inverters IV5 and IV6 respectively receive a latch signal LS and an inverted latch signal LSB. The AND gate AD1 receives mode information DCMA and DCMB. The NAND gate ND5 receives the output signal of the AND gate AD1 and the output signal of the inverter IV5, and the NAND gate ND5 generates a channel enable signal ONCH1. The NAND gate ND6 receives the output signal of the AND gate AD1 and the output signal of the inverter IV6, and the NAND gate ND6 generates a channel enable signal ONCH2.

[0041] In this embodiment, the latches LA31, LA32, and LA4 are SR-type latches. In addition, Figure 4 the circuit details of the single trigger circuits 421 and 422 in Figure 4 are only illustrative examples and are not used to limit the scope of implementation of the present invention. Those of ordinary skill in the art know that the single trigger circuit can be constructed in a variety of different ways, and the present invention has no special restrictions. Similarly, the composition of the circuit components in the logic circuit 430 is not limited to being the same as Figure 4 The circuit details of the logic circuit 430 in

[0042] are also only illustrative examples for explanation. Figure 4 and Figure 5 , Figure 5 are the signal waveform diagrams of the core circuits of the embodiments of the present invention. Among them, when the mode information DCMA and DCMB are at a high logic value, the positive pulse widths of the control signals PWMA and PWMB can be correspondingly increased, so as to achieve hysteresis control of the voltage conversion circuit in the DCM mode. Figure 4 Please also synchronously refer to

[0043] below and Figure 1 , Figure 6A and Figure 6B , Figure 6Aand Figure 6B is a waveform diagram of the switching voltage, inductor current, and output voltage of the voltage conversion circuit of the present invention under different loads. In Figure 6A , for example, the voltage conversion circuit 100 operates in a load state of 1.5 amperes. The currents IL1 and IL2 passing through the inductors LA and LB respectively have a phase difference and exhibit a quasi-interleaved state. Similarly, the switching voltages SWA and SWB also exhibit a quasi-interleaved state. In such a state, the ripple state of the output voltage Vout can be reduced by the quasi-interleaved operation. In Figure 6B , the voltage conversion circuit 100 operates, for example, in a load state of 0.8 amperes. The currents IL1 and IL2 passing through the inductors LA and LB respectively have a larger phase difference and exhibit a fully interleaved state. Similarly, the switching voltages SWA and SWB also exhibit a fully interleaved state. In such a state, the ripple state of the output voltage Vout can be effectively reduced by the fully interleaved operation.

[0044] In summary, the voltage conversion circuit of the present invention controlled by the interleaving controller can effectively operate in a quasi-interleaved or fully interleaved state. And thereby, the ripple of the output voltage can be effectively reduced, and the stability of the output voltage can be improved.

[0045] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A voltage conversion circuit, characterized in that, Comprising: A plurality of voltage converters, which are connected in parallel with each other and respectively generate an output voltage according to a plurality of control signals; A feedback circuit, coupled to the plurality of voltage converters, and generates a plurality of feedback signals according to the switching voltage on the power switch of each of the plurality of voltage converters and the error voltage between the output voltage and a first reference voltage; And An interleaving controller, coupled between the feedback circuit and the plurality of voltage converters, the interleaving controller includes a plurality of phase-locked loops respectively corresponding to the plurality of voltage converters, and the interleaving controller turns on or off the phase-locking mechanism according to the zero-crossing detection state of the power switch, and when the phase-locking mechanism is turned off, generates the plurality of control signals respectively according to the plurality of feedback signals and the zero-crossing detection state; Wherein, the interleaving controller includes: A core circuit, which generates a first channel enable signal according to a first control signal and first mode information, and generates a second channel enable signal according to a second control signal and second mode information; A first phase-locked loop, which receives the first mode information, the first control signal and a first clock signal, and outputs a first adjustment signal to a first pulse generator; The first pulse generator, which provides a first pulse wave according to the first mode information, the first control signal and the first adjustment signal; A second pulse generator, which provides a second pulse wave according to the first control signal, wherein there is a first time delay between the first pulse wave and the second pulse wave; A first logic circuit, which generates the first control signal according to the first channel enable signal, a first feedback signal, the first pulse wave and the second pulse wave; A second phase-locked loop, which receives second mode information, a second control signal and a second clock signal, and outputs a second adjustment signal to a third pulse generator; The third pulse generator, which provides a third pulse wave according to the second mode information, the second control signal and the second adjustment signal; A fourth pulse generator, which provides a fourth pulse wave according to the second control signal, wherein there is a second time delay between the third pulse wave and the fourth pulse wave; and A second logic circuit, which generates the second control signal according to the second channel enable signal, a second feedback signal, the third pulse wave and the fourth pulse wave.

2. The voltage conversion circuit according to claim 1, wherein The plurality of voltage converters include: A first voltage converter, which receives an input voltage; and A second voltage converter, the output terminal of the second voltage converter is coupled to the output terminal of the first voltage converter, and the second voltage converter receives the input voltage, Wherein the first voltage converter and the second voltage converter respectively convert the input voltage according to a first control signal and a second control signal to jointly generate the output voltage.

3. The voltage conversion circuit according to claim 2, wherein The voltage conversion circuit further includes: A first current sensor, which is used to sense the current on the first power switch of the first voltage converter to generate first current information, and obtains the first zero-crossing detection state of the first power switch and the first mode information according to the first current information; and A second current sensor is configured to sense the current on the second power switch of the second voltage converter to generate second current information, and obtain the second zero-crossing detection state of the second power switch and the second mode information according to the second current information.

4. The voltage conversion circuit according to claim 3, characterized in that, The feedback circuit includes: A first signal processing circuit that extracts and amplifies the DC component and the AC component of the first switching voltage of the first power switch of the first voltage converter to generate a first ramp voltage and a second ramp voltage respectively; A first signal adder that sums the first ramp voltage, the first reference voltage, and the first error voltage to generate a first comparison voltage, and sums the second ramp voltage, the output voltage, and the second error voltage to generate a second comparison voltage; A first comparator that generates a first feedback signal by comparing the first comparison voltage and the second comparison voltage; A second signal processing circuit that extracts and amplifies the DC component and the AC component of the second switching voltage of the second power switch of the second voltage converter to generate a third ramp voltage and a fourth ramp voltage respectively; A second signal adder that sums the third ramp voltage, the first reference voltage, and the first error voltage to generate a third comparison voltage, and sums the fourth ramp voltage, the output voltage, and the second error voltage to generate a fourth comparison voltage; A second comparator that generates a second feedback signal by comparing the third comparison voltage and the fourth comparison voltage; and An error voltage generator configured to calculate the error between the output voltage and the first reference voltage to generate the first error voltage and the second error voltage.

5. The voltage conversion circuit according to claim 4, wherein The error voltage generator includes: An error amplifier, the positive input terminal of the error amplifier receives the first reference voltage, the negative input terminal of the error amplifier receives the output voltage, and the output terminal of the error amplifier generates the first error voltage; A first resistor and a first capacitor, serially coupled between the output terminal of the error amplifier and the reference ground terminal; and A second resistor, the first terminal of the second resistor is coupled to the output terminal of the error amplifier, and the second terminal of the second resistor generates the second error voltage.

6. The voltage conversion circuit according to claim 4, wherein Each of the first signal processing circuit and the second signal processing circuit includes: A third resistor, the first terminal of the third resistor is configured to receive the first switching voltage or the second switching voltage; A second capacitor, coupled between the second terminal of the third resistor and the reference ground terminal; A DC signal extractor, coupled to the second terminal of the third resistor, configured to extract the DC component of the first switching voltage or the second switching voltage; and A signal amplifier that amplifies the DC component and the AC component according to a gain to generate the first ramp voltage and the second ramp voltage respectively, or generate the third ramp voltage and the fourth ramp voltage respectively.

7. The voltage conversion circuit according to claim 1, wherein The first logic circuit enables the first control signal according to the first pulse wave and disables the first control signal according to the second pulse wave. The second logic circuit enables the second control signal according to the third pulse wave and disables the second control signal according to the fourth pulse wave.

8. The voltage conversion circuit according to claim 1, wherein Each of the first logic circuit and the second logic circuit includes: A NAND gate that receives the first feedback signal and the first channel enable signal, or receives the second feedback signal and the second channel enable signal; A NOR gate, where the first input terminal of the NOR gate receives the first pulse wave or the third pulse wave, and the second input terminal of the NOR gate is coupled to the output terminal of the NAND gate; and A latch, where the set terminal of the latch is coupled to the output terminal of the NOR gate, the reset terminal of the latch receives the second pulse wave or the fourth pulse wave, and the output terminal of the latch generates the first control signal or the second control signal.

9. The voltage conversion circuit according to claim 1, characterized in that, The core circuit includes: A first signal delay unit that receives the first control signal and adjusts the width of the first signal according to a set delay time; A second signal delay unit that receives the second control signal and adjusts the width of the second signal according to the set delay time; A first monostable circuit that receives the first signal and generates a first pulse wave according to the edge transition of the first signal; A second monostable circuit that receives the second signal and generates a second pulse wave according to the edge transition of the first signal; A first latch that generates a latch signal and an inverted latch signal according to the first pulse wave and the second pulse wave; and A third logic circuit that generates the first channel enable signal and the second channel enable signal according to the latch signal, the inverted latch signal, the first mode information, and the second mode information.

10. The voltage conversion circuit according to claim 9, wherein Each of the first signal delay unit and the second signal delay unit includes: A second latch having a set terminal that receives the first control signal or the second control signal; A switch having a control terminal coupled to the inverted output terminal of the second latch; A capacitor coupled in parallel with the switch; A current source for supplying current to the capacitor or the switch; An operational amplifier having a negative input terminal coupled to the connection terminal of the capacitor and the current source, and a positive input terminal of the operational amplifier receives a second reference voltage; and An inverter coupled between the output terminal of the operational amplifier and the reset terminal of the latch.

11. The voltage conversion circuit according to claim 9, characterized in that, The set delay time is greater than half of the operating cycle of the voltage conversion circuit.

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