A multi-subframe cascade device data caching method and system

Abstract

A multi-subframe cascade device data caching method and system belongs to the field of storage space management technology, including collecting the data inflow of the switching chip, the data outflow of the first-level cache, and the total amount of data cache of the switching chip for each subframe; calculating the TRIX index and TRMA index of the data outflow of the first-level cache in the current cycle by combining the number of cycles and the data outflow; calculating the corrected value of the TRIX index and the corrected M_TRIX index of the current cycle by combining the number of cycles, the data outflow threshold, the data outflow, and the total amount of data cache; enabling the second-level cache when the data outflow of the first-level cache exceeds the data outflow threshold for multiple consecutive sampling cycles and the M_TRIX index is greater than the TRMA index; after the second-level cache is enabled, the second-level cache is disabled when the M_TRIX index is less than the TRMA index. This application can accurately predict the trend changes of the data traffic flowing into and out of each subframe switching chip, and timely enable and disable the second-level cache to ensure the data caching capacity of the subframe.

Description

Technical Field

[0001] The present application relates to the field of storage space management, and in particular to a data caching method and system for multi-subframe cascaded devices. Background Art

[0002] To meet the rapid development of big data services such as 5G, AR, and VR, transmission equipment is becoming increasingly complex. To meet the demands of big data services, the functions of a single network element (NE) are typically implemented by cascading multiple sub-frames and using the cards within them (also known as single disks). When the number of cascaded sub-frames and single disks increases, the amount of communication data carried by the upstream switching chips in the cascaded sub-frames increases dramatically.

[0003] When the default cache preset by the upstream cascade sub-frame switching chip is insufficient and the data processing capability is limited, and there is a large amount of burst data between frames (such as broadcast collection performance, single-disk configuration, etc.), the switching chip is prone to data congestion, cache overflow, data delay transmission and other problems, which in turn lead to data loss or transmission timeout between frames. Summary of the Invention

[0004] The present application provides a data caching method and system for a multi-sub-frame cascade device, which can solve the technical problem in the prior art that when there is a large amount of burst data between frames, data loss or transmission timeout may easily occur due to the limited default cache and data processing capabilities preset by the sub-frame switching chip.

[0005] In a first aspect, an embodiment of the present application provides a data caching method for a multi-subframe cascade device, the method comprising:

[0006] For each sub-frame, the data inflow of the switch chip, the data outflow of the first-level cache, and the total data cache of the switch chip are collected in each sampling period;

[0007] The triple exponential moving average (TRIX) indicator of the L1 cache data outflow volume in the current sampling period is calculated by combining the number of the current sampling period, the number of the lookback period, and the data outflow volume of the L1 cache in each sampling period. The TRIX indicator is used to represent the trend of the data outflow volume of the L1 cache in the current sampling period.

[0008] Combined with the current sampling period number, the amount of data outflow from the first-level cache, the total amount of data cache in the switching chip, and the preset threshold value of the amount of data outflow from the first-level cache in each sampling period, a correction value of the TRIX indicator for the current sampling period and a corrected TRIX indicator are calculated; the correction value is positively correlated with the amount of data outflow and the total amount of data cache, and negatively correlated with the preset threshold value;

[0009] Combining the current sampling period and the TRIX indicator, the triangular moving average (TRMA) indicator of the TRIX indicator in the specified period is calculated;

[0010] When the data outflow from the first-level cache exceeds the preset threshold value in multiple consecutive sampling periods and the corrected TRIX indicator is greater than the TRMA indicator, the second-level cache of the sub-frame is started, and the first-level cache and the second-level cache are used to store data; when the corrected TRIX indicator is not greater than the TRMA indicator, the second-level cache of the sub-frame is closed, and the first-level cache is used to store data.

[0011] In conjunction with the first aspect, in one embodiment, the first-level cache is a default storage space in a switch chip;

[0012] The secondary cache is additional storage space in the switch chip and / or other storage units in the sub-frame.

[0013] In conjunction with the first aspect, in one embodiment, the calculation of the TRIX indicator specifically includes the following steps:

[0014] Calculate the data outflow D of the first-level cache in the mth sampling period m The average value of the index AX over N lookback periods m , then:

[0015] AX m =(2×D m +(N-1)×AX m-1 ) / (N+1)

[0016] Calculate AX for the mth sampling period m The average index value BX of N retrospective periods m , then:

[0017] BX m =(2×AX m +(N-1)×BX m-1 ) / (N+1)

[0018] Calculate BX for the mth sampling period m The average TRIX index of N lookback periods m , then:

[0019] TRIX m =(2*BX m +(N-1)*TRIX m-1 ) / (N+1).

[0020] In combination with the first aspect, in one embodiment, the correction value of the current sampling period is calculated using the following formula:

[0021] δ m =[(D out_m -D th )+DIF m ] / D th

[0022] in,

[0023] m represents the period number of the current sampling period;

[0024] δ m Indicates the correction value of the mth sampling period;

[0025] Dout_ m Indicates the data outflow of the first-level cache in the mth sampling period;

[0026] Dth represents the preset threshold value of the first-level cache in each sampling period; the preset threshold value is 70% to 80% of the maximum amount of single-cycle inter-frame data interaction of the first-level cache in each sampling period;

[0027] DIF m Indicates the total amount of data cached by the exchange chip at the end of the mth sampling period.

[0028] In conjunction with the first aspect, in one embodiment, the modified TRIX indicator is calculated using the following formula:

[0029] M_TRIX m =TRIX m +δ m

[0030] in,

[0031] m represents the period number of the current sampling period;

[0032] M_TRIX m Indicates the mth sampling period for TRIX m Corrected value;

[0033] TRIX m The TRIX indicator represents the amount of data flowing out of the L1 cache during the mth sampling period.

[0034] δ m Indicates the correction value of the mth sampling period.

[0035] In conjunction with the first aspect, in one embodiment, the TRMA index is calculated using the following formula:

[0036]

[0037] in,

[0038] TRMAm Indicates TRIX of the mth sampling period m Moving average of the value over M specified periods;

[0039] M represents the calculation of TRIX m The specified number of periods;

[0040] m represents the period number of the current sampling period;

[0041] TRIX i TRIX value indicating the amount of data flowing out of the L1 cache during the i-th sampling period.

[0042] In conjunction with the first aspect, in one embodiment, the period is calculated using the following formula:

[0043]

[0044] in,

[0045] T represents the duration of the sampling period;

[0046] Cach_total represents the storage space capacity of the first-level cache;

[0047] Rated indicates the maximum inter-chassis data communication rate per second of the L1 cache in each sampling period.

[0048] N represents the number of lookback periods for calculating the TRIX indicator.

[0049] In combination with the first aspect, in one embodiment, the method further includes:

[0050] After the secondary cache is enabled, when data is sent to the control disk, the data is stored in the secondary cache and preprocessed. Then, the preprocessed data is stored from the secondary cache to the primary cache according to the maximum inter-frame data communication rate per second of the primary cache in each sampling period, and the control disk extracts the corresponding data from the primary cache.

[0051] After closing the secondary cache, when sending data to the control disk, the data is stored in the primary cache, and the control disk extracts the corresponding data from the primary cache;

[0052] The control disk sends data outward through the first-level cache at a transmission rate that does not exceed the maximum rate of inter-frame data communication per second in each preset sampling period.

[0053] In combination with the first aspect, in one embodiment, the method further includes:

[0054] The pre-processing includes classifying the data and then merging and compressing each type of data.

[0055] In a second aspect, an embodiment of the present application provides a multi-subframe cascade device data caching system, the system comprising:

[0056] The data collection module is used to collect the data inflow of the switch chip, the data outflow of the first-level cache, and the total data cache of the switch chip for each sub-frame in each sampling period;

[0057] A data processing module is configured to calculate a triple exponential moving average (TRIX) indicator of the data outflow volume of the first-level cache in the current sampling period based on the number of the current sampling period, the number of the lookback period, and the data outflow volume of the first-level cache in each sampling period. The TRIX indicator is used to characterize the trend of the data outflow volume change of the first-level cache in the current sampling period. A data processing module is configured to calculate a correction value of the TRIX indicator in the current sampling period and a corrected TRIX indicator based on the number of the current sampling period, the data outflow volume of the first-level cache, the total amount of the data cache of the switching chip, and the preset threshold value of the data outflow volume of the first-level cache in each sampling period. The correction value is positively correlated with the data outflow volume and the total amount of the data cache, and negatively correlated with the preset threshold value. A TRMA indicator of the TRIX indicator in a specified period is calculated based on the number of the current sampling period and the TRIX indicator.

[0058] A cache management module is used to start the secondary cache of the sub-frame and use the primary cache and the secondary cache to store data when the data outflow from the primary cache exceeds the preset threshold value in multiple consecutive sampling periods and the corrected TRIX indicator is greater than the TRMA indicator; when the corrected TRIX indicator is not greater than the TRMA indicator, close the secondary cache of the sub-frame and use the primary cache to store data.

[0059] The beneficial effects of the technical solutions provided in the embodiments of the present application include:

[0060] The TRMA, TRIX, and its modified M_TRIX indicator for data outflow in the current sampling period are calculated by combining the current sampling period number, the backtracking period number, and the switch chip's data inflow, L1 cache outflow, and total data cache volume during each sampling period. Compared to the TRIX indicator, the modified TRIX indicator (i.e., M_TRIX) can more accurately predict the trend of L1 cache data outflow. By comparing the M_TRIX indicator with the mean TRMA indicator, it is possible to accurately predict whether the trend of L1 cache data outflow is increasing or decreasing, thereby determining whether to enable or disable the L2 cache in advance. Specifically, enabling the L2 cache before inter-chassis data transmission surges can improve the data caching capacity of the sub-chassis and avoid data loss or transmission timeouts caused by cache overflows. Alternatively, disabling the L2 cache when inter-chassis data outflow and total data cache volume have returned to normal and cache overflows are no longer a possibility can free up the L2 cache for other functions and improve overall device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] Figure 1 This is a flow chart of an embodiment of a method for caching data in a multi-subframe cascaded device of the present application;

[0062] Figure 2 This is a schematic diagram of the architecture of an embodiment of a multi-subframe cascade device of the present application;

[0063] Figure 3 This is a schematic diagram of the internal data flow of the switching chip when the L2 cache switch is turned off in one embodiment of the present application;

[0064] Figure 4 This is a schematic diagram of the internal data flow of the switching chip when the L2 cache switch is turned on in one embodiment of the present application;

[0065] Figure 5 This is a schematic diagram of the data volume and indicator values ​​of the switching chip in each cycle obtained from actual testing in one embodiment of the present application;

[0066] Figure 6 This is a schematic diagram of the total amount of cache memory of the switch chip in each cycle obtained from actual testing in one embodiment of the present application;

[0067] Figure 7 This is a functional module diagram of an embodiment of a multi-subframe cascade device data cache system of the present application. DETAILED DESCRIPTION

[0068] In order to enable those skilled in the art to better understand the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0069] First, some technical terms in this application are explained to facilitate those skilled in the art to understand this application.

[0070] TRIX (Triple Exponentially Smoothed Average) is a medium- to long-term indicator and a technical analysis tool used to study stock price trends (or the decay of a building's lifespan, for example). It filters out unnecessary fluctuations to reflect the long-term fluctuation trend of stock prices.

[0071] TRMA indicator: Triangular Moving Average in English, the full name is triangular moving average, which is a dynamic technical indicator. It is a moving average that calculates price fluctuations. It can be used to confirm the direction of price trends (or the decay trend of building life, etc.) and judge the strength of the trend.

[0072] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0073] In a first aspect, an embodiment of the present application provides a data caching method for a multi-subframe cascade device.

[0074] In one embodiment, referring to Figure 1 , Figure 1 This is a flow chart of an embodiment of a multi-subframe cascade device data caching method of the present application, as shown in FIG. Figure 1 As shown, the data caching method for multi-subframe cascade devices includes:

[0075] Step S1: For each sub-frame, the data inflow of the switch chip, the data outflow of the first-level cache, and the total data cache of the switch chip are collected in each sampling period.

[0076] Step S2: Combine the number of the current sampling period, the number of the backtracking period, and the data outflow volume of the first-level cache in each sampling period to calculate the TRIX index of the data outflow volume of the current sampling period. The TRIX index is used to characterize the trend of the data outflow volume change of the first-level cache in the backtracking period.

[0077] Step S3: Calculate a correction value for the TRIX indicator of the current sampling period and a corrected TRIX indicator based on the current sampling period number, the amount of data flowing out of the L1 cache, the total amount of data buffered in the switch chip, and the preset threshold value for the amount of data flowing out of the L1 cache in each sampling period. The correction value is positively correlated with the amount of data flowing out and the total amount of data buffered, and negatively correlated with the preset threshold value.

[0078] Step S4: Combine the current sampling period and the TRIX indicator to calculate the TRMA indicator of the TRIX indicator in the specified period.

[0079] Step S5: When the data outflow exceeds the preset threshold value for multiple consecutive sampling periods and the modified TRIX index is greater than the TRMA index, the sub-frame's L2 cache is enabled and the L1 and L2 caches are used to store data. When the modified TRIX index is not greater than the TRMA index, the sub-frame's L2 cache is disabled and the L1 cache is used to store data.

[0080] In this embodiment, refer to Figure 2 , Figure 2 This is an architectural diagram of an embodiment of a multi-subframe cascade device of the present application. Usually, the function of a network element needs to be implemented by multiple subframes after cascading based on the single disks in the multiple subframes. The multiple single disks in the subframe can be divided into a control disk (referred to as the frame control) and a service disk. The control disk in the same subframe manages each service disk. All single disks in the same subframe are connected to the switching chip in the frame. The default cache of the switching chip is the first-level cache of the subframe. The control disk is responsible for data transmission with the service disk in the subframe and the upstream and downstream subframes cascaded with it. The interactive data between the control disk and the service disk in the subframe is intra-frame data, and the interactive data between the control disk and other subframes is inter-frame data. Both inter-frame data and intra-frame data enter and exit from the first-level cache.

[0081] The switching chip is typically integrated into the control panel, but can also be integrated into the service panel or sub-frame. Each sub-frame is connected to upstream and downstream sub-frames through the data interface (such as an Ethernet port) and network cable (such as an RJ45 cable). The data interface in the frame is connected to the switching chip, and the control panel transmits data to the outside world through the switching chip.

[0082] Among all control panels, the one used to manage all sub-frames and single disks of the entire network element is the main control panel. Other control panels are called frame control panels. The sub-frame where the main control panel is located is the main frame, and the other sub-frames are extension frames.

[0083] Under normal circumstances, the inter-chassis data traffic between the control disk and the service disks within its own sub-chassis, as well as the individual disks in other sub-chassis, is relatively balanced and small. This means that the inter-chassis data rate flowing out of the L1 cache is significantly lower than the designed maximum inter-chassis data rate. The maximum inter-chassis data rate indicates the maximum inter-chassis data communication rate per second of the L1 cache during each sampling period.

[0084] When there is a large amount of burst data between frames (such as broadcast collection performance, single-disk configuration, etc.), the inter-frame data flowing into the first-level cache increases sharply. When the rate of intra-frame data and inter-frame data flowing into the first-level cache is greater than the designed maximum inter-frame data rate, the first-level cache will usually only send inter-frame data outward at the preset maximum inter-frame data rate.

[0085] In addition, the data within the frame that interacts between the business disk on the downstream cascade sub-frame and the main control disk must pass through the first-level cache on the upstream cascade sub-frame, resulting in a larger amount of circulating data in the first-level cache on the cascade sub-frame closer to the main frame. That is, when the number of cascaded sub-frames and single disks is large, the communication data carried by the first-level cache of the upstream cascade sub-frame will increase sharply. Therefore, the first-level cache on the upstream cascade sub-frame is more likely to have problems such as data congestion, cache overflow, and delayed data transmission due to insufficient preset cache.

[0086] In order to solve the problem of insufficient default cache space preset by the switching chip or the cascade sub-frame, and limited data processing capacity, the present invention combines the above-mentioned sampling period number, the period of the backtracking period, and the data inflow of the switching chip in each sampling period, the data outflow of the first-level cache and the total amount of data cache of the switching chip (referred to as cache amount), and calculates the TRMA index, TRIX index and its revised M_TRIX index of the data outflow of the current sampling period. Compared with the TRIX index, the revised TRIX index (i.e., the M_TRIX index) can more accurately predict the changing trend of the first-level cache data outflow. By comparing the M_TRIX index with the mean TRMA index, it is possible to accurately predict whether the changing trend of the first-level cache data outflow is strengthening or weakening, thereby judging whether to open or close the second-level cache switch in advance, that is, to open the second-level cache in advance before the data transmission between frames surges to improve the data caching capacity of the sub-frame, and avoid problems such as data loss or transmission timeout. That is, when the inter-chassis data outflow and the total data cache have returned to normal levels and no cache overflow will occur, the L2 cache switch is turned off, releasing the L2 cache for other functions and improving the overall performance of the device.

[0087] Furthermore, in one embodiment, the above-mentioned first-level cache is a default storage space in the switching chip.

[0088] The above-mentioned secondary cache is additional storage space in the switching chip and / or other storage units in the above-mentioned sub-frame.

[0089] In this embodiment, the secondary cache may be other caches / slices in the switch chip except the default cache, or may be other storage units in the subframe except the switch chip, such as a memory chip.

[0090] Switch chips are a standard feature of sub-frames, providing L1 cache. Memory chips are also standard features in some sub-frames, or are easily added and managed. Therefore, L1 and L2 caches can be used to improve the data caching capabilities of sub-frames. If sub-frames already have switch chips and memory chips, this method can improve storage capacity without adding or modifying hardware, thus reducing the cost of cascading multiple sub-frames.

[0091] Furthermore, in one embodiment, the calculation of the TRIX indicator specifically includes the following steps:

[0092] Calculate the data outflow volume D of the first-level cache in the mth sampling period m The average value of the index AX over N lookback periods m , then:

[0093] AX m =(2×D m +(N-1)×AX m-1 ) / (N+1)

[0094] Calculate AX for the mth sampling period m The average index value BX of N retrospective periods m , then:

[0095] BX m =(2×AX m +(N-1)×BX m-1 ) / (N+1)

[0096] Calculate BX for the mth sampling period m The average TRIX index of N lookback periods m , then:

[0097] TRIX m =(2*BX m +(N-1)*TRIX m-1 ) / (N+1).

[0098] In this embodiment, refer to Figure 3 and Figure 4 , Figure 3 This is a schematic diagram of the internal architecture of a switching chip in an embodiment of the present application. Figure 4This is a schematic diagram of the internal data flow of the switching chip when the secondary cache switch is turned on in one embodiment of the present application. Figure 3 and Figure 4 As shown, the switch chip contains a default cache and a secondary cache. The default cache is also the primary cache. The secondary cache is enabled and disabled by the secondary cache switch (not shown). When enabled, the secondary cache can receive and store data, then send the data to the primary cache for storage. When disabled, the secondary cache no longer receives data. Ports 1, 2, and 3 are both data inflow and outflow ports. The solid arrows in the figure indicate the data inflow direction, and the dashed arrows indicate the data outflow direction.

[0099] The switching chip also includes a data transceiver unit 11, a traffic monitoring unit 21, a data cache preprocessing unit 32, and a data sending preprocessing unit 31. The data transceiver unit 11 is responsible for receiving and sending data from each port that the control disk communicates with other single disks through the first-level cache, and sending the data to the traffic monitoring unit 21 for data analysis. The data cache preprocessing unit 32 can preprocess the data that needs to be stored in the second-level cache, and the data sending preprocessing unit 31 can preprocess the data output by the second-level cache.

[0100] Specifically, the traffic monitoring unit 21 periodically (according to a sampling period) analyzes the data that the control disk communicates with other single disks through the switching chip, and counts the amount of data flowing into and out of the switching chip.

[0101] The traffic monitoring unit 21 takes a time period T as a cycle, counts the data inflow Din of the switching chip and the data outflow Dout of the first-level cache within a sampling cycle, and calculates the total data cache amount DIF = (Din-Dout) in the current sampling cycle. Din is the amount of data flowing into the first-level cache before the second-level cache switch is turned on, and is the amount of data flowing into the second-level cache after the second-level cache switch is turned on.

[0102] In addition, the traffic monitoring unit 21 counts the total amount of data cached in each cycle. For example, at the end of the mth sampling cycle, the total amount of data cached in the switching chip DIF m Calculated using the following formula (1):

[0103]

[0104] The TRIX indicator is a long-term technical analysis indicator for studying commodity price trends. It can be used to predict future growth or decline in commodity prices. The M_TRIX indicator value is calculated using the improved TRIX algorithm, using the L1 cache data outflow volume Dout at the end of each sampling period as the commodity price. The M_TRIX indicator can be used to determine the growth or decline of L1 cache data outflow and to enable or disable L2 cache when the M_TRIX indicator value meets the conditions.

[0105] The amount of data outflow from the first-level cache during the current sampling period (assuming it is the mth sampling period) is D m The average index value of N lookback periods AX is recorded as AX m , AX m-1 is the amount of data outflow from the first-level cache calculated in the previous sampling period, D m-1 The index average of N back-test periods. The back-test period is the number of past sampling periods including the current sampling period. The number of back-test periods N is selected based on actual needs. m Calculated using the following formula (2):

[0106] AX m =(2 × D m + (N - 1) × AX m-1 ) / (N + 1) (2)

[0107] The average value BX of the N back-test period index of the current sampling period AX is denoted as BX m , BX m-1 AX calculated for the previous sampling period m-1 The exponential average of N lookback periods. BX m Calculated using the following formula (3):

[0108] BX m = (2 × AX m + (N - 1) × BX m-1 ) / (N + 1) (3)

[0109] The average value of the N back-test period index TRIX of the current sampling period BX is recorded as TRIX m , TRIX m-1 BX calculated for the previous sampling period m-1 The average value of the N-year exponential trend. m Calculated using the following formula (4):

[0110] TRIX m = (2 * BX m + (N - 1)* TRIXm-1 ) / (N + 1) (4)

[0111] The moving average value TRMA of the TRIX value in the current sampling period for M specified periods, denoted as TRMA m , TRMA i Indicates the TRIX value of the i-th cycle. The value of the specified period M is selected according to actual needs. m Calculated using the following formula (5):

[0112]

[0113] Among them, TRMA m Indicates TRIX of the current sampling period m m The moving average value of the specified M period. M represents the value used to calculate TRIX. m The specified cycle number. m represents the cycle number of the current sampling cycle. TRIX i Indicates the TRIX indicator value of the i-th sampling period.

[0114] TRIX traditional usage: When TRIX m >TRMA m , indicating that the upward momentum of commodity prices is strengthening. You can consider buying commodities at low prices in combination with other indicators. m <TRMA m , indicating that the downward momentum of commodity prices is strengthening. You can consider selling commodities at high prices in combination with other indicators.

[0115] Most of the time, the data flow between frames is relatively small, and the Dout of each sampling period is m Relatively stable and meets TRIX m <TRMA m When the data traffic between frames gradually increases, Dout m Corresponding TRIX m 、TRMA m will increase accordingly (TRIX m Growth trend than TRMA m According to traditional usage, once TRIX m >TRMA m Then perform a buy operation, that is, turn on the data secondary cache switch.

[0116] When the actual data flow between frames is low and the first-level cache consumption is very small, occasional large changes in traffic may also cause TRIX m >TRMA mThis will inevitably lead to unnecessary switching actions on the L2 cache. In order to increase the reliability and availability of judging the growth or decline trend of data outflow between L1 cache frames, based on the characteristics of data traffic flowing through the L1 cache, we have modified the traditional TRIX m The calculation method is improved, that is, the TRIX obtained by the traditional calculation method is corrected using the correction value. m By making corrections, we can obtain the TRIX indicator that can more accurately reflect the trend of data outflow between L1 cache frames.

[0117] Furthermore, according to conventional usage, if each sampling period Dout m The TRIX value is not modified. Once the TRIX m <TRMA m , then make a sell operation, that is, turn off the secondary cache switch, and there may be a risk of cache overflow. m The value decreases, and TRIX m <TRMA m This only indicates that the amount of inter-frame data flowing out of the L1 cache is decreasing, that is, it is showing a downward trend. It does not mean that the previously cached inter-frame data and intra-frame data have been processed, nor does it mean that no data is flowing into the L1 cache at this time. At this time, the total amount of data cache in the switch chip may still be at a high level (the data inflow has been greater than the data outflow for a long time in the early stage, resulting in a large amount of cached data in the switch chip). At this time, turning off the L2 cache switch may still cause the risk of cache overflow or the L2 cache switch being frequently turned on and off.

[0118] Therefore, it is necessary to revise the TRIX indicator calculated by traditional methods to improve the prediction accuracy.

[0119] Furthermore, in one embodiment, the correction value of the current sampling period is calculated using the following formula (6):

[0120] δ m = [( D out_m -D th )+ DIF m ] / D th (6)

[0121] Where m represents the period number of the current sampling period. m Indicates the correction value of the mth sampling period. m Indicates the data outflow of the first-level cache in the mth sampling period. Dth represents the preset threshold value of the first-level cache in each sampling period. The above preset threshold value is 70% to 80% of the maximum single-cycle inter-frame data interaction volume of the first-level cache in each sampling period. mIndicates the total amount of data cached by the exchange chip at the end of the mth sampling period.

[0122] The modified TRIX indicator is calculated using the following formula (7):

[0123] M_TRIX m = TRIX m +δ m (7)

[0124] Where m represents the period number of the current sampling period. m Indicates the mth sampling period for TRIX m Corrected value. TRIX m The TRIX indicator representing the amount of data outflow from the first-level cache in the mth sampling period. m Indicates the correction value of the mth sampling period.

[0125] In this embodiment, Drated is the designed maximum data interaction amount between the first-level cache frames in each sampling cycle, such as the common 100Mbits\1000Mbits (corresponding rates are 100Mbps\1000Mbps respectively), and Dth is the threshold value. It has been tested and verified that a Drated value of 70% to 80% is most suitable.

[0126] In addition to directly replacing TRIX in formula (7) m and δ m Add to TRIX m In addition to the correction method, it can also be based on δ m Size correction TRIX m , for example, increase or decrease TRIX proportionally according to the size of δ m The value of .

[0127] M_TRIX modified according to this method m The value can perfectly solve the above-mentioned problem caused by directly using TRIXm to predict the growth or decline trend of the first-level cache data outflow and then turning on or off the second-level cache.

[0128] In order to more clearly show the effectiveness and reliability of the M_TRIX value calculated by the modified TRIX algorithm in predicting the rising or falling trend of the amount of data flowing out of the first-level cache frame, a table is drawn based on the data obtained from actual tests. Figure 5 and Figure 6 , Figure 5 This is a schematic diagram of the data volume and index values ​​of the switching chip in each cycle obtained from actual testing in one embodiment of the present application. Figure 6This is a schematic diagram of the total cache capacity of the switch chip at various cycles, obtained from actual testing of an embodiment of this application. In the actual test, the TRIX value cycle N was set to 12, M to 15, the preset threshold for data outflow per second was 70 Mbits, T was set to 1 second, and the maximum outflow per second was designed to be 100 Mbits. The units of L_IN, L_OUT, and DIF in the table are 10 Mbits.

[0129] from Figure 5 It can be clearly seen that according to M_TRIX m Determine whether to enable the secondary cache switch, which can effectively filter TRIX when the data flow between frames is low. m >TRMA m The switch of the secondary cache is turned on, such as Figure 5 The 16th to 46th sampling periods in the first level cache fluctuate due to the data flowing into the first level cache. The amount of data flowing into the first level cache in some sampling periods changes significantly compared with the previous sampling periods, resulting in the TRIX of each sampling period. m Both are greater than TRMA m value, but the first-level cache still has enough space to store data, so there is no need to enable the second-level cache.

[0130] from Figure 5 It can be clearly seen that when the data outflow of the first-level cache exceeds the Dth threshold for two consecutive cycles and M_TRIX m >TRMA m The strategy of turning on the secondary cache switch only when the secondary cache switch is turned on can effectively filter the occasional large changes in the amount of data flow between frames, which may cause the M_TRIX m >TRMA m Then turn on the secondary cache switch, such as Figure 5 M_TRIX of each sampling period from the 27th to the 39th sampling period m Both are greater than TRMA m But there is only one sampling period in which the Dout value is greater than 70Mbits. Figure 5 , the amount of data flowing into the first-level cache increases around the 70th sampling period, resulting in the amount of data flowing out of the first-level cache Dout m And the total amount of data cache DIF for each m sampling period m At the same time, the outflow of the first-level cache exceeds the Dth threshold in the 69th and 70th sampling cycles, and M_TRIX in the 70th sampling cycle m >TRMA m Based on this, it can be predicted that the amount of data flowing into the first-level cache will increase sharply. At this time, opening the second-level cache in advance can avoid the problem of cache overflow in the first-level cache due to the rapid increase in the amount of data flowing in subsequently.

[0131] from Figure 5 and Figure 6 It can be clearly seen that when the amount of data flowing out of the switch chip in each sampling period reaches the rated maximum data outflow of 100Mbits in each sampling period, most of the sampling periods TRIX m Already smaller than TRMA m However, the total amount of data in the exchange chip cache during these sampling cycles has remained at a high level. At this time, turning off the secondary cache switch still poses a risk of data overflow. For example, TRIX has already appeared in the 89th sampling cycle. m Already smaller than TRMA m However, the total amount of data cached by the switch chip is 977.4Mbits, which is at a high cache level. The L2 cache switch should not be turned off at this time.

[0132] from Figure 5 and Figure 6 It can be clearly seen that after turning on the secondary cache switch, the M_TRIX value calculated according to the improved method appears M_TRIX m Smaller than TRMA m When each sampling period Dout m The outflow volume and total data cache volume have returned to normal levels. At this time, turning off the L2 cache switch will basically eliminate the risk of data overflow.

[0133] In summary, this method can solve or greatly improve problems such as switch chip cache overflow and data delay during big data collection in sub-frame cascade scenarios, reduce operation and maintenance manpower and economic costs, and improve customer experience.

[0134] Furthermore, in one embodiment, the above period is calculated using the following formula (8):

[0135]

[0136] Where T represents the sampling period. Cache_total represents the storage capacity of the L1 cache. Rated represents the maximum inter-chassis data communication rate per second of the L1 cache during each sampling period. N represents the number of lookback periods used to calculate the TRIX indicator.

[0137] In this embodiment, during actual implementation, the default cache space of some switching chips may be small. When the switching chip's data exchange rate is relatively high, the default cache will quickly fill up when a large amount of burst data arrives. To effectively monitor data flowing into or out of the switching chip, the duration T of each sampling cycle needs to be properly configured. Where Cach_total is the default cache space size of the switching chip (i.e., the storage space capacity of the first-level cache), Rated is the designed maximum inter-frame data communication rate per second, and N is the number of cycles used to calculate TRIX and M_TRIX.

[0138] In addition, in the implementation process, in order to increase the reliability and availability of the growth or decline trend of the data outflow between the first-level cache of the switching chip, and to effectively filter the TRIX that may occur due to the occasional large changes in the data flow between the frames, m >M_TRMA m In this case, you can set the M_TRIX to be used only when the outflow of the primary cache data exceeds the Dth threshold value for two or more consecutive sampling cycles. m Determines whether to enable or disable the secondary cache.

[0139] Furthermore, in one embodiment, the above method further includes:

[0140] After the above-mentioned secondary cache is enabled, when sending data to the control disk, the data is stored in the secondary cache and preprocessed. Then, the preprocessed data is stored from the secondary cache to the primary cache according to the maximum inter-frame data communication rate per second of the primary cache in each sampling period, and the control disk extracts the corresponding data from the primary cache.

[0141] After closing the above-mentioned secondary cache, when sending data to the control disk, the data is stored in the primary cache, and the control disk extracts the corresponding data from the primary cache.

[0142] The control disk sends data outward through the first-level cache at a transmission rate that does not exceed the maximum rate of inter-frame data communication per second in each preset sampling period.

[0143] Furthermore, in one embodiment, the above method further includes:

[0144] The above sub-frames send inter-frame data to other sub-frames according to the rated flow through the first-level cache.

[0145] In this embodiment, the data transmission pre-processing unit 31 periodically retrieves data from the L2 cache and sends the inter-frame data to the default cache (i.e., L1 cache) of the switch chip at a preset maximum inter-frame rate (Rated). The switch chip also transmits inter-frame data exchanged between the main control board and each board in each cascade sub-frame at the preset maximum inter-frame rate corresponding to Rated, ensuring that the data sent from the switch chip remains at a stable level, thereby achieving traffic balance between the main control board and each cascade sub-frame.

[0146] Furthermore, in one embodiment, the above method further includes:

[0147] The above preprocessing includes classifying the data and then merging and compressing each type of data.

[0148] In this embodiment, after the data secondary cache switch is turned on, when the data transceiver unit 11 receives inter-frame data exchanged between the main control board and each board on each level of the tandem sub-frame, the data is not sent to the default cache of the switching chip, but is sent to the data cache preprocessing unit 32. After receiving the data, the cache preprocessing unit classifies it according to the IP address and uses the memory for temporary storage, then merges and compresses the data stored in the memory, and sends the processed data to the secondary cache for data caching. This can reduce the amount of data transmitted between frames and improve the efficiency of inter-frame data transmission.

[0149] Later, after the master receives the data reported by the downstream sub-frame, it decompresses and splits the data and identifies the correctness of the split data.

[0150] In a second aspect, an embodiment of the present application further provides a multi-sub-frame cascade device data cache system.

[0151] In one embodiment, referring to Figure 7 , Figure 7 This is a functional module diagram of an embodiment of the multi-subframe cascade device data cache system of this application. Figure 7 As shown, the multi-subframe cascade device data cache system includes:

[0152] The data collection module 1 is used to collect the data inflow of the switch chip, the data outflow of the first-level cache, and the total data cache of the switch chip for each sub-frame in each sampling period. The data transceiver unit 11 belongs to the data collection module 1.

[0153] The data processing module 2 is used to calculate the triple exponential moving average (TRIX) indicator of the first-level cache data outflow in the current sampling period by combining the current sampling period number, the lookback period number, and the first-level cache data outflow in each sampling period. The TRIX indicator is used to characterize the trend of the data outflow change of the first-level cache in the current sampling period. The correction value of the TRIX indicator of the current sampling period and the corrected TRIX indicator are calculated by combining the current sampling period number, the first-level cache data outflow, the total amount of the switching chip data cache, and the preset threshold value of the first-level cache data outflow in each sampling period. The above correction value is positively correlated with the above-mentioned data outflow and the total amount of data cache, and negatively correlated with the above-mentioned preset threshold value. Combined with the current sampling period number and the TRIX indicator, the moving average (TRMA) indicator of the TRIX indicator in the specified period is calculated. The traffic monitoring unit 21 belongs to the data processing module 2.

[0154] Cache management module 3 is configured to activate the sub-frame's L2 cache and use both the L1 and L2 caches to store data when the L1 cache data outflow exceeds a preset threshold for multiple consecutive sampling periods and the modified TRIX index is greater than the TRMA index. If the modified TRIX index is no greater than the TRMA index, the sub-frame's L2 cache is disabled and the L1 cache is used to store data. Data transmission preprocessing unit 31 and data cache preprocessing unit 32 are part of cache management module 3.

[0155] To address the issues of insufficient default cache space and limited data processing capabilities in the switching chip or cascade sub-frame, the present invention combines the current sampling period, the backtracking period, the switching chip's data inflow, the L1 cache data outflow, and the total switching chip data cache volume in each sampling period to calculate the TRMA indicator, the TRIX indicator, and its modified M_TRIX indicator for the L1 cache data outflow volume in the current sampling period. Compared with the TRIX indicator, the modified TRIX indicator (i.e., the M_TRIX indicator) can more accurately predict the changing trend of the L1 cache data outflow volume. By comparing the M_TRIX indicator with the mean TRMA indicator, you can accurately predict whether the trend of the L1 cache data outflow is increasing or decreasing, and thus determine whether to enable or disable the L2 cache in advance. That is, before the inter-chassis data transmission volume surges, quickly enable the L2 cache in advance to improve the data caching capacity of the sub-chassis and avoid problems such as data loss or transmission timeouts caused by cache overflow. Alternatively, disable the L2 cache switch when the inter-chassis data outflow volume and the total data cache volume have returned to normal levels and cache overflow is no longer expected, freeing up the L2 cache for other functions and improving overall device performance.

[0156] The functional implementation of each module in the above-mentioned multi-sub-frame cascade device data caching apparatus corresponds to each step in the above-mentioned multi-sub-frame cascade device data caching method embodiment, and their functions and implementation processes are not repeated here one by one.

[0157] It should be noted that the serial numbers of the above-mentioned embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0158] The terms "including" and "having" and any variations thereof in the specification and claims of this application and the above-mentioned drawings are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices. The terms "first", "second" and "third" are used to distinguish different objects, etc., and do not represent a sequence, nor do they limit the "first", "second" and "third" to different types.

[0159] In the description of the embodiments of this application, the words "exemplary," "for example," or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary," "for example," or "for example" in the embodiments of this application should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary," "for example," or "for example" is intended to present the relevant concepts in a concrete manner.

[0160] In the description of the embodiments of the present application, unless otherwise specified, “ / ” means or, for example, A / B can mean A or B; “and / or” in the text is merely a description of the association relationship of associated objects, indicating that three relationships may exist, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in the description of the embodiments of the present application, “multiple” refers to two or more than two.

[0161] In some processes described in the embodiments of the present application, multiple operations or steps are included that appear in a specific order. However, it should be understood that these operations or steps may not be performed in the order in which they appear in the embodiments of the present application or may be performed in parallel. The sequence numbers of the operations are only used to distinguish between different operations, and the sequence numbers themselves do not represent any order of execution. In addition, these processes may include more or fewer operations, and these operations or steps may be performed in sequence or in parallel, and these operations or steps may be combined.

[0162] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus the necessary general hardware platform, of course, it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes a number of instructions for enabling a terminal device to execute the methods described in each embodiment of the present application.

[0163] The above are only preferred embodiments of the present application and do not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A data caching method for a multi-subframe cascade device, characterized in that: The method comprises: For each sub-frame, the data inflow of the switch chip, the data outflow of the first-level cache, and the total data cache of the switch chip are collected in each sampling period; The triple exponential moving average (TRIX) indicator of the L1 cache data outflow volume for the current sampling period is calculated by combining the number of the current sampling period, the number of the lookback period, and the data outflow volume of the L1 cache for each sampling period. The TRIX indicator is used to represent the trend of the data outflow volume of the L1 cache in the current sampling period. Combined with the current sampling period number, the amount of data outflow from the first-level cache, the total amount of data cache in the switching chip, and the preset threshold value of the amount of data outflow from the first-level cache in each sampling period, a correction value of the TRIX indicator for the current sampling period and a corrected TRIX indicator are calculated; the correction value is positively correlated with the amount of data outflow and the total amount of data cache, and negatively correlated with the preset threshold value; Combine the current sampling period and the TRIX indicator to calculate the triangular moving average (TRMA) indicator of the TRIX indicator in the specified period; When the data outflow from the first-level cache exceeds the preset threshold value in multiple consecutive sampling periods and the corrected TRIX indicator is greater than the TRMA indicator, the second-level cache of the sub-frame is started, and the first-level cache and the second-level cache are used to store data; when the corrected TRIX indicator is not greater than the TRMA indicator, the second-level cache of the sub-frame is closed, and the first-level cache is used to store data.

2. The multi-subframe cascade device data caching method according to claim 1, wherein: The first-level cache is the default storage space in the switch chip; The secondary cache is additional storage space in the switch chip and / or other storage units in the sub-frame.

3. The multi-subframe cascade device data caching method according to claim 1, wherein: The calculation of the TRIX indicator specifically includes the following steps: Calculate the data outflow D of the first-level cache in the mth sampling period m The average value of the index AX over N lookback periods m , then: AX m =(2 × D m + (N - 1)×AX m-1 ) / (N + 1) Calculate AX for the mth sampling period m The average index value BX of N retrospective periods m , then: BX m = (2 × AX m + (N - 1)×BX m-1 ) / (N + 1) Calculate BX for the mth sampling period m The average TRIX index of N lookback periods m , then: TRIX m = (2 * BX m + (N - 1)* TRIX m-1 ) / (N + 1)。 4. The multi-subframe cascade device data caching method according to claim 1, wherein: The correction value of the current sampling period is calculated using the following formula: δ m =[( D out_m - D th )+ DIF m ] / D th in, m represents the period number of the current sampling period; δ m Indicates the correction value of the mth sampling period; D out_m Indicates the data outflow of the first-level cache in the mth sampling period; D th Indicates the preset threshold value of the first-level cache in each sampling period; the preset threshold value is 70% to 80% of the maximum single-cycle inter-frame data interaction volume of the first-level cache in each sampling period; DIF m Indicates the total amount of data cached by the exchange chip at the end of the mth sampling period.

5. The multi-subframe cascade device data caching method according to claim 1, wherein: The modified TRIX indicator is calculated using the following formula: M_TRIX m = THREE m +δ m in, m represents the period number of the current sampling period; M_TRIX m Indicates the mth sampling period for TRIX m Corrected value; TRIX m The TRIX indicator represents the amount of data flowing out of the L1 cache during the mth sampling period. δ m Indicates the correction value of the mth sampling period.

6. The multi-subframe cascade device data caching method according to claim 1, wherein: The TRMA indicator is calculated using the following formula: Among them, TRMAm represents the TRIX of the mth sampling period m Moving average of the value over M specified periods; M represents the calculation of TRIX m The specified number of periods; m represents the period number of the current sampling period; TRIXi represents the TRIX value of the L1 cache data outflow in the i-th sampling period.

7. The multi-subframe cascade device data caching method according to claim 1, wherein: The period is calculated using the following formula: in, T represents the duration of the sampling period; Cach_total represents the storage space capacity of the first-level cache; Rated indicates the maximum inter-chassis data communication rate per second of the L1 cache in each sampling period. N represents the number of lookback periods for calculating the TRIX indicator.

8. The multi-subframe cascade device data caching method according to claim 1, wherein: The method further comprises: After the secondary cache is enabled, when data is sent to the control disk, the data is stored in the secondary cache and preprocessed. Then, the preprocessed data is stored from the secondary cache to the primary cache according to the maximum inter-frame data communication rate per second of the primary cache in each sampling period, and the control disk extracts the corresponding data from the primary cache. After closing the secondary cache, when sending data to the control disk, the data is stored in the primary cache, and the control disk extracts the corresponding data from the primary cache; The control disk sends data outward through the first-level cache at a transmission rate that does not exceed the maximum rate of inter-frame data communication per second in each preset sampling period.

9. The multi-subframe cascade device data caching method according to claim 8, characterized in that: The method further comprises: The pre-processing includes classifying the data and then merging and compressing each type of data.

10. A multi-subframe cascade device data cache system, characterized in that: The system comprises: The data collection module is used to collect the data inflow of the switch chip, the data outflow of the first-level cache, and the total data cache of the switch chip for each sub-frame in each sampling period; A data processing module is configured to calculate a triple exponential moving average (TRIX) indicator of the data outflow volume of the first-level cache in the current sampling period based on the number of the current sampling period, the number of the lookback period, and the data outflow volume of the first-level cache in each sampling period. The TRIX indicator is used to represent the trend of the data outflow volume change of the first-level cache in the current sampling period. A data processing module is configured to calculate a correction value of the TRIX indicator in the current sampling period and a corrected TRIX indicator based on the number of the current sampling period, the data outflow volume of the first-level cache, the total amount of the data cache of the switch chip, and the preset threshold value of the data outflow volume of the first-level cache in each sampling period. The correction value is positively correlated with the data outflow volume and the total amount of the data cache, and negatively correlated with the preset threshold value. A triangular moving average (TRMA) indicator of the TRIX indicator in a specified period is calculated based on the number of the current sampling period and the TRIX indicator. A cache management module is used to start the secondary cache of the sub-frame and use the primary cache and the secondary cache to store data when the data outflow from the primary cache exceeds the preset threshold value in multiple consecutive sampling periods and the corrected TRIX indicator is greater than the TRMA indicator; when the corrected TRIX indicator is not greater than the TRMA indicator, close the secondary cache of the sub-frame and use the primary cache to store data.

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