Semiconductor structure and method for forming the same

Abstract

This disclosure relates to the field of semiconductor technology, specifically to a semiconductor structure and a method for forming the same. The method comprises: providing a substrate including a bitline material layer; forming a polysilicon layer on a surface of the bitline material layer; etching the polysilicon layer and the bitline material layer to form a plurality of silicon nanowires and a bitline structure located beneath the plurality of silicon nanowires; ion-treating the plurality of silicon nanowires to form a plurality of amorphous silicon pillars; and recrystallizing the plurality of amorphous silicon pillars to form a plurality of single-crystal silicon pillars. The disclosed method can simplify the process, reduce structural defects, and improve product yield.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] 3D Dynamic Random Access Memory (3D DRAM) is widely used in mobile devices such as mobile phones and tablets due to its advantages such as small size, high integration, and fast transmission speed. However, the silicon pillar manufacturing process for 3D DRAM is relatively difficult and prone to structural defects due to process limitations, resulting in low product yield.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the Invention

[0004] In view of this, the present disclosure provides a semiconductor structure and a method for forming the same, which can simplify the process, reduce structural defects, and improve product yield.

[0005] According to one aspect of the present disclosure, a method for forming a semiconductor structure is provided, comprising:

[0006] providing a substrate, the substrate comprising a bit line material layer;

[0007] forming a polysilicon layer on a surface of the bit line material layer;

[0008] Etching the polysilicon layer and the bit line material layer to form a plurality of silicon nanowires and a bit line structure located below the plurality of silicon nanowires;

[0009] performing ion treatment on the plurality of silicon nanowires to form a plurality of amorphous silicon pillars;

[0010] The plurality of amorphous silicon pillars are recrystallized to form a plurality of single crystal silicon pillars.

[0011] In an exemplary embodiment of the present disclosure, some of the single crystal silicon pillars in the plurality of single crystal silicon pillars have different crystal orientations.

[0012] In an exemplary embodiment of the present disclosure, a plurality of the silicon nanowires form a plurality of semiconductor pillar groups spaced apart along a first direction, the semiconductor pillar groups include a plurality of silicon nanowires spaced apart along a second direction, and a bit line structure is formed below each semiconductor pillar group; the first direction intersects the second direction; and the polysilicon layer and the bit line material layer are etched to form silicon nanowires and a bit line structure located below the silicon nanowires, including:

[0013] Etching the polysilicon layer and the bit line material layer to form a plurality of first trenches spaced apart along the first direction and extending along the second direction, wherein the first trenches penetrate the polysilicon layer and the bit line material layer;

[0014] forming a first isolation structure in the first trench, wherein the first isolation structure fills the first trench;

[0015] Etching the polysilicon layer and the first isolation structure to form a plurality of second trenches divided along the second direction and extending along the first direction, wherein the second trenches do not penetrate the polysilicon layer, and the second trenches and the first trenches divide the polysilicon layer into the plurality of silicon nanowires;

[0016] A second isolation structure is formed in the second trench, and the second isolation structure fills the second trench, wherein the second isolation structure and the remaining first isolation structure together form a shallow trench isolation structure.

[0017] In an exemplary embodiment of the present disclosure, forming the polysilicon layer includes:

[0018] forming a polysilicon material layer on a surface of the bit line material layer;

[0019] performing thermal annealing on the polysilicon material layer at a first preset temperature and a first preset time to form the polysilicon layer, wherein the unit cell size of the polysilicon layer is in the micrometer order;

[0020] The first preset temperature includes 500° C. to 600° C., and the first preset time includes 2 hours to 10 hours.

[0021] In an exemplary embodiment of the present disclosure, the height of the silicon nanowires is 80 nm to 150 nm in a direction perpendicular to the substrate; and ion treatment is performed on the silicon nanowires to form amorphous silicon pillars, comprising:

[0022] The silicon nanowires are bombarded with ions having a preset energy, wherein the preset energy includes 10keV-100keV.

[0023] In an exemplary embodiment of the present disclosure, the amorphous silicon pillars are recrystallized to form single crystal silicon pillars, comprising:

[0024] performing annealing treatment on the amorphous silicon pillars at a second preset temperature and a second preset time to convert the amorphous silicon pillars into single crystal silicon pillars;

[0025] The second preset temperature is 550° C. to 650° C., and the second preset time is 3 hours to 8 hours.

[0026] According to one aspect of the present disclosure, 7. The formation method according to any one of the above items is provided, further comprising:

[0027] Etching the shallow trench isolation structure to expose at least a portion of the sidewall of the single crystal silicon pillar;

[0028] forming a gate oxide layer on the surface of the exposed sidewall of the single crystal silicon pillar;

[0029] A gate electrode layer is formed on the surface of the gate oxide layer.

[0030] In an exemplary embodiment of the present disclosure, the forming method further includes:

[0031] A passivation layer is formed on the surface of the gate electrode layer, and the passivation layer fills the gap between two adjacent single crystal silicon pillars.

[0032] According to one aspect of the present disclosure, there is provided a semiconductor structure comprising:

[0033] A bit line structure comprising a bit line material layer and a polysilicon layer located on a surface of the bit line material layer;

[0034] A plurality of single crystal silicon pillars are all located on a surface of the polysilicon layer away from the bit line material layer, and some of the single crystal silicon pillars have different crystal orientations.

[0035] In an exemplary embodiment of the present disclosure, the plurality of single crystal silicon columns form a plurality of single crystal silicon column groups spaced apart along a first direction, the single crystal silicon column groups include a plurality of single crystal silicon columns spaced apart along a second direction, a bit line structure is formed under each of the single crystal silicon column groups, and the first direction intersects with the second direction.

[0036] In an exemplary embodiment of the present disclosure, the semiconductor structure further includes:

[0037] a gate oxide layer, located on the sidewall surface of the single crystal silicon pillar;

[0038] The gate electrode layer is located on the surface of the gate oxide layer.

[0039] In an exemplary embodiment of the present disclosure, the semiconductor structure further includes:

[0040] The shallow trench isolation structure fills the gap between two adjacent bit line structures and the gap between the single crystal silicon pillars.

[0041] The method for forming a semiconductor structure disclosed herein, on the one hand, can form a polysilicon layer on the surface of a bit line material layer. In the process of forming silicon nanowires, the bit line material layer and the polysilicon layer can be etched simultaneously to form a bit line structure. In the above process, there is no need to first form silicon nanowires and then bury the bit lines under the silicon nanowires, which helps to reduce the difficulty of the process. On the other hand, since polysilicon cells are usually large, most of the silicon nanowires formed after etching the polysilicon layer are located in the polysilicon cells. After ion treatment of the silicon nanowires, amorphous silicon pillars can be obtained. During the recrystallization process of the amorphous silicon pillars, the inside of the amorphous silicon pillars will naturally grow epitaxially into single crystal silicon. Even if a small number of silicon nanowires are located on the polysilicon grain boundaries, during the recrystallization process, the grain boundaries will grow along the amorphous silicon pillars. In this process, since the lateral size of the amorphous silicon pillars is relatively small, the grain boundaries will end at the boundaries of the amorphous silicon pillars after growing a very short distance, and the other parts will grow in the form of single crystals, thereby obtaining single crystal silicon pillars. During the above process, the probability of structural defects occurring in the single crystal silicon column is low, which helps to improve product yield.

[0042] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0044] Figure 1 Flowchart of a method for forming a semiconductor structure in an embodiment of the present disclosure.

[0045] Figure 2 Schematic diagram of the substrate and polysilicon layer in an embodiment of the present disclosure.

[0046] Figure 3 This is a top view after step S130 is completed in the embodiment of the present disclosure.

[0047] Figure 4 In the embodiment of the present disclosure, step S130 is completed. Figure 3 Cross-sectional view taken along the aa' direction.

[0048] Figure 5 In the embodiment of the present disclosure, step S130 is completed. Figure 3 Cross-sectional view taken along the bb' direction.

[0049] Figure 6It is a top view after completing step S310 in the embodiment of the present disclosure.

[0050] Figure 7 This is a top view after step S320 is completed in the embodiment of the present disclosure.

[0051] Figure 8 This is a top view after step S340 is completed in the embodiment of the present disclosure.

[0052] Figure 9 In the embodiment of the present disclosure, step S340 is completed. Figure 8 Cross-sectional view taken along the aa' direction.

[0053] Figure 10 Schematic diagram of an amorphous silicon column in an embodiment of the present disclosure.

[0054] Figure 11 Schematic diagram of a single crystal silicon column in an embodiment of the present disclosure.

[0055] Figure 12 Schematic diagram of the gate trench in an embodiment of the present disclosure.

[0056] Figure 13 Schematic diagram of the gate oxide layer and the gate electrode layer in the embodiment of the present disclosure.

[0057] Figure 14 1 is a top view of the gate oxide layer and the gate electrode layer in the embodiment of the present disclosure.

[0058] Description of reference numerals:

[0059] 1. Substrate; 11. Base; 12. Dielectric layer; 13. Bit line material layer; 2. Polysilicon layer; 21. Silicon nanowire; 22. Amorphous silicon pillar; 23. Single crystal silicon pillar; 201. First trench; 202. Second trench; 3. Shallow trench isolation structure; 31. First isolation structure; 32. Second isolation structure; 33. Passivation layer; 301. Gate trench; 100. Bit line structure; 200. Semiconductor pillar group; 4. Gate oxide layer; 5. Gate electrode layer; x, first direction; y, second direction. DETAILED DESCRIPTION

[0060] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0061] Although relative terms such as "upper" and "lower" are used in this specification to describe the relationship of one illustrated component to another, these terms are used herein for convenience only, such as in accordance with the orientation of the illustrations in the accompanying drawings. It will be understood that if the illustrated device were flipped upside down, the component described as "upper" would become the component "lower." When a structure is referred to as "on" another structure, this may mean that the structure is integrally formed with the other structure, that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via the other structure.

[0062] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.; the terms "first" and "second" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0063] The following two approaches are commonly used in the fabrication of vertical nanowire transistors in memory: 1) In the 4F2DRAM process, silicon nanowires are first formed on a silicon substrate, and then the bitline structure is embedded at the bottom of the silicon nanowires. However, embedding the bitline structure from above the silicon nanowires is a process that is more difficult. 2) In the 3D DRAM process, multi-layer silicon pillar structures are typically formed on a silicon substrate through epitaxial growth. However, as the number of layers grown increases, the process becomes more difficult, and the defect density of the formed silicon pillars increases, resulting in lower product yields.

[0064] Based on this, the present disclosure provides a method for forming a semiconductor structure. Figure 1 A flow chart showing a method for forming a semiconductor structure of the present disclosure is shown in FIG. Figure 1 As shown, the forming method includes steps S110 to S150, wherein:

[0065] Step S110, providing a substrate, wherein the substrate includes a bit line material layer;

[0066] Step S120, forming a polysilicon layer on the surface of the bit line material layer;

[0067] Step S130, etching the polysilicon layer and the bit line material layer to form a plurality of silicon nanowires and a bit line structure located below the plurality of silicon nanowires;

[0068] Step S140, performing ion treatment on the plurality of silicon nanowires to form a plurality of amorphous silicon pillars;

[0069] Step S150 , recrystallizing the plurality of amorphous silicon pillars to form a plurality of single crystal silicon pillars.

[0070] The method for forming a semiconductor structure disclosed herein, on the one hand, can form a polysilicon layer on the surface of a bit line material layer. During the process of forming silicon nanowires, the bit line material layer and the polysilicon layer can be etched simultaneously to form a bit line structure. In the above process, there is no need to first form silicon nanowires and then bury the bit lines under the silicon nanowires, which helps to reduce the difficulty of the process. On the other hand, since polysilicon cells are usually large, most of the silicon nanowires formed after etching the polysilicon layer are located within the polysilicon cells. After ion treatment of the silicon nanowires, amorphous silicon pillars can be obtained. During the process of recrystallization of the amorphous silicon pillars, the amorphous silicon pillars can be formed into single crystal silicon pillars on the polysilicon cells by, for example, low-temperature solid phase epitaxy. Even if a small portion of the silicon nanowires is located on the polysilicon grain boundaries, during the recrystallization process, the grain boundaries will grow along the amorphous silicon pillars. In this process, due to the relatively small lateral size of the amorphous silicon pillars, the grain boundaries will terminate at the boundaries of the amorphous silicon pillars after growing a very short distance, and the remaining portions will grow in the form of single crystals, thereby obtaining single crystal silicon pillars. During the above process, the probability of structural defects occurring in the single crystal silicon column is low, which helps to improve product yield.

[0071] The following is a detailed description of the steps and details of the method for forming a semiconductor structure disclosed herein:

[0072] like Figure 1 As shown, in step S110 , a substrate is provided, wherein the substrate includes a bit line material layer.

[0073] In some embodiments of the present disclosure, Figure 2 As shown, the substrate 1 may include a base 11, a dielectric layer 12, and a bit line material layer 13, wherein: the base 11 may be a flat plate structure, which may be rectangular, circular, elliptical, polygonal, or irregular in shape. The base 11 may be a carrier, a wafer, or a structure after any process in the semiconductor manufacturing process. The shape and material of the base 11 are not particularly limited here. The dielectric layer 12 may cover the surface of the base 11. The material of the dielectric layer 12 may be an insulating material, for example, the material may be silicon oxide. The dielectric layer 12 may be formed on the surface of the base 11 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The bit line material layer 13 is located on the surface of the dielectric layer 12 and can be used to form a bit line structure. The material of the bit line material layer 13 may be a conductive material, for example, the material may include titanium nitride and / or tungsten. The bit line material layer 13 can be formed on the surface of the dielectric layer 12 by chemical vapor deposition, physical vapor deposition or atomic layer deposition. Of course, the bit line material layer 13 can also be formed by other methods. The formation method of the bit line material layer 13 is not particularly limited here.

[0074] like Figure 1As shown, in step S120 , a polysilicon layer 2 is formed on the surface of the bit line material layer 13 .

[0075] Please continue to see Figure 2 As shown, the polysilicon layer 2 can be a thin film covering the surface of the bit line material layer 13, or it can be a coating covering the surface of the bit line material layer 13. The specific form of the polysilicon layer 2 is not particularly limited herein. The polysilicon layer 2 can be formed on the surface of the bit line material layer 13 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Of course, the polysilicon layer 2 can also be formed by other methods. The method for forming the polysilicon layer 2 is not particularly limited herein. In some embodiments of the present disclosure, the thickness of the polysilicon layer 2 can be 100nm~200nm. For example, its thickness can be 100nm, 120nm, 140nm, 160nm, 180nm or 200nm. Of course, it can also be other thicknesses, which are not listed here.

[0076] In an exemplary embodiment of the present disclosure, forming the polysilicon layer 2 may include steps S210 and S220, wherein:

[0077] Step S210 , forming a polysilicon material layer on the surface of the bit line material layer 13 .

[0078] The material of the polysilicon material layer can be polysilicon, and polysilicon can be deposited on the surface of the bit line material layer 13 by chemical vapor deposition, physical vapor deposition or atomic layer deposition to form a polysilicon material layer. Of course, the polysilicon material layer can also be formed by other methods. The formation method of the polysilicon material layer is not specifically limited here.

[0079] Step S220 , thermally annealing the polysilicon material layer at a first preset temperature and a first preset time to form the polysilicon layer 2 , wherein the unit cell size of the polysilicon layer 2 is in the micrometer order.

[0080] The unit cell size in the polysilicon material layer can be controlled by thermal annealing. For example, the polysilicon material layer can be thermally annealed at a first preset temperature and a first preset time to make the unit cells in the polysilicon material layer grow to the micron level. The first preset temperature may include 500°C to 600°C. For example, it may be 500°C, 520°C, 540°C, 560°C, 580°C or 600°C. Of course, it can also be other temperatures, which are not listed here one by one. The first preset time may include 2h to 10h. For example, it can be 2h, 4h, 6h, 8h or 10h. Of course, it can also be other times, which are not listed here one by one. It should be noted that the polysilicon material layer after thermal annealing can be used as the polysilicon layer 2.

[0081] like Figure 1As shown, in step S130 , the polysilicon layer 2 and the bit line material layer 13 are etched to form a plurality of silicon nanowires 21 and a bit line structure 100 located below the plurality of silicon nanowires 21 .

[0082] like Figure 3-Figure 5 As shown, the polysilicon layer 2 and the bitline material layer 13 located below the polysilicon layer 2 can be etched through a dry etching process, thereby forming a plurality of silicon nanowires 21 distributed in an array within the polysilicon layer 2. During this process, a bitline structure 100 can also be formed below the silicon nanowires 21. For example, the plurality of silicon nanowires 21 can form a plurality of semiconductor pillar groups 200 spaced apart along a first direction x. Each semiconductor pillar group 200 can include a plurality of silicon nanowires 21 spaced apart along a second direction y, and a bitline structure 100 is formed below each semiconductor pillar group 200. The first direction x and the second direction y intersect; for example, the first direction x and the second direction y can be perpendicular to each other. It should be noted that perpendicular can mean absolutely perpendicular or approximately perpendicular, and deviations are inevitable during the manufacturing process. In the present disclosure, the angle between the first direction x and the second direction y may have a certain deviation due to angular deviation caused by manufacturing process limitations. As long as the angular deviation between the first direction x and the second direction y is within a predetermined range, the first direction x and the second direction y can be considered perpendicular. For example, the preset range may be 10°, that is, when the angle between the first direction x and the second direction y is greater than or equal to 80° and less than or equal to 100°, the first direction x and the second direction y may be considered perpendicular.

[0083] In an exemplary embodiment of the present disclosure, etching the polysilicon layer 2 and the bit line material layer 13 to form the silicon nanowire 21 and the bit line structure 100 located below the silicon nanowire 21 (i.e., step S130) may include steps S310 to S340, wherein:

[0084] In step S310 , the polysilicon layer 2 and the bit line material layer 13 are etched to form a plurality of first trenches 201 spaced apart along the first direction x and extending along the second direction y, wherein the first trenches 201 penetrate the polysilicon layer 2 and the bit line material layer 13 .

[0085] like Figure 6 As shown, a dry etching process can be used to etch the polysilicon layer 2 and the bitline material layer 13, thereby forming a plurality of first trenches 201 spaced apart along a first direction x. The etching gas can be a mixture of chlorine and argon. The first trenches 201 can be strip-shaped and extend along a second direction y. In a direction perpendicular to the substrate 1, the first trenches 201 can penetrate the polysilicon layer 2 and the bitline material layer 13; in the second direction y, the first trenches 201 can penetrate both the polysilicon layer 2 and the bitline material layer 13.

[0086] Step S320 , forming a first isolation structure 31 in the first trench 201 , wherein the first isolation structure 31 fills the first trench 201 .

[0087] like Figure 7 As shown, the material of the first isolation structure 31 can be an insulating material, for example, silicon oxide. The insulating material can be filled into the first trench 201 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition, thereby forming the first isolation structure 31 in the first trench 201. Of course, the first isolation structure 31 can also be formed by other methods, and the method for forming the first isolation structure 31 is not particularly limited herein. In some embodiments of the present disclosure, the first isolation structure 31 can completely fill the first trench 201, and its top surface can be flush with the top surface of the polysilicon layer 2.

[0088] In the process of forming the first isolation structure 31, for the convenience of the process, insulating material can be deposited on the surface of the polysilicon layer 2 until the insulating material fills each first groove 201 and the deposition is stopped. Subsequently, the insulating material can be planarized to remove the insulating material on the surface of the polysilicon layer 2, and the surface of the insulating material in the first groove 201 is made flush with the surface of the polysilicon layer 2. The insulating material remaining in the first groove 201 after the planarization process can be used as the first isolation structure 31.

[0089] In step S330, the polysilicon layer 2 and the first isolation structure 31 are etched to form a plurality of second grooves 202 divided along the second direction y and extending along the first direction x. The second grooves 202 do not penetrate the polysilicon layer 2. The second grooves 202 and the first grooves 201 divide the polysilicon layer 2 into a plurality of silicon nanowires 21.

[0090] Please continue to see Figure 3 As shown, the structure formed by the polysilicon layer 2 and the first isolation structure 31 can be etched using a dry etching process to form a plurality of second trenches 202 spaced apart along a second direction y. The dry etching gas used can be a mixture of chlorine and argon. The second trenches 202 can be strip-shaped and extend along a first direction x. In the first direction x, the second trenches 202 can penetrate both ends of the polysilicon layer 2. In a direction perpendicular to the substrate 1, the second trenches 202 do not penetrate the polysilicon layer 2. That is, compared to the first trenches 201, the depth of the second trenches 202 is relatively shallow, and the polysilicon layer 2 remains at the bottom of the second trenches 202. The second trenches 202 intersect with the first trenches 201, and the second trenches 202 and the first trenches 201 can separate the polysilicon layer 2 into a plurality of silicon nanowires 21 distributed in an array. The cross-section of the silicon nanowires 21 can be rectangular in a direction parallel to the substrate 1.

[0091] In some embodiments of the present disclosure, in a direction perpendicular to the substrate 1, the thickness of the polysilicon layer 2 remaining at the bottom of the second trench 202 may be 20 nm to 50 nm. For example, its thickness may be 20 nm, 30 nm, 40 nm, or 50 nm. Of course, other thicknesses are also possible and are not listed here. In some embodiments of the present disclosure, in a direction perpendicular to the substrate 1, the height of the silicon nanowire 21 may be 80 nm to 150 nm. For example, its height may be 80 nm, 100 nm, 120 nm, 140 nm, or 150 nm. In a direction parallel to the substrate 1, the lateral dimension of the silicon nanowire 21 is less than 10 nm. Of course, the silicon nanowire 21 may also have other dimensions and are not listed here.

[0092] It should be noted that the portion of the polysilicon layer 2 above the bottom of the second trench 202 can be used as the silicon nanowire 21, and the portion below the bottom of the second trench 202 can be used as part of the bitline structure 100. That is, the bitline structure 100 can include the polysilicon layer 2 located below the semiconductor pillar group 200 composed of the silicon nanowire 21 and the bitline material layer 13 directly below the polysilicon layer 2. Because the first trench 201 divides the bitline material layer 13 and the polysilicon layer 2 into multiple strip-shaped structures, a bitline structure 100 can be formed below each semiconductor pillar group 200. At the same time, because the first isolation structure 31 fills the first trench 201 used to divide the bitline material layer 13 and the polysilicon layer 2, adjacent bitline structures 100 can be insulated and isolated by the first isolation structure 31, thereby reducing the risk of short circuits and improving product yield.

[0093] Step S340 , forming a second isolation structure 32 in the second trench 202 , wherein the second isolation structure 32 fills the second trench 202 , wherein the second isolation structure 32 and the remaining first isolation structure 31 together form a shallow trench isolation structure 3 .

[0094] like Figure 8 and Figure 9 As shown, the material of the second isolation structure 32 can be the same as that of the first isolation structure 31. For example, the material of the second isolation structure 32 and the material of the first isolation structure 31 can both be insulating materials. For example, the material of the second isolation structure 32 and the material of the first isolation structure 31 can both be silicon oxide. The insulating material can be filled into the second trench 202 by chemical vapor deposition, physical vapor deposition or atomic layer deposition, thereby forming the second isolation structure 32 in the second trench 202. Of course, the second isolation structure 32 can also be formed by other methods. The formation method of the second isolation structure 32 is not particularly limited here. In some embodiments of the present disclosure, such as Figure 9As shown, the second isolation structure 32 may fill the second trench 202 , and the top surface thereof may be flush with the top surface of the polysilicon layer 2 .

[0095] In the process of forming the first isolation structure 31, for the convenience of the process, insulating material can be deposited on the surface of the structure jointly formed by the polysilicon layer 2 and the first isolation structure 31 until the deposition is stopped after the insulating material fills each second trench 202. Subsequently, the insulating material can be flattened to remove the insulating material located on the surface of the polysilicon layer 2 and the first isolation structure 31, and the surface of the insulating material located in the second trench 202 is made flush with the surface of the polysilicon layer 2. The insulating material remaining in the second trench 202 after the flattening treatment can be used as the second isolation structure 32.

[0096] like Figure 1 As shown, in step S140 , ion treatment is performed on the plurality of silicon nanowires 21 to form a plurality of amorphous silicon pillars 22 .

[0097] like Figure 10 As shown, the silicon nanowires 21 can be ion-treated by ion bombardment, thereby converting the silicon nanowires 21 into amorphous silicon pillars 22. For example, ions having a preset energy can be used to bombard the silicon nanowires 21. The ions can be silicon ions, germanium ions, or arsenic ions. The preset energy can include 10keV to 100keV, for example, 10keV, 30keV, 50keV, 70keV, 90keV, or 100keV. Of course, other energies are also possible and are not listed here. It should be noted that multiple silicon nanowires 21 can be ion-treated simultaneously, thereby forming multiple amorphous silicon pillars 22 simultaneously.

[0098] like Figure 1 As shown, in step S150 , the plurality of amorphous silicon pillars 22 are recrystallized to form a plurality of single crystal silicon pillars 23 .

[0099] like Figure 11As shown, in some embodiments of the present disclosure, amorphous silicon pillars 22 can be recrystallized through low-temperature solid-phase epitaxy, thereby converting them into single-crystal silicon pillars 23. During the recrystallization process, since polycrystalline silicon unit cells are typically large, most of the silicon nanowires 21 formed after etching the polycrystalline silicon layer 2 are located within the polycrystalline silicon unit cells. Ion treatment of the silicon nanowires 21 results in amorphous silicon pillars 22. During the recrystallization process of the amorphous silicon pillars 22, the interior of the amorphous silicon pillars 22 naturally undergoes epitaxial growth to form single-crystal silicon. Even if a small portion of the silicon nanowires 21 is located on the polycrystalline silicon grain boundaries, the grain boundaries will grow along the amorphous silicon pillars 22 during the recrystallization process. During this process, due to the relatively small lateral dimensions of the amorphous silicon pillars 22, the grain boundaries will terminate at the boundaries of the amorphous silicon pillars 22 after a very short growth distance, while the remaining portion will grow as a single crystal, thereby obtaining single-crystal silicon pillars 23. In this process, the probability of structural defects in the single-crystal silicon pillars 23 is low, which helps to improve product yield.

[0100] In an exemplary embodiment of the present disclosure, the amorphous silicon column 22 can be annealed at a second preset temperature and a second preset time, thereby converting the amorphous silicon column 22 into a single crystal silicon column 23. The second preset temperature may include 550°C to 650°C, for example, it may be 550°C, 570°C, 590°C, 610°C, 630°C or 650°C. Of course, it can also be other temperatures, which are not listed here one by one. The second preset time may include 3h to 8h (h represents hours), for example, it can be 3h, 4h, 5h, 6h, 7h or 8h. Of course, it can also be other durations, which are not listed here one by one. It should be noted that the amorphous silicon columns 22 after annealing are basically converted into single crystal silicon columns 23.

[0101] In an exemplary embodiment of the present disclosure, multiple amorphous silicon pillars 22 can be recrystallized simultaneously to form multiple single crystal silicon pillars 23. It should be noted that some of the multiple single crystal silicon pillars 23 have different crystal orientations. For example, 2 is a seed layer. Since the polycrystalline silicon layer 2 directly below the multiple amorphous silicon pillars 22 may be derived from different unit cells, and the crystal orientations of different unit cells may be different, the single crystal silicon pillars 23 grown from different unit cells may have different crystal orientations. For example, if multiple single crystal silicon columns 23 are grown based on unit cells with two different crystal orientations, the multiple single crystal silicon columns 23 may include at least two single crystal silicon columns 23 with different crystal orientations; if multiple single crystal silicon columns 23 are grown based on unit cells with three different crystal orientations, the multiple single crystal silicon columns 23 may include at least three single crystal silicon columns 23 with different crystal orientations; if multiple single crystal silicon columns 23 are grown based on unit cells with four different crystal orientations, the multiple single crystal silicon columns 23 may include at least four single crystal silicon columns 23 with different crystal orientations, and so on.

[0102] In an exemplary embodiment of the present disclosure, the method for forming a semiconductor structure of the present disclosure may further include steps S160 to S180, wherein:

[0103] Step S160 , etching the shallow trench isolation structure 3 to expose at least a portion of the sidewall of the single crystal silicon pillar 23 .

[0104] like Figure 12 As shown, after forming the single crystal silicon pillars 23, the first isolation structure 31 and / or the second isolation structure 32 can be etched through a dry etching process or a wet etching process to form a gate trench 301 that exposes at least a portion of the sidewalls of the single crystal silicon pillars 23, so as to facilitate the subsequent formation of the gate oxide layer 4 on the sidewall surfaces of the single crystal silicon pillars 23. For example, the gate trench 301 formed after etching back the first isolation structure 31 and / or the second isolation structure 32 can expose the sidewall of the upper half of each single crystal silicon pillar 23; alternatively, the gate trench 301 formed after etching back the first isolation structure 31 and / or the second isolation structure 32 can expose the entire sidewall of the single crystal silicon pillar 23.

[0105] It should be noted that the etching gas or etching solution can be selected according to the specific material of the first isolation structure 31 and / or the second isolation structure 32. The etching solution or etching gas only needs to be able to etch away the first isolation structure 31 and / or the second isolation structure 32 without damaging the single crystal silicon column 23.

[0106] In step S170 , a gate oxide layer 4 is formed on the surface of the exposed sidewall of the single crystal silicon pillar 23 .

[0107] like Figure 13 As shown, the material of the gate oxide layer 4 can be silicon oxide, and the gate oxide layer 4 can be formed on the surface of the sidewall exposed in the single crystal silicon pillar 23 by thermal oxidation, in-situ water vapor oxidation or atomic layer deposition. Of course, the gate oxide layer 4 can also be formed by other methods, and the formation method of the gate oxide layer 4 is not particularly limited here. The gate oxide layer 4 can cover a portion of the surface of the sidewall exposed in the single crystal silicon pillar 23. For example, when the cross-section of the single crystal silicon pillar 23 is rectangular, the gate oxide layer 4 can cover the surface of one sidewall of the single crystal silicon pillar 23; alternatively, the gate oxide layer 4 can cover the surface of two oppositely distributed sidewalls in the single crystal silicon pillar 23; alternatively, the gate oxide layer 4 can cover the sidewall of the single crystal silicon pillar 23.

[0108] Step S180 , forming a gate electrode layer 5 on the surface of the gate oxide layer 4 .

[0109] Please continue to see Figure 13As shown, the material of the gate electrode layer 5 may be a conductive material, for example, it may include titanium nitride, tungsten or polysilicon. The gate electrode layer 5 may be formed on the surface of the gate oxide layer 4 by chemical vapor deposition, physical vapor deposition or atomic layer deposition. Of course, the gate electrode layer 5 may also be formed by other methods. The formation method of the gate electrode layer 5 is not particularly limited here. In some embodiments of the present disclosure, when the cross-section of the single crystal silicon column 23 is rectangular and the gate oxide layer 4 covers the surfaces of two oppositely distributed side walls in the single crystal silicon column 23, the gate electrode layer 5 may respectively cover the surfaces of the two gate oxide layers 4, thereby forming a dual-gate structure; or, as Figure 14 As shown, when the gate oxide layer 4 covers the sidewall of the single crystal silicon pillar 23, the gate electrode layer 5 can extend along the first direction x and wrap around the periphery of each single crystal silicon pillar 23 distributed along the first direction x, thereby forming a full-ring gate structure.

[0110] In an exemplary embodiment of the present disclosure, the method for forming a semiconductor structure of the present disclosure may further include:

[0111] In step S190 , a passivation layer 33 is formed on the surface of the gate electrode layer 5 , and the passivation layer 33 fills the gap between two adjacent single crystal silicon pillars 23 .

[0112] Please continue to see Figure 13 As shown, after forming the gate electrode layer 5, a passivation layer 33 can be formed on top of the gate electrode layer 5. The material of the passivation layer 33 is the same as that of the first isolation structure 31 and the second isolation structure 32. For example, the passivation layer 33, the first isolation structure 31, and the second isolation structure 32 can all be made of silicon oxide. The passivation layer 33 can insulate the surface of the gate electrode layer 5, which can help reduce the risk of short circuits between the gate electrode layer 5 and other subsequently formed structures, thereby improving product yield. The first isolation structure 31, the second isolation structure 32, and the passivation layer 33 can collectively constitute the shallow trench isolation structure 3.

[0113] In some embodiments of the present disclosure, the semiconductor structure formed by the semiconductor structure formation method of the present disclosure can be a 4F2 DRAM. During the 4F2 DRAM manufacturing process, a bitline material layer 13 can be first deposited, and then a polysilicon layer 2 can be formed on the surface of the bitline material layer 13 by deposition. The polysilicon layer 2 is then processed to obtain vertical single crystal silicon pillars 23. This process is relatively simple and has a low probability of defects. In other embodiments of the present disclosure, the semiconductor structure formation method of the present disclosure can be used to form a multi-layer stacked semiconductor structure, thereby obtaining a high-density 3D DRAM.

[0114] It should be noted that although the steps of the method for forming a semiconductor structure in the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all steps must be performed to achieve the desired results. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps.

[0115] The present disclosure also provides a semiconductor structure, which is formed by the method for forming a semiconductor structure in any of the above embodiments. Figure 13 and Figure 14 As shown, the semiconductor structure includes a bit line structure 100 and a plurality of single crystal silicon pillars 23, wherein:

[0116] The bit line structure 100 includes a bit line material layer 13 and a polysilicon layer 2 located on the surface of the bit line material layer 13;

[0117] The plurality of single crystal silicon pillars 23 are all located on the surface of the polysilicon layer 2 away from the bit line material layer 13 , and some of the single crystal silicon pillars 23 have different crystal orientations.

[0118] In some embodiments of the present disclosure, bitline structure 100 may be located on a substrate, which may include a base 11 and a dielectric layer 12. Base 11 may be a flat plate structure, which may be rectangular, circular, elliptical, polygonal, or irregular in shape. Base 11 may be a carrier, a wafer, or a structure that has undergone any process in the semiconductor manufacturing process. The shape and material of base 11 are not particularly limited herein. Dielectric layer 12 may cover the surface of base 11 and may be made of an insulating material, such as silicon oxide.

[0119] The bitline structure 100 can be strip-shaped and extend along the second direction y. There can be multiple bitline structures 100, and the multiple bitline structures 100 can be spaced apart along the first direction x. The bitline structure 100 can include a bitline material layer 13 and a polysilicon layer 2 located on a surface of the bitline material layer 13. The bitline material layer 13 can be a conductive material, such as titanium nitride and / or tungsten. The polysilicon layer 2 can be made of polysilicon.

[0120] The multiple single crystal silicon pillars 23 can be organized into multiple groups of single crystal silicon pillars 23 spaced apart along a first direction x. Each group of single crystal silicon pillars 23 can include multiple single crystal silicon pillars 23 spaced apart along a second direction y. A bit line structure 100 is disposed beneath each group of single crystal silicon pillars 23. Some of the multiple single crystal silicon pillars 23 have different crystal orientations. For example, the amorphous silicon pillars 22 are recrystallized using the polycrystalline silicon layer 2 directly beneath them as a seed layer. Because the polycrystalline silicon layer 2 directly beneath the multiple amorphous silicon pillars 22 may originate from different unit cells, and the crystal orientations of different unit cells may differ, the single crystal silicon pillars 23 grown from the different unit cells may have different crystal orientations. For example, if multiple single crystal silicon columns 23 are grown based on unit cells with two different crystal orientations, the multiple single crystal silicon columns 23 may include at least two single crystal silicon columns 23 with different crystal orientations; if multiple single crystal silicon columns 23 are grown based on unit cells with three different crystal orientations, the multiple single crystal silicon columns 23 may include at least three single crystal silicon columns 23 with different crystal orientations; if multiple single crystal silicon columns 23 are grown based on unit cells with four different crystal orientations, the multiple single crystal silicon columns 23 may include at least four single crystal silicon columns 23 with different crystal orientations, and so on.

[0121] In an exemplary embodiment of the present disclosure, the semiconductor structure of the present disclosure may further include a gate oxide layer 4 and a gate electrode layer 5, wherein:

[0122] The gate oxide layer 4 may be made of silicon oxide and may be located on the sidewall surfaces of the single crystal silicon pillar 23. For example, the gate oxide layer 4 may cover a portion of the sidewall surface of the single crystal silicon pillar 23. For example, when the cross-section of the single crystal silicon pillar 23 is rectangular, the gate oxide layer 4 may cover the surface of one sidewall of the single crystal silicon pillar 23; alternatively, the gate oxide layer 4 may cover the surfaces of two oppositely distributed sidewalls of the single crystal silicon pillar 23; or alternatively, the gate oxide layer 4 may cover the entire sidewall of the single crystal silicon pillar 23.

[0123] The gate electrode layer 5 is located on the surface of the gate oxide layer 4. The material of the gate electrode layer 5 can be a conductive material, for example, it can include titanium nitride, tungsten or polysilicon. In some embodiments of the present disclosure, when the cross-section of the single crystal silicon column 23 is rectangular and the gate oxide layer 4 covers the surfaces of two oppositely distributed side walls of the single crystal silicon column 23, the gate electrode layer 5 can cover the surfaces of the two gate oxide layers 4 respectively, thereby forming a dual-gate structure; alternatively, when the gate oxide layer 4 covers the side walls of the single crystal silicon column 23, the gate electrode layer 5 can extend along the first direction x and wrap around the outer periphery of each single crystal silicon column 23 distributed along the first direction x, thereby forming a full-ring gate structure.

[0124] In some embodiments of the present disclosure, the semiconductor structure of the present disclosure may further include a shallow trench isolation structure 3. The material of the shallow trench isolation structure 3 may be an insulating material, for example, silicon oxide. The shallow trench isolation structure 3 may fill the gap between two adjacent bit line structures 100, as well as the gap between each single crystal silicon pillar 23. The shallow trench isolation structure 3 may be used to insulate and isolate adjacent bit line structures 100. At the same time, the shallow trench isolation structure 3 may also be used to insulate and isolate the gate electrode layers 5 on different single crystal silicon pillars 23, thereby reducing the probability of coupling or short circuiting between different gate electrode layers 5, and also reducing the probability of coupling or short circuiting between the gate electrode layer 5 and other subsequently formed structures, thereby helping to improve product yield.

[0125] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate, the substrate comprising a bit line material layer; forming a polysilicon layer on a surface of the bit line material layer; Etching the polysilicon layer and the bit line material layer to form a plurality of silicon nanowires and a bit line structure located below the plurality of silicon nanowires; performing ion treatment on the plurality of silicon nanowires to form a plurality of amorphous silicon pillars; The plurality of amorphous silicon pillars are recrystallized to form a plurality of single crystal silicon pillars.

2. The forming method according to claim 1, wherein: Some of the single crystal silicon columns among the plurality of single crystal silicon columns have different crystal orientations.

3. The forming method according to claim 1, wherein: The plurality of silicon nanowires form a plurality of semiconductor pillar groups spaced apart along a first direction, the semiconductor pillar groups include a plurality of silicon nanowires spaced apart along a second direction, and a bit line structure is formed under each semiconductor pillar group; the first direction intersects the second direction; Etching the polysilicon layer and the bit line material layer to form a silicon nanowire and a bit line structure located below the silicon nanowire, comprising: Etching the polysilicon layer and the bit line material layer to form a plurality of first trenches spaced apart along the first direction and extending along the second direction, wherein the first trenches penetrate the polysilicon layer and the bit line material layer; forming a first isolation structure in the first trench, wherein the first isolation structure fills the first trench; Etching the polysilicon layer and the first isolation structure to form a plurality of second trenches divided along the second direction and extending along the first direction, wherein the second trenches do not penetrate the polysilicon layer, and the second trenches and the first trenches divide the polysilicon layer into the plurality of silicon nanowires; A second isolation structure is formed in the second trench, and the second isolation structure fills the second trench, wherein the second isolation structure and the remaining first isolation structure together form a shallow trench isolation structure.

4. The forming method according to any one of claims 1 to 3, characterized in that: Forming the polysilicon layer includes: forming a polysilicon material layer on a surface of the bit line material layer; performing thermal annealing on the polysilicon material layer at a first preset temperature and a first preset time to form the polysilicon layer, wherein the unit cell size of the polysilicon layer is in the micrometer order; The first preset temperature includes 500° C. to 600° C., and the first preset time includes 2 hours to 10 hours.

5. The forming method according to any one of claims 1 to 3, characterized in that: In a direction perpendicular to the substrate, the height of the silicon nanowire is 80 nm to 150 nm; The silicon nanowires are subjected to ion treatment to form amorphous silicon pillars, comprising: The silicon nanowires are bombarded with ions having a preset energy, wherein the preset energy includes 10keV-100keV.

6. The forming method according to any one of claims 1 to 3, characterized in that: Recrystallizing the amorphous silicon pillars to form single crystal silicon pillars, comprising: performing annealing treatment on the amorphous silicon pillars at a second preset temperature and a second preset time to convert the amorphous silicon pillars into single crystal silicon pillars; The second preset temperature is 550° C. to 650° C., and the second preset time is 3 hours to 8 hours.

7. The forming method according to claim 3, wherein: The forming method further comprises: Etching the shallow trench isolation structure to expose at least a portion of the sidewall of the single crystal silicon pillar; forming a gate oxide layer on the surface of the exposed sidewall of the single crystal silicon pillar; A gate electrode layer is formed on the surface of the gate oxide layer.

8. The forming method according to claim 7, wherein: The forming method further comprises: A passivation layer is formed on the surface of the gate electrode layer, and the passivation layer fills the gap between two adjacent single crystal silicon pillars.

9. A semiconductor structure, characterized in that include: A bit line structure comprising a bit line material layer and a polysilicon layer located on a surface of the bit line material layer; a plurality of single crystal silicon pillars, all located on a surface of the polysilicon layer away from the bit line material layer, and some of the single crystal silicon pillars have different crystal orientations; Wherein, the semiconductor structure is obtained by the formation method according to any one of claims 1-8.

10. The semiconductor structure according to claim 9, wherein: The plurality of single crystal silicon columns form a plurality of single crystal silicon column groups spaced apart along a first direction, the single crystal silicon column groups include a plurality of single crystal silicon columns spaced apart along a second direction, a bit line structure is formed under each of the single crystal silicon column groups, and the first direction intersects with the second direction.

11. The semiconductor structure according to claim 9, wherein: The semiconductor structure further comprises: a gate oxide layer, located on the sidewall surface of the single crystal silicon pillar; The gate electrode layer is located on the surface of the gate oxide layer.

12. The semiconductor structure according to claim 9, wherein: The semiconductor structure further comprises: The shallow trench isolation structure fills the gap between two adjacent bit line structures and the gap between the single crystal silicon pillars.

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