Method for preparing a three-dimensional dynamic random access memory array

Abstract

The present invention relates to a method for fabricating a three-dimensional dynamic random access memory array, which relates to the field of semiconductor technology and solves the stability issues faced by existing 3D DRAM structures at high integration densities. The method comprises the following steps: sequentially forming a plurality of vertically stacked layers; forming a plurality of rows of through-holes and first isolation layers alternately arranged along a first horizontal direction in the plurality of vertically stacked layers; etching the first and second dielectric layers between the through-holes along a second horizontal direction to form channel regions and isolation regions, respectively; forming a third dielectric layer; forming a channel layer and a second isolation layer in the partially filled channel regions and isolation regions, respectively; and forming bit lines and capacitors in the bit line through-holes and capacitor through-holes, respectively.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for preparing a three-dimensional dynamic random access memory array. Background Art

[0002] Dynamic random access memory (DRAM) is a commonly used computer memory technology that represents binary data by storing charge in capacitors. Because capacitors naturally discharge over time, DRAM requires periodic refreshes to maintain stored data. A DRAM memory cell typically consists of a transistor and a capacitor. Compared to static random access memory (SRAM), DRAM offers higher storage density and lower cost.

[0003] Three-dimensional DRAM (3D DRAM) is an advanced memory technology that increases storage capacity per unit area by vertically stacking memory cells, thereby improving memory density and performance. Compared to traditional two-dimensional DRAM, 3D DRAM can significantly increase storage density while maintaining or even improving data transfer rates and energy efficiency. The development of this technology is particularly important for meeting the memory needs of applications such as high-performance computing, big data storage, and artificial intelligence. 3D DRAM with vertically stacked memory cells is considered a potential development direction for the next generation of DRAM due to its higher storage density and lower cost. However, 3D DRAM solutions based on a vertical word line (WL) architecture face serious stability issues at high integration densities, such as the row hammer effect and the passing gate effect (PGE). Summary of the Invention

[0004] In view of the above analysis, embodiments of the present invention aim to provide a three-dimensional dynamic random access memory array and a method for manufacturing the same, so as to solve the stability problem faced by the existing 3D DRAM structure at high integration density.

[0005] In one aspect, an embodiment of the present invention provides a method for fabricating a three-dimensional dynamic random access memory array, comprising the following steps:

[0006] forming a plurality of vertically stacked layers in sequence, wherein each layer comprises a first electrode layer, a first dielectric layer, a second electrode layer, and a second dielectric layer in sequence, wherein the thickness of the second dielectric layer is greater than that of the first dielectric layer;

[0007] forming a plurality of rows of through holes and first isolation layers alternately arranged along a first horizontal direction in the plurality of vertically stacked stacks, wherein the through holes are alternately arranged with the stacks along a second horizontal direction, the first horizontal direction and the second horizontal direction being perpendicular to each other, and the through holes include bit line through holes and capacitor through holes alternately arranged along the second horizontal direction;

[0008] Etching the first dielectric layer and the second dielectric layer between the through holes along a second horizontal direction to form a channel region and an isolation region respectively;

[0009] forming a third dielectric layer, wherein the third dielectric layer covers the surfaces of the plurality of vertically stacked layers after etching, and the third dielectric layer partially fills the channel region and the isolation region;

[0010] A channel layer and a second isolation layer are formed in the partially filled channel region and the isolation region, respectively, and a bit line and a capacitor are formed in the bit line through hole and the capacitor through hole, respectively.

[0011] Based on a further improvement of the above preparation method, forming a plurality of rows of through holes and first isolation layers alternately arranged along a first horizontal direction in the plurality of vertically stacked layers comprises:

[0012] forming a plurality of rows of through holes alternately arranged along a first horizontal direction in the plurality of vertically stacked laminates;

[0013] forming a first isolation layer in the through hole;

[0014] The plurality of vertically stacked layers between adjacent first isolation layers in each row are etched to form through holes.

[0015] Based on a further improvement of the above preparation method, forming the third dielectric layer includes:

[0016] A high dielectric constant medium is deposited on the surfaces of the etched multiple vertically stacked layers using an atomic layer deposition process.

[0017] Based on a further improvement of the above preparation method, forming a channel layer in the partially filled channel region includes:

[0018] Depositing a channel material on the surface of the third dielectric layer using an atomic layer deposition process, wherein the channel material fills the partially filled channel area;

[0019] A wet etching process is used to remove the channel material on the surface of the third dielectric layer, leaving the channel material in the channel area.

[0020] Based on a further improvement of the above preparation method, forming a second isolation layer in the partially filled isolation area includes:

[0021] Depositing a dielectric material on the surface of the plurality of vertically stacked layers forming the channel layer using an atomic layer deposition process, wherein the dielectric material fills the partially filled isolation region;

[0022] A wet etching process is used to remove dielectric materials on surfaces of the plurality of vertically stacked layers forming the channel layer, leaving the dielectric material in the isolation region.

[0023] Based on a further improvement of the above-mentioned preparation method, forming a bit line in the bit line through hole includes:

[0024] The bit line through hole is filled with an electrode material and patterned.

[0025] Based on a further improvement of the above preparation method, the electrode material of the first electrode layer and the second electrode layer is titanium nitride.

[0026] Based on further improvement of the above preparation method, the channel material is indium gallium zinc oxide.

[0027] Based on a further improvement of the above preparation method, the material of the first dielectric layer and the second dielectric layer is silicon oxide.

[0028] Based on a further improvement of the above preparation method, the high dielectric constant medium is hafnium oxide.

[0029] Based on further improvements to the above preparation method, the thicknesses of the first electrode layer, the first dielectric layer, and the second electrode layer are 10 nanometers to 50 nanometers, and the thickness of the second dielectric layer is 50 nanometers to 150 nanometers.

[0030] Based on further improvement of the above preparation method, the thickness of the first isolation layer along the second horizontal direction is 100 nm to 300 nm, and the interval between two adjacent rows of the first isolation layers along the second horizontal direction is 500 nm to 1000 nm.

[0031] Based on further improvement of the above preparation method, the thickness of the channel layer is 1 nanometer to 20 nanometers.

[0032] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0033] 1. The present invention realizes the parallel integration of multi-layer dual-gate 1T1C (1Transistor-1Capacitor) DRAM arrays, which has 6F 2The memory cell feature size of 1 / 4N (N is the number of parallel integrated layers) has great application prospects in high-integration applications such as high-resolution displays and high-density dynamic random access memory.

[0034] 2. Compared with the 3D DRAM structure with a vertical word line architecture, the vertical bit line architecture 3D DRAM solution proposed in the present invention has a more stable sensing margin.

[0035] In the present invention, the above-mentioned technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of the present invention will be described in the following description, and some advantages will become apparent from the description or be learned through practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the contents particularly pointed out in the description and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The accompanying drawings are only used for the purpose of illustrating specific embodiments and are not to be considered as limiting the present invention. Throughout the drawings, the same reference symbols denote the same components.

[0037] Figure 1 FIG. 4 is a flow chart of a method for fabricating a three-dimensional dynamic random access memory array according to an embodiment of the present invention.

[0038] Figure 2 FIG. 4 is a conceptual 3D structural diagram illustrating a plurality of vertically stacked layers according to an embodiment of the present invention.

[0039] Figure 3 A conceptual 3D structural diagram of a through hole and a first isolation layer formed in a plurality of vertically stacked layers according to an embodiment of the present invention is shown.

[0040] Figure 4-1 to Figure 4-3 Shows the formation Figure 3 A conceptual process flow diagram of the 3D structure shown.

[0041] Figure 5-1 to Figure 5-2 FIG. 4 is a conceptual 3D structural diagram of a channel region and an isolation region formed in a plurality of vertically stacked layers according to an embodiment of the present invention.

[0042] Figure 6-1 to Figure 6-2 FIG. 4 is a conceptual 3D structural diagram of a third dielectric layer formed on a plurality of vertically stacked layers according to an embodiment of the present invention.

[0043] Figure 7-1 to Figure 7-2 FIG. 4 is a conceptual 3D structural diagram of a channel layer formed in a plurality of vertically stacked layers according to an embodiment of the present invention.

[0044] Figure 8-1 to Figure 8-2 Shows the formation Figure 7-1 to Figure 7-2 Schematic diagram of a conceptual intermediate process flow for the 3D structure shown.

[0045] Figure 9-1 to Figure 9-2 FIG. 4 is a conceptual 3D structural diagram of a second isolation layer formed in a plurality of vertically stacked layers according to an embodiment of the present invention.

[0046] Figure 10-1 to Figure 10-2 FIG. 4 is a conceptual 3D structural diagram of a bit line and a capacitor formed in a plurality of vertically stacked layers according to an embodiment of the present invention. DETAILED DESCRIPTION

[0047] The preferred embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, wherein the accompanying drawings constitute a part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, and are not used to limit the scope of the present invention.

[0048] Figure 1 FIG. 4 is a flow chart of a method for fabricating a three-dimensional dynamic random access memory array according to an embodiment of the present invention.

[0049] The following combination Figure 1 An embodiment of the present invention will be described.

[0050] like Figure 1 As shown, the method for preparing the three-dimensional dynamic random access memory array includes the following steps:

[0051] Step 101: forming a plurality of vertically stacked layers in sequence.

[0052] Figure 2 A conceptual 3D structural diagram of a plurality of vertically stacked layers according to an embodiment of the present invention is shown. Figure 2 Step 101 will be described.

[0053] In this embodiment, a repeated stacking structure of the first electrode layer / first dielectric layer / second electrode layer / second dielectric layer can be formed on the substrate by a deposition process such as magnetron sputtering, plasma enhanced chemical vapor deposition, and atomic layer deposition. Figure 2 As shown, each stacked structure of the first electrode layer / first dielectric layer / second electrode layer / second dielectric layer is a stack in this embodiment. In each stack, the thickness of the second dielectric layer is greater than the thickness of the first dielectric layer.

[0054] For example, the first electrode layer can be formed by depositing a certain thickness of electrode material on a substrate via a magnetron sputtering deposition process and then patterning it. Patterning here refers to transferring the pattern on the mask to the deposited first layer of electrode material through exposure using a photolithography process. The electrode material of the first electrode layer can be titanium nitride. The thickness of the first electrode layer can range from 10 nanometers to 50 nanometers. Preferably, the thickness of the first electrode layer is 30 nanometers.

[0055] For example, the first dielectric layer can be formed by depositing a predetermined thickness of dielectric material on the first electrode layer using a magnetron sputtering deposition process and then patterning the material. Patterning herein refers to transferring the pattern on the mask to the deposited dielectric material through exposure using a photolithography process. The dielectric material of the first dielectric layer can be silicon oxide. The thickness of the first dielectric layer can range from 10 nanometers to 50 nanometers. Preferably, the thickness of the first dielectric layer is 30 nanometers.

[0056] For example, the second electrode layer can be formed by depositing a predetermined thickness of electrode material on the first dielectric layer using a magnetron sputtering deposition process and then patterning the material. Patterning here refers to transferring the pattern on the mask to the deposited electrode material through exposure using a photolithography process. The electrode material of the second electrode layer can be titanium nitride. The thickness of the second electrode layer can range from 10 nanometers to 50 nanometers. Preferably, the thickness of the second electrode layer is 30 nanometers.

[0057] For example, the second dielectric layer can be formed by depositing a predetermined thickness of dielectric material on the second electrode layer using a magnetron sputtering deposition process and then patterning the material. Patterning herein refers to transferring the pattern on the mask to the deposited dielectric material through exposure using a photolithography process. The dielectric material of the second dielectric layer can be silicon oxide. The thickness of the second dielectric layer can range from 50 nanometers to 150 nanometers. Preferably, the thickness of the second dielectric layer is 100 nanometers.

[0058] exist Figure 2 In the embodiment, stack 1 includes, from bottom to top, a first electrode layer, a first dielectric layer, a second electrode layer, and a second dielectric layer. Stack 2 also includes, from bottom to top, a first electrode layer, a first dielectric layer, a second electrode layer, and a second dielectric layer. Figure 2 Each stack represents a stack structure of "first electrode layer / first dielectric layer / second electrode layer / second dielectric layer". The stacks are stacked together in the vertical direction to form Figure 2 The structure shown.

[0059] In other embodiments, a repeated stacking structure of electrode material / dielectric material / electrode material / dielectric material can be first deposited on a substrate by a magnetron sputtering deposition process, wherein each layer of electrode material / dielectric material has a certain thickness, and then the repeated stacking structure is patterned to obtain Figure 2 The repeated stacking structure of the first electrode layer / first dielectric layer / second electrode layer / second dielectric layer is shown.

[0060] Step 102: forming a plurality of rows of through holes and first isolation layers alternately arranged along a first horizontal direction in the plurality of vertically stacked layers.

[0061] Figure 3 A conceptual 3D structural diagram of a through hole and a first isolation layer formed in a plurality of vertically stacked layers according to an embodiment of the present invention is shown. Figure 4-1 to Figure 4-3 Shows the formation Figure 3 A conceptual process flow diagram of the 3D structure shown below. Figure 4-1 to Figure 4-3 Step 102 will be described.

[0062] Figure 4-1 The stacked structure shown in FIG1 includes 7 layers, which are the first electrode layer, the first dielectric layer, the second electrode layer, the second dielectric layer, the first electrode layer, the first dielectric layer, and the second electrode layer formed according to step 101 . Figure 4-1 The top view of the stacked structure is also shown. For the convenience of description, the following Figure 4-2 to Figure 4-3 Step 102 is described using a top view of the 7-layer stacked structure as an observation perspective.

[0063] like Figure 4-2 As shown, multiple rows of through holes spaced apart along a first horizontal direction can be etched on the seven-layer stacked structure. In this embodiment, multiple rows of through holes spaced apart along the first horizontal direction can be etched using a dry etching technique such as reactive ion etching, inductively coupled plasma etching, or magnetic neutral line plasma etching. In this embodiment, the first horizontal direction can be the horizontal direction of the top view of the seven-layer stacked structure. Figure 4-2 The second horizontal direction described below is also shown. The second horizontal direction in this embodiment can be the vertical direction of the top view of the 7-layer stacked structure. In some embodiments, Figure 4-2 The length of the through hole in the second horizontal direction is 100 nm to 300 nm. Preferably, the length of the through hole in the second horizontal direction is 200 nm. In some embodiments, Figure 4-2 The interval between two adjacent through holes in the second horizontal direction is 500 nm to 1000 nm. Preferably, the interval between two adjacent through holes in the second horizontal direction is 750 nm.

[0064] Next, if Figure 4-3As shown, the first isolation layer can be formed in the through hole by a deposition process such as magnetron sputtering, plasma enhanced chemical vapor deposition, atomic layer deposition, etc. For example, the through hole can be filled with an isolation material by a magnetron sputtering deposition process and then smoothed by a chemical mechanical polishing process to obtain the first isolation layer.

[0065] Finally, if Figure 3 As shown, the 7-layer stacked structure can be etched so that two adjacent first isolation layers along the first horizontal direction are opened up, leaving a through hole. In this embodiment, the through hole can be through in the vertical direction. In this embodiment, the through hole can be etched by dry etching techniques such as reactive ion etching, inductively coupled plasma etching, and magnetic neutral line plasma etching. Figure 3 The through holes shown in the figure are formed Figure 3 After the through holes are shown, the through holes can be marked, wherein each row of through holes (ie, along the first horizontal direction) is marked as bit line through holes or capacitor through holes, and the bit line through holes and the capacitor through holes are alternately distributed along the second horizontal direction.

[0066] Step 103 : etching the first dielectric layer and the second dielectric layer between the through holes along a second horizontal direction to form a channel region and an isolation region, respectively.

[0067] Figure 5-1 to Figure 5-2 A conceptual 3D structural diagram of a channel region and an isolation region formed in a plurality of vertically stacked layers according to an embodiment of the present invention is shown. Figure 5-1 to Figure 5-2 Step 103 will be described.

[0068] It should be noted that Figure 5-1 to Figure 5-2 Yes Figure 3 The schematic 3D structure diagram is shown for further processing. Figure 5-1 As shown, in this embodiment, the first dielectric layer and the second dielectric layer in the 7-layer stacked structure can be laterally etched along the second horizontal direction by a wet etching process, so that the through hole is connected in the second horizontal direction. Figure 5-2 FIG. 1 shows a front view of the 7-layer stacked structure after etching, viewed along the second horizontal direction. Figure 5-2 As shown, after the first dielectric layer and the second dielectric layer between the adjacent through holes in the second horizontal direction are removed, the through holes are connected in the second horizontal direction. Figure 5-1 to Figure 5-2 In the embodiment, the through hole region left after the first dielectric layer is removed is the channel region, and the through hole region left after the second dielectric layer is removed is the isolation region.

[0069] Step 104: forming a third dielectric layer.

[0070] Figure 6-1 to Figure 6-2FIG. 1 shows a conceptual 3D structural diagram of a third dielectric layer formed on a plurality of vertically stacked layers according to an embodiment of the present invention. Figure 6-1 to Figure 6-2 Step 104 will be described.

[0071] It should be noted that Figure 6-1 to Figure 6-2 Yes Figure 5-1 to Figure 5-2 In this embodiment, the 3D structure can be further processed by atomic layer deposition process. Figure 5-1 to Figure 5-2 A layer of dielectric material is deposited on the surface of the stacked structure in a wrap-around manner. Figure 6-1 The schematic diagram of the 3D structure after the wrapping deposition of a layer of dielectric material is shown. Figure 6-1 Represented by red pigment. Figure 6-2 The cross section composed of the second horizontal direction and the vertical direction Figure 6-1 It should be noted that the first horizontal direction is Figure 6-2 In the image, a certain degree of depth of field is used. Figure 6-2 As shown, the dielectric material deposited by the package is partially filled Figure 5-1 to Figure 5-2 The channel region and isolation region in Figure 5-1 to Figure 5-2 The channel region and the isolation region in the vertical direction are shortened. In some embodiments, the dielectric material deposited by the wrapping method is Figure 5-1 to Figure 5-2 The length of the channel region in the vertical direction is shortened by 10 nm to 40 nm. Figure 5-1 to Figure 5-2 The channel region in the vertical direction is shortened by 24 nanometers.

[0072] although Figure 5-1 to Figure 5-2 The channel region in Figure 6-2 The vertical direction of the shortening occurs, but Figure 6-2 The length of the channel region in the vertical direction is still greater than zero (i.e. Figure 6-2 In some embodiments, the thickness of the "gap" in is greater than zero. Figure 6-2 The thickness of the "gap" is 1 nm to 20 nm. Preferably, Figure 6-2 The thickness of the "gap" in the film is 6 nanometers.

[0073] In some embodiments, the encapsulated deposited dielectric material may be a high-k dielectric, such as hafnium oxide.

[0074] Step 105 : forming a channel layer and a second isolation layer in the partially filled channel region and the isolation region, respectively, and forming a bit line and a capacitor in the bit line through hole and the capacitor through hole, respectively.

[0075] Figure 7-1 to Figure 7-2FIG. 4 is a conceptual 3D structural diagram of a channel layer formed in a plurality of vertically stacked layers according to an embodiment of the present invention. Figure 8-1 to Figure 8-2 Shows the formation Figure 7-1 to Figure 7-2 A conceptual intermediate process flow diagram of the 3D structure shown below. Figure 8-1 to Figure 8-2 Step 105 will be described.

[0076] It should be noted that Figure 8-1 to Figure 8-2 Yes Figure 6-1 to Figure 6-2 In this embodiment, the atomic layer deposition process can be used to further process the schematic 3D structure shown in FIG. Figure 6-1 to Figure 6-2 The surface of the stacked structure shown is continuously deposited with channel material until the channel material is completely filled. Figure 6-1 to Figure 6-2 The channel region in Figure 6-1 to Figure 6-2 the “gap” in the ). Figure 8-1 The channel material is completely filled to Figure 6-1 to Figure 6-2 Schematic diagram of the 3D structure of the channel region in the Figure 8-1 Represented by green pigment. Figure 8-2 The cross section composed of the second horizontal direction and the vertical direction Figure 8-1 It should be noted that the first horizontal direction is Figure 8-2 In the image, a certain degree of depth of field is used. Figure 8-2 As shown, the channel material is completely filled to Figure 6-1 to Figure 6-2 The channel area in the middle; at the same time, the channel material is partially filled to Figure 6-1 to Figure 6-2 To achieve this effect, the thickness of the second dielectric layer needs to be set to be greater than the thickness of the first dielectric layer. In some embodiments, the channel material can be indium gallium zinc oxide.

[0077] Next, if Figure 7-1 to Figure 7-2 As shown, wet etching process can be used to remove Figure 8-1 to Figure 8-2 The channel material on the surface of the third dielectric layer is removed, leaving the channel material in the channel region, thereby obtaining a channel layer.

[0078] Figure 9-1 to Figure 9-2 FIG. 1 shows a conceptual 3D structural diagram of a second isolation layer formed in a plurality of vertically stacked layers according to an embodiment of the present invention. Figure 9-1 to Figure 9-2 Step 105 will be described.

[0079] It should be noted that Figure 9-1 to Figure 9-2 Yes Figure 7-1 to Figure 7-2 In this embodiment, the atomic layer deposition process can be used to further process the schematic 3D structure shown in FIG. Figure 7-1 to Figure 7-2 The surface of the stacked structure shown is continuously deposited with isolation material until the isolation material is completely filled. Figure 7-1 to Figure 7-2Next, a wet etching process can be used to remove the isolation material on the surface of the third dielectric layer, leaving the isolation material in the isolation area, thereby obtaining a second isolation layer. Figure 9-1 to Figure 9-2 It should be noted that the method for forming the second isolation layer is similar to the method for forming the channel layer. This article will not show the intermediate process flow diagram for forming the second isolation layer. For details, please refer to Figure 8-1 to Figure 8-2 Schematic diagram of the intermediate process flow is shown.

[0080] Figure 10-1 to Figure 10-2 FIG2 shows a conceptual 3D structure diagram of a bit line and a capacitor formed in a plurality of vertically stacked layers according to an embodiment of the present invention. Figure 10-1 to Figure 10-2 Step 105 will be described.

[0081] It should be noted that Figure 10-1 to Figure 10-2 Yes Figure 9-1 to Figure 9-2 In this embodiment, the 3D structure can be further processed by magnetron sputtering, plasma enhanced chemical vapor deposition, atomic layer deposition and other deposition processes. Figure 9-1 to Figure 9-2 The bitline vias in the stacked structure shown are filled with electrode material and patterned to form the bitline. Patterning here refers to transferring the pattern on the mask to the deposited electrode material through exposure using a photolithography process. In some embodiments, the electrode material for the bitline can be titanium nitride.

[0082] In this embodiment, deposition processes such as magnetron sputtering, plasma enhanced chemical vapor deposition, and atomic layer deposition can be used to deposit Figure 9-1 to Figure 9-2 The capacitor through hole in the stacked structure shown is filled with electrode material and patterned to obtain one electrode of the capacitor. The same process can then be used to form the dielectric layer of the capacitor and the other electrode of the capacitor on the capacitor electrode in sequence, thereby obtaining Figure 10-1 The capacitor structure is shown.

[0083] Figure 10-1 to Figure 10-2 A conceptual structural diagram of a 3D DRAM array formed by a method for preparing a three-dimensional dynamic random access memory array according to an embodiment of the present invention is also shown. Figure 10-1 to Figure 10-2 The 3D DRAM array in the embodiment of the present invention is described. Figure 10-2 The cross section composed of the second horizontal direction and the vertical direction Figure 10-1 The 3D structure in the figure is truncated into a 3D schematic diagram. Figure 10-2As shown, the 3D DRAM array consists of two layers. In the first layer, the three-layer "sandwich" structure encircled by black circles is the source, drain, and channel layer of the transistor (the green area is the channel layer). The "vertical bit line 1" on the left side of the "sandwich" structure is the first gate of the transistor. The right side of the "sandwich" structure is a capacitor electrode, which constitutes the second gate of the transistor. Therefore, the solution of the present invention is a 3D DRAM integration solution based on planar dual-gate transistors.

[0084] Compared with the prior art, the embodiments of the present invention can achieve at least one of the following beneficial effects:

[0085] 1. The present invention realizes the parallel integration of multi-layer dual-gate 1T1C (1Transistor-1Capacitor) DRAM arrays, which has 6F 2 The memory cell feature size of 1 / 4N (N is the number of parallel integrated layers) has great application prospects in high-integration applications such as high-resolution displays and high-density dynamic random access memory.

[0086] 2. Compared with the 3D DRAM structure with a vertical word line architecture, the vertical bit line architecture 3D DRAM solution proposed in the present invention has a more stable sensing margin.

[0087] The above description is only a preferred specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by any technician familiar with this technical field within the technical scope disclosed by the present invention should be covered by the scope of protection of the present invention.

Claims

1. A method for preparing a three-dimensional dynamic random access memory array, characterized in that: The steps include: forming a plurality of vertically stacked layers in sequence, wherein each layer comprises a first electrode layer, a first dielectric layer, a second electrode layer, and a second dielectric layer in sequence, wherein the thickness of the second dielectric layer is greater than that of the first dielectric layer; forming a plurality of rows of through holes and first isolation layers alternately arranged along a first horizontal direction in the plurality of vertically stacked stacks, wherein the through holes are alternately arranged with the stacks along a second horizontal direction, the first horizontal direction and the second horizontal direction being perpendicular to each other, and the through holes include bit line through holes and capacitor through holes alternately arranged along the second horizontal direction; Etching the first dielectric layer and the second dielectric layer between the through holes along a second horizontal direction to form a channel region and an isolation region respectively; forming a third dielectric layer, wherein the third dielectric layer covers the surfaces of the plurality of vertically stacked layers after etching, and the third dielectric layer partially fills the channel region and the isolation region; A channel layer and a second isolation layer are formed in the partially filled channel region and the isolation region, respectively, and a bit line and a capacitor are formed in the bit line through hole and the capacitor through hole, respectively.

2. The preparation method according to claim 1, characterized in that Forming a plurality of rows of through holes and first isolation layers alternately arranged along a first horizontal direction in the plurality of vertically stacked layers comprises: forming a plurality of rows of through holes alternately arranged along a first horizontal direction in the plurality of vertically stacked laminates; forming a first isolation layer in the through hole; The plurality of vertically stacked layers between adjacent first isolation layers in each row are etched to form through holes.

3. The preparation method according to claim 1, characterized in that The forming of the third dielectric layer comprises: A high dielectric constant medium is deposited on the surfaces of the etched multiple vertically stacked layers using an atomic layer deposition process.

4. The preparation method according to claim 1, characterized in that Forming a channel layer in the partially filled channel region includes: Depositing a channel material on the surface of the third dielectric layer using an atomic layer deposition process, wherein the channel material fills the partially filled channel area; A wet etching process is used to remove the channel material on the surface of the third dielectric layer, leaving the channel material in the channel area.

5. The preparation method according to claim 1, characterized in that Forming a second isolation layer at the partially filled isolation region includes: Depositing a dielectric material on the surface of the plurality of vertically stacked layers forming the channel layer using an atomic layer deposition process, wherein the dielectric material fills the partially filled isolation region; A wet etching process is used to remove dielectric materials on surfaces of the plurality of vertically stacked layers forming the channel layer, leaving the dielectric material in the isolation region.

6. The preparation method according to claim 1, characterized in that Forming a bit line in the bit line through hole includes: The bit line through hole is filled with an electrode material and patterned.

7. The preparation method according to claim 1, characterized in that The electrode material of the first electrode layer and the second electrode layer is titanium nitride.

8. The preparation method according to claim 4, characterized in that The channel material is indium gallium zinc oxide.

9. The preparation method according to claim 1, characterized in that The material of the first dielectric layer and the second dielectric layer is silicon oxide.

10. The preparation method according to claim 3, characterized in that The high dielectric constant medium is hafnium oxide.

11. The preparation method according to claim 1, characterized in that The thickness of the first electrode layer, the first dielectric layer and the second electrode layer is 10 nanometers to 50 nanometers, and the thickness of the second dielectric layer is 50 nanometers to 150 nanometers.

12. The preparation method according to claim 1, characterized in that The thickness of the first isolation layer along the second horizontal direction is 100 nanometers to 300 nanometers, and the interval between two adjacent rows of the first isolation layer along the second horizontal direction is 500 nanometers to 1000 nanometers.

13. The preparation method according to claim 1, characterized in that The thickness of the channel layer is 1 nanometer to 20 nanometers.

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