Pixel circuit, driving method and display device

Abstract

The application provides a pixel circuit, a driving method and a display device. The pixel circuit comprises a driving circuit, a first on-off control circuit, a light emitting element, a second on-off control circuit, a first control circuit and a second control circuit; the first on-off control circuit controls the connection or disconnection between the second node and the third node under the control of the potential of the first control node; the second on-off control circuit controls the connection or disconnection between the second electrode of the light emitting element and the first voltage end under the control of the potential of the second control node; the first control circuit controls the potential of the first control node according to the first time control data voltage under the control of the first control signal; and the second control circuit controls the potential of the second control node according to the second time control data voltage under the control of the second control signal. Different gray scales are realized by the cooperation of current regulation and light emitting time regulation.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a pixel circuit, a driving method and a display device. BACKGROUND

[0002] With the listing and promotion of Mini LED (Mini Light Emitting Diode) direct display products, Micro LED (Micro Light Emitting Diode) display technology is also imminent. The photoelectric characteristics of Micro LED and Mini LED are high photoelectric conversion efficiency under high current density, low photoelectric conversion efficiency under low current density, and different brightness between LED chips (chips) under low current density, as well as color shift characteristics. As the size of LED decreases from Mini LED to Micro LED level, the proportion of photoelectric efficiency decline caused by defects in LED process will be amplified, resulting in low efficiency of Micro LED. The low photoelectric efficiency of Micro LED and the problems of color and brightness under low current density result in that the pixel driving circuit used by Mini LED cannot be directly applied, and the corresponding pixel circuit needs to be developed according to the characteristics of Micro LED. SUMMARY

[0003] In one aspect, the embodiment of the present application provides a pixel circuit, comprising a driving circuit, a first on-off control circuit, a light emitting element, a second on-off control circuit, a first control circuit and a second control circuit;

[0004] The first end of the driving circuit is electrically connected with a first node, and the second end of the driving circuit is electrically connected with a second node; the driving circuit is used for generating a driving current for driving the light emitting element under the control of the potential at the control end thereof;

[0005] The first on-off control circuit is used for controlling the communication or disconnection between the second node and a third node under the control of the potential at the first control node;

[0006] The first pole of the light emitting element is electrically connected with the third node;

[0007] The second on-off control circuit is used for controlling the communication or disconnection between the second pole of the light emitting element and a first voltage end under the control of the potential at the second control node;

[0008] The first control circuit is electrically connected with a first control end, a data line, a first light emitting time control end, a second light emitting time control end and the first control node respectively, and is used for controlling the communication between the first light emitting time control end or the second light emitting time control end and the first control node under the control of the first control signal provided by the first control end according to the first time control data voltage provided by the data line.

[0009] The second control circuit is electrically connected with the second control end, the data line, the second light-emitting time control end, the third light-emitting time control end and the second control node respectively, and is used for controlling the second light-emitting time control end or the third light-emitting time control end to be in communication with the second control node under the control of a second control signal provided by the second control end and according to a second time control data voltage provided by the data line.

[0010] Optionally, the first control circuit comprises a first write-in circuit, a first energy storage circuit, a first switch control circuit and a second switch control circuit.

[0011] The first write-in circuit is electrically connected with the first control end, the data line and a first switch node respectively, and is used for writing the first time control data voltage into the first switch node under the control of a first control signal provided by the first control end.

[0012] The first energy storage circuit is electrically connected with the first switch node, and is used for maintaining the potential of the first switch node.

[0013] The first switch control circuit is electrically connected with the first switch node, the second light-emitting time control end and the first control node respectively, and is used for controlling the first control node to be in communication or disconnected with the second light-emitting time control end under the control of the potential of the first switch node.

[0014] The second switch control circuit is electrically connected with the first switch node, the first light-emitting time control end and the first control node respectively, and is used for controlling the first control node to be in communication or disconnected with the first light-emitting time control end under the control of the potential of the first switch node.

[0015] Optionally, the second control circuit comprises a second write-in circuit, a second energy storage circuit, a third switch control circuit and a fourth switch control circuit.

[0016] The second write-in circuit is electrically connected with the second control end, the data line and a second switch node respectively, and is used for writing the second time control data voltage provided by the data line into the second switch node under the control of a second control signal provided by the second control end.

[0017] The second energy storage circuit is electrically connected with the second switch node, and is used for maintaining the potential of the second switch node.

[0018] The third switch control circuit is electrically connected with the second switch node, the third light-emitting time control end and the second control node respectively, and is used for controlling the second control node and the third light-emitting time control end to be in communication or disconnected under the control of the potential of the second switch node.

[0019] The fourth switch control circuit is electrically connected with the second switch node, the second light-emitting time control end and the second control node respectively, and is used for controlling the second control node and the second light-emitting time control end to be in communication or disconnected under the control of the potential of the second switch node.

[0020] Optionally, the first control circuit comprises a third write-in circuit, a fourth write-in circuit, a fifth switch control circuit, a sixth switch control circuit, a third energy storage circuit and a fourth energy storage circuit; and the first control end comprises a first reset control end and a second reset control end.

[0021] The third write-in circuit is electrically connected with the first reset control end, the data line and the third switch node respectively, and is used for writing third time control data voltage provided by the data line into the third switch node under the control of a first reset control signal provided by the first reset control end.

[0022] The third energy storage circuit is electrically connected with the third switch node, and is used for maintaining the potential of the third switch node.

[0023] The fourth write-in circuit is electrically connected with the second reset control end, the data line and the fourth switch node respectively, and is used for writing fourth time control data voltage provided by the data line into the fourth switch node under the control of a second reset control signal provided by the second reset control end.

[0024] The fourth energy storage circuit is electrically connected with the fourth switch node, and is used for maintaining the potential of the fourth switch node.

[0025] The fifth switch control circuit is electrically connected with the third switch node, the second light-emitting time control end and the first control node respectively, and is used for controlling the second light-emitting time control end and the first control node to be in communication or disconnected under the control of the potential of the third switch node.

[0026] The sixth switch control circuit is electrically connected with the fourth switch node, the first light-emitting time control end and the first control node respectively, and is used for controlling the first light-emitting time control end and the first control node to be in communication or disconnected under the control of the potential of the fourth switch node.

[0027] Optionally, the second control circuit comprises a fifth write-in circuit, a sixth write-in circuit, a seventh switch control circuit, an eighth switch control circuit, a fifth energy storage circuit and a sixth energy storage circuit; the second control terminal comprises a third reset control terminal and a fourth reset control terminal;

[0028] The fifth write-in circuit is electrically connected with the third reset control terminal, the data line and a fifth switch node respectively, and is configured to write a fifth time control data voltage provided by the data line into the fifth switch node under control of a third reset control signal provided by the third reset control terminal;

[0029] The fifth energy storage circuit is electrically connected with the fifth switch node, and is configured to maintain the potential of the fifth switch node;

[0030] The sixth write-in circuit is electrically connected with the fourth reset control terminal, the data line and a sixth switch node respectively, and is configured to write a sixth time control data voltage provided by the data line into the sixth switch node under control of a fourth reset control signal provided by the fourth reset control terminal;

[0031] The sixth energy storage circuit is electrically connected with the sixth switch node, and is configured to maintain the potential of the sixth switch node;

[0032] The seventh switch control circuit is electrically connected with the fifth switch node, a second light-emitting time control terminal and a second control node respectively, and is configured to control the second light-emitting time control terminal and the second control node to be in communication or disconnected under control of the potential of the fifth switch node;

[0033] The eighth switch control circuit is electrically connected with the sixth switch node, a third light-emitting time control terminal and a second control node respectively, and is configured to control the third light-emitting time control terminal and the second control node to be in communication or disconnected under control of the potential of the sixth switch node.

[0034] Optionally, the driving circuit comprises a driving transistor;

[0035] The gate of the driving transistor is electrically connected with the control terminal of the driving circuit, the first pole of the driving circuit is electrically connected with the first node, and the second pole of the driving circuit is electrically connected with the second node;

[0036] The first pass-through control circuit comprises a first control transistor, and the second pass-through control circuit comprises a second control transistor;

[0037] The gate of the first control transistor is electrically connected with the first control node, the first pole of the first control transistor is electrically connected with the second node, and the second pole of the first control transistor is electrically connected with the third node;

[0038] The gate of the second control transistor is electrically connected to the second control node, the first electrode of the second control transistor is electrically connected to the second electrode of the light-emitting element, and the second electrode of the second control transistor is electrically connected to the first voltage terminal.

[0039] Optionally, the first writing circuit includes a first transistor, the first energy storage circuit includes a first capacitor, the first switch control circuit includes a second transistor, and the second switch control circuit includes a third transistor.

[0040] The gate of the first transistor is electrically connected to the first control terminal, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the first switching node.

[0041] The first terminal of the first capacitor is electrically connected to the first switching node, and the second terminal of the first capacitor is electrically connected to the initial voltage terminal.

[0042] The gate of the second transistor is electrically connected to the first switching node, the first electrode of the second transistor is electrically connected to the second emission time control terminal, and the second electrode of the second transistor is electrically connected to the first control node.

[0043] The gate of the third transistor is electrically connected to the first switching node, the first electrode of the third transistor is electrically connected to the first emission time control terminal, and the second electrode of the third transistor is electrically connected to the first control node.

[0044] Optionally, the second writing circuit includes a fourth transistor, the second energy storage circuit includes a second capacitor, the third switch control circuit includes a fifth transistor, and the fourth switch control circuit includes a sixth transistor.

[0045] The gate of the fourth transistor is electrically connected to the second control terminal, the first terminal of the fourth transistor is electrically connected to the data line, and the second terminal of the fourth transistor is electrically connected to the second switching node.

[0046] The first terminal of the second capacitor is electrically connected to the second switching node, and the second terminal of the second capacitor is electrically connected to the initial voltage terminal.

[0047] The gate of the fifth transistor is electrically connected to the second switching node, the first terminal of the fifth transistor is electrically connected to the third emission time control terminal, and the second terminal of the fifth transistor is electrically connected to the second control node.

[0048] The gate of the sixth transistor is electrically connected with the second switch node, the first pole of the sixth transistor is electrically connected with the second light-emitting time control end, and the second pole of the sixth transistor is electrically connected with the second control node.

[0049] Optionally, the third write circuit comprises a seventh transistor, the fourth write circuit comprises an eighth transistor, the third energy storage circuit comprises a third capacitor, the fourth energy storage circuit comprises a fourth capacitor, the fifth switch control circuit comprises a ninth transistor, and the sixth switch control circuit comprises a tenth transistor.

[0050] The gate of the seventh transistor is electrically connected with the first reset control end, the first pole of the seventh transistor is electrically connected with the data line, and the second pole of the seventh transistor is electrically connected with a third switch node.

[0051] The first end of the third capacitor is electrically connected with the third switch node, and the second end of the third capacitor is electrically connected with an initial voltage end.

[0052] The gate of the eighth transistor is electrically connected with the second reset control end, the first pole of the eighth transistor is electrically connected with the data line, and the second pole of the eighth transistor is electrically connected with a fourth switch node.

[0053] The first end of the fourth capacitor is electrically connected with the fourth switch node, and the second end of the fourth capacitor is electrically connected with the initial voltage end.

[0054] The gate of the ninth transistor is electrically connected with the third switch node, the first pole of the ninth transistor is electrically connected with the second light-emitting time control end, and the second pole of the ninth transistor is electrically connected with the first control node.

[0055] The gate of the tenth transistor is electrically connected with the fourth switch node, the first pole of the tenth transistor is electrically connected with the first light-emitting time control end, and the second pole of the tenth transistor is electrically connected with the first control node.

[0056] Optionally, the fifth write circuit comprises an eleventh transistor, the sixth write circuit comprises a twelfth transistor, the seventh switch control circuit comprises a thirteenth transistor, the eighth switch control circuit comprises a fourteenth transistor, the fifth energy storage circuit comprises a fifth capacitor, and the sixth energy storage circuit comprises a sixth capacitor.

[0057] The gate of the eleventh transistor is electrically connected with the third reset control end, the first pole of the eleventh transistor is electrically connected with the data line, and the second pole of the eleventh transistor is electrically connected with a fifth switch node.

[0058] A first end of the fifth capacitor is electrically connected with the fifth switch node, and a second end of the fifth capacitor is electrically connected with an initial voltage terminal;

[0059] A gate of the twelfth transistor is electrically connected with the fourth reset control terminal, a first pole of the twelfth transistor is electrically connected with the data line, and a second pole of the twelfth transistor is electrically connected with the sixth switch node;

[0060] A first end of the sixth capacitor is electrically connected with the sixth switch node, and a second end of the sixth capacitor is electrically connected with the initial voltage terminal;

[0061] A gate of the thirteenth transistor is electrically connected with the fifth switch node, a first pole of the thirteenth transistor is electrically connected with the second light-emitting time control terminal, and a second pole of the thirteenth transistor is electrically connected with the second control node;

[0062] A gate of the fourteenth transistor is electrically connected with the sixth switch node, a first pole of the fourteenth transistor is electrically connected with the third light-emitting time control terminal, and a second pole of the fourteenth transistor is electrically connected with the second control node.

[0063] Optionally, the pixel circuit further comprises a data writing circuit, a compensation control circuit and a seventh energy storage circuit.

[0064] The data writing circuit is electrically connected with the scan line, the data line and the first node respectively, and is configured to write a current control data voltage provided by the data line to the first node under control of a scan signal provided by the scan line.

[0065] The compensation control circuit is electrically connected with the scan line, a control terminal of the driving circuit and the second node respectively, and is configured to control the control terminal of the driving circuit and the second node to be connected or disconnected under control of the scan signal.

[0066] The seventh energy storage circuit is electrically connected with the control terminal of the driving circuit, and is configured to store electric energy.

[0067] Optionally, the pixel circuit further comprises a first initialization circuit and a second initialization circuit.

[0068] The first initialization circuit is electrically connected with the first control terminal, the initial voltage terminal and the control terminal of the driving circuit respectively, and is configured to write an initial voltage provided by the initial voltage terminal to the control terminal of the driving circuit under control of a first control signal provided by the first control terminal.

[0069] The second initialization circuit is electrically connected with the first control end, the initial voltage end and the first electrode of the light emitting element respectively, and is used for writing the initial voltage into the first electrode of the light emitting element under the control of the first control signal.

[0070] Optionally, the pixel circuit further comprises a light emitting control circuit.

[0071] The light emitting control circuit is electrically connected with the second light emitting time control end, the power voltage end and the first node respectively, and is used for controlling the communication between the power voltage end and the first node under the control of the second light emitting time control signal provided by the second light emitting time control end.

[0072] Optionally, the first control end comprises a first reset control end and a second reset control end.

[0073] The pixel circuit further comprises a first initialization circuit and a second initialization circuit.

[0074] The first initialization circuit is electrically connected with the first reset control end, the initial voltage end and the control end of the driving circuit respectively, and is used for writing the initial voltage provided by the initial voltage end into the control end of the driving circuit under the control of the first reset control signal provided by the first reset control end.

[0075] The second initialization circuit is electrically connected with the first reset control end, the initial voltage end and the first electrode of the light emitting element respectively, and is used for writing the initial voltage into the first electrode of the light emitting element under the control of the first reset control signal.

[0076] Optionally, the pixel circuit further comprises a compensation control circuit, a data writing circuit and an eighth energy storage circuit; the first node is electrically connected with the power voltage end.

[0077] The first end of the eighth energy storage circuit is electrically connected with the control end of the driving circuit; and the eighth energy storage circuit is used for storing electric energy.

[0078] The compensation control circuit is electrically connected with a scanning line, the control end of the driving circuit and a second node respectively, and is used for controlling the communication or disconnection between the control end of the driving circuit and the second node under the control of a scanning signal provided by the scanning line.

[0079] The data writing circuit is electrically connected with the scanning line, a data line and the second end of the eighth energy storage circuit respectively, and is used for writing a current control data voltage provided by the data line into the second end of the eighth energy storage circuit under the control of the scanning signal.

[0080] Optionally, the pixel circuit further comprises a reference voltage writing circuit.

[0081] The reference voltage writing circuit is electrically connected with the first control end, the second light-emitting time control end, the reference voltage end and the second end of the eighth energy storage circuit respectively, and is configured to write the reference voltage provided by the reference voltage end to the second end of the eighth energy storage circuit under the control of the first control signal provided by the first control end, and write the reference voltage to the second end of the eighth energy storage circuit under the control of the second light-emitting time control signal provided by the second light-emitting time control end.

[0082] Optionally, the data writing circuit comprises a fifteenth transistor, the compensation control circuit comprises a sixteenth transistor, and the seventh energy storage circuit comprises a first storage capacitor.

[0083] The gate of the fifteenth transistor is electrically connected with the scan line, the first pole of the fifteenth transistor is electrically connected with the data line, and the second pole of the fifteenth transistor is electrically connected with the first node.

[0084] The gate of the sixteenth transistor is electrically connected with the scan line, the first pole of the sixteenth transistor is electrically connected with the control end of the driving circuit, and the second pole of the sixteenth transistor is electrically connected with the second node.

[0085] The first end of the first storage capacitor is electrically connected with the control end of the driving circuit, and the second end of the first storage capacitor is electrically connected with the power voltage end.

[0086] Optionally, the first initialization circuit comprises a seventeenth transistor, and the second initialization circuit comprises an eighteenth transistor.

[0087] The gate of the seventeenth transistor is electrically connected with the first control end, the first pole of the seventeenth transistor is electrically connected with the initial voltage end, and the second pole of the seventeenth transistor is electrically connected with the control end of the driving circuit.

[0088] The gate of the eighteenth transistor is electrically connected with the first control end, the first pole of the eighteenth transistor is electrically connected with the initial voltage end, and the second pole of the eighteenth transistor is electrically connected with the first pole of the light-emitting element.

[0089] Optionally, the light-emitting control circuit comprises a nineteenth transistor.

[0090] The gate of the nineteenth transistor is electrically connected with the second light-emitting time control end, the first pole of the nineteenth transistor is electrically connected with the power voltage end, and the second pole of the nineteenth transistor is electrically connected with the first node.

[0091] Optionally, the first initialization circuit comprises a seventeenth transistor, and the second initialization circuit comprises an eighteenth transistor.

[0092] The gate of the seventeenth transistor is electrically connected with the first reset control end, the first electrode of the seventeenth transistor is electrically connected with the initial voltage end, and the second electrode of the seventeenth transistor is electrically connected with the control end of the drive circuit.

[0093] The gate of the eighteenth transistor is electrically connected with the first reset control end, the first electrode of the eighteenth transistor is electrically connected with the initial voltage end, and the second electrode of the eighteenth transistor is electrically connected with the first electrode of the light emitting element.

[0094] Optionally, the compensation control circuit comprises a sixteenth transistor, the data writing circuit comprises a fifteenth transistor, and the eighth energy storage circuit comprises a second storage capacitor.

[0095] The first end of the second storage capacitor is electrically connected with the control end of the drive circuit.

[0096] The gate of the sixteenth transistor is electrically connected with the scanning line, the first electrode of the sixteenth transistor is electrically connected with the control end of the drive circuit, and the second electrode of the sixteenth transistor is electrically connected with the second node.

[0097] The gate of the fifteenth transistor is electrically connected with the scanning line, the first electrode of the fifteenth transistor is electrically connected with the data line, and the second electrode of the fifteenth transistor is electrically connected with the second end of the second storage capacitor.

[0098] Optionally, the reference voltage writing circuit comprises a nineteenth transistor and a twentieth transistor.

[0099] The gate of the nineteenth transistor is electrically connected with the first control end, the first electrode of the nineteenth transistor is electrically connected with the reference voltage end, and the second electrode of the nineteenth transistor is electrically connected with the second end of the eighth energy storage circuit.

[0100] The gate of the twentieth transistor is electrically connected with the second light emitting time control end, the first electrode of the twentieth transistor is electrically connected with the reference voltage end, and the second electrode of the twentieth transistor is electrically connected with the second end of the eighth energy storage circuit.

[0101] In a second aspect, an embodiment of the present application provides a driving method applied to the pixel circuit, and the driving method comprises the following steps of:

[0102] The drive circuit generates a drive current for driving the light emitting element under the control of the potential at the control end of the drive circuit.

[0103] The first on / off control circuit controls the connection or disconnection between the second node and the third node under the control of the potential of the first control node;

[0104] The second on / off control circuit controls the connection or disconnection between the second electrode of the light-emitting element and the first voltage terminal under the control of the potential of the second control node;

[0105] Under the control of the first control signal, the first control circuit controls the connection between the first light emission time control terminal or the second light emission time control terminal and the first control node according to the first time control data voltage provided by the data line.

[0106] Under the control of the second control signal, the second control circuit controls the connection between the second light emission time control terminal or the third light emission time control terminal and the second control node according to the second time control data voltage provided by the data line.

[0107] In a third aspect, embodiments of the present invention provide a display device including the pixel circuit described above. Attached Figure Description

[0108] Figure 1 This is a structural diagram of the pixel circuit according to at least one embodiment of the present invention;

[0109] Figure 2 This is a structural diagram of the pixel circuit according to at least one embodiment of the present invention;

[0110] Figure 3 This is a structural diagram of the pixel circuit according to at least one embodiment of the present invention;

[0111] Figure 4 This is a structural diagram of the pixel circuit according to at least one embodiment of the present invention;

[0112] Figure 5 This is a structural diagram of the pixel circuit according to at least one embodiment of the present invention;

[0113] Figure 6 This is a structural diagram of the pixel circuit according to at least one embodiment of the present invention;

[0114] Figure 7 This is a circuit diagram of the pixel circuit according to at least one embodiment of the present invention;

[0115] Figure 8 This is the present invention. Figure 7 The timing diagram of at least one embodiment of the pixel circuit shown;

[0116] Figure 9A This is the present invention. Figure 7 The diagram shows the operating state of at least one embodiment of the pixel circuit in the first stage.

[0117] Figure 9B is the pixel circuit of the present application Figure 7 is a schematic diagram of the working state of at least one embodiment of the pixel circuit in the second stage;

[0118] Figure 9C is the pixel circuit of the present application Figure 7 is a schematic diagram of the working state of at least one embodiment of the pixel circuit in the third stage;

[0119] Figure 9D is the pixel circuit of the present application Figure 7 is a schematic diagram of the working state of at least one embodiment of the pixel circuit in the fourth stage;

[0120] Figure 9E is the pixel circuit of the present application Figure 7 is a schematic diagram of the working state of at least one embodiment of the pixel circuit in the fifth stage;

[0121] Figure 10 is the pixel circuit of the present application Figure 7 is a timing diagram of the working state of at least one embodiment of the pixel circuit;

[0122] Figure 11 is the pixel circuit of the present application Figure 7 is a timing diagram of the working state of at least one embodiment of the pixel circuit;

[0123] Figure 12 is the pixel circuit of the present application Figure 7 is a timing diagram of the working state of at least one embodiment of the pixel circuit;

[0124] Figure 13 is a circuit diagram of the pixel circuit of at least one embodiment of the present application;

[0125] Figure 14 is the pixel circuit of the present application Figure 13 is a timing diagram of the working state of at least one embodiment of the pixel circuit; Figure 15 is a circuit diagram of the pixel circuit of at least one embodiment of the present application. DETAILED DESCRIPTION

[0126] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0127] The transistors used in all the embodiments of the present application can be thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present application, in order to distinguish the two poles of the transistor except the gate, one pole is called the first pole and the other pole is called the second pole.

[0128] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0129] This invention provides a novel Micro LED pixel driving circuit that enables a high-quality Micro LED display device with lossless gamma. Through the pixel driving circuit and the matching timing, high grayscale, low grayscale, medium grayscale, and even super low grayscale can be achieved.

[0130] The Gamma 2.2 curve is a grayscale curve that is more suitable for the human eye. Typically, OLED (Organic Light Emitting Diode) or LED display panels cannot fit a Gamma 2.2 curve at low or ultra-low grayscale levels due to inherent defects in their TFT (Thin Film Transistor) devices or light-emitting devices. Lossless gamma spectroscopy, through a combination of several emission durations, can achieve all points of 8-bit (256 grayscale levels) or 10-bit (1024 grayscale levels) on the Gamma 2.2 curve.

[0131] In at least one embodiment of the present invention, when there are 256 gray levels, L128 to L255 can be medium-high gray levels, L0 to L127 can be medium-low gray levels, L16 and below can be ultra-low gray levels, and low gray levels can be L17 to L127, wherein L128 is gray level 128, L255 is gray level 255, L0 is gray level 0, L127 is gray level 127, and L17 is gray level 17.

[0132] However, this is not the only limit.

[0133] The pixel circuit described in this embodiment of the invention achieves different gray levels through the combination of current adjustment and emission time adjustment. Medium-high gray levels, medium-low gray levels, low gray levels, and ultra-low gray levels are achieved by using different emission currents and the duty cycles of the emission time control signals provided by each emission time control terminal.

[0134] like Figure 1 As shown, the pixel circuit of at least one embodiment of the present invention includes a driving circuit 10, a first on / off control circuit 11, a light-emitting element EL, a second on / off control circuit 12, a first control circuit 13, and a second control circuit 14.

[0135] The first end of the driving circuit 10 is electrically connected to the first node N1, and the second end of the driving circuit 10 is electrically connected to the second node N2; the driving circuit 10 is used to generate a driving current for driving the light-emitting element EL under the control of the potential at its control end.

[0136] The first on-off control circuit 11 is electrically connected with the first control node NC1, the second node N2 and the third node N3 respectively, and is used for controlling the second node N2 and the third node N3 to be connected or disconnected under the control of the potential of the first control node NC1.

[0137] The first pole of the light emitting element EL is electrically connected with the third node N3.

[0138] The second on-off control circuit 12 is electrically connected with the second control node NC2, the second pole of the light emitting element EL and the first voltage terminal V1 respectively, and is used for controlling the second pole of the light emitting element EL and the first voltage terminal V1 to be connected or disconnected under the control of the potential of the second control node NC2.

[0139] The first control circuit 13 is electrically connected with the first control terminal R1, the data line DL, the first light emitting time control terminal HF, the second light emitting time control terminal EML and the first control node NC1 respectively, and is used for controlling the first light emitting time control terminal HF or the second light emitting time control terminal EML and the first control node NC1 to be connected under the control of the first control signal provided by the first control terminal R1 and according to the first time control data voltage provided by the data line DL.

[0140] The second control circuit 14 is electrically connected with the second control terminal SL, the data line DL, the second light emitting time control terminal EML, the third light emitting time control terminal EMS and the second control node NC2 respectively, and is used for controlling the second light emitting time control terminal EML or the third light emitting time control terminal EMS and the second control node NC2 to be connected under the control of the second control signal provided by the second control terminal SL and according to the second time control data voltage provided by the data line DL.

[0141] Optionally, the first voltage terminal can be a low voltage terminal, but is not limited thereto.

[0142] The present application Figure 1 At least one embodiment of the pixel circuit shown in the working process can include a first stage, a second stage and a third stage arranged in sequence.

[0143] In the first stage, the first control circuit 13 controls the first light emitting time control terminal HF or the second light emitting time control terminal EML and the first control node NC1 to be connected under the control of the first control signal provided by the first control terminal R1 and according to the first time control data voltage provided by the data line DL.

[0144] When displaying the ultra-low gray scale, the first control circuit 13 can control the first light-emitting time control end HF to be in communication with the first control node NC1;

[0145] When displaying the medium-high gray scale and the medium-low gray scale, the first control circuit 13 can control the second light-emitting time control end EML to be in communication with the first control node NC1;

[0146] When displaying the low gray scale, the first control circuit 13 can control the first light-emitting time control end HF to be in communication with the first control node NC1;

[0147] The first light-emitting time control end HF is configured to provide a first light-emitting time control signal, and the second light-emitting time control end EML is configured to provide a second light-emitting time control signal.

[0148] The second stage is a compensation stage and a data voltage writing time for controlling a light-emitting current.

[0149] In the third stage, the second control circuit 14 controls the second light-emitting time control end EML or the third light-emitting time control end EMS to be in communication with the second control node NC2 under the control of the second control signal according to the second time control data voltage provided by the data line DL.

[0150] When displaying the ultra-low gray scale, the second control circuit 14 controls the third light-emitting time control end EMS to be in communication with the second control node NC2.

[0151] When displaying the medium-high gray scale, the second control circuit 14 controls the second light-emitting time control end EML to be in communication with the second control node NC2.

[0152] When displaying the medium-low gray scale, the second control circuit 14 controls the third light-emitting time control end EMS to be in communication with the second control node NC2.

[0153] When displaying the low gray scale, the second control circuit 14 controls the third light-emitting time control end EMS to be in communication with the second control node NC2.

[0154] The third light-emitting time control end EMS is configured to provide a third light-emitting time control signal.

[0155] In a specific implementation, when the transistor included in the first on-off control circuit 11 is a p-type transistor and the transistor included in the second on-off control circuit 12 is a p-type transistor, the duty ratio of the first light-emitting time control signal provided by the first light-emitting time control terminal HF is greater than the duty ratio of the third light-emitting time control signal provided by the third light-emitting time control terminal EMS, and the duty ratio of the third light-emitting time control signal is greater than the duty ratio of the second light-emitting time control signal provided by the second light-emitting time control terminal EML;

[0156] When the transistor included in the first on-off control circuit 11 is an n-type transistor and the transistor included in the second on-off control circuit 12 is an n-type transistor, the duty ratio of the first light-emitting time control signal provided by the first light-emitting time control terminal HF is less than the duty ratio of the third light-emitting time control signal provided by the third light-emitting time control terminal EMS, and the duty ratio of the third light-emitting time control signal is less than the duty ratio of the second light-emitting time control signal provided by the second light-emitting time control terminal EML;

[0157] However, the application is not limited thereto.

[0158] In at least one embodiment of the application, the first control circuit includes a first write-in circuit, a first energy storage circuit, a first switch control circuit, and a second switch control circuit.

[0159] The first write-in circuit is electrically connected with the first control terminal, the data line, and the first switch node, respectively, and is configured to write the first time control data voltage into the first switch node under the control of the first control signal provided by the first control terminal.

[0160] The first energy storage circuit is electrically connected with the first switch node, and is configured to maintain the potential of the first switch node.

[0161] The first switch control circuit is electrically connected with the first switch node, the second light-emitting time control terminal, and the first control node, respectively, and is configured to control the first control node and the second light-emitting time control terminal to be in communication or disconnected under the control of the potential of the first switch node.

[0162] The second switch control circuit is electrically connected with the first switch node, the first light-emitting time control terminal, and the first control node, respectively, and is configured to control the first control node and the first light-emitting time control terminal to be in communication or disconnected under the control of the potential of the first switch node.

[0163] In a specific implementation, the first control circuit can include a first write circuit, a first energy storage circuit, a first switch control circuit and a second switch control circuit; the first write circuit writes a first time control data voltage to the first switch node under control of a first control signal; the first energy storage circuit maintains a potential of the first switch node; the first switch control circuit controls communication or disconnection between the first control node and the second light-emitting time control terminal under control of the potential of the first switch node; and the second switch control circuit controls communication or disconnection between the first control node and the first light-emitting time control terminal under control of the potential of the first switch node.

[0164] In at least one embodiment of the present application, the second control circuit includes a second write circuit, a second energy storage circuit, a third switch control circuit and a fourth switch control circuit.

[0165] The second write circuit is electrically connected with a second control terminal, the data line and a second switch node respectively, and is configured to write a second time control data voltage provided by the data line to the second switch node under control of a second control signal provided by the second control terminal;

[0166] The second energy storage circuit is electrically connected with the second switch node, and is configured to maintain a potential of the second switch node;

[0167] The third switch control circuit is electrically connected with the second switch node, a third light-emitting time control terminal and the second control node respectively, and is configured to control communication or disconnection between the second control node and the third light-emitting time control terminal under control of the potential of the second switch node;

[0168] The fourth switch control circuit is electrically connected with the second switch node, a second light-emitting time control terminal and the second control node respectively, and is configured to control communication or disconnection between the second control node and the second light-emitting time control terminal under control of the potential of the second switch node.

[0169] In a specific implementation, the second control circuit can include a second write circuit, a second energy storage circuit, a third switch control circuit and a fourth switch control circuit; the second write circuit writes a second time control data voltage to the second switch node under control of a second control signal; the second energy storage circuit maintains a potential of the second switch node; the third switch control circuit controls communication or disconnection between the second control node and the third light-emitting time control terminal under control of the potential of the second switch node; and the fourth switch control circuit controls communication or disconnection between the second control node and the second light-emitting time control terminal under control of the potential of the second switch node.

[0170] As Figure 2As shown in Figure 1 The first control circuit comprises a first write-in circuit 21, a first energy storage circuit 22, a first switch control circuit 23 and a second switch control circuit 24 based on at least one embodiment of the pixel circuit shown;

[0171] The first write-in circuit 21 is electrically connected with the first control end R1, the data line DL and the first switch node NK1 respectively, and is used for writing the first time control data voltage provided by the data line DL into the first switch node NK1 under the control of the first control signal provided by the first control end R1;

[0172] The first energy storage circuit 22 is electrically connected with the first switch node NK1, and is used for maintaining the potential of the first switch node NK1;

[0173] The first switch control circuit 23 is electrically connected with the first switch node NK1, the second light-emitting time control end EML and the first control node NC1 respectively, and is used for controlling the first control node NC1 to be in communication or disconnected with the second light-emitting time control end EML under the control of the potential of the first switch node NK1;

[0174] The second switch control circuit 24 is electrically connected with the first switch node NK1, the first light-emitting time control end HF and the first control node NC1 respectively, and is used for controlling the first control node NC1 to be in communication or disconnected with the first light-emitting time control end HF under the control of the potential of the first switch node NK1;

[0175] The second control circuit comprises a second write-in circuit 25, a second energy storage circuit 26, a third switch control circuit 27 and a fourth switch control circuit 28;

[0176] The second write-in circuit 25 is electrically connected with the second control end SL, the data line DL and the second switch node NK2 respectively, and is used for writing the second time control data voltage provided by the data line DL into the second switch node NK2 under the control of the second control signal provided by the second control end SL;

[0177] The second energy storage circuit 26 is electrically connected with the second switch node NK2, and is used for maintaining the potential of the second switch node NK2;

[0178] The third switch control circuit 27 is electrically connected with the second switch node NK2, the third light-emitting time control end EMS and the second control node NC2 respectively, and is used for controlling the second control node NC2 to be in communication or disconnected with the third light-emitting time control end EMS under the control of the potential of the second switch node NK2;

[0179] The fourth switch control circuit 28 is electrically connected with the second switch node NK2, the second light-emitting time control end EML and the second control node NC2 respectively, and is used for controlling the second control node NC2 and the second light-emitting time control end EML to be connected or disconnected under the control of the potential of the second switch node NK2.

[0180] The present application Figure 2 At least one embodiment of the pixel circuit shown in operation, the display period can include the first stage, the second stage and the third stage arranged in turn;

[0181] In the first stage, the first write circuit 21 writes the first time control data voltage provided by the data line DL into the first switch node NK1 under the control of the provided first control signal;

[0182] In the display of the ultra-low gray scale, the second switch control circuit 24 controls the first control node NC1 and the first light-emitting time control end HF to be connected under the control of the potential of the first switch node NK1;

[0183] In the display of the middle-high gray scale, the first switch control circuit 23 controls the first control node NC1 and the second light-emitting time control end EML to be connected under the control of the potential of the first switch node NK1;

[0184] In the display of the middle-low gray scale, the first switch control circuit 23 controls the first control node NC1 and the second light-emitting time control end EML to be connected under the control of the potential of the first switch node NK1;

[0185] In the display of the low gray scale, the second switch control circuit 24 controls the first control node NC1 and the first light-emitting time control end HF to be connected under the control of the potential of the first switch node NK1;

[0186] In the third stage, the second write circuit 25 writes the second time control data voltage provided by the data line DL into the second switch node NK2 under the control of the second control signal provided by the second control end SL;

[0187] In the display of the ultra-low gray scale, the third switch control circuit 27 controls the second control node NC2 and the third light-emitting time control end EMS to be connected under the control of the potential of the second switch node NK2;

[0188] In displaying middle-high gray scale, the fourth switch control circuit 28 controls the second control node NC2 to communicate with the second light emitting time control end EML under the control of the potential of the second switch node NK2;

[0189] In displaying middle-low gray scale, the third switch control circuit 27 controls the second control node NC2 to communicate with the third light emitting time control end EMS under the control of the potential of the second switch node NK2;

[0190] In displaying low gray scale, the third switch control circuit 27 controls the second control node NC2 to communicate with the third light emitting time control end EMS under the control of the potential of the second switch node NK2.

[0191] In at least one embodiment of the present application, the first control circuit comprises a third write-in circuit, a fourth write-in circuit, a fifth switch control circuit, a sixth switch control circuit, a third energy storage circuit and a fourth energy storage circuit; the first control end comprises a first reset control end and a second reset control end;

[0192] The third write-in circuit is electrically connected with the first reset control end, the data line and a third switch node respectively, and is used for writing third time control data voltage provided by the data line into the third switch node under the control of a first reset control signal provided by the first reset control end;

[0193] The third energy storage circuit is electrically connected with the third switch node, and is used for maintaining the potential of the third switch node;

[0194] The fourth write-in circuit is electrically connected with the second reset control end, the data line and a fourth switch node respectively, and is used for writing fourth time control data voltage provided by the data line into the fourth switch node under the control of a second reset control signal provided by the second reset control end;

[0195] The fourth energy storage circuit is electrically connected with the fourth switch node, and is used for maintaining the potential of the fourth switch node;

[0196] The fifth switch control circuit is electrically connected with the third switch node, a second light emitting time control end and the first control node respectively, and is used for controlling the second light emitting time control end to communicate with or disconnect from the first control node under the control of the potential of the third switch node;

[0197] The sixth switch control circuit is electrically connected with the fourth switch node, a first light emitting time control end and the first control node respectively, and is used for controlling the first light emitting time control end to communicate with or disconnect from the first control node under the control of the potential of the fourth switch node.

[0198] In a specific implementation, the first control circuit can include a third write-in circuit, a fourth write-in circuit, a fifth switch control circuit, a sixth switch control circuit, a third energy storage circuit and a fourth energy storage circuit; the first control end includes a first reset control end and a second reset control end; the third write-in circuit writes a third time control data voltage into the third switch node under control of a first reset control signal; the third energy storage circuit maintains the potential of the third switch node; the fourth write-in circuit writes a fourth time control data voltage into the fourth switch node under control of a second reset control signal; the fourth energy storage circuit maintains the potential of the fourth switch node; the fifth switch control circuit controls the communication or disconnection between the second light-emitting time control end and the first control node under control of the potential of the third switch node; and the sixth switch control circuit controls the communication or disconnection between the first light-emitting time control end and the first control node under control of the potential of the fourth switch node.

[0199] In at least one embodiment of the application, the second control circuit includes a fifth write-in circuit, a sixth write-in circuit, a seventh switch control circuit, an eighth switch control circuit, a fifth energy storage circuit and a sixth energy storage circuit; the second control end includes a third reset control end and a fourth reset control end;

[0200] The fifth write-in circuit is electrically connected with the third reset control end, the data line and a fifth switch node respectively, and is configured to write a fifth time control data voltage provided by the data line into the fifth switch node under control of a third reset control signal provided by the third reset control end;

[0201] The fifth energy storage circuit is electrically connected with the fifth switch node, and is configured to maintain the potential of the fifth switch node;

[0202] The sixth write-in circuit is electrically connected with the fourth reset control end, the data line and a sixth switch node respectively, and is configured to write a sixth time control data voltage provided by the data line into the sixth switch node under control of a fourth reset control signal provided by the fourth reset control end;

[0203] The sixth energy storage circuit is electrically connected with the sixth switch node, and is configured to maintain the potential of the sixth switch node;

[0204] The seventh switch control circuit is electrically connected with the fifth switch node, a second light-emitting time control end and a second control node respectively, and is configured to control the communication or disconnection between the second light-emitting time control end and the second control node under control of the potential of the fifth switch node;

[0205] The eighth switch control circuit is electrically connected to the sixth switch node, the third emission time control terminal, and the second control node, respectively, and is used to control the connection or disconnection between the third emission time control terminal and the second control node under the control of the potential of the sixth switch node.

[0206] In a specific implementation, the second control circuit may include a fifth writing circuit, a sixth writing circuit, a seventh switch control circuit, an eighth switch control circuit, a fifth energy storage circuit, and a sixth energy storage circuit; the second control terminal includes a third reset control terminal and a fourth reset control terminal; the fifth writing circuit, under the control of the third reset control signal, writes the fifth time control data voltage into the fifth switch node; the fifth energy storage circuit maintains the potential of the fifth switch node; the sixth writing circuit, under the control of the fourth reset control signal, writes the sixth time control data voltage into the sixth switch node; the sixth energy storage circuit maintains the potential of the sixth switch node; the seventh switch control circuit, under the control of the potential of the fifth switch node, controls the connection or disconnection between the second light emission time control terminal and the second control node; the eighth switch control circuit, under the control of the potential of the sixth switch node, controls the connection or disconnection between the third light emission time control terminal and the second control node.

[0207] like Figure 3 As shown, in Figure 1 Based on at least one embodiment of the pixel circuit shown, the first control circuit includes a third write circuit 31, a fourth write circuit 32, a fifth switch control circuit 33, a sixth switch control circuit 34, a third energy storage circuit 35, and a fourth energy storage circuit 36; the first control terminal includes a first reset control terminal RA and a second reset control terminal RB.

[0208] The third writing circuit 31 is electrically connected to the first reset control terminal RA, the data line DL and the third switch node NK3 respectively, and is used to write the third time control data voltage provided by the data line DL into the third switch node NK3 under the control of the first reset control signal provided by the first reset control terminal RA.

[0209] The third energy storage circuit 35 is electrically connected to the third switching node NK3 and is used to maintain the potential of the third switching node NK3.

[0210] The fourth writing circuit 32 is electrically connected to the second reset control terminal RB, the data line DL and the fourth switch node NK4 respectively, and is used to write the fourth time control data voltage provided by the data line DL into the fourth switch node NK4 under the control of the second reset control signal provided by the second reset control terminal RB.

[0211] The fourth energy storage circuit 36 is electrically connected with the fourth switch node NK4, and is configured to maintain the potential of the fourth switch node NK4;

[0212] The fifth switch control circuit 33 is electrically connected with the third switch node NK3, the second light-emitting time control terminal EML and the first control node NC1 respectively, and is configured to control the communication or disconnection between the second light-emitting time control terminal EML and the first control node NC1 under the control of the potential of the third switch node NK3;

[0213] The sixth switch control circuit 34 is electrically connected with the fourth switch node NK4, the first light-emitting time control terminal HF and the first control node NC1 respectively, and is configured to control the communication or disconnection between the first light-emitting time control terminal HF and the first control node NC1 under the control of the potential of the fourth switch node NK4;

[0214] The second control circuit comprises a fifth write-in circuit 37, a sixth write-in circuit 38, a seventh switch control circuit 39, an eighth switch control circuit 310, a fifth energy storage circuit 311 and a sixth energy storage circuit 312; and the second control terminal comprises a third reset control terminal RC and a fourth reset control terminal RD.

[0215] The fifth write-in circuit 37 is electrically connected with the third reset control terminal RC, the data line DL and a fifth switch node NK5 respectively, and is configured to write a fifth time control data voltage provided by the data line DL into the fifth switch node NK5 under the control of a third reset control signal provided by the third reset control terminal RC;

[0216] The fifth energy storage circuit 311 is electrically connected with the fifth switch node NK5, and is configured to maintain the potential of the fifth switch node NK5;

[0217] The sixth write-in circuit 38 is electrically connected with the fourth reset control terminal RD, the data line DL and a sixth switch node NK6 respectively, and is configured to write a sixth time control data voltage provided by the data line DL into the sixth switch node NK6 under the control of a fourth reset control signal provided by the fourth reset control terminal RD;

[0218] The sixth energy storage circuit 312 is electrically connected with the sixth switch node NK6, and is configured to maintain the potential of the sixth switch node NK6;

[0219] The seventh switch control circuit 39 is electrically connected with the fifth switch node NK5, the second light-emitting time control end EML and the second control node NC2 respectively, and is used for controlling the second light-emitting time control end EML and the second control node NC2 to be connected or disconnected under the control of the potential of the fifth switch node NK5.

[0220] The eighth switch control circuit 310 is electrically connected with the sixth switch node NK6, the third light-emitting time control end EMS and the second control node NC2 respectively, and is used for controlling the third light-emitting time control end EMS and the second control node NC2 to be connected or disconnected under the control of the potential of the sixth switch node NK6.

[0221] The present application Figure 3 At least one embodiment of the pixel circuit shown in the working process, the display period can include the first stage, the second stage and the third stage arranged in turn;

[0222] In the first stage, the third write circuit 31 writes the third time control data voltage provided by the data line DL into the third switch node NK3 under the control of the first reset control signal provided by the first reset control end RA; the third energy storage circuit 35 maintains the potential of the third switch node NK3; the fourth write circuit 32 writes the fourth time control data voltage provided by the data line DL into the fourth switch node NK4 under the control of the second reset control signal provided by the second reset control end RB; and the fourth energy storage circuit 36 maintains the potential of the fourth switch node NK4.

[0223] When displaying ultra-low gray scale and low gray scale, the sixth switch control circuit 34 controls the first light-emitting time control end HF and the first control node NC1 to be connected under the control of the potential of the fourth switch node NK4.

[0224] When displaying medium-high gray scale and medium-low gray scale, the fifth switch control circuit 33 controls the second light-emitting time control end EML and the first control node NC1 to be connected under the control of the potential of the third switch node NK3.

[0225] In the third stage, the fifth write circuit 37 writes the fifth time control data voltage provided by the data line DL into the fifth switch node NK5 under the control of the third reset control signal provided by the third reset control end RC; the fifth energy storage circuit 311 maintains the potential of the fifth switch node NK5; the sixth write circuit 38 writes the sixth time control data voltage provided by the data line DL into the sixth switch node NK6 under the control of the fourth reset control signal provided by the fourth reset control end RD; the sixth energy storage circuit 312 maintains the potential of the sixth switch node NK6;

[0226] When displaying ultra-low gray scale, medium-low gray scale and low gray scale, the eighth switch control circuit 310 controls the communication or disconnection between the third light-emitting time control end EMS and the second control node NC2 under the control of the potential of the sixth switch node NK6;

[0227] When displaying medium-high gray scale, the seventh switch control circuit 39 controls the communication between the second light-emitting time control end EML and the second control node NC2 under the control of the potential of the fifth switch node NK5.

[0228] Optionally, the first write circuit comprises a first transistor, the first energy storage circuit comprises a first capacitor, the first switch control circuit comprises a second transistor, and the second switch control circuit comprises a third transistor.

[0229] The gate of the first transistor is electrically connected with the first control end, the first pole of the first transistor is electrically connected with the data line, and the second pole of the first transistor is electrically connected with the first switch node.

[0230] The first end of the first capacitor is electrically connected with the first switch node, and the second end of the first capacitor is electrically connected with an initial voltage end.

[0231] The gate of the second transistor is electrically connected with the first switch node, the first pole of the second transistor is electrically connected with the second light-emitting time control end, and the second pole of the second transistor is electrically connected with the first control node.

[0232] The gate of the third transistor is electrically connected with the first switch node, the first pole of the third transistor is electrically connected with the first light-emitting time control end, and the second pole of the third transistor is electrically connected with the first control node.

[0233] Optionally, the second write circuit comprises a fourth transistor, the second energy storage circuit comprises a second capacitor, the third switch control circuit comprises a fifth transistor, and the fourth switch control circuit comprises a sixth transistor.

[0234] The gate of the fourth transistor is electrically connected with the second control end, the first electrode of the fourth transistor is electrically connected with the data line, and the second electrode of the fourth transistor is electrically connected with the second switch node;

[0235] The first end of the second capacitor is electrically connected with the second switch node, and the second end of the second capacitor is electrically connected with the initial voltage end;

[0236] The gate of the fifth transistor is electrically connected with the second switch node, the first electrode of the fifth transistor is electrically connected with the third light-emitting time control end, and the second electrode of the fifth transistor is electrically connected with the second control node;

[0237] The gate of the sixth transistor is electrically connected with the second switch node, the first electrode of the sixth transistor is electrically connected with the second light-emitting time control end, and the second electrode of the sixth transistor is electrically connected with the second control node.

[0238] Optionally, the third write circuit comprises a seventh transistor, the fourth write circuit comprises an eighth transistor, the third energy storage circuit comprises a third capacitor, the fourth energy storage circuit comprises a fourth capacitor, the fifth switch control circuit comprises a ninth transistor, and the sixth switch control circuit comprises a tenth transistor;

[0239] The gate of the seventh transistor is electrically connected with the first reset control end, the first electrode of the seventh transistor is electrically connected with the data line, and the second electrode of the seventh transistor is electrically connected with the third switch node;

[0240] The first end of the third capacitor is electrically connected with the third switch node, and the second end of the third capacitor is electrically connected with the initial voltage end;

[0241] The gate of the eighth transistor is electrically connected with the second reset control end, the first electrode of the eighth transistor is electrically connected with the data line, and the second electrode of the eighth transistor is electrically connected with the fourth switch node;

[0242] The first end of the fourth capacitor is electrically connected with the fourth switch node, and the second end of the fourth capacitor is electrically connected with the initial voltage end;

[0243] The gate of the ninth transistor is electrically connected with the third switch node, the first electrode of the ninth transistor is electrically connected with the second light-emitting time control end, and the second electrode of the ninth transistor is electrically connected with the first control node;

[0244] The gate of the tenth transistor is electrically connected with the fourth switch node, the first electrode of the tenth transistor is electrically connected with the first light-emitting time control end, and the second electrode of the tenth transistor is electrically connected with the first control node.

[0245] Optionally, the fifth write circuit comprises an eleventh transistor, the sixth write circuit comprises a twelfth transistor, the seventh switch control circuit comprises a thirteenth transistor, the eighth switch control circuit comprises a fourteenth transistor, the fifth energy storage circuit comprises a fifth capacitor, and the sixth energy storage circuit comprises a sixth capacitor.

[0246] The gate of the eleventh transistor is electrically connected with the third reset control end, the first pole of the eleventh transistor is electrically connected with the data line, and the second pole of the eleventh transistor is electrically connected with the fifth switch node.

[0247] The first end of the fifth capacitor is electrically connected with the fifth switch node, and the second end of the fifth capacitor is electrically connected with an initial voltage end.

[0248] The gate of the twelfth transistor is electrically connected with the fourth reset control end, the first pole of the twelfth transistor is electrically connected with the data line, and the second pole of the twelfth transistor is electrically connected with the sixth switch node.

[0249] The first end of the sixth capacitor is electrically connected with the sixth switch node, and the second end of the sixth capacitor is electrically connected with the initial voltage end.

[0250] The gate of the thirteenth transistor is electrically connected with the fifth switch node, the first pole of the thirteenth transistor is electrically connected with the second light-emitting time control end, and the second pole of the thirteenth transistor is electrically connected with the second control node.

[0251] The gate of the fourteenth transistor is electrically connected with the sixth switch node, the first pole of the fourteenth transistor is electrically connected with the third light-emitting time control end, and the second pole of the fourteenth transistor is electrically connected with the second control node.

[0252] The pixel circuit also comprises a data write circuit, a compensation control circuit and a seventh energy storage circuit.

[0253] The data write circuit is electrically connected with a scanning line, the data line and the first node respectively, and is used for writing a current control data voltage provided by the data line into the first node under the control of a scanning signal provided by the scanning line.

[0254] The compensation control circuit is electrically connected with the scanning line, a control end of the driving circuit and the second node respectively, and is used for controlling the control end of the driving circuit and the second node to be in communication or disconnected under the control of the scanning signal.

[0255] The seventh energy storage circuit is electrically connected with the control end of the driving circuit, and is used for storing electric energy.

[0256] In a specific implementation, the pixel circuit may further include a data writing circuit, a compensation control circuit, and a seventh energy storage circuit. Under the control of the scanning signal, the data writing circuit writes the current provided by the data line to control the data voltage into the first node. Under the control of the scanning signal, the compensation control circuit controls the connection or disconnection between the control terminal of the driving circuit and the second node.

[0257] The pixel circuit described in at least one embodiment of the present invention further includes a first initialization circuit and a second initialization circuit;

[0258] The first initialization circuit is electrically connected to the first control terminal, the initial voltage terminal, and the control terminal of the driving circuit, respectively, and is used to write the initial voltage provided by the initial voltage terminal into the control terminal of the driving circuit under the control of the first control signal provided by the first control terminal.

[0259] The second initialization circuit is electrically connected to the first control terminal, the initial voltage terminal, and the first electrode of the light-emitting element, respectively, and is used to write the initial voltage into the first electrode of the light-emitting element under the control of the first control signal.

[0260] In a specific implementation, the pixel circuit may further include a first initialization circuit and a second initialization circuit; the first initialization circuit, under the control of a first control signal, writes the initial voltage provided by the initial voltage terminal into the control terminal of the driving circuit to initialize the potential of the control terminal of the driving circuit; the second initialization circuit, under the control of the first control signal, writes the initial voltage into the first electrode of the light-emitting element to initialize the potential of the first electrode of the light-emitting element.

[0261] The pixel circuit described in at least one embodiment of the present invention further includes a light-emitting control circuit;

[0262] The light emission control circuit is electrically connected to the second light emission time control terminal, the power supply voltage terminal, and the first node, respectively, and is used to control the connection or disconnection between the power supply voltage terminal and the first node under the control of the second light emission time control signal provided by the second light emission time control terminal.

[0263] In a specific implementation, the pixel circuit may further include a light emission control circuit, which is used to control the connection or disconnection between the power supply voltage terminal and the first node under the control of the second light emission time control signal provided by the second light emission time control terminal, so as to perform light emission control.

[0264] like Figure 4 As shown, in Figure 2Based on the at least one embodiment of the pixel circuit shown, the pixel circuit in at least one embodiment of the present application can further include a data writing circuit 41, a compensation control circuit 42 and a seventh energy storage circuit 43.

[0265] The data writing circuit 41 is electrically connected with the scan line GL, the data line DL and the first node N1 respectively, and is configured to write a current control data voltage provided by the data line DL to the first node N1 under the control of a scan signal provided by the scan line GL.

[0266] The compensation control circuit 42 is electrically connected with the scan line GL, the control end of the driving circuit 10 and the second node N2 respectively, and is configured to control the connection or disconnection between the control end of the driving circuit 10 and the second node N2 under the control of the scan signal.

[0267] The seventh energy storage circuit 43 is electrically connected with the control end of the driving circuit 10, and is configured to store electrical energy.

[0268] The pixel circuit in at least one embodiment of the present application can further include a first initialization circuit 44 and a second initialization circuit 45.

[0269] The first initialization circuit 44 is electrically connected with the first control end R1, the initial voltage end I1 and the control end of the driving circuit 10 respectively, and is configured to write an initial voltage Vinit provided by the initial voltage end I1 to the control end of the driving circuit 10 under the control of a first control signal provided by the first control end R1.

[0270] The second initialization circuit 45 is electrically connected with the first control end R1, the initial voltage end I1 and the first pole of the light emitting element EL respectively, and is configured to write the initial voltage Vinit to the first pole of the light emitting element EL under the control of the first control signal.

[0271] The pixel circuit in at least one embodiment of the present application can further include a light emitting control circuit 46.

[0272] The light emitting control circuit 46 is electrically connected with the second light emitting time control end EML, the power voltage end ELVDD and the first node N1 respectively, and is configured to control the connection or disconnection between the power voltage end ELVDD and the first node N1 under the control of a second light emitting time control signal provided by the second light emitting time control end EML.

[0273] The present application Figure 4 In the working process of the at least one embodiment of the pixel circuit shown, the display period can include a first stage and a second stage arranged in sequence.

[0274] In the first stage, the first initialization circuit 44 writes the initial voltage Vinit provided by the initial voltage terminal I1 into the control terminal of the drive circuit 10 under the control of the first control signal provided by the first control terminal R1, so that the drive circuit 10 can turn on the connection between the first terminal and the second terminal at the beginning of the second stage; the second initialization circuit 45 writes the initial voltage Vinit into the first electrode of the light emitting element EL under the control of the first control signal, to control the light emitting element EL not to emit light and to clear the charge remaining in the first electrode of the light emitting element EL.

[0275] In the second stage, the data writing circuit 41 writes the current control data voltage Vdata provided by the data line DL into the first node N1 under the control of the scan signal provided by the scan line GL; the compensation control circuit 42 controls the communication between the control terminal of the drive circuit 10 and the second node N2 under the control of the scan signal.

[0276] At the beginning of the second stage, the drive circuit 10 turns on the connection between the first node N1 and the second node N2, to charge the seventh energy storage circuit 43 by the current control data voltage Vdata, to raise the potential of the control terminal of the drive circuit 10, until the potential of the control terminal of the drive circuit 10 becomes Vdata+Vth, Vth is the threshold voltage of the drive transistor included in the drive circuit 10, the drive circuit 10 turns off the connection between the first node N1 and the second node N2, to stop charging, to perform threshold voltage compensation.

[0277] In at least one embodiment of the present application, the first control terminal includes a first reset control terminal and a second reset control terminal.

[0278] The pixel circuit further includes a first initialization circuit and a second initialization circuit.

[0279] The first initialization circuit is electrically connected with the first reset control terminal, the initial voltage terminal and the control terminal of the drive circuit respectively, and is configured to write the initial voltage provided by the initial voltage terminal into the control terminal of the drive circuit under the control of the first reset control signal provided by the first reset control terminal.

[0280] The second initialization circuit is electrically connected with the first reset control terminal, the initial voltage terminal and the first electrode of the light emitting element respectively, and is configured to write the initial voltage into the first electrode of the light emitting element under the control of the first reset control signal.

[0281] As shown in Figure 5 the first reset control terminal and the second reset control terminal are provided in the first stage, and the first reset control terminal and the second reset control terminal are provided in the second stage. Figure 3Based on the at least one embodiment of the pixel circuit shown, the pixel circuit in at least one embodiment of the present application can further include a data writing circuit 41, a compensation control circuit 42 and a seventh energy storage circuit 43.

[0282] The data writing circuit 41 is electrically connected with the scan line GL, the data line DL and the first node N1 respectively, and is configured to write a current control data voltage provided by the data line DL to the first node N1 under the control of a scan signal provided by the scan line GL.

[0283] The compensation control circuit 42 is electrically connected with the scan line GL, the control end of the driving circuit 10 and the second node N2 respectively, and is configured to control the control end of the driving circuit 10 and the second node N2 to be connected or disconnected under the control of the scan signal.

[0284] The seventh energy storage circuit 43 is electrically connected with the control end of the driving circuit 10, and is configured to store electrical energy.

[0285] The pixel circuit in at least one embodiment of the present application can further include a first initialization circuit 44 and a second initialization circuit 45.

[0286] The first initialization circuit 44 is electrically connected with a first reset control end RA, an initial voltage end I1 and the control end of the driving circuit 10 respectively, and is configured to write an initial voltage Vinit provided by the initial voltage end I1 to the control end of the driving circuit 10 under the control of a first reset control signal provided by the first reset control end RA.

[0287] The second initialization circuit 45 is electrically connected with the first reset control end RA, the initial voltage end I1 and the first electrode of the light emitting element EL respectively, and is configured to write the initial voltage Vinit to the first electrode of the light emitting element EL under the control of the first reset control signal.

[0288] The pixel circuit in at least one embodiment of the present application can further include a light emitting control circuit 46.

[0289] The light emitting control circuit 46 is electrically connected with a second light emitting time control end EML, a power voltage end ELVDD and the first node N1 respectively, and is configured to control the power voltage end ELVDD and the first node N1 to be connected or disconnected under the control of a second light emitting time control signal provided by the second light emitting time control end EML.

[0290] The present application Figure 5 In the working process of the at least one embodiment of the pixel circuit shown, a display period can include a first stage and a second stage arranged in sequence.

[0291] In the first stage, the first initialization circuit 44 writes the initial voltage Vinit provided by the initial voltage terminal I1 to the control terminal of the drive circuit 10 under the control of the first reset control signal, so that the drive circuit 10 can turn on the connection between the first terminal and the second terminal at the beginning of the second stage; the second initialization circuit 45 writes the initial voltage Vinit to the first electrode of the light emitting element EL under the control of the first reset control signal, to control the light emitting element EL not to emit light and clear the charge remaining in the first electrode of the light emitting element EL;

[0292] In the second stage, the data writing circuit 41 writes the current control data voltage Vdata provided by the data line DL to the first node N1 under the control of the scan signal provided by the scan line GL; the compensation control circuit 42 controls the communication between the control terminal of the drive circuit 10 and the second node N2 under the control of the scan signal.

[0293] At the beginning of the second stage, the drive circuit 10 turns on the connection between the first node N1 and the second node N2, to charge the seventh energy storage circuit 43 through the current control data voltage Vdata, to raise the potential of the control terminal of the drive circuit 10, until the potential of the control terminal of the drive circuit 10 becomes Vdata+Vth, Vth is the threshold voltage of the drive transistor included in the drive circuit 10, the drive circuit 10 turns off the connection between the first node N1 and the second node N2, to stop charging, to perform threshold voltage compensation.

[0294] The pixel circuit in at least one embodiment of the present application further comprises a compensation control circuit, a data writing circuit and an eighth energy storage circuit; the first node is electrically connected with the power voltage terminal;

[0295] The first end of the eighth energy storage circuit is electrically connected with the control terminal of the drive circuit; the eighth energy storage circuit is used for storing electric energy;

[0296] The compensation control circuit is electrically connected with the scan line, the control terminal of the drive circuit and the second node respectively, and is used for controlling the communication or disconnection between the control terminal of the drive circuit and the second node under the control of the scan signal provided by the scan line;

[0297] The data writing circuit is electrically connected with the scan line, the data line and the second end of the eighth energy storage circuit respectively, and is used for writing the current control data voltage provided by the data line to the second end of the eighth energy storage circuit under the control of the scan signal.

[0298] The pixel circuit in at least one embodiment of the present application further comprises a reference voltage writing circuit;

[0299] The reference voltage writing circuit is electrically connected with the first control end, the second light-emitting time control end, the reference voltage end and the second end of the eighth energy storage circuit respectively, and is used for writing the reference voltage provided by the reference voltage end into the second end of the eighth energy storage circuit under the control of the first control signal provided by the first control end, and writing the reference voltage into the second end of the eighth energy storage circuit under the control of the second light-emitting time control signal provided by the second light-emitting time control end.

[0300] As shown in Figure 6 At least one embodiment of the pixel circuit shown in Figure 2 At least one embodiment of the pixel circuit shown in

[0301] The pixel circuit further comprises a compensation control circuit 42, a data writing circuit 41 and an eighth energy storage circuit 40.

[0302] The first end of the eighth energy storage circuit 40 is electrically connected with the control end of the driving circuit 10, and the eighth energy storage circuit 40 is used for storing electric energy.

[0303] The compensation control circuit 42 is electrically connected with the scan line GL, the control end of the driving circuit 10 and the second node respectively, and is used for controlling the control end of the driving circuit 10 to be connected or disconnected with the second node N2 under the control of the scan signal provided by the scan line GL.

[0304] The data writing circuit 41 is electrically connected with the scan line GL, the data line DL and the second end of the eighth energy storage circuit 40 respectively, and is used for writing the current control data voltage Vdata provided by the data line DL into the second end of the eighth energy storage circuit 40 under the control of the scan signal.

[0305] The pixel circuit further comprises a first initialization circuit 44.

[0306] The first initialization circuit 44 is electrically connected with the first control end R1, the initial voltage end I1 and the control end of the driving circuit 10 respectively, and is used for writing the initial voltage Vinit provided by the initial voltage end I1 into the control end of the driving circuit 10 under the control of the first control signal provided by the first control end R1.

[0307] The pixel circuit further comprises a reference voltage writing circuit 47.

[0308] The reference voltage writing circuit 47 is electrically connected with the first control end R1, the second light-emitting time control end EML, the reference voltage end VR and the second end of the eighth energy storage circuit 40 respectively, and is configured to write the reference voltage Vref provided by the reference voltage end VR into the second end of the eighth energy storage circuit 40 under the control of the first control signal provided by the first control end R1, and write the reference voltage Vref into the second end of the eighth energy storage circuit 40 under the control of the second light-emitting time control signal provided by the second light-emitting time control end EML.

[0309] The present application Figure 6 At least one embodiment of the pixel circuit shown in the working process, the display period can include a first stage and a second stage arranged in turn;

[0310] In the first stage, the first initialization circuit 44 writes the initial voltage Vinit provided by the initial voltage end I1 into the control end of the driving circuit 10 under the control of the first control signal provided by the first control end R1, so that the driving circuit 10 can turn on the connection between the power voltage end ELVDD and the second node N2 at the beginning of the second stage; the reference voltage writing circuit 47 writes the reference voltage Vref provided by the reference voltage end VR into the second end of the eighth energy storage circuit 40 under the control of the first control signal, so as to initialize the potential of the second end of the eighth energy storage circuit 40, so that the potential of the second end of the eighth energy storage circuit 40 is Vref;

[0311] In the second stage, the data writing circuit 41 is electrically connected with the scan line GL, the data line DL and the second end of the eighth energy storage circuit 40 respectively, and is configured to write the current control data voltage Vdata provided by the data line DL into the second end of the eighth energy storage circuit 40 under the control of the scan signal; the compensation control circuit 42 controls the communication between the control end of the driving circuit 10 and the second node N2 under the control of the scan signal, so as to charge the eighth energy storage circuit 40, until the driving circuit 10 breaks the connection between the power voltage end ELVDD and the second node N2 under the control of the potential of the control end, so as to perform threshold voltage compensation.

[0312] Optionally, the data writing circuit comprises a fifteenth transistor, the compensation control circuit comprises a sixteenth transistor, and the seventh energy storage circuit comprises a first storage capacitor;

[0313] The gate of the fifteenth transistor is electrically connected with the scan line, the first pole of the fifteenth transistor is electrically connected with the data line, and the second pole of the fifteenth transistor is electrically connected with the first node;

[0314] A gate of the sixteenth transistor is electrically connected with the scan line, a first pole of the sixteenth transistor is electrically connected with the control end of the driving circuit, and a second pole of the sixteenth transistor is electrically connected with the second node.

[0315] A first end of the first storage capacitor is electrically connected with the control end of the driving circuit, and a second end of the first storage capacitor is electrically connected with the power voltage end.

[0316] Optionally, the first initialization circuit comprises a seventeenth transistor, and the second initialization circuit comprises an eighteenth transistor.

[0317] A gate of the seventeenth transistor is electrically connected with the first control end, a first pole of the seventeenth transistor is electrically connected with the initial voltage end, and a second pole of the seventeenth transistor is electrically connected with the control end of the driving circuit.

[0318] A gate of the eighteenth transistor is electrically connected with the first control end, a first pole of the eighteenth transistor is electrically connected with the initial voltage end, and a second pole of the eighteenth transistor is electrically connected with the first pole of the light emitting element.

[0319] Optionally, the light emitting control circuit comprises a nineteenth transistor.

[0320] A gate of the nineteenth transistor is electrically connected with the second light emitting time control end, a first pole of the nineteenth transistor is electrically connected with the power voltage end, and a second pole of the nineteenth transistor is electrically connected with the first node.

[0321] Optionally, the first initialization circuit comprises a seventeenth transistor, and the second initialization circuit comprises an eighteenth transistor.

[0322] A gate of the seventeenth transistor is electrically connected with the first reset control end, a first pole of the seventeenth transistor is electrically connected with the initial voltage end, and a second pole of the seventeenth transistor is electrically connected with the control end of the driving circuit.

[0323] A gate of the eighteenth transistor is electrically connected with the first reset control end, a first pole of the eighteenth transistor is electrically connected with the initial voltage end, and a second pole of the eighteenth transistor is electrically connected with the first pole of the light emitting element.

[0324] Optionally, the compensation control circuit comprises a sixteenth transistor, the data writing circuit comprises a fifteenth transistor, and the eighth energy storage circuit comprises a second storage capacitor.

[0325] A first end of the second storage capacitor is electrically connected with the control end of the driving circuit.

[0326] The gate of the sixteenth transistor is electrically connected with the scan line, the first pole of the sixteenth transistor is electrically connected with the control end of the driving circuit, and the second pole of the sixteenth transistor is electrically connected with the second node.

[0327] The gate of the fifteenth transistor is electrically connected with the scan line, the first pole of the fifteenth transistor is electrically connected with the data line, and the second pole of the fifteenth transistor is electrically connected with the second end of the second storage capacitor.

[0328] Optionally, the reference voltage writing circuit comprises a nineteenth transistor and a twentieth transistor.

[0329] The gate of the nineteenth transistor is electrically connected with the first control end, the first pole of the nineteenth transistor is electrically connected with the reference voltage end, and the second pole of the nineteenth transistor is electrically connected with the second end of the eighth energy storage circuit.

[0330] The gate of the twentieth transistor is electrically connected with the second light-emitting time control end, the first pole of the twentieth transistor is electrically connected with the reference voltage end, and the second pole of the twentieth transistor is electrically connected with the second end of the eighth energy storage circuit.

[0331] In at least one embodiment of the present application, the light-emitting element can be a micro light-emitting diode, but is not limited thereto. In actual operation, the light-emitting element can also be a mini light-emitting diode, an organic light-emitting diode, or other types of light-emitting elements.

[0332] As shown in Figure 7 At least one embodiment of the pixel circuit shown in Figure 4 The light-emitting element is a micro light-emitting diode ML based on at least one embodiment of the pixel circuit shown in

[0333] The first writing circuit comprises a first transistor T1, the first energy storage circuit comprises a first capacitor C1, the first switch control circuit comprises a second transistor T2, and the second switch control circuit comprises a third transistor T3.

[0334] The gate of the first transistor T1 is electrically connected with the first control end R1, the source of the first transistor T1 is electrically connected with the data line DL, and the drain of the first transistor T1 is electrically connected with a first switch node NK1.

[0335] The first end of the first capacitor C1 is electrically connected with the first switch node NK1, and the second end of the first capacitor is electrically connected with an initial voltage end I1; the initial voltage end I1 is used to provide an initial voltage Vinit.

[0336] The gate of the second transistor T2 is electrically connected with the first switch node NK1, the source of the second transistor T2 is electrically connected with the second light-emitting time control end EML, and the drain of the second transistor T2 is electrically connected with the first control node NC1;

[0337] The gate of the third transistor T3 is electrically connected with the first switch node NK1, the source of the third transistor T3 is electrically connected with the first light-emitting time control end HF, and the drain of the third transistor T3 is electrically connected with the first control node NC1;

[0338] T1 and T2 are p-type transistors, and T3 is an n-type transistor;

[0339] The second write circuit comprises a fourth transistor T4, the second energy storage circuit comprises a second capacitor C2, the third switch control circuit comprises a fifth transistor T5, and the fourth switch control circuit comprises a sixth transistor T6;

[0340] The gate of the fourth transistor T4 is electrically connected with the second control end SL, the source of the fourth transistor T4 is electrically connected with the data line DL, and the drain of the fourth transistor T4 is electrically connected with the second switch node NK2;

[0341] The first end of the second capacitor C2 is electrically connected with the second switch node NK2, and the second end of the second capacitor C2 is electrically connected with an initial voltage end I1;

[0342] The gate of the fifth transistor T5 is electrically connected with the second switch node NK2, the source of the fifth transistor T5 is electrically connected with the third light-emitting time control end EMS, and the drain of the fifth transistor T5 is electrically connected with the second control node NC2;

[0343] The gate of the sixth transistor T6 is electrically connected with the second switch node NK2, the source of the sixth transistor T6 is electrically connected with the second light-emitting time control end EML, and the drain of the sixth transistor T6 is electrically connected with the second control node NC2;

[0344] T4 and T5 are p-type transistors, and T6 is an n-type transistor;

[0345] The driving circuit comprises a driving transistor T0;

[0346] The gate of the driving transistor T0 is connected with a driving control node N0, the source of the driving transistor T0 is electrically connected with the first node N1, and the drain of the driving transistor T0 is electrically connected with the second node N2;

[0347] The first on-off control circuit comprises a first control transistor TC1, and the second on-off control circuit comprises a second control transistor TC2;

[0348] The gate of the first control transistor TC1 is electrically connected with the first control node NC1, the source of the first control transistor TC1 is electrically connected with the second node N2, and the drain of the first control transistor TC1 is electrically connected with the third node N3; the third node N3 is electrically connected with the anode of the micro light emitting diode ML;

[0349] The gate of the second control transistor TC2 is electrically connected with the second control node NC2, the source of the second control transistor TC2 is electrically connected with the cathode of the micro light emitting diode ML, and the drain of the second control transistor TC2 is electrically connected with a low voltage end ELVSS;

[0350] T0 is a p-type transistor, TC1 and TC2 are p-type transistors;

[0351] The data writing circuit comprises a fifteenth transistor T15, the compensation control circuit comprises a sixteenth transistor T16, and the seventh energy storage circuit comprises a first storage capacitor Cs1;

[0352] The gate of the fifteenth transistor T15 is electrically connected with the scanning line GL, the source of the fifteenth transistor T15 is electrically connected with the data line DL, and the drain of the fifteenth transistor T15 is electrically connected with the first node N1;

[0353] The gate of the sixteenth transistor T16 is electrically connected with the scanning line GL, the source of the sixteenth transistor T16 is electrically connected with the driving control node N0, and the drain of the sixteenth transistor T16 is electrically connected with the second node N2;

[0354] T15 and T16 are p-type transistors;

[0355] The first end of the first storage capacitor Cs1 is electrically connected with the control end of the driving circuit 10, and the second end of the first storage capacitor Cs1 is electrically connected with a power voltage end ELVDD;

[0356] The first initialization circuit comprises a seventeenth transistor T17, and the second initialization circuit comprises an eighteenth transistor T18;

[0357] The gate of the seventeenth transistor T17 is electrically connected with the first control end R1, the source of the seventeenth transistor T17 is electrically connected with the initial voltage end I1, and the drain of the seventeenth transistor T17 is electrically connected with the driving control node N0;

[0358] The gate of the eighteenth transistor T18 is electrically connected to the first control terminal R1, the source of the eighteenth transistor T18 is electrically connected to the initial voltage terminal I1, and the drain of the eighteenth transistor T18 is electrically connected to the anode of the miniature light-emitting diode ML.

[0359] The light-emitting control circuit includes a nineteenth transistor T19;

[0360] The gate of the nineteenth transistor T19 is electrically connected to the second light emission timing control terminal EML, the source of the nineteenth transistor T19 is electrically connected to the power supply voltage terminal ELVDD, and the drain of the nineteenth transistor T19 is electrically connected to the first node N1.

[0361] T17, T18, and T19 are p-type transistors.

[0362] like Figure 8 As shown, the present invention Figure 7 In at least one embodiment of the pixel circuit shown, when displaying ultra-low grayscale, the display cycle includes a first stage t1, a second stage t2, a third stage t3, a fourth stage t4, and a fifth stage t5 set sequentially.

[0363] In the first phase t1, EML provides a high voltage signal, R1 provides a low voltage signal, GL provides a high voltage signal, SL provides a high voltage signal, DL provides a high voltage signal, EMS provides a high voltage signal, and HF provides a high voltage signal. Figure 9A As shown, T1 is turned on, C1 maintains the potential of NK1 at a high voltage, T3 is turned on to control the connection between NC1 and HF, and TC1 is turned off; T17 is turned on to write the initial voltage Vinit to the drive control node N0 so that T0 can be turned on when the second stage t2 begins; T18 is turned on to write Vinit to the anode of ML to initialize the anode potential of ML and clear the residual charge on the anode of ML.

[0364] like Figure 9A As shown, in the first stage t1, T19 is turned off, T16 is turned off, T15 is turned off, and T4 is turned off.

[0365] In the second stage t2, EML provides a high voltage signal, R1 provides a high voltage signal, GL provides a low voltage signal, SL provides a high voltage signal, DL provides the current control data voltage Vdata, EMS provides a high voltage signal, and HF provides a high voltage signal; as shown Figure 9B As shown, C1 maintains NK1 at a high voltage, T3 is turned on to control the connection between NC1 and HF, TC1 is turned off; T15 is turned on to write Vdata to the first node N1, and T16 is turned on.

[0366] At the beginning of the second stage t2, T0 is turned on to charge Cs1 through Vdata until T0 is turned off, and the potential of N0 becomes Vdata+Vth, Vth being the threshold voltage of T0;

[0367] As shown in the second stage t2, T19 is turned off, T17 is turned off, T18 is turned off, T1 is turned off, and T4 is turned off; Figure 9B

[0368] In the third stage t3, EML provides a high voltage signal, R1 provides a high voltage signal, GL provides a high voltage signal, SL provides a low voltage signal, DL provides a low voltage signal, EMS provides a high voltage signal, and HF provides a high voltage signal; as shown in the third stage t3, T4 is turned on, C2 maintains the potential of NK2 as a low voltage, T5 is turned on to control the communication between NK2 and EMS so that the potential of NK2 is a high voltage, and TC2 is turned off; Figure 9C

[0369] As shown in the third stage t3, T19 is turned off, T15 is turned off, T17 is turned off, T16 is turned off, T18 is turned off, TC1 is turned off, T1 is turned off, T2 is turned off, and T6 is turned off; Figure 9C

[0370] In the fourth stage t4, EML provides a low voltage signal, R1 provides a high voltage signal, GL provides a high voltage signal, SL provides a high voltage signal, DL provides a low voltage signal, and EMS provides a high voltage signal; as shown in the fourth stage t4, T19 is turned on, C1 maintains the potential of NK1 as a high voltage, T3 is turned on to control the communication between HF and NC1, TC1 is turned on when HF provides a low voltage signal, C2 maintains the potential of NK2 as a low voltage, T5 is turned on to control the communication between NC2 and EMS, TC2 is turned off, and O1 does not emit light; Figure 9D

[0371] As shown in the fourth stage t4, T15 is turned off, T17 is turned off, T18 is turned off, T16 is turned off, T1 is turned off, T2 is turned off, T4 is turned off, and T6 is turned off; Figure 9D

[0372] In the fifth stage t5, R1 provides a high voltage signal, GL provides a high voltage signal, and SL provides a high voltage signal; as shown in the fifth stage t5, T3 is turned on to control the communication between HF and NC1, and T5 is turned on to control the communication between EMS and NC2; as shown in the fifth stage t5, when EML, HF, and EMS all provide low voltage signals, T0 drives O1 to emit light; Figure 9E Figure 9E

[0373] As shown in the fifth stage t5, T2 is turned off, T1 is turned off, T4 is turned off, T6 is turned off, T16 is turned off, T17 is turned off, and T17 is turned off. Figure 9E

[0374] ​​​​​​​​The first stage t1 can be the initialization stage and the first data writing stage; the second stage t2 can be the second data writing stage and the compensation stage; the third stage t3 can be the third data writing time, as well as the selection time for long-term light emission and short-term light emission; the fourth stage t4 can be the selective light emission stage; and the fifth stage t5 can be the light emission stage.

[0375] exist Figure 8 In the diagram, the current labeled Id represents the drive current generated by the driving transistor T0.

[0376] This invention Figure 7 In at least one embodiment of the pixel circuit shown, during operation, in the second stage t2, the Vdata written by DL determines the light-emitting current. The value of Vdata can be greater than or equal to 12V and less than or equal to 18V. In the first stage t1 and the third stage t3, the voltage value of the voltage signal written by DL controls the corresponding transistor to turn on or off. When the voltage signal written by DL controls the n-type transistor to turn on, the voltage value of the voltage signal can be greater than or equal to 14V and less than or equal to 18V. When the voltage signal written by DL controls the p-type transistor to turn on, the voltage value of the voltage signal can be greater than or equal to -2V and less than or equal to 0V.

[0377] In at least one embodiment of the present invention, the voltage value of the low voltage signal provided by ELVSS can be 2V, and the voltage value of the power supply voltage signal provided by ELVDD can be 16V, but is not limited thereto.

[0378] This invention Figure 7 At least one embodiment of the pixel circuit shown operates in the second stage t2.

[0379] When displaying high grayscale, the voltage value of Vdata provided by DL can be greater than or equal to 12V and less than or equal to 15V;

[0380] When displaying low grayscale, the voltage value of Vdata provided by DL can be greater than or equal to 15V and less than or equal to 18V;

[0381] However, this is not the only limit.

[0382] Figure 10 This is the present invention. Figure 7 The timing diagram of at least one embodiment of the pixel circuit shown is displayed at high gray levels. Figure 11 This is the present invention. Figure 7 The timing diagram of at least one embodiment of the pixel circuit shown is displayed at low gray levels.

[0383] Figure 12 This invention Figure 7 The timing diagram of at least one embodiment of the pixel circuit shown is shown when displaying low grayscale.

[0384] As shown in Figure 10 at least one embodiment of the pixel circuit shown in the present application Figure 7 at least one embodiment of the pixel circuit shown in the present application

[0385] In the first stage t1, the DL provides a low voltage signal, T2 is turned on, and the EML is connected with the NC1;

[0386] In the third stage t3, the DL provides a high voltage signal, T6 is turned on, and the EML is connected with the NC2.

[0387] As shown in Figure 11 at least one embodiment of the pixel circuit shown in the present application Figure 7 at least one embodiment of the pixel circuit shown in the present application

[0388] In the first stage t1, the DL provides a low voltage signal, T2 is turned on, and the EML is connected with the NC1;

[0389] In the third stage t3, the DL provides a low voltage signal, T5 is turned on, and the EMS is connected with the NC2.

[0390] As shown in Figure 12 at least one embodiment of the pixel circuit shown in the present application Figure 7 at least one embodiment of the pixel circuit shown in the present application

[0391] In the first stage t1, the DL provides a high voltage signal, T3 is turned on, and the HF is connected with the NC1;

[0392] In the third stage t3, the DL provides a low voltage signal, T5 is turned on, and the EMS is connected with the NC2.

[0393] As shown in Figure 13 at least one embodiment of the pixel circuit shown in the present application Figure 5 at least one embodiment of the pixel circuit shown in the present application

[0394] The third write circuit comprises a seventh transistor T7, the fourth write circuit comprises an eighth transistor T8, the third energy storage circuit comprises a third capacitor C3, the fourth energy storage circuit comprises a fourth capacitor C4, the fifth switch control circuit comprises a ninth transistor T9, and the sixth switch control circuit comprises a tenth transistor T10;

[0395] The gate of the seventh transistor T7 is electrically connected with the first reset control end RA, the source of the seventh transistor T7 is electrically connected with the data line DL, and the drain of the seventh transistor T7 is electrically connected with the third switch node NK3;

[0396] A first end of the third capacitor C3 is electrically connected with the third switch node NK3, and a second end of the third capacitor C3 is electrically connected with the initial voltage terminal I1; the initial voltage terminal I1 is configured to provide an initial voltage Vinit.

[0397] A gate of the eighth transistor T8 is electrically connected with the second reset control terminal RB, a source of the eighth transistor T8 is electrically connected with the data line DL, and a drain of the eighth transistor T8 is electrically connected with the fourth switch node NK4;

[0398] A first end of the fourth capacitor C4 is electrically connected with the fourth switch node NK4, and a second end of the fourth capacitor C4 is electrically connected with the initial voltage terminal I1;

[0399] A gate of the ninth transistor T9 is electrically connected with the third switch node NK3, a source of the ninth transistor T9 is electrically connected with the second light-emitting time control terminal EML, and a drain of the ninth transistor T9 is electrically connected with the first control node NC1;

[0400] A gate of the tenth transistor T10 is electrically connected with the fourth switch node NK4, a source of the tenth transistor T10 is electrically connected with the first light-emitting time control terminal HF, and a drain of the tenth transistor T10 is electrically connected with the first control node NC1;

[0401] The fifth write-in circuit comprises an eleventh transistor T11, the sixth write-in circuit comprises a twelfth transistor T12, the seventh switch control circuit comprises a thirteenth transistor T13, the eighth switch control circuit comprises a fourteenth transistor T14, the fifth energy storage circuit comprises a fifth capacitor C5, and the sixth energy storage circuit comprises a sixth capacitor C6;

[0402] A gate of the eleventh transistor T11 is electrically connected with the third reset control terminal RC, a source of the eleventh transistor T11 is electrically connected with the data line DL, and a drain of the eleventh transistor T11 is electrically connected with the fifth switch node NK5;

[0403] A first end of the fifth capacitor C5 is electrically connected with the fifth switch node NK5, and a second end of the fifth capacitor C5 is electrically connected with the initial voltage terminal I1;

[0404] A gate of the twelfth transistor T12 is electrically connected with the fourth reset control terminal RD, a source of the twelfth transistor T12 is electrically connected with the data line DL, and a drain of the twelfth transistor T12 is electrically connected with the sixth switch node NK6;

[0405] A first end of the sixth capacitor C6 is electrically connected with the sixth switch node NK6, and a second end of the sixth capacitor C6 is electrically connected with the initial voltage terminal I1;

[0406] The gate of the thirteenth transistor T13 is electrically connected with the fifth switch node NK5, the source of the thirteenth transistor T13 is electrically connected with the second light-emitting time control terminal EML, and the drain of the thirteenth transistor T13 is electrically connected with the second control node NC2;

[0407] The gate of the fourteenth transistor T14 is electrically connected with the sixth switch node NK6, the source of the fourteenth transistor T14 is electrically connected with the third light-emitting time control terminal EMS, and the drain of the fourteenth transistor T14 is electrically connected with the second control node NC2;

[0408] The driving circuit comprises a driving transistor T0;

[0409] The gate of the driving transistor T0 is connected with a driving control node N0, the source of the driving transistor T0 is electrically connected with the first node N1, and the drain of the driving transistor T0 is electrically connected with the second node N2;

[0410] The first on-off control circuit comprises a first control transistor TC1, and the second on-off control circuit comprises a second control transistor TC2;

[0411] The gate of the first control transistor TC1 is electrically connected with the first control node NC1, the source of the first control transistor TC1 is electrically connected with the second node N2, and the drain of the first control transistor TC1 is electrically connected with the third node N3; the third node N3 is electrically connected with the anode of the micro light-emitting diode ML;

[0412] The gate of the second control transistor TC2 is electrically connected with the second control node NC2, the source of the second control transistor TC2 is electrically connected with the cathode of the micro light-emitting diode ML, and the drain of the second control transistor TC2 is electrically connected with a low-voltage terminal ELVSS;

[0413] The data writing circuit comprises a fifteenth transistor T15, the compensation control circuit comprises a sixteenth transistor T16, and the seventh energy storage circuit comprises a first storage capacitor Cs1;

[0414] The gate of the fifteenth transistor T15 is electrically connected with the scanning line GL, the source of the fifteenth transistor T15 is electrically connected with the data line DL, and the drain of the fifteenth transistor T15 is electrically connected with the first node N1;

[0415] The gate of the sixteenth transistor T16 is electrically connected with the scan line GL, the source of the sixteenth transistor T16 is electrically connected with the driving control node N0, and the drain of the sixteenth transistor T16 is electrically connected with the second node N2;

[0416] The first end of the first storage capacitor Cs1 is electrically connected with the driving control node N0, and the second end of the first storage capacitor Cs1 is electrically connected with the power voltage terminal ELVDD;

[0417] The first initialization circuit comprises a seventeenth transistor T17, and the second initialization circuit comprises an eighteenth transistor T18;

[0418] The gate of the seventeenth transistor T17 is electrically connected with the first reset control terminal RA, the source of the seventeenth transistor T17 is electrically connected with the initial voltage terminal I1, and the drain of the seventeenth transistor T17 is electrically connected with the driving control node N0; the initial voltage terminal I1 is used for providing an initial voltage Vinit;

[0419] The gate of the eighteenth transistor T18 is electrically connected with the first reset control terminal RA, the source of the eighteenth transistor T18 is electrically connected with the initial voltage terminal I1, and the drain of the eighteenth transistor T18 is electrically connected with the anode of the micro light emitting diode ML;

[0420] The light emitting control circuit comprises a nineteenth transistor T19;

[0421] The gate of the nineteenth transistor T19 is electrically connected with the second light emitting time control terminal EML, the source of the nineteenth transistor T19 is electrically connected with the power voltage terminal ELVDD, and the drain of the nineteenth transistor T19 is electrically connected with the first node N1.

[0422] In Figure 13 In at least one embodiment of the pixel circuit shown, all the transistors are p-type transistors, but the present application is not limited thereto.

[0423] As Figure 14 The present application Figure 13 In at least one embodiment of the pixel circuit shown, when displaying an ultra-low gray scale, the display period comprises a first stage t1, a second stage t2, a third stage t3, a fourth stage t4, a fifth stage t5 and a sixth stage t6 arranged in sequence in the working process;

[0424] In the first stage t1, the RA provides a low voltage signal, the T17 and T18 are turned on, the I1 provides an initial voltage Vinit to the driving control node N0 and the third node N3; the DL provides a high voltage signal, the T7 is turned on, the potential of the NK3 is high voltage, the T9 is turned off; the RB, the RC and the RD provide high voltage signals, the EML provides a high voltage signal, the T19 is turned off, the GL provides a high voltage signal, and the ML does not emit light;

[0425] In the second stage t2, the EML provides a high voltage signal, the T19 is still turned off, the EMS provides a high voltage signal, the HF provides a high voltage signal, the RA provides a high voltage signal, the T17 and the T18 are turned off, the GL provides a low voltage signal, the T15 and the T16 are turned on, the DL provides a current control data voltage Vdata, and the N0 and the N2 are connected;

[0426] At the beginning of the second stage t2, the T0 is turned on to charge the Cs1 by the Vdata until the T0 is turned off, and the potential of the N0 is Vdata+Vth; the Vth is a threshold voltage of the T0;

[0427] In the third stage t3, the EML provides a high voltage signal, the T19 is still kept in the turned-off state, the RA, the RC and the RD all provide high voltage signals, the T7, the T11 and the T12 are turned off, the RB provides a low voltage signal, the T8 is turned on, the DL provides a low voltage signal, the potential of the NK4 is low voltage, the T10 is turned on, the NC1 is connected with the HF, the HF provides a high voltage signal, and the potential of the NC1 is high voltage;

[0428] In the fourth stage t4, the EML provides a high voltage signal, the T19 is kept in the turned-off state, the RA, the RB and the RD all provide high voltage signals, the T7, the T8 and the T12 are turned off, the RC provides a low voltage signal, the T11 is turned on, the DL provides a high voltage signal, the potential of the NK5 is a high voltage signal, and the T13 is turned off;

[0429] In the fifth stage t5, the EML provides a high voltage signal, the T9 is kept in the turned-off state, the RA, the RB and the RC all provide high voltage signals, the T7, the T8 and the T11 are all turned off, the RD provides a low voltage signal, the T12 is turned on, the DL provides a low voltage signal, the potential of the NK6 is a low voltage signal, the T14 is turned on, the NC2 is connected with the EMS, and the potential of the NC2 is high voltage.

[0430] In the sixth stage t6, RA, RB, RC and RD all provide high voltage signals, GL provides a high voltage signal, EML provides a low voltage signal, T19 is turned on, C3 and C5 maintain the potential of NK3 and the potential of NK5 as high voltage, C4 and C6 maintain the potential of NK4 and the potential of NK6 as low voltage, T10 and T14 are opened, when HF and EMS provide low voltage signals at the same time, the potential of NC1 and the potential of NC2 are low voltage, TC1 and TC2 are turned on, T0 drives O1 to emit light.

[0431] The present application Figure 13 At least one embodiment of the pixel circuit shown in the present application can display low gray scale,

[0432] In the first stage, RA provides a low voltage signal, RB provides a high voltage signal, RC and RD both provide high voltage signals, DL provides a low voltage signal, T7 and T9 are turned on, EML is communicated with NC1;

[0433] In the third stage, RC provides a high voltage signal, RD provides a low voltage signal, RA and RB both provide high voltage signals, DL provides a low voltage signal, T12 and T14 are turned on, EMS is communicated with NC2.

[0434] The present application Figure 13 At least one embodiment of the pixel circuit shown in the present application can display low gray scale,

[0435] In the first stage, RA provides a high voltage signal, RB provides a low voltage signal, RC and RD both provide high voltage signals, DL provides a low voltage signal, T8 and T10 are turned on, HF is communicated with NC1;

[0436] In the third stage, RC provides a high voltage signal, RD provides a low voltage signal, RA and RB both provide high voltage signals, DL provides a low voltage signal, T12 and T14 are turned on, EMS is communicated with NC2.

[0437] In the present application Figure 13 In at least one embodiment of the pixel circuit shown in the present application, the gate of T17 and the gate of T18 can also be replaced by being electrically connected with the first control end R1.

[0438] As Figure 15 As Figure 6 In at least one embodiment of the pixel circuit shown in the present application, the light emitting element is a micro light emitting diode ML;

[0439] The first write-in circuit comprises a first transistor T1, the first energy storage circuit comprises a first capacitor C1, the first switch control circuit comprises a second transistor T2, and the second switch control circuit comprises a third transistor T3.

[0440] The gate of the first transistor T1 is electrically connected with the first control end R1, the source of the first transistor T1 is electrically connected with the data line DL, and the drain of the first transistor T1 is electrically connected with the first switch node NK1;

[0441] The first end of the first capacitor C1 is electrically connected with the first switch node NK1, and the second end of the first capacitor is electrically connected with the initial voltage end I1; the initial voltage end I1 is used for providing an initial voltage Vinit;

[0442] The gate of the second transistor T2 is electrically connected with the first switch node NK1, the source of the second transistor T2 is electrically connected with the second light-emitting time control end EML, and the drain of the second transistor T2 is electrically connected with the first control node NC1;

[0443] The gate of the third transistor T3 is electrically connected with the first switch node NK1, the source of the third transistor T3 is electrically connected with the first light-emitting time control end HF, and the drain of the third transistor T3 is electrically connected with the first control node NC1;

[0444] T1 and T2 are p-type transistors, and T3 is an n-type transistor;

[0445] The second write circuit comprises a fourth transistor T4, the second energy storage circuit comprises a second capacitor C2, the third switch control circuit comprises a fifth transistor T5, and the fourth switch control circuit comprises a sixth transistor T6;

[0446] The gate of the fourth transistor T4 is electrically connected with the second control end SL, the source of the fourth transistor T4 is electrically connected with the data line DL, and the drain of the fourth transistor T4 is electrically connected with the second switch node NK2;

[0447] The first end of the second capacitor C2 is electrically connected with the second switch node NK2, and the second end of the second capacitor C2 is electrically connected with the initial voltage end I1;

[0448] The gate of the fifth transistor T5 is electrically connected with the second switch node NK2, the source of the fifth transistor T5 is electrically connected with the third light-emitting time control end EMS, and the drain of the fifth transistor T5 is electrically connected with the second control node NC2;

[0449] The gate of the sixth transistor T6 is electrically connected with the second switch node NK2, the source of the sixth transistor T6 is electrically connected with the second light-emitting time control end EML, and the drain of the sixth transistor T6 is electrically connected with the second control node NC2;

[0450] T4 and T5 are p-type transistors, and T6 is an n-type transistor.

[0451] The driving circuit comprises a driving transistor T0;

[0452] The gate of the driving transistor T0 is connected with the driving control node N0, the source of the driving transistor T0 is electrically connected with the power voltage terminal ELVDD, and the drain of the driving transistor T0 is electrically connected with the second node N2;

[0453] The first on-off control circuit comprises a first control transistor TC1, and the second on-off control circuit comprises a second control transistor TC2;

[0454] The gate of the first control transistor TC1 is electrically connected with the first control node NC1, the source of the first control transistor TC1 is electrically connected with the second node N2, and the drain of the first control transistor TC1 is electrically connected with the third node N3; and the third node N3 is electrically connected with the anode of the micro light emitting diode ML;

[0455] The gate of the second control transistor TC2 is electrically connected with the second control node NC2, the source of the second control transistor TC2 is electrically connected with the cathode of the micro light emitting diode ML, and the drain of the second control transistor TC2 is electrically connected with the low voltage terminal ELVSS;

[0456] T0 is a p-type transistor, TC1 and TC2 are p-type transistors;

[0457] The first initialization circuit comprises a seventeenth transistor T17;

[0458] The gate of the seventeenth transistor T17 is electrically connected with the first control terminal R1, the source of the seventeenth transistor T17 is electrically connected with the initial voltage terminal I1, and the drain of the seventeenth transistor T17 is electrically connected with the driving control node N0;

[0459] T17 is a p-type transistor;

[0460] The compensation control circuit comprises a sixteenth transistor T16, the data writing circuit comprises a fifteenth transistor T15, and the eighth energy storage circuit comprises a second storage capacitor Cs2;

[0461] The first end of the second storage capacitor Cs2 is electrically connected with the driving control node N0;

[0462] The gate of the sixteenth transistor T16 is electrically connected with the scanning line GL, the source of the sixteenth transistor T16 is electrically connected with the driving control node N0, and the drain of the sixteenth transistor T16 is electrically connected with the second node N2;

[0463] The gate of the fifteenth transistor T15 is electrically connected with the scan line GL, the source of the fifteenth transistor T15 is electrically connected with the data line DL, and the drain of the fifteenth transistor T15 is electrically connected with the second end of the second storage capacitor Cs2;

[0464] Both T15 and T16 are p-type transistors;

[0465] The reference voltage writing circuit comprises a nineteenth transistor T19 and a twentieth transistor T20;

[0466] The gate of the nineteenth transistor T19 is electrically connected with the first control end R1, the source of the nineteenth transistor T19 is electrically connected with the reference voltage end VR, and the drain of the nineteenth transistor T19 is electrically connected with the second end of the second storage capacitor Cs2;

[0467] The gate of the twentieth transistor T20 is electrically connected with the second light-emitting time control end EML, the source of the twentieth transistor T20 is electrically connected with the reference voltage end VR, and the drain of the twentieth transistor T20 is electrically connected with the second end of the second storage capacitor Cs2;

[0468] Both T19 and T20 are p-type transistors.

[0469] The application Figure 15 At least one embodiment of the driving circuit shown in the working process, when displaying an ultra-low gray scale, the display period comprises a first stage, a second stage, a third stage, a fourth stage and a fifth stage t5 arranged in sequence;

[0470] In the first stage, EML provides a high voltage signal, R1 provides a low voltage signal, GL provides a high voltage signal, SL provides a high voltage signal, DL provides a high voltage signal, EMS provides a high voltage signal, HF provides a high voltage signal, T1 is turned on, C1 maintains the potential of NK1 as a high voltage, T3 is turned on to control the communication between NC1 and HF, TC1 is turned off; T17 is turned on to write the initial voltage Vinit to the driving control node N0, so that T0 can be turned on when the second stage t2 starts; VR provides a reference voltage Vref, T19 is turned on to write Vref to the second end of Cs2;

[0471] In the second stage, EML provides a high voltage signal, R1 provides a high voltage signal, GL provides a low voltage signal, SL provides a high voltage signal, DL provides a current control data voltage Vdata, EMS provides a high voltage signal, and HF provides a high voltage signal; C1 maintains the potential of NK1 as a high voltage, T3 is turned on to control the communication between NC1 and HF, TC1 is turned off; T15 is turned on to write Vdata to the second end of C2, and T16 is turned on;

[0472] At the beginning of the second stage, T0 is turned on to charge Cs2 until T0 is turned off, and the potential of N0 becomes Vdd+Vth, where Vdd is the voltage value of the power supply signal provided by ELVDD, and Vth is the threshold voltage of T0;

[0473] In the third stage, EML provides a high voltage signal, R1 provides a high voltage signal, GL provides a high voltage signal, SL provides a low voltage signal, DL provides a low voltage signal, EMS provides a high voltage signal, and HF provides a high voltage signal; T4 is turned on to maintain the potential of NK2 as a low voltage by C2, T5 is turned on to control the communication between NK2 and EMS so that the potential of NK2 is a high voltage, and TC2 is turned off;

[0474] In the fourth stage, EML provides a low voltage signal, R1 provides a high voltage signal, GL provides a high voltage signal, SL provides a high voltage signal, DL provides a low voltage signal, EMS provides a high voltage signal, T19 is turned on, C1 maintains the potential of NK1 as a high voltage, T3 is turned on to control the communication between HF and NC1, TC1 is turned on when HF provides a low voltage signal, C2 maintains the potential of NK2 as a low voltage, T5 is turned on to control the communication between NC2 and EMS, TC2 is turned off, and O1 does not emit light;

[0475] In the fourth stage, VR provides a reference voltage Vref, EML provides a low voltage signal, T20 is turned on, the potential of Cs2 changes from Vdata to Vref, and the potential of N0 changes to Vdd+Vth+Vref-Vdata;

[0476] In the fifth stage, R1 provides a high voltage signal, GL provides a high voltage signal, SL provides a high voltage signal, T3 is turned on to control the communication between HF and NC1, T5 is turned on to control the communication between EMS and NC2, and T0 drives O1 to emit light when EML, HF, and EMS all provide low voltage signals.

[0477] The pixel circuit shown in at least one embodiment of the present application can be used in a display, Figure 15 The pixel circuit shown in at least one embodiment of the present application can be used in a display,

[0478] In the first stage, DL provides a low voltage signal, T2 is turned on to control the communication between EML and NC1;

[0479] In the third stage, DL provides a high voltage signal, T6 is turned on to control the communication between EML and NC2.

[0480] The pixel circuit shown in at least one embodiment of the present application can be used in a display, Figure 15 The pixel circuit shown in at least one embodiment of the present application can be used in a display,

[0481] In the first stage, DL provides a low voltage signal, T2 is turned on to control the communication between EML and NC1;

[0482] In the third stage, the DL provides a low voltage signal, T5 is turned on, and the EMS is connected with the NC2.

[0483] The present application Figure 15 At least one embodiment of the pixel circuit shown in the present application can be used to display low gray scale,

[0484] In the first stage, the DL provides a high voltage signal, T3 is turned on, and the HF is connected with the NC1.

[0485] In the third stage, the DL provides a low voltage signal, T5 is turned on, and the EMS is connected with the NC2.

[0486] The present application Figure 15 The timing diagram of at least one embodiment of the pixel circuit shown in the present application can be the same as the timing diagram of the pixel circuit shown in the present application, but is not limited thereto. Figure 7 The timing diagram of at least one embodiment of the pixel circuit shown in the present application can be the same as the timing diagram of the pixel circuit shown in the present application, but is not limited thereto.

[0487] The present application provides a driving method, which is applied to the pixel circuit described above, and the driving method comprises the following steps:

[0488] The driving circuit generates a driving current for driving the light emitting element under the control of the potential at the control end thereof;

[0489] The first on-off control circuit controls the connection or disconnection between the second node and the third node under the control of the potential at the first control node;

[0490] The second on-off control circuit controls the connection or disconnection between the second electrode of the light emitting element and the first voltage end under the control of the potential at the second control node;

[0491] The first control circuit controls the connection between the first light emitting time control end or the second light emitting time control end and the first control node under the control of the first time control data voltage provided by the data line according to the first control signal;

[0492] The second control circuit controls the connection between the second light emitting time control end or the third light emitting time control end and the second control node under the control of the second time control data voltage provided by the data line according to the second control signal.

[0493] The present application provides a display device, which comprises the pixel circuit described above.

[0494] The above description is the preferred embodiment of the present application, and it should be pointed out that those skilled in the art can make some improvements and refinements without departing from the principles of the present application, and these improvements and refinements should also be considered as the protection scope of the present application.

Claims

1. A pixel circuit, characterized in that, It includes a driving circuit, a first on / off control circuit, a light-emitting element, a second on / off control circuit, a first control circuit, and a second control circuit; The first end of the driving circuit is electrically connected to the first node, and the second end of the driving circuit is electrically connected to the second node; the driving circuit is used to generate a driving current for driving the light-emitting element under the control of the potential at its control end. The first on / off control circuit is used to control the connection or disconnection between the second node and the third node under the control of the potential of the first control node; The first electrode of the light-emitting element is electrically connected to the third node; The first terminal of the second on / off control circuit is electrically connected to the second electrode of the light-emitting element, and the second terminal of the second on / off control circuit is electrically connected to the first voltage terminal. The second on / off control circuit is used to control the connection or disconnection between the second electrode of the light-emitting element and the first voltage terminal under the control of the potential of the second control node. The first control circuit is electrically connected to the first control terminal, the data line, the first light emission time control terminal, the second light emission time control terminal, and the first control node, respectively. It is used to control the first light emission time control terminal or the second light emission time control terminal to connect with the first control node according to the first time control data voltage provided by the data line under the control of the first control signal provided by the first control terminal. The second control circuit is electrically connected to the second control terminal, the data line, the second light emission time control terminal, the third light emission time control terminal, and the second control node, respectively. It is used to control the connection between the second light emission time control terminal or the third light emission time control terminal and the second control node according to the second time control data voltage provided by the data line under the control of the second control signal provided by the second control terminal.

2. The pixel circuit as described in claim 1, characterized in that, The first control circuit includes a first writing circuit, a first energy storage circuit, a first switch control circuit, and a second switch control circuit. The first writing circuit is electrically connected to the first control terminal, the data line and the first switch node respectively, and is used to write the first time control data voltage into the first switch node under the control of the first control signal provided by the first control terminal; The first energy storage circuit is electrically connected to the first switching node and is used to maintain the potential of the first switching node; The first switch control circuit is electrically connected to the first switch node, the second light emission time control terminal and the first control node respectively, and is used to control the connection or disconnection between the first control node and the second light emission time control terminal under the control of the potential of the first switch node; The second switch control circuit is electrically connected to the first switch node, the first light emission time control terminal, and the first control node, respectively, and is used to control the connection or disconnection between the first control node and the first light emission time control terminal under the control of the potential of the first switch node.

3. The pixel circuit as described in claim 1, characterized in that, The second control circuit includes a second writing circuit, a second energy storage circuit, a third switch control circuit, and a fourth switch control circuit; The second writing circuit is electrically connected to the second control terminal, the data line, and the second switch node, respectively, and is used to write the second time control data voltage provided by the data line into the second switch node under the control of the second control signal provided by the second control terminal; The second energy storage circuit is electrically connected to the second switching node to maintain the potential of the second switching node; The third switch control circuit is electrically connected to the second switch node, the third light emission time control terminal and the second control node respectively, and is used to control the connection or disconnection between the second control node and the third light emission time control terminal under the control of the potential of the second switch node. The fourth switch control circuit is electrically connected to the second switch node, the second light emission time control terminal, and the second control node, respectively, and is used to control the connection or disconnection between the second control node and the second light emission time control terminal under the control of the potential of the second switch node.

4. The pixel circuit as described in claim 1, characterized in that, The first control circuit includes a third write circuit, a fourth write circuit, a fifth switch control circuit, a sixth switch control circuit, a third energy storage circuit, and a fourth energy storage circuit; the first control terminal includes a first reset control terminal and a second reset control terminal. The third writing circuit is electrically connected to the first reset control terminal, the data line and the third switch node respectively, and is used to write the third time control data voltage provided by the data line into the third switch node under the control of the first reset control signal provided by the first reset control terminal. The third energy storage circuit is electrically connected to the third switching node and is used to maintain the potential of the third switching node; The fourth writing circuit is electrically connected to the second reset control terminal, the data line and the fourth switch node respectively, and is used to write the fourth time control data voltage provided by the data line into the fourth switch node under the control of the second reset control signal provided by the second reset control terminal. The fourth energy storage circuit is electrically connected to the fourth switching node and is used to maintain the potential of the fourth switching node; The fifth switch control circuit is electrically connected to the third switch node, the second light emission time control terminal and the first control node respectively, and is used to control the connection or disconnection between the second light emission time control terminal and the first control node under the control of the potential of the third switch node. The sixth switch control circuit is electrically connected to the fourth switch node, the first light emission time control terminal, and the first control node, respectively, and is used to control the connection or disconnection between the first light emission time control terminal and the first control node under the control of the potential of the fourth switch node.

5. The pixel circuit as described in claim 1, characterized in that, The second control circuit includes a fifth write circuit, a sixth write circuit, a seventh switch control circuit, an eighth switch control circuit, a fifth energy storage circuit, and a sixth energy storage circuit; the second control terminal includes a third reset control terminal and a fourth reset control terminal. The fifth writing circuit is electrically connected to the third reset control terminal, the data line and the fifth switch node respectively, and is used to write the fifth time control data voltage provided by the data line into the fifth switch node under the control of the third reset control signal provided by the third reset control terminal. The fifth energy storage circuit is electrically connected to the fifth switching node and is used to maintain the potential of the fifth switching node; The sixth writing circuit is electrically connected to the fourth reset control terminal, the data line and the sixth switch node respectively, and is used to write the sixth time control data voltage provided by the data line into the sixth switch node under the control of the fourth reset control signal provided by the fourth reset control terminal. The sixth energy storage circuit is electrically connected to the sixth switching node and is used to maintain the potential of the sixth switching node; The seventh switch control circuit is electrically connected to the fifth switch node, the second light emission time control terminal, and the second control node, respectively, and is used to control the connection or disconnection between the second light emission time control terminal and the second control node under the control of the potential of the fifth switch node. The eighth switch control circuit is electrically connected to the sixth switch node, the third emission time control terminal, and the second control node, respectively, and is used to control the connection or disconnection between the third emission time control terminal and the second control node under the control of the potential of the sixth switch node.

6. The pixel circuit as described in claim 1, characterized in that, The driving circuit includes a driving transistor; The gate of the driving transistor is electrically connected to the control terminal of the driving circuit, the first terminal of the driving circuit is electrically connected to the first node, and the second terminal of the driving circuit is electrically connected to the second node. The first on / off control circuit includes a first control transistor, and the second on / off control circuit includes a second control transistor; The gate of the first control transistor is electrically connected to the first control node, the first electrode of the first control transistor is electrically connected to the second node, and the second electrode of the first control transistor is electrically connected to the third node. The gate of the second control transistor is electrically connected to the second control node, the first electrode of the second control transistor is electrically connected to the second electrode of the light-emitting element, and the second electrode of the second control transistor is electrically connected to the first voltage terminal.

7. The pixel circuit as described in claim 2, characterized in that, The first writing circuit includes a first transistor, the first energy storage circuit includes a first capacitor, the first switch control circuit includes a second transistor, and the second switch control circuit includes a third transistor. The gate of the first transistor is electrically connected to the first control terminal, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the first switching node. The first terminal of the first capacitor is electrically connected to the first switching node, and the second terminal of the first capacitor is electrically connected to the initial voltage terminal. The gate of the second transistor is electrically connected to the first switching node, the first electrode of the second transistor is electrically connected to the second emission time control terminal, and the second electrode of the second transistor is electrically connected to the first control node. The gate of the third transistor is electrically connected to the first switching node, the first electrode of the third transistor is electrically connected to the first emission time control terminal, and the second electrode of the third transistor is electrically connected to the first control node.

8. The pixel circuit as described in claim 3, characterized in that, The second writing circuit includes a fourth transistor, the second energy storage circuit includes a second capacitor, the third switch control circuit includes a fifth transistor, and the fourth switch control circuit includes a sixth transistor. The gate of the fourth transistor is electrically connected to the second control terminal, the first terminal of the fourth transistor is electrically connected to the data line, and the second terminal of the fourth transistor is electrically connected to the second switching node. The first terminal of the second capacitor is electrically connected to the second switching node, and the second terminal of the second capacitor is electrically connected to the initial voltage terminal. The gate of the fifth transistor is electrically connected to the second switching node, the first terminal of the fifth transistor is electrically connected to the third emission time control terminal, and the second terminal of the fifth transistor is electrically connected to the second control node. The gate of the sixth transistor is electrically connected to the second switching node, the first electrode of the sixth transistor is electrically connected to the second light emission timing control terminal, and the second electrode of the sixth transistor is electrically connected to the second control node.

9. The pixel circuit as described in claim 4, characterized in that, The third write circuit includes a seventh transistor, the fourth write circuit includes an eighth transistor, the third energy storage circuit includes a third capacitor, the fourth energy storage circuit includes a fourth capacitor, the fifth switch control circuit includes a ninth transistor, and the sixth switch control circuit includes a tenth transistor. The gate of the seventh transistor is electrically connected to the first reset control terminal, the first terminal of the seventh transistor is electrically connected to the data line, and the second terminal of the seventh transistor is electrically connected to the third switch node. The first terminal of the third capacitor is electrically connected to the third switching node, and the second terminal of the third capacitor is electrically connected to the initial voltage terminal. The gate of the eighth transistor is electrically connected to the second reset control terminal, the first terminal of the eighth transistor is electrically connected to the data line, and the second terminal of the eighth transistor is electrically connected to the fourth switch node. The first terminal of the fourth capacitor is electrically connected to the fourth switching node, and the second terminal of the fourth capacitor is electrically connected to the initial voltage terminal. The gate of the ninth transistor is electrically connected to the third switching node, the first terminal of the ninth transistor is electrically connected to the second light emission timing control terminal, and the second terminal of the ninth transistor is electrically connected to the first control node. The gate of the tenth transistor is electrically connected to the fourth switching node, the first electrode of the tenth transistor is electrically connected to the first light emission timing control terminal, and the second electrode of the tenth transistor is electrically connected to the first control node.

10. The pixel circuit as described in claim 5, characterized in that, The fifth write circuit includes an eleventh transistor, the sixth write circuit includes a twelfth transistor, the seventh switch control circuit includes a thirteenth transistor, the eighth switch control circuit includes a fourteenth transistor, the fifth energy storage circuit includes a fifth capacitor, and the sixth energy storage circuit includes a sixth capacitor. The gate of the eleventh transistor is electrically connected to the third reset control terminal, the first terminal of the eleventh transistor is electrically connected to the data line, and the second terminal of the eleventh transistor is electrically connected to the fifth switch node. The first terminal of the fifth capacitor is electrically connected to the fifth switching node, and the second terminal of the fifth capacitor is electrically connected to the initial voltage terminal. The gate of the twelfth transistor is electrically connected to the fourth reset control terminal, the first terminal of the twelfth transistor is electrically connected to the data line, and the second terminal of the twelfth transistor is electrically connected to the sixth switch node. The first terminal of the sixth capacitor is electrically connected to the sixth switch node, and the second terminal of the sixth capacitor is electrically connected to the initial voltage terminal. The gate of the thirteenth transistor is electrically connected to the fifth switching node, the first terminal of the thirteenth transistor is electrically connected to the second light emission timing control terminal, and the second terminal of the thirteenth transistor is electrically connected to the second control node; The gate of the fourteenth transistor is electrically connected to the sixth switching node, the first terminal of the fourteenth transistor is electrically connected to the third emission timing control terminal, and the second terminal of the fourteenth transistor is electrically connected to the second control node.

11. The pixel circuit according to any one of claims 1 to 10, characterized in that, It also includes a data writing circuit, a compensation control circuit, and a seventh energy storage circuit; The data writing circuit is electrically connected to the scan line, the data line and the first node respectively, and is used to write the current-controlled data voltage provided by the data line into the first node under the control of the scan signal provided by the scan line. The compensation control circuit is electrically connected to the scan line, the control terminal of the drive circuit, and the second node, respectively, and is used to control the connection or disconnection between the control terminal of the drive circuit and the second node under the control of the scan signal. The seventh energy storage circuit is electrically connected to the control terminal of the drive circuit and is used to store electrical energy.

12. The pixel circuit according to any one of claims 1 to 3, characterized in that, It also includes a first initialization circuit and a second initialization circuit; The first initialization circuit is electrically connected to the first control terminal, the initial voltage terminal, and the control terminal of the driving circuit, respectively, and is used to write the initial voltage provided by the initial voltage terminal into the control terminal of the driving circuit under the control of the first control signal provided by the first control terminal. The second initialization circuit is electrically connected to the first control terminal, the initial voltage terminal, and the first electrode of the light-emitting element, respectively, and is used to write the initial voltage into the first electrode of the light-emitting element under the control of the first control signal.

13. The pixel circuit as described in claim 11, characterized in that, It also includes a light-emitting control circuit; The light emission control circuit is electrically connected to the second light emission time control terminal, the power supply voltage terminal, and the first node, respectively, and is used to control the connection between the power supply voltage terminal and the first node under the control of the second light emission time control signal provided by the second light emission time control terminal.

14. The pixel circuit as described in claim 4 or 5, characterized in that, The first control terminal includes a first reset control terminal and a second reset control terminal; The pixel circuit further includes a first initialization circuit and a second initialization circuit. The first initialization circuit is electrically connected to the first reset control terminal, the initial voltage terminal, and the control terminal of the drive circuit, respectively, and is used to write the initial voltage provided by the initial voltage terminal into the control terminal of the drive circuit under the control of the first reset control signal provided by the first reset control terminal. The second initialization circuit is electrically connected to the first reset control terminal, the initial voltage terminal, and the first electrode of the light-emitting element, respectively, and is used to write the initial voltage into the first electrode of the light-emitting element under the control of the first reset control signal.

15. The pixel circuit according to any one of claims 1 to 3, characterized in that, It also includes a compensation control circuit, a data writing circuit, and an eighth energy storage circuit; the first node is electrically connected to the power supply voltage terminal; The first terminal of the eighth energy storage circuit is electrically connected to the control terminal of the drive circuit; the eighth energy storage circuit is used to store electrical energy. The compensation control circuit is electrically connected to the scan line, the control terminal of the drive circuit, and the second node, respectively, and is used to control the connection or disconnection between the control terminal of the drive circuit and the second node under the control of the scan signal provided by the scan line. The data writing circuit is electrically connected to the scan line, the data line, and the second terminal of the eighth energy storage circuit, respectively, and is used to write the data voltage controlled by the current provided by the data line into the second terminal of the eighth energy storage circuit under the control of the scan signal.

16. The pixel circuit as described in claim 15, characterized in that, It also includes a reference voltage writing circuit; The reference voltage writing circuit is electrically connected to the first control terminal, the second emission time control terminal, the reference voltage terminal, and the second terminal of the eighth energy storage circuit, respectively. It is used to write the reference voltage provided by the reference voltage terminal into the second terminal of the eighth energy storage circuit under the control of the first control signal provided by the first control terminal, and to write the reference voltage into the second terminal of the eighth energy storage circuit under the control of the second emission time control signal provided by the second emission time control terminal.

17. The pixel circuit as described in claim 11, characterized in that, The data writing circuit includes a fifteenth transistor, the compensation control circuit includes a sixteenth transistor, and the seventh energy storage circuit includes a first storage capacitor; The gate of the fifteenth transistor is electrically connected to the scan line, the first terminal of the fifteenth transistor is electrically connected to the data line, and the second terminal of the fifteenth transistor is electrically connected to the first node. The gate of the sixteenth transistor is electrically connected to the scan line, the first terminal of the sixteenth transistor is electrically connected to the control terminal of the driving circuit, and the second terminal of the sixteenth transistor is electrically connected to the second node. The first end of the first storage capacitor is electrically connected to the control terminal of the driving circuit, and the second end of the first storage capacitor is electrically connected to the power supply voltage terminal.

18. The pixel circuit as described in claim 12, characterized in that, The first initialization circuit includes a seventeenth transistor, and the second initialization circuit includes an eighteenth transistor; The gate of the seventeenth transistor is electrically connected to the first control terminal, the first terminal of the seventeenth transistor is electrically connected to the initial voltage terminal, and the second terminal of the seventeenth transistor is electrically connected to the control terminal of the driving circuit. The gate of the eighteenth transistor is electrically connected to the first control terminal, the first electrode of the eighteenth transistor is electrically connected to the initial voltage terminal, and the second electrode of the eighteenth transistor is electrically connected to the first electrode of the light-emitting element.

19. The pixel circuit as described in claim 13, characterized in that, The light-emitting control circuit includes a nineteenth transistor; The gate of the nineteenth transistor is electrically connected to the second light emission timing control terminal, the first terminal of the nineteenth transistor is electrically connected to the power supply voltage terminal, and the second terminal of the nineteenth transistor is electrically connected to the first node.

20. The pixel circuit as described in claim 14, characterized in that, The first initialization circuit includes a seventeenth transistor, and the second initialization circuit includes an eighteenth transistor; The gate of the seventeenth transistor is electrically connected to the first reset control terminal, the first terminal of the seventeenth transistor is electrically connected to the initial voltage terminal, and the second terminal of the seventeenth transistor is electrically connected to the control terminal of the driving circuit. The gate of the eighteenth transistor is electrically connected to the first reset control terminal, the first terminal of the eighteenth transistor is electrically connected to the initial voltage terminal, and the second terminal of the eighteenth transistor is electrically connected to the first terminal of the light-emitting element.

21. The pixel circuit as described in claim 15, characterized in that, The compensation control circuit includes a sixteenth transistor, the data writing circuit includes a fifteenth transistor, and the eighth energy storage circuit includes a second storage capacitor; The first terminal of the second storage capacitor is electrically connected to the control terminal of the driving circuit; The gate of the sixteenth transistor is electrically connected to the scan line, the first terminal of the sixteenth transistor is electrically connected to the control terminal of the driving circuit, and the second terminal of the sixteenth transistor is electrically connected to the second node. The gate of the fifteenth transistor is electrically connected to the scan line, the first terminal of the fifteenth transistor is electrically connected to the data line, and the second terminal of the fifteenth transistor is electrically connected to the second terminal of the second storage capacitor.

22. The pixel circuit as described in claim 16, characterized in that, The reference voltage writing circuit includes a nineteenth transistor and a twentieth transistor; The gate of the nineteenth transistor is electrically connected to the first control terminal, the first terminal of the nineteenth transistor is electrically connected to the reference voltage terminal, and the second terminal of the nineteenth transistor is electrically connected to the second terminal of the eighth energy storage circuit. The gate of the twentieth transistor is electrically connected to the second light emission timing control terminal, the first terminal of the twentieth transistor is electrically connected to the reference voltage terminal, and the second terminal of the twentieth transistor is electrically connected to the second terminal of the eighth energy storage circuit.

23. A driving method applied to a pixel circuit as described in any one of claims 1 to 22, characterized in that, The driving method includes: The driving circuit generates a driving current to drive the light-emitting element under the control of the potential at its control terminal; The first on / off control circuit controls the connection or disconnection between the second node and the third node under the control of the potential of the first control node; The second on / off control circuit controls the connection or disconnection between the second electrode of the light-emitting element and the first voltage terminal under the control of the potential of the second control node; Under the control of the first control signal, the first control circuit controls the connection between the first light emission time control terminal or the second light emission time control terminal and the first control node according to the first time control data voltage provided by the data line. Under the control of the second control signal, the second control circuit controls the connection between the second light emission time control terminal or the third light emission time control terminal and the second control node according to the second time control data voltage provided by the data line.

24. A display device, characterized in that, Includes the pixel circuit as described in any one of claims 1 to 22.

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