Data receiving circuit and semiconductor device

Abstract

Embodiments of the present disclosure provide a data receiving circuit and a semiconductor device. The data receiving circuit includes multiple data paths, each of which includes an adder and a limiter. The adder is configured to receive multiple feedback signals and adjust the level of a first signal based on the multiple feedback signals, where the first signal is generated based on received input data; the limiter is configured to receive the first signal and sample the first signal in response to a corresponding sampling clock to output target data via an output node and provide a corresponding output signal to each of the multiple feedback nodes; wherein the feedback nodes that provide feedback signals to the adders of the data paths that receive the previous 3-bit input data are different from each other.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and more particularly to a data receiving circuit and a semiconductor device. Background Art

[0002] In memory applications, as signal transmission rates increase and clock frequencies rise, input data channel losses increasingly impact signal quality, easily leading to intersymbol interference (ISI). ISI refers to the phenomenon where previously transmitted input data affects the transmission of currently transmitted input data due to bandwidth limitations of the input data channel. Currently, equalization circuits are commonly used to compensate for the input data channel in order to reduce the adverse effects of intersymbol interference. Equalization circuits can be selected from CTLE (Continuous Time Linear Equalizer) or DFE (Decision Feedback Equalizer).

[0003] However, in current data receiving circuits, the rate of compensating input data needs to be further improved. Summary of the Invention

[0004] The embodiments of the present disclosure provide a data receiving circuit and a semiconductor device, which are at least conducive to shortening the feedback time of the first 2-bit input data participating in the DFE.

[0005] According to some embodiments of the present disclosure, on the one hand, an embodiment of the present disclosure provides a data receiving circuit, comprising: M data paths, each data path receiving input data and a sampling clock and outputting target data, and the phases of the sampling clocks received by each data path are different from each other, the i-th data path is any one of the M data paths, 1≤i≤M, M≥3; wherein the i-th data path comprises: an adder, configured to receive multiple feedback signals, and adjust the level of a first signal based on the multiple feedback signals, each feedback signal corresponds to an output signal output by a data path, and the data paths corresponding to the respective feedback signals are different from each other, wherein the first signal is generated based on the received input data; a limiter, configured to receive the first signal and sample the first signal in response to the corresponding sampling clock to output the target data via an output node, and provide a corresponding output signal to each feedback node in a plurality of feedback nodes; wherein the feedback nodes that provide the feedback signal to the adder of the data path receiving the previous 3-bit input data are different from each other.

[0006] In some embodiments, the i-th data path further includes: a first inverter having a first input terminal and a first output terminal, wherein the first input terminal and the first output terminal are respectively connected to different feedback nodes; wherein the feedback node connected to one of the first input terminal and the first output terminal provides the feedback signal to the adder of the data path receiving the previous 3-bit input data, and the feedback node connected to the other provides the feedback signal to the adder of the data path receiving the previous 2-bit input data.

[0007] In some embodiments, the multiple feedback nodes include a first feedback node and a second feedback node; the output signal output by the first feedback node is provided to the adder of the data path receiving the previous 1-bit input data; the output signal output by the second feedback node is provided to the adder of the data path receiving the previous 2-bit input data; wherein the output signal output by the first feedback node and the output signal output by the second feedback node are in phase with each other; the first input end is connected to the adder of the data path receiving the previous 3-bit input data; and the first output end is connected to the adder of the data path receiving the previous 2-bit input data.

[0008] In some embodiments, the limiter has a first output node and a second output node, and the signals of the first output node and the second output node are in phase; wherein the first output node serves as the first feedback node, and the second output node is connected to the first input terminal.

[0009] In some embodiments, the limiter includes: a sampling circuit, configured to receive the corresponding sampling clock to sample the first signal to output a second signal; a first output circuit, configured to delay and invert the second signal by a first delay amount to output one output signal via a first output node; a second output circuit, configured to delay and invert the second signal by a second delay amount to output another output signal via a second output node; wherein the first delay amount is less than the second delay amount.

[0010] In some embodiments, the first input terminal is further connected to the adder of the data path receiving the previous 4-bit input data.

[0011] In some embodiments, the multiple feedback nodes include a first feedback node and a second feedback node; the output signal output by the first feedback node is provided to the adder of the data path receiving the previous 1-bit input data; the output signal output by the second feedback node is provided to the adder of the data path receiving the previous 2-bit input data; wherein the output signal output by the first feedback node and the output signal output by the second feedback node are in anti-phase relationship with each other; the first input end is connected to the adder of the data path receiving the previous 2-bit input data; and the first output end is connected to the adder of the data path receiving the previous 3-bit input data.

[0012] In some embodiments, the limiter has a first output node and a second output node, and the signals of the first output node and the second output node are inverted; wherein the first output node serves as the first feedback node, and the second output node serves as the second feedback node and is connected to the first input terminal.

[0013] In some embodiments, the limiter includes: a sampling circuit, configured to receive the corresponding sampling clock to sample the first signal to output a second signal; a first output circuit, configured to delay the second signal by a first delay amount and invert the second signal to output one output signal via the first output node; a second output circuit, configured to delay the second signal by a second delay amount to output another output signal via the second output node; wherein the first delay amount is less than the second delay amount.

[0014] In some embodiments, the slicer is further configured so that the feedback nodes providing the output signals to the adders of the data paths receiving previous 4-bit input data are different from each other.

[0015] In some embodiments, the i-th data path further includes: a zeroth inverter having a second input terminal and a second output terminal, the second input terminal being connected to the feedback node; wherein the second input terminal is connected to the adder of the data path receiving the previous 3-bit input data, and the second output terminal is connected to the adder of the data path receiving the previous 4-bit input data.

[0016] In some embodiments, the data receiving circuit further includes an amplifier, which is used to receive the input data and output the first signal; wherein the amplifier includes a first comparison node and a second comparison node for providing the first signal; the adder is further configured to determine, based on the phase of each of the received feedback signals, whether the feedback signal is provided to the first comparison node or the second comparison node.

[0017] In some embodiments, M is 4.

[0018] According to some other embodiments of the present disclosure, another aspect of the present disclosure further provides a semiconductor device, comprising the data receiving circuit provided by any of the above embodiments.

[0019] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0020] In the technical solution of the data receiving circuit provided by the embodiment of the present disclosure, each data path includes an adder and a limiter, wherein the adder is configured to receive multiple feedback signals and adjust the level of a first signal based on the multiple feedback signals, each feedback signal corresponds to an output signal output by a data path, and the data paths corresponding to the feedback signals are different from each other, wherein the first signal is generated based on the received input data. The limiter is configured to receive the first signal and sample the first signal in response to a corresponding sampling clock to output target data via an output node and provide a corresponding output signal to each of the multiple feedback nodes; wherein the feedback nodes that provide feedback signals to the adder of the data path that receives the previous 3-bit input data are different from each other. Because the feedback signals corresponding to Tap-2 and Tap-3 are provided at different feedback nodes, the load on the transmission path of the feedback signal corresponding to Tap-2 can be reduced, and the startup speed of the adder controlled by the feedback signal corresponding to Tap-2 can be improved. This shortens the feedback time required for the Tap-2 feedback signal to participate in the DFE, and further shortens the feedback time for the first 2-bit input data to participate in the DFE. This improves the inter-symbol crosstalk problem while increasing the data transmission rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplifications do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the figures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0022] Figure 1 is a block diagram of a data receiving circuit;

[0023] Figure 2 A block diagram of a data receiving circuit provided in an embodiment of the present disclosure;

[0024] Figure 3 and Figure 4 Two different block diagrams of the data receiving circuit provided by the embodiments of the present disclosure;

[0025] Figure 5 1 is a waveform diagram of a signal at the first output terminal of the first inverter in the embodiment of the present disclosure and a waveform diagram of a corresponding signal when the first inverter is not provided;

[0026] Figure 6 For Figure 3 An architectural diagram of a data receiving circuit based on FIG.

[0027] Figure 7 for Figure 3 or Figure 6 A schematic diagram of a circuit structure of an adder;

[0028] Figure 8 1 is a schematic diagram of a circuit structure of an amplifier;

[0029] Figure 9 for Figure 3 and Figure 6 A circuit structure diagram of a corresponding limiter;

[0030] Figure 10 For Figure 4 An architectural diagram of a data receiving circuit based on FIG.

[0031] Figure 11 for Figure 10 A schematic diagram of a circuit structure of a middle limiter;

[0032] Figure 12 for Figure 10 A circuit structure diagram of the adder. DETAILED DESCRIPTION

[0033] As known from the background art, the rate at which a data receiving circuit compensates input data needs to be further improved.

[0034] Depending on the number of bits of previously transmitted input data participating in the DFE, the feedback equalization circuit in the data receiving circuit can be divided into 1-tap, 2-tap, 3-tap, and 4-tap equalization circuits. The feedback equalization circuit can even have more taps (i.e., more than 4). A tap is a tap. It can be understood that the feedback equalization circuit can include multiple tap adjustment circuits, each corresponding to a tap signal, which in turn corresponds to one bit of data. The currently transmitted input data is adjusted based on the tap signal. 1-tap refers to the participation of 1 bit of previously transmitted data in the DFE; 2-tap refers to the participation of 2 bits of previously transmitted data in the DFE; 3-tap refers to the participation of 3 bits of previously transmitted data in the DFE; and 4-tap refers to the participation of 4 bits of previously transmitted data in the DFE.

[0035] It should be noted that, unless otherwise specified, in the disclosed embodiments, "n-tap" refers to the nth bit of data previously transmitted participating in the DFE, and "Tap-n" refers to the nth bit of data previously transmitted participating in the DFE. For example, "Tap-1" refers to the first bit of data previously transmitted participating in the DFE, and "Tap-2" refers to the second bit of data previously transmitted participating in the DFE.

[0036] Figure 1 This is a block diagram of a data receiving circuit. Figure 1 Taking the data receiving circuit as an example, each data path includes an adder and a sampler (or slicer). The adders in the four data paths are represented by Summer#1, Summer#2, Summer#3, and Summer#4, respectively. The corresponding samplers are represented by Slicer#1, Slicer#2, Slicer#3, and Slicer#4, respectively. The target data output by the corresponding data paths are represented by OUT_I, OUT_Q, OUT_IB, and OUT_QB, respectively. The data receiving path may further include a DQ pin 11 that provides input data and an amplifier 12 connected to DQ pin 11. Amplifier 12 is connected to the adder. Multiple data paths may share amplifier 12. The phases of the sampling clocks received by the data paths that output the target data OUT_I, OUT_Q, OUT_IB, and OUT_QB may be 0°, 90°, 180°, and 270°, respectively.

[0037] For the data path of the output target data OUT_I: Adder Summer#1 receives the feedback signal from the output of sampler Slicer#4 as Tap-1 participating in DFE; receives the feedback signal from the output of sampler Slicer#3 as Tap-2 participating in DFE; receives the feedback signal from the output of sampler Slicer#2 as Tap-3 participating in DFE; receives the feedback signal from the output of sampler Slicer#1 as Tap-4 participating in DFE.

[0038] For the data path of the output target data OUT_Q: Adder Summer#2 receives the feedback signal from the output of sampler Slicer#1 as Tap-1 participating in DFE; receives the feedback signal from the output of sampler Slicer#4 as Tap-2 participating in DFE; receives the feedback signal from the output of sampler Slicer#3 as Tap-3 participating in DFE; receives the feedback signal from the output of sampler Slicer#2 as Tap-4 participating in DFE.

[0039] For the data path of the output target data OUT_IB: Adder Summer#3 receives the feedback signal from the output of sampler Slicer#2 as Tap-1 participating in DFE; receives the feedback signal from the output of sampler Slicer#1 as Tap-2 participating in DFE; receives the feedback signal from the output of sampler Slicer#4 as Tap-3 participating in DFE; receives the feedback signal from the output of sampler Slicer#3 as Tap-4 participating in DFE.

[0040] For the data path of the output target data OUT_QB: Adder Summer#4 receives the feedback signal from the output of sampler Slicer#3 as Tap-1 participating in DFE; receives the feedback signal from the output of sampler Slicer#2 as Tap-2 participating in DFE; receives the feedback signal from the output of sampler Slicer#11 as Tap-3 participating in DFE; receives the feedback signal from the output of sampler Slicer#4 as Tap-4 participating in DFE.

[0041] Each data path's limiter has a first feedback node (or first output port) for outputting Tap-1, and second feedback nodes (or second output ports) for outputting Tap-2, Tap-3, and Tap-4. The first feedback node and the second feedback node are independent of each other. The first feedback node is connected to only one adder, while the second feedback node must be directly connected to three adders.

[0042] In the above data path, the feedback time of Tap-1, Tap-2, Tap-3, and Tap-4 affects the effectiveness of DFE. Taking Tap-1 as an example, the feedback time of Tap-1 includes the time it takes for the feedback signal from Slicer #4 to be transmitted to Summer #1 and the time required for Summer #1 to start. Decision feedback equalization can only be effectively performed after Summer #1 starts. If the feedback time corresponding to each tap is long, it will not only affect the decision feedback equalization rate, but also make it difficult to increase the data transmission rate.

[0043] In the above data path, the feedback time requirements for each tap are different, with the feedback times for Tap-1, Tap-2, Tap-3, and Tap-4 increasing gradually. For example, the feedback time for Tap-1 is typically less than 1 UI (Unit Interval), the feedback time for Tap-2 is typically less than 2 UI, the feedback time for Tap-3 is typically less than 3 UI, and the feedback time for Tap-4 is typically less than 4 UI.

[0044] refer to Figure 1 It's not difficult to find that for each data path, the transmission path of the sampler's output as the feedback signal for Tap-1 is a separate feedback path. In other words, the sampler has a separate first output port, and the feedback signal output by the first output port serves as Tap-1 for another data path. This feedback path is relatively short, has a relatively small load, and has a relatively small parasitic resistance. Therefore, although Tap-1 has the most stringent feedback time requirements, the above-mentioned data receiving circuit can meet Tap-1's feedback time requirements.

[0045] Continue to refer Figure 1 Tap-2, Tap-3, and Tap-4 share the sampler's output port. The second output port corresponding to Tap-2, Tap-3, and Tap-4 in each data path is indicated by a dashed box. Because Tap-2, Tap-3, and Tap-4 share the second output port, the corresponding feedback path is relatively long, with a relatively large load and parasitic capacitance. Therefore, in the above circuit, the feedback time of Tap-2 is unlikely to be less than 2UI, resulting in a late startup time for Tap-2 in the adder.

[0046] From the above analysis, it can be seen that reducing the feedback time required by Tap-2 can enable the data receiving circuit to be used in storage systems with faster transmission rates, and can also ensure the effect of improving inter-symbol interference and improving data transmission rate.

[0047] The embodiments of the present disclosure provide a data receiving circuit that is at least beneficial in reducing the feedback time corresponding to Tap-2 and improving the data transmission rate. The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the embodiments of the present disclosure to help readers better understand the embodiments of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the embodiments of the present disclosure can be implemented.

[0048] Figure 2 A block diagram of a data receiving circuit provided in an embodiment of the present disclosure.

[0049] refer to Figure 2 The data receiving circuit includes M data paths. Each data path receives input data and a sampling clock CLK and outputs target data, and the sampling clock received by each data path has a different phase. The i-th data path is any data path among the M data paths, where 1≤i≤M and M≥3.

[0050] The i-th data path includes an adder 101 and a limiter 102. The adder 101 is configured to receive multiple feedback signals and adjust the level of the first signal based on the multiple feedback signals. Each feedback signal corresponds to an output signal output by a data path, and the data paths corresponding to the feedback signals are different from each other. The first signal is generated based on the received input data. The limiter 102 is configured to receive the first signal and sample the first signal in response to a corresponding sampling clock CLK to output target data via an output node and provide a corresponding output signal to each of the multiple feedback nodes; wherein the feedback nodes providing feedback signals to the adder 101 of the data path that received the previous 3-bit input data are different from each other.

[0051] Because each data path provides a different feedback node for the adder 101 of the data path receiving the previous 3-bit input data, Tap-1, Tap-2, and Tap-3 do not need to share the same output port of limiter 102. This avoids the problem of excessive startup time of adder 101 caused by Tap-2 and Tap-3 sharing the same output port of the limiter, and also reduces the load and parasitic capacitance of the feedback path corresponding to Tap-2. Therefore, the disclosed embodiments help reduce the feedback time corresponding to Tap-2, thereby improving the decision feedback equalization capability to improve the inter-symbol interference effect, and can also increase the data transmission rate.

[0052] The data receiving circuit provided by the embodiment of the present disclosure will be described in more detail below with reference to the accompanying drawings.

[0053] Continue to refer Figure 2 Taking M as 4 as an example, the four data paths are respectively the first data path, the second data path, the third data path and the fourth data path in ascending order of the phase of the sampling clock.

[0054] In order to illustrate the corresponding relationship between the adder 101 and the limiter 102 and each data path, the following description is made:

[0055] In the first data path, adder 101 is adder #1, limiter 102 is limiter #1, and the first signal is S1 #1. In the second data path, adder 101 is adder #2, limiter 102 is limiter #2, and the first signal is S1 #2. In the third data path, adder 101 is adder #3, limiter 102 is limiter #3, and the first signal is S1 #3. In the fourth data path, adder 101 is adder #4, limiter 102 is limiter #4, and the first signal is S1 #4.

[0056] It is understandable that, unless otherwise specified, the corresponding relationships among the data paths, the first signal, the adder, and the limiter in the subsequent figures all satisfy the above description.

[0057] The feedback node providing the feedback signal corresponding to Tap-1 is labeled n1 and can be defined as the first feedback node n1. In other words, the output signal output by the first feedback node n1 is provided to the adder 101 of the data path receiving the previous 1-bit input data. The feedback node providing the feedback signal corresponding to Tap-2 is labeled n2 and can be defined as the second feedback node n2. In other words, the output signal output by the second feedback node n2 is provided to the adder 101 of the data path receiving the previous 2-bit input data. The feedback node providing the feedback signal corresponding to Tap-3 is labeled n3 and can be defined as the third feedback node n3. In other words, the output signal output by the third feedback node n3 is provided to the adder 101 of the data path receiving the previous 3-bit input data.

[0058] The second feedback node n2 is different from the first feedback node n1, and the second feedback node n2 is different from the third feedback node n3. In other words, the second feedback node n2 and the third feedback node n3 are not directly connected. Direct connection means that there are no other components between the two nodes, and only a connecting line or a connecting wire exists between them.

[0059] Taking M as 4 as an example, the phases of the sampling clocks can be 0°, 90°, 180°, and 270° respectively.

[0060] It is understandable that in other embodiments, M may also be 3, that is, the data receiving circuit has 3 data paths. M may also be greater than or equal to 5. It should be noted that the following specific description will be given based on the embodiment of the present disclosure where M is 4.

[0061] Figure 3 and Figure 4 Two different block diagrams of the data receiving circuit provided in the embodiments of the present disclosure.

[0062] refer to Figure 3 and Figure 4 The i-th data path (or each data path) further includes a first inverter INV_1. The first inverter INV_1 has a first input terminal and a first output terminal, each of which is connected to a different feedback node. The feedback node connected to one of the first input terminal and the first output terminal provides a feedback signal to the adder 101 of the data path receiving the previous 3-bit input data, and the feedback node connected to the other of the first input terminal and the first output terminal provides a feedback signal to the adder 101 of the data path receiving the previous 2-bit input data.

[0063] In a specific example, the feedback node n3 connected to the first input terminal can provide a feedback signal to the adder 101 of the data path receiving the previous 3-bit input data, and the feedback node n2 connected to the first output terminal can provide a feedback signal to the adder 101 of the data path receiving the previous 2-bit input data. Figure 3 and Figure 4 As shown, the feedback node n2 is connected between the first output terminal of the first inverter INV_1 and the adder # 2 , and the feedback node n3 is connected between the first input terminal of the first inverter INV_1 and the adder # 3 .

[0064] Compared to the rising edge time and falling edge time of the signal received at the first input terminal of the first inverter INV_1, the rising edge time and falling edge time of the signal output after passing through the first inverter INV_1 can be reduced. That is, the signal can reach the maximum voltage level or the minimum voltage level in a shorter time, so that the adder 101 can be turned on more quickly. Accordingly, the time required for the adder 101 to reach the turned-on state is shortened, thereby shortening the response time of the adder 101, so that the adder 101 can more quickly correct the voltage level of the first signal based on the previously transmitted signal. It can be understood that if the signal received at the first input terminal of the first inverter INV_1 has a rising edge, the signal output at the first output terminal of the first inverter INV_1 has a corresponding falling edge; if the signal received at the input terminal of the first inverter INV_1 has a falling edge, the signal output at the first output terminal of the first inverter INV_1 has a corresponding rising edge.

[0065] Figure 5 1 is a waveform diagram of a signal at the first output terminal of the first inverter in an embodiment of the present disclosure and a waveform diagram of a corresponding signal when the first inverter is not provided.

[0066] refer to Figure 5 , the solid line 1 is a waveform diagram of the signal at the first output terminal of the first inverter, and the dotted line 2 is a waveform diagram of the corresponding signal when the first inverter is not provided.

[0067] Taking the case of a signal changing from a low-level signal to a high-level signal as an example, the time required for the corresponding signal to reach its maximum level when the first inverter is not provided is defined as t1, i.e., the rising edge time of the signal is t1. In the embodiment of the present disclosure, the time required for the signal to reach its maximum level is t2, i.e., the rising edge time of the signal is t2, and the delay caused by the first inverter INV_1 itself is t3. Therefore, compared to the solution without the first inverter, the overall response time of the adder 101 in the embodiment of the present disclosure is reduced by Δt, which is as follows:

[0068] △t=t1-t2-t3 (1)

[0069] Combined with the above analysis, combined with reference Figure 3 and Figure 5 The feedback signal provided by the second feedback node n2 can reach the maximum level or the minimum level more quickly, thereby speeding up the startup time of Tap-2 in the corresponding adder #2. That is, the feedback time of Tap-2 in adder #2 can be further shortened, thereby further improving the feedback speed of Tap-2 participating in the DFE.

[0070] Combined with the above analysis, combined with reference Figure 4 and Figure 5 The feedback signal provided by the third feedback node n3 can reach the maximum level or the minimum level more quickly, thereby speeding up the startup time of Tap-3 in the corresponding adder #3. That is, the feedback time of Tap-3 in adder #3 can be further shortened, thereby improving the feedback speed of Tap-3 participating in the DFE.

[0071] Figure 6 For Figure 3 An architectural diagram of a data receiving circuit based on FPGA.

[0072] Combined with reference Figure 3 and Figure 6The output signal output by the first feedback node n1 and the output signal output by the second feedback node n2 are in phase with each other. The first input terminal of the first inverter INV_1 is connected to the adder 101 of the data path receiving the previous 3-bit input data, and the first output terminal of the first inverter INV_1 is connected to the adder 101 of the data path receiving the previous 2-bit input data.

[0073] That is, the first input terminal is directly connected to the third feedback node n3, and the first output terminal is directly connected to the second feedback node n2.

[0074] The data receiving circuit may further include a DQ pin 103, an amplifier 104, and a clock pin 105. DQ pin 103 is used to provide input data, and amplifier 104 is used to receive the input data and output a first signal. Clock pin 105 is used to provide a sampling clock CLK. The sampling clocks received by each data path may be identified as CLK_I, CLK_Q, CLK_IB, and CLK_QB, respectively.

[0075] It is understandable that the adders 101 of different data paths can share the same amplifier 104. The embodiments of the present disclosure do not limit the connection relationship between the amplifier 104 and the adders 101 of each data path, as long as the input data can be transmitted. For example, different data paths can have independent amplifiers, and each amplifier is connected to the DQ pin, or every two data paths can be connected to the same amplifier, and each amplifier is connected to the DQ pin.

[0076] Figure 7 for Figure 3 or Figure 6 A schematic diagram of the circuit structure of the adder in FIG. It is understandable that due to the limited space, Figure 7 The parts corresponding to Tap-3 and Tap-4 are not shown separately, but are represented by Tap-n.

[0077] The first signal may be a differential signal pair, and the amplifier 101 includes a first comparison node NET1 and a second comparison node NET2 for providing the first signal. The adder 101 is configured to determine whether to provide the feedback signal to the first comparison node NET1 or the second comparison node NET2 based on the phase of each received feedback signal.

[0078] Adder 101 is connected to a first comparison node NET1 and a second comparison node NET2, which are used to provide a first signal. Adder 101 includes multiple current accumulators 11, each connected to the first comparison node NET1 and the second comparison node NET2. Four current accumulators 11 correspond to Tap-1, Tap-2, Tap-3, and Tap-4, respectively. The feedback signal received by each current accumulator 11 is also a differential signal pair, labeled FBn_P and FBn_N. The switch transistor can be a first NMOS transistor MN1.

[0079] Each current accumulator 11 includes two switching transistors 111. One switching transistor 111 is connected between a first feedback node NET1 and a load 131, and the other switching transistor 111 is connected between a second feedback node NET2 and the load 131. The load 131 is connected to a ground terminal GND. Each current accumulator 11 also includes a first selector 1211 and a second selector 1212. The output of the first selector 1211 is connected to the control terminal of one switching transistor 111. The first selector 1211 receives feedback signals FBn_P and FBn_N and outputs either feedback signal FBn_P or feedback signal FBn_N in response to the control signals. The output of the second selector 1212 is connected to the control terminal of the other switching transistor 111. The second selector 1212 receives feedback signals FBn_P and FBn_N and outputs either feedback signal FBn_P or feedback signal FBn_N in response to the control signals. The first and second control signals received by each current accumulator 11 are labeled TnT and TnB, respectively.

[0080] The following description will take the current accumulator 11 corresponding to Tap-1 as an example:

[0081] The control signal includes a first control signal T1T and a second control signal T1B which are inverted to each other; the first selector 1211 includes a first transmission gate TG1 and a second transmission gate TG2.

[0082] The first transmission gate TG1 has a first positive control terminal and a first negative control terminal, an input terminal receiving a feedback signal FB1_P, an output terminal connected to the control terminal of the corresponding switch tube 111, the first positive control terminal receiving a first control signal T1T, and the first negative control terminal receiving a second control signal T1B.

[0083] The second transmission gate TG2 has a second positive control terminal and a second negative control terminal, an input terminal receiving the feedback signal FB1_N, an output terminal connected to the control terminal of the corresponding switch tube 111, the second positive control terminal receiving the second control signal T1B, and the second negative control terminal receiving the first control signal T1T.

[0084] The second selector 1212 includes a third transmission gate TG3 and a fourth transmission gate TG4 .

[0085] The third transmission gate TG3 has a third positive control terminal and a third negative control terminal, an input terminal for receiving the feedback signal FB1_P, an output terminal connected to the control terminal of the corresponding switch tube 111, the third positive control terminal for receiving the second control signal T1B, and the third negative control terminal for receiving the first control signal T1T;

[0086] The fourth transmission gate TG4 has a fourth positive control terminal and a fourth negative control terminal, an input terminal receiving the feedback signal FB1_N, and an output terminal connected to the control terminal of the corresponding switch tube 111. The fourth positive control terminal receives the first control signal T1T, and the fourth negative control terminal receives the second control signal T1B.

[0087] For any transmission gate among the first transmission gate TG1, the second transmission gate TG2, the third transmission gate TG3 and the fourth transmission gate TG4, each has a positive control end and a negative control end. If the control signal received by the positive control end is a high-level signal and the control signal received by the negative control end is a low-level signal, the input end and the output end of the transmission gate are connected, that is, the transmission gate is turned on; if the control signal received by the positive control end is a low-level signal and the control signal received by the negative control end is a high-level signal, the input end and the output end of the transmission gate are cut off, that is, the transmission gate is cut off.

[0088] It should be noted that because Tap-2 and Tap-3 are in anti-phase relation, the conduction logic of the first selector 1211 and the second selector 1212 in the current accumulator 11 corresponding to Tap-2 and Tap-3 differs. Specifically, if, in the current accumulator 11 corresponding to Tap-1, the first selector 1211 is turned on to enable the feedback signal FB1_P to adjust the voltage level of the first comparison node NET1, and the second selector 1212 is turned on to enable the feedback signal FB1_N to adjust the voltage level of the second comparison node NET2, then, in the current accumulator 11 corresponding to Tap-2, the first selector 1211 is turned on to enable the feedback signal FB2_N to adjust the voltage level of the first comparison node NET1, and the second selector 1212 is turned on to enable the feedback signal FB2_P to adjust the voltage level of the second comparison node NET2. Based on this logic, the connection relationship between the first control signal T2T and the second control signal T2B and the control terminals of each transmission gate in the current accumulator 11 corresponding to Tap-2 is appropriately selected.

[0089] The first inverter IVN_1 can be composed of multiple MOS transistors. The ratio of the channel width of the MOS transistors forming the first inverter INV_1 to the channel width of the MOS transistors forming the switch transistor can be within a range of 1:2 to 1:1. Thus, the first inverter INV_1 is composed of relatively small MOS transistors, which means that the first inverter INV_1 occupies a relatively small circuit area and the parasitic capacitance introduced by the first inverter INV_1 is also relatively small.

[0090] In addition, the first inverter INV_1 may be disposed at a position close to the adder 101 .

[0091] Figure 8 This is a circuit diagram of an amplifier. It should be noted that: Figure 8 This is only an example, and the embodiment of the present disclosure does not limit the specific circuit structure of the amplifier, as long as it can receive input data and output a first signal corresponding to the input data.

[0092] refer to Figure 8 The amplifier may include a first resistor R1 and a second resistor R2 connected to an operating power supply VDD. It also includes a ninth NMOS transistor MN9 and a tenth NMOS transistor MN10. The drain of the ninth NMOS transistor MN9 is connected to one end of the first resistor R1 and to a first comparison node NET1, and its gate receives a reference voltage Vref. The drain of the tenth NMOS transistor MN10 is connected to one end of the second resistor R2 and to a second comparison node NET2, and its gate receives input data DQ. The sources of the ninth NMOS transistor MN9 and the tenth NMOS transistor MN10 are connected to a ground terminal GND via a current source I.

[0093] Figure 9 for Figure 3 and Figure 6 A circuit structure diagram of the corresponding limiter.

[0094] Combined with reference Figure 3 、 Figure 6 and Figure 9 The limiter 102 has a first output node O1 and a second output node O2. The signals of the first output node O1 and the second output node O2 are in phase. The first output node O1 serves as a first feedback node n1, and the second output node O2 is connected to the first input terminal. The second output node O2 serves as a third feedback node n3.

[0095] Specifically, the second output node O2 is directly connected to the input of the first inverter INV_1 , the second feedback node n2 is directly connected to the output of the first inverter INV_1 , and the second feedback node n2 is directly connected to the adder 101 .

[0096] It is understood that the output signal can be a differential signal pair. Accordingly, the first output node O1 includes first output nodes n1_b and n1_p for outputting the differential signal pair; the second output node O2 includes second output nodes n2_b and n2_p for outputting the differential signal pair. The first output node n1_b is used to output the feedback signal FB1_N, and the first output node n1_p is used to output the feedback signal FB1_P.

[0097] The signals of the first output node O1 and the second output node O2 are in phase, which means that the signals of the first output node n1_b and the second output node n2_b are in phase with each other, and the signals of the first output node n1_p and the second output node n2_p are in phase with each other.

[0098] Continue to refer Figure 9 The limiter 102 may include: a sampling circuit 112, configured to receive a corresponding sampling clock CLK to sample the first signal (not labeled) to output a second signal (not labeled); a first output circuit 122, configured to delay the second signal by a first delay amount and invert the second signal to output an output signal via a first output node O1; a second output circuit 132, configured to delay the second signal by a second delay amount and invert the second signal to output another output signal via a second output node O2; wherein the first delay amount is smaller than the second delay amount.

[0099] The sampling circuit 112 may include a comparison circuit, a latch circuit, and a reset circuit.

[0100] The comparison circuit may include a first MOS transistor M1 and a second MOS transistor M2, wherein the gate of the first MOS transistor M1 is connected to the second comparison node NET2, the gate of the second MOS transistor M2 is connected to the first comparison node NET1, and one end of the first MOS transistor M1 and one end of the second MOS transistor M2 are both connected to the ground terminal GND.

[0101] The latch circuit includes a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, and a sixth MOS transistor M6. The gate of the third MOS transistor M3 is connected to the gate of the fifth MOS transistor M5, and is connected to the first output circuit 122 and the second output circuit 132. One end of the third MOS transistor M3 is connected to one end of the fifth MOS transistor. The gate of the fourth MOS transistor M4 is connected to the gate of the sixth MOS transistor M6. One end of the third MOS transistor M3 is connected to one end of the fifth MOS transistor M5, and is also connected to the first output circuit 122 and the second output circuit 132.

[0102] The reset circuit may include a seventh MOS transistor M7, an eighth MOS transistor M8, and a ninth MOS transistor M9. The gate of the seventh MOS transistor M7 receives a sampling clock and is connected between the first MOS transistor M1 and the fifth MOS transistor M5. The gate of the eighth MOS transistor M8 receives a sampling clock and is connected between the second MOS transistor M2 and the sixth MOS transistor 6. The gate of the ninth MOS transistor M9 receives a sampling clock and is connected between the fifth MOS transistor M5 and the sixth MOS transistor M6.

[0103] The reset circuit may further include a tenth MOS transistor M10 and an eleventh MOS transistor M11. The gates of the tenth MOS transistor M10 and the eleventh MOS transistor M11 each receive a sampling clock CLK. One end of the tenth MOS transistor M10, one end of the third MOS transistor M3, one end of the fourth MOS transistor M4, and one end of the eleventh MOS transistor M11 are all connected to an operating power supply VDD.

[0104] The sampling circuit has two output terminals for outputting a differential signal pair, with reference to Figure 9 The two output ends are respectively the connection node between the third MOS transistor M3 and the fifth MOS transistor M5, and the connection node between the fourth MOS transistor M4 and the sixth MOS transistor M6.

[0105] Continue to refer Figure 9 The first output circuit 122 may include a second inverter INV_2 connected between the first output node O1 and the output terminal of the sampling circuit. Specifically, the first output circuit 122 includes the second inverter INV_2 connected between the first output node n1_p and one end of the third MOS transistor M3, and also includes a second inverter INV_2 connected between the first output node n1_b and one end of the fourth MOS transistor M4.

[0106] Continue to refer Figure 9 The second output circuit 132 may include an SR latch and a third inverter INV_3. The SR latch includes a first NAND gate A1 and a second NAND gate A2, and the R input terminal and the S input terminal are respectively connected to the two output terminals of the sampling circuit, and a third inverter is provided between the Q output terminal of the SR latch and the second output node n2_b.

[0107] INV_3, A third inverter INV_3 is provided between the output terminal and the second output node n2_p.

[0108] In addition, the second output node O2 may serve as an output node for outputting target data.

[0109] It should be noted that the embodiments of the present disclosure do not limit the specific circuitry of the sampling circuit. Other specific circuit structures capable of sampling the first signal in response to a sampling clock can also serve as the sampling circuit in the embodiments of the present disclosure. Similarly, as long as the first delay amount can be less than the second delay amount, other circuits can also serve as the first output circuit and the second output circuit.

[0110] Combined with reference Figure 3 、 Figure 6 as well as Figure 9 , the first input terminal can also be connected to the adder 101 of the data path of the previous 4-bit input data. In other words, the feedback signal corresponding to Tap-3 and the feedback signal corresponding to Tap-4 can share the same feedback path. That is, the third feedback node used to provide the feedback signal corresponding to Tap-3 and the fourth feedback node used to provide the feedback signal corresponding to Tap-4 share the same feedback node. In other words, the second output node O2 is also connected to the adder 101 of the data path that receives the previous 4-bit data.

[0111] The limiter 102 can also be configured so that the feedback nodes providing output signals to the adder 101 of the data path receiving the previous 4-bit input data are different from each other. In other words, the third feedback node n3 and the fourth feedback node n4 are not shared, or in other words, the third feedback node n3 and the fourth feedback node n4 are not directly connected. Similarly, since the third feedback node n3 and the fourth feedback node n3 are not shared, the feedback speed for Tap-3 in the adder 101 can be reduced, further shortening the time required for decision feedback equalization. Accordingly, the i-th data path also includes: a zero-th inverter having a second input and a second output, the second input connected to a feedback node; wherein the second input is connected to the adder 101 of the data path receiving the previous 3-bit data, and the second output is connected to the adder 101 of the data path receiving the previous 4-bit data.

[0112] Figure 10 For Figure 4 An architectural diagram of a data receiving circuit based on . Figure 4 and Figure 10 The output signal output by the first feedback node n1 and the output signal output by the second feedback node n2 are in anti-phase relationship with each other; the first input end is connected to the adder 101 of the data path receiving the previous 2-bit data; the first output end is connected to the adder 101 of the data path receiving the previous 3-bit data.

[0113] Specifically, the first feedback node n1 is directly connected to the first output node O1, and the second feedback node n2 is directly connected to the second output node O2. Since the signals of the first output node O1 and the second output node O2 are in anti-phase relation, the output signal output by the first feedback node n1 and the output signal output by the second feedback node n2 are in anti-phase relation.

[0114] The signals of the first output node O1 and the second output node O2 are in anti-phase, which means that the signals of the first output node n1_b and the second output node n2_b are in anti-phase with each other, and the signals of the first output node n1_p and the second output node n2_p are in anti-phase with each other.

[0115] The first input terminal serves as the second feedback node n2, and the first output terminal serves as the third feedback node n3. Tap-2 and Tap-3 thus employ distributed loads, with each Tap having a separate feedback path. This reduces the load on the feedback paths of Tap-2 and Tap-3, shortening the time delay on these paths and thereby increasing the feedback rate of the DFE.

[0116] Furthermore, a first inverter INV_1 can be provided between the third feedback node n3 and the fourth feedback node n4. This allows Tap-2, Tap-3, and Tap-4 to all employ distributed loads, with each Tap having a separate feedback path. This reduces the load on the feedback paths corresponding to Tap-2, Tap-3, and Tap-4, shortening the time delay on these paths and thereby increasing the feedback rate of the DFE.

[0117] It is understandable that, in some examples, the third feedback node n3 and the fourth feedback node n4 may also be the same feedback node.

[0118] A first inverter INV_1 may also be provided between the fourth feedback node n4 and the output node no. In this way, the driving capability of the target data transmitted from the fourth feedback node n4 to the output node no can be improved.

[0119] Figure 11 for Figure 10 A circuit diagram of a mid-limiter. Figure 11 and Figure 9 The corresponding structures are roughly the same, the main difference is Figure 11 The SR latch is directly connected to the second output node O2 without an inverter.

[0120] refer to Figure 10 and Figure 11The limiter 102 has a first output node O1 and a second output node O2. The signals of the first output node O1 and the second output node O2 are in opposite phases. The first output node O1 serves as a first feedback node n1, and the second output node O2 serves as a second feedback node n2 and is connected to the first input terminal.

[0121] The limiter 101 includes: a sampling circuit 112, configured to receive a corresponding sampling clock CLK to sample a first signal to output a second signal; a first output circuit 122, configured to delay and invert the second signal by a first delay amount to output an output signal via a first output node O1; a second output circuit 132, configured to delay the second signal by a second delay amount to output another output signal via a second output node O2; wherein the first delay amount is smaller than the second delay amount.

[0122] Figure 12 for Figure 10 A schematic diagram of a circuit structure of the adder in FIG. It should be noted that, Figure 12 and Figure 7 The circuit structure of the corresponding adder is roughly the same. For the specific structure of the adder, please refer to Figure 7 The corresponding descriptions will not be repeated below.

[0123] It should be noted that, in conjunction with the reference Figure 11 and Figure 12 Because a first inverter INV_1 is provided between each of the second feedback node n2, the third feedback node n3, and the fourth feedback node n4, to ensure that the feedback signal correctly adjusts the voltage levels of the first comparison node NET1 and the second comparison node NET2, the control logic of the control signal for the current accumulators 11 of Tap-2 and Tap-4 is different from the control logic of the control signal for the current accumulators of Tap-1 and Tap-3.

[0124] If, in the current accumulators 11 corresponding to Tap-1 and Tap-3, the first selector 1211 is turned on to enable the feedback signal FBn_P to adjust the voltage level of the first comparison node NET1, and the second selector 1212 is turned on to enable the feedback signal FBn_N to adjust the voltage level of the second comparison node NET2, then, in the current accumulators 11 corresponding to Tap-2 and Tap-4, the first selector 1211 is turned on to enable the feedback signal FBn_N to adjust the voltage level of the first comparison node NET1, and the second selector 1212 is turned on to enable the feedback signal FBn_P to adjust the voltage level of the second comparison node NET2. Based on this logic, the connection relationship between the first control signal T2T and the second control signal T2B and the control terminals of each transmission gate in the current accumulator corresponding to Tap-2 is appropriately selected. For Tap-1, FBn_P and FBn_N refer to FB1_P and FB1_N, respectively. For Tap-2, FBn_P and FBn_N refer to FB2_P and FB2_N, respectively. For Tap-3, FBn_P and FBn_N refer to FB3_P and FB3_N, respectively. For Tap-4, FBn_P and FBn_N refer to FB4_P and FB4_N, respectively.

[0125] The data receiving circuit provided by the disclosed embodiments can reduce the feedback time required for the feedback signal corresponding to Tap-2 to participate in decision feedback equalization, reduce the time delay of the feedback signal corresponding to Tap-2 on the transmission path to the corresponding adder 101, and also help increase the speed at which the current accumulator corresponding to Tap-2 in the adder is turned on. In summary, the disclosed embodiments are conducive to improving the decision feedback equalization rate, while improving the data transmission rate while alleviating inter-symbol interference.

[0126] Accordingly, an embodiment of the present disclosure further provides a semiconductor device, comprising the data receiving circuit provided by the above embodiment.

[0127] The semiconductor device may be a DRAM or an SRAM. The DRAM may be an SDRAM, which may be a DDR SDRAM, such as DDR4, DDR5, DDR6, LPDDR4, LPDDR5, or LPDDR6. In some embodiments, the semiconductor device may be a memory chip, which may be a DRAM chip or an SRAM chip. In addition, the input data may be DQ input data.

[0128] In some examples, M can be 4.

[0129] From the above analysis, it can be seen that the semiconductor device can improve the inter-symbol interference problem while at least reducing the feedback delay of the previously transmitted 2-bit input data participating in the DFE, thereby improving the DFE effect and increasing the data transmission rate.

[0130] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present disclosure, and in actual applications, various changes may be made to them in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure. Therefore, the scope of protection of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A data receiving circuit, characterized in that: include: M data paths, each data path receives input data and a sampling clock and outputs target data, and the sampling clocks received by each data path have different phases, the i-th data path is any one of the M data paths, 1≤i≤M, M≥3; wherein the i-th data path includes: an adder configured to receive a plurality of feedback signals and adjust a level of a first signal based on the plurality of feedback signals, wherein each feedback signal corresponds to an output signal output by a data path, and the data paths corresponding to the feedback signals are different from each other, wherein the first signal is generated based on the received input data; The limiter is configured to receive the first signal and sample the first signal in response to the corresponding sampling clock to output the target data via an output node and provide a corresponding output signal to each of a plurality of feedback nodes; wherein the feedback nodes that provide the feedback signal to the adder of the data path that receives the previous 3-bit input data are different from each other.

2. The data receiving circuit according to claim 1, wherein: The i-th data path further includes: A first inverter has a first input terminal and a first output terminal, wherein the first input terminal and the first output terminal are respectively connected to different feedback nodes; The feedback node connected to one of the first input terminal and the first output terminal provides the feedback signal to the adder of the data path receiving the previous 3-bit input data, and the feedback node connected to the other one provides the feedback signal to the adder of the data path receiving the previous 2-bit input data.

3. The data receiving circuit according to claim 2, wherein: The plurality of feedback nodes include a first feedback node and a second feedback node; the output signal output by the first feedback node is provided to the adder of the data path receiving the previous 1-bit input data; the output signal output by the second feedback node is provided to the adder of the data path receiving the previous 2-bit input data; The output signal output by the first feedback node and the output signal output by the second feedback node are in phase with each other; the first input end is connected to the adder of the data path receiving the previous 3-bit input data; and the first output end is connected to the adder of the data path receiving the previous 2-bit input data.

4. The data receiving circuit according to claim 3, wherein: The limiter has a first output node and a second output node, and the signals of the first output node and the second output node are in phase; wherein the first output node serves as the first feedback node, and the second output node is connected to the first input terminal.

5. The data receiving circuit according to claim 4, wherein: The limiter comprises: a sampling circuit configured to receive the corresponding sampling clock to sample the first signal to output a second signal; The first output circuit is configured to delay the second signal by a first delay amount and invert the second signal so as to The first output node outputs the output signal; a second output circuit configured to delay the second signal by a second delay amount and invert the second signal to output another output signal via a second output node; The first delay amount is smaller than the second delay amount.

6. The data receiving circuit according to claim 3, wherein: The first input terminal is further connected to the adder of the data path receiving the previous 4-bit input data.

7. The data receiving circuit according to claim 2, wherein: The plurality of feedback nodes include a first feedback node and a second feedback node; the output signal output by the first feedback node is provided to the adder of the data path receiving the previous 1-bit input data; the output signal output by the second feedback node is provided to the adder of the data path receiving the previous 2-bit input data; The output signal output by the first feedback node and the output signal output by the second feedback node are in anti-phase relationship with each other; the first input end is connected to the adder of the data path receiving the previous 2-bit input data; and the first output end is connected to the adder of the data path receiving the previous 3-bit input data.

8. The data receiving circuit according to claim 7, wherein: The limiter has a first output node and a second output node, and the signals of the first output node and the second output node are inverted; wherein the first output node serves as the first feedback node, and the second output node serves as the second feedback node and is connected to the first input terminal.

9. The data receiving circuit according to claim 8, wherein: The limiter comprises: a sampling circuit configured to receive the corresponding sampling clock to sample the first signal to output a second signal; a first output circuit configured to delay the second signal by a first delay amount and invert the second signal to output the output signal via the first output node; a second output circuit configured to delay the second signal by a second delay amount to output another output signal via the second output node; The first delay amount is smaller than the second delay amount.

10. The data receiving circuit according to claim 1, wherein: The slicer is further configured so that the feedback nodes providing the output signals to the adders of the data paths receiving previous 4-bit input data are different from each other.

11. The data receiving circuit according to claim 10, wherein: The i-th data path further includes: The zeroth inverter has a second input terminal and a second output terminal, wherein the second input terminal is connected to the feedback node; The second input end is connected to the adder of the data path that receives the previous 3-bit input data, and the second output end is connected to the adder of the data path that receives the previous 4-bit input data.

12. The data receiving circuit according to claim 1, wherein: The data receiving circuit also includes an amplifier, which is used to receive the input data and output the first signal; wherein the amplifier includes a first comparison node and a second comparison node for providing the first signal; the adder is further configured to determine whether the feedback signal is provided to one of the first comparison node or the second comparison node based on the phase of each received feedback signal.

13. The data receiving circuit according to claim 1, wherein: The M is 4.

14. A semiconductor device, characterized in that: include: The data receiving circuit according to any one of claims 1 to 13.

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