A method for manufacturing a power VDMOS with reduced EMI

Abstract

The application discloses a power VDMOS manufacturing method for reducing EMI, and belongs to the field of semiconductor devices. A silicon wafer material is provided, a first conductive type well region, a fourth dielectric oxide layer field oxide, a second conductive type source end heavily doped region and a first conductive type heavily doped body contact region are formed on the silicon wafer; a first dielectric oxide layer gate oxide is formed through furnace tube thermal oxidation; polycrystal is deposited twice through LPCVD respectively, high-temperature annealing is performed to activate impurities, and a gate polycrystal silicon electrode is formed; the thickness of the polycrystal deposited the second time is greater than that of the first time; SiO2 is deposited to form a second dielectric oxide layer; SiN is deposited through plasma enhanced chemical vapor deposition to form a third dielectric high-K material; and finally, an ohmic contact hole, a source and a drain are sequentially formed. The application realizes EMI noise optimization by designing a new device structure and a new process, optimizing device parameters C gs , Rg, reducing di / dt and dv / dt of the power VDMOS.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to a method for manufacturing a power VDMOS with reduced EMI. Background Technology

[0002] The increasing power capacity and power density of modern electronic devices have led to increasingly complex internal electromagnetic environments, resulting in more and more severe electromagnetic interference (EMI) affecting the power grid and its surrounding electromagnetic environment. Power VDMOS transistors, as power switching transistors in switching power supplies, operate in a rapid on-off cycle, with drastic changes in voltage and current. This makes them a major source of electric and magnetic field coupling interference, and one of the main sources of EMI in switching power supplies.

[0003] The di / dt and dv / dt generated by power VDMOS devices during switching processes produce EMI transient noise through parasitic capacitance and inductance in the circuit. In the VDMOS gate drive circuit, this noise is generated by the internal parasitic gate resistance R. g Gate lead inductance L g and gate-source parasitic capacitance C gs An RLC series resonant circuit is formed between them. For a series resonant circuit, its quality factor Q = ωL g / R g =(ωR) g C gs ) -1 The smaller the Q value, the worse its frequency selectivity, the smaller the oscillation amplitude, and the smoother the subsequent oscillation. Therefore, the smaller the parasitic gate inductance, the larger the gate resistance, and the larger the gate-source capacitance in the RLC resonant circuit, the smoother the oscillation of the gate drive signal (gate voltage). Wherein, L... g Related to the parasitic inductance of the gate bonding lead itself, R g It is related to the doping concentration of the polysilicon gate and the gate routing. C gs It is mainly determined by the capacitance between the polysilicon gate and the N+ source, the P-type base region, and the source metal. Summary of the Invention

[0004] The purpose of this invention is to provide a method for manufacturing a power VDMOS that reduces EMI, thereby solving the EMI problem generated by power VDMOS during switching.

[0005] To address the aforementioned technical problems, this invention provides a method for manufacturing a power VDMOS with reduced EMI, comprising:

[0006] Step 1: Provide silicon wafer material, with the silicon wafer material numbered n from bottom to top. + silicon substrate, n-buffer layer and n -Epitaxial layer;

[0007] Step 2: Form a first conductivity type well region on the silicon wafer;

[0008] Step 3: Deposit SiO2, coat with photoresist and expose the pattern window, wet etch SiO2 to remove the photoresist and form the fourth dielectric oxide layer, field oxygen.

[0009] Step 4: Form a heavily doped source region of the second conductivity type on the well region of the first conductivity type;

[0010] Step 5: Form a heavily doped contact region of the first conductivity type on the well region of the first conductivity type;

[0011] Step Six: Thermal oxidation of the furnace tubes to form the first dielectric oxide layer, gate oxide;

[0012] Step 7: Perform two LPCVD depositions of polysilicon, followed by high-temperature annealing to activate impurities, coating with photoresist and exposing the patterned window, polysilicon etching, removal of photoresist, and formation of the gate polysilicon electrode; wherein the polysilicon thickness of the second deposition is greater than that of the first.

[0013] Step 8: Plasma-enhanced chemical vapor deposition (PECVD) deposits SiO2 to form the second dielectric oxide layer; Plasma-enhanced chemical vapor deposition (PECVD) deposits SiN to form the third dielectric high-K material.

[0014] Step 9: Coat photoresist and expose the patterned window, dry etch SiN and SiO2, remove the photoresist, and form ohmic contact holes; deposit metal, coat photoresist and expose the patterned window, perform metal etching, remove the photoresist, and form the source electrode;

[0015] Step 10: Thin the silicon wafer and sputter TiNiAg metal on the back to form the drain.

[0016] In one implementation, the n + The resistivity of the silicon substrate is 0.002–0.004 Ω·cm; the resistivity of the n-buffer layer is 0.5 Ω·cm, and the thickness is 10 μm; the n-buffer layer... - The resistivity of the epitaxial layer is 9 Ω·cm and the thickness is 45 μm.

[0017] In one embodiment, step two includes: coating a photoresist and exposing a patterned window, implanting boron ions at an implantation energy of 100 keV and an implantation dose of 5 × 10⁻⁶. 13 cm -2 Remove the photoresist; perform push-junction at 1150°C for 200 minutes to form a first conductivity type well region.

[0018] In one embodiment, step four includes: coating a photoresist and exposing a patterned window, implanting phosphorus ions at an implantation energy of 100 keV and an implantation dose of 5 × 10⁻⁶. 15 cm -2 The photoresist is removed, and the mixture is pushed together at 900°C for 30 minutes to form a heavily doped source region of the second conductivity type.

[0019] In one embodiment, step five includes: coating a photoresist and exposing a patterned window, implanting boron ions at an implantation energy of 45 keV and an implantation dose of 5 × 10⁻⁶. 15 cm -2 The photoresist is removed, and the mixture is pushed together at 900°C for 30 minutes to form a heavily doped contact region of the first conductivity type.

[0020] In one embodiment, in step seven, a polycrystalline material with a thickness of 150 nm is first deposited by LPCVD, and phosphorus ions are implanted at an implantation energy of 45 keV and an implantation dose of 5 × 10⁻⁶. 15 cm -2 The second LPCVD deposition of polycrystalline material, with a thickness of 650 nm, was followed by phosphorus ion implantation at an energy of 45 keV and a dose of 5 × 10⁻⁶. 15 cm -2 .

[0021] This invention provides a method for manufacturing power VDMOS with reduced EMI by designing a new device structure and a new process, and optimizing the device parameter C. gs Rg reduces the di / dt and dv / dt of the power VDMOS, thereby optimizing EMI noise. Attached Figure Description

[0022] Figure 1 This is a cross-sectional view of a cell in a specific implementation method;

[0023] Figure 2 These are top views and cross-sectional views of the polycrystalline gate interconnects in the field region in a specific implementation embodiment;

[0024] Figure 3 This is a schematic diagram of secondary polycrystalline deposition doping in a specific implementation method.

[0025] 11 is the first conductivity type well region of the cell region, 12 is the first conductivity type heavily doped contact region; 21 is the second conductivity type substrate, 22 is the second conductivity type buffer layer, 23 is the second conductivity type drift region, 24 is the second conductivity type source end heavily doped region; 31 is the first dielectric oxide layer gate oxide, 32 is the second dielectric oxide layer, 33 is the third dielectric high-K material, 34 is the fourth dielectric oxide layer field oxide; 41 is the gate polycrystalline silicon electrode, which is divided into two layers, 41-1 is the first polycrystalline layer, 41-2 is the second polycrystalline layer; 51 is the source metal, 52 is the drain metal. Detailed Implementation

[0026] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a method for manufacturing a power VDMOS with reduced EMI according to the present invention. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0027] In constituting C gs In the VDMOS, the capacitance between the polysilicon gate and the N+ source and P-type base regions is mainly determined by the gate oxide thickness and impurity concentration. Since the gate oxide thickness and impurity concentration affect the normal characteristics of VDMOS, adjusting the gate oxide thickness and impurity concentration will destroy the original characteristics of the device. The capacitance between the polysilicon gate and the source metal is mainly determined by the dielectric material and dielectric thickness. The dielectric between the polysilicon gate and the source metal has no effect on the normal characteristics of VDMOS and can be used to adjust the gate-source capacitance.

[0028] Similarly, adjusting Rg should not worsen other device parameters. This requires keeping the polycrystalline gate work function and polycrystalline-metal contact resistance constant while adjusting Rg.

[0029] The low-EMI power VDMOS manufacturing method provided by this invention optimizes device parameters C by designing a new device structure and a new process flow. gs Rg reduces the di / dt and dv / dt of the power VDMOS, thereby optimizing EMI noise.

[0030] This invention is used to control C gs The methods for using Rg include:

[0031] 1) Increase the dielectric constant of the dielectric layer between the polysilicon gate and the source metal by using a composite dielectric layer and replacing silicon oxide with silicon nitride, which has a higher dielectric constant;

[0032] 2) The polycrystalline silicon gate is deposited and doped in two stages, so that the upper and lower surfaces of the polycrystalline layer are highly doped and the middle layer is low doped.

[0033] 3) A slot is cut on the polycrystalline gate bus in the field region, and the polycrystalline sidewall and the source metal sidewall form a MOM capacitor.

[0034] This invention provides a method for manufacturing power VDMOS with reduced EMI, see below. Figures 1-3 ,in Figure 1 This is a cross-sectional view of a cell. Figure 2 These are top and cross-sectional views of the polycrystalline gate interconnects in the field area. Figure 3 This is a schematic diagram of secondary polycrystalline deposition doping. The fabrication method includes the following steps:

[0035] Step 1: Provide silicon wafer material, with the silicon wafer material numbered n from bottom to top. + Silicon substrate 21, n-buffer layer 22, and n-epitaxial layer 23; wherein n + The resistivity of the silicon substrate 21 is 0.002–0.004 Ω·cm; the resistivity of the buffer layer 22 is 0.5 Ω·cm, and its thickness is 10 μm; - The resistivity of epitaxial layer 23 is 9 Ω·cm, and the thickness is 45 μm;

[0036] Step 2: Coat the silicon wafer with photoresist and expose the patterned window. Implant boron ions at an energy of 100 keV and an implantation dose of 5 × 10⁻⁶. 13 cm -2 Remove the photoresist. Perform push-bonding at 1150°C for 200 minutes to form a first conductivity type well region 11;

[0037] Step 3: LPCVD deposition of SiO2 with a thickness of 800nm. Photoresist is coated and the patterned window is exposed. SiO2 is then wet-etched to remove the photoresist, forming the fourth dielectric oxide layer, field oxygen 34.

[0038] Step 4: Coat with photoresist and expose the pattern window, then implant phosphorus ions at an energy of 100 keV and a dose of 5 × 10⁻⁶. 15 cm -2 Remove the photoresist and perform push-bonding at 900℃ for 30 minutes to form a second conductivity type source end heavily doped region 24;

[0039] Step 5: Coat with photoresist and expose the pattern window, then implant boron ions at an energy of 45 keV and a dose of 5 × 10⁻⁶. 15 cm -2 Remove the photoresist and perform push bonding at 900℃ for 30 minutes to form a first conductivity type heavily doped contact region 12;

[0040] Step 6: Thermal oxidation of the furnace tube, with an oxide layer thickness of 100nm, to form the first dielectric oxide layer gate oxide 31;

[0041] Step 7: First LPCVD deposition of polycrystalline material, 150 nm thick, followed by phosphorus ion implantation at an energy of 45 keV and a dose of 5 × 10⁻⁶. 15 cm -2 The second LPCVD deposition of polycrystalline material, with a thickness of 650 nm, was followed by phosphorus ion implantation at an energy of 45 keV and a dose of 5 × 10⁻⁶. 15 cm -2 Impurities were activated by annealing at 850℃ for 30 minutes. Photoresist was coated and the patterned window was exposed. Polycrystalline etching was performed to remove the photoresist, forming the gate polycrystalline silicon electrode 41. A schematic diagram of secondary polycrystalline deposition and implantation doping is shown below. Figure 3 As shown;

[0042] In step 7, increasing the polycrystalline thickness increases the sidewall capacitance and decreases the polycrystalline gate resistance, and the decrease in resistance leads to an increase in the quality factor. Similarly, increasing the doping concentration decreases the polycrystalline gate resistance, also leading to an increase in the quality factor. Therefore, it is necessary to design the polycrystalline thickness and doping to reduce the quality factor without affecting the polycrystalline work function and the ohmic contact between the polycrystalline and metal. This invention uses a two-step polycrystalline deposition and implantation process. The first step involves a relatively small polycrystalline thickness, ranging from 100 nm to 200 nm, with an implantation dose of 3 × 10⁻⁶. 15 cm -2 ~1×10 16 cm -2 The high impurity concentration at the polycrystalline-gate oxide interface after doping ensures the work function of the gate polycrystalline structure. The second-step polycrystalline thickness is relatively large, ranging from 500 nm to 1000 nm, with an implantation dose of 3 × 10⁻⁶. 15 cm -2 ~1×10 16 cm -2 After implantation and doping, the surface concentration of the polycrystalline material is relatively high, which ensures the ohmic contact between the polycrystalline material and the metal. The middle part of the two-layer polycrystalline material has relatively low doping and is used to adjust the gate resistance Rg.

[0043] Step 8: PECVD deposition of SiO2 with a thickness of 100 nm forms the second dielectric oxide layer 32; PECVD deposition of SiN with a thickness of 100 nm forms the third dielectric high-K material 33. A schematic diagram of the dielectric isolation between the polycrystalline gate and source metal on the gate interconnect is shown below. Figure 2 As shown;

[0044] In step 8, conventional processes use USG (undoped silicon glass) and BPSG (boron-phosphorus-doped silicon glass) for isolation between polycrystalline and metal materials. BPSG has a low breakdown field strength but exhibits some reflow characteristics, while silicon nitride has higher dielectric constant and breakdown field strength than BPSG. This invention uses a single-layer metal, therefore the isolation dielectric is USG+SiN.

[0045] The slot size on the field region polycrystalline gate interconnect GateBus, the width of the slot is determined by the polycrystalline thickness, the second dielectric oxide layer 32, and the third dielectric high-K material 33, so as to better form the MOM capacitor between the polycrystalline sidewall and the source metal sidewall.

[0046] Step 9: Coat photoresist and expose the patterned window, dry etch SiN and SiO2, remove the photoresist, and form an ohmic contact hole; deposit a metal thickness of 5μm, coat photoresist and expose the patterned window, perform metal etching, remove the photoresist, and form the source electrode 51;

[0047] Step 10: The silicon wafer thickness is reduced to 250μm, and TiNiAg metal is sputtered on the back side with a thickness of 2μm to form the drain electrode 52.

[0048] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A method for manufacturing a power VDMOS with reduced EMI, characterized in that, include: Step 1: Provide silicon wafer material, with the silicon wafer material numbered n from bottom to top. + Silicon substrate (21), n-buffer layer (22) and n - Epitaxial layer (23); Step 2: Form a first conductivity type well region (11) on the silicon wafer; Step 3: Deposit SiO2, coat photoresist and expose patterned windows, wet etch SiO2 to remove photoresist and form the fourth dielectric oxide layer field oxygen (34); Step 4: Form a second conductivity type source end heavily doped region (24) on the first conductivity type well region (11); Step 5: Form a first conductivity type heavily doped contact region (12) on the first conductivity type well region (11); Step 6: Thermal oxidation of the furnace tubes to form the first dielectric oxide layer (31); Step 7: Perform two LPCVD depositions of polysilicon, perform high-temperature annealing to activate impurities, coat with photoresist and expose the pattern window, etch the polysilicon, remove the photoresist, and form the gate polysilicon electrode (41); wherein the thickness of the polysilicon deposited in the second deposition is greater than that in the first deposition. Step 8: Plasma-enhanced chemical vapor deposition (PECVD) deposits SiO2 to form a second dielectric oxide layer (32); Plasma-enhanced chemical vapor deposition (PECVD) deposits SiN to form a third dielectric high-K material (33); Step 9: Coat photoresist and expose the pattern window, dry etch SiN and SiO2, remove photoresist, and form ohmic contact holes; deposit metal, coat photoresist and expose the pattern window, perform metal etching, remove photoresist, and form the source electrode (51). Step 10: Thin the silicon wafer and sputter TiNiAg metal on the back to form the drain (52).

2. The method for manufacturing a power VDMOS with reduced EMI as described in claim 1, characterized in that, The n + The resistivity of the silicon substrate (21) is 0.002–0.004 Ω·cm; the resistivity of the n-buffer layer (22) is 0.5 Ω·cm, and the thickness is 10 μm; the n-buffer layer (22) has a thickness of 10 μm. - The resistivity of the epitaxial layer (23) is 9 Ω·cm and the thickness is 45 μm.

3. The method for manufacturing a power VDMOS with reduced EMI as described in claim 1, characterized in that, Step two includes: coating a photoresist and exposing a patterned window, implanting boron ions at an energy of 100 keV and an implantation dose of 5 × 10⁻⁶ keV. 13 cm -2 Remove the photoresist; perform push junction at 1150°C for 200 minutes to form a first conductivity type well region (11).

4. The method for manufacturing a power VDMOS with reduced EMI as described in claim 1, characterized in that, Step four includes: coating a photoresist and exposing a patterned window, implanting phosphorus ions at an implantation energy of 100 keV and an implantation dose of 5 × 10⁻⁶ keV. 15 cm -2 Remove the photoresist and push the junction at 900°C for 30 minutes to form a second conductivity type source end heavily doped region (24).

5. The method for manufacturing a power VDMOS with reduced EMI as described in claim 1, characterized in that, Step five includes: coating a photoresist and exposing a patterned window, implanting boron ions at an implantation energy of 45 keV and an implantation dose of 5 × 10⁻⁶. 15 cm -2 Remove the photoresist and perform push bonding at 900℃ for 30 minutes to form a first conductivity type heavily doped contact region (12).

6. The method for manufacturing a power VDMOS with reduced EMI as described in claim 1, characterized in that, In step seven, a polycrystalline material with a thickness of 150 nm is first deposited by LPCVD, followed by phosphorus ion implantation at an energy of 45 keV and an implantation dose of 5 × 10⁻⁶. 15 cm -2 ; The second LPCVD deposition of polycrystalline material, with a thickness of 650 nm, was followed by phosphorus ion implantation at an energy of 45 keV and an implantation dose of 5 × 10⁻⁶. 15 cm -2 .

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