Layout structure of integrated circuit and memory

Abstract

The disclosed embodiments relate to the field of semiconductors and provide an integrated circuit layout structure and memory. The integrated circuit includes a symmetrical transistor and an asymmetrical transistor connected in series with the symmetrical transistor. The integrated circuit layout structure comprises: a substrate; the symmetrical transistor includes a first gate located on the substrate, and first and second source / drain regions located within the substrate and on opposite sides of the first gate, the first source / drain region being composed of a first doped region and the second source / drain region being composed of a second doped region; the asymmetrical transistor includes a second gate located on the substrate, a second doped region, a third doped region located within the substrate and on a side of the second gate away from the second doped region, and a lightly doped source / drain region; and a fourth doped region located within the substrate and connected to a first power supply along with the third doped region. This can reduce leakage current in a semiconductor structure corresponding to the integrated circuit layout structure.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and more particularly to a layout structure of an integrated circuit and a memory. Background Art

[0002] An integrated circuit is a miniature electronic device or component. Using a specific process, the transistors, resistors, capacitors, inductors, and other components required for a circuit, along with their interconnected wiring, are fabricated on one or several small semiconductor wafers or dielectric substrates. These components are then packaged within a housing, resulting in a miniature structure that performs the required circuit functions. The structural integration of all components has made this a significant step forward in the development of miniaturization, low power consumption, intelligence, and high reliability of electronic components.

[0003] Connecting two transistors in series is a common integrated circuit. However, there is currently a problem of large leakage current in the integrated circuit after the transistors are connected in series. Summary of the Invention

[0004] The embodiments of the present disclosure provide a layout structure of an integrated circuit, which can at least improve the performance of a semiconductor structure corresponding to the integrated circuit layout structure.

[0005] According to some embodiments of the present disclosure, on one hand, an embodiment of the present disclosure provides a layout structure of an integrated circuit, wherein the integrated circuit includes a symmetrical transistor and an asymmetrical transistor connected in series with the symmetrical transistor, and the layout structure of the integrated circuit includes: a substrate; the symmetrical transistor includes a first gate located on the substrate and a first source-drain region and a second source-drain region located in the substrate and located on opposite sides of the first gate, the first source-drain region being composed of a first doped region, and the second source-drain region being composed of a second doped region; the asymmetrical transistor includes a second gate located on the substrate, the second doped region, and a third doped region and a lightly doped source-drain region located in the substrate and located on a side of the second gate away from the second doped region; a fourth doped region is located in the substrate, and both the fourth doped region and the third doped region are connected to a first power supply.

[0006] In some embodiments, the first doping region, the second doping region, the third doping region and the lightly doped source and drain region have a first conductivity type; and the substrate and the fourth doping region have a second conductivity type.

[0007] In some embodiments, the first doped region is connected to a first node output terminal; the first gate is connected to a first voltage input terminal; and the second gate is connected to a second voltage input terminal.

[0008] In some embodiments, the present invention further includes: a first conductive plug, the first conductive plug is in contact and electrically connected with the first doped region, and the top surface of the first conductive plug is higher than the top surface of the substrate; a second conductive plug, the second conductive plug is in contact and electrically connected with the second doped region, and the top surface of the second conductive plug is higher than the top surface of the substrate; and a third conductive plug, the third conductive plug is in contact and electrically connected with the third doped region, and the top surface of the third conductive plug is higher than the top surface of the substrate.

[0009] In some embodiments, it also includes: a first wiring layer, the first wiring layer is located on the top surface of the first conductive plug and is insulated from the first gate and the second gate, and the first node output end is located in the first wiring layer; a second wiring layer, the second wiring layer is located on the top surface of the second conductive plug and is insulated from the first gate and the second gate; a third wiring layer, the third wiring layer is located on the top surface of the third conductive plug and is insulated from the first gate and the second gate, the first power supply is located in the third wiring layer, and the first wiring layer, the second wiring layer and the third wiring layer are arranged on the same layer.

[0010] In some embodiments, the device further includes: a first conductive column, the first conductive column is in contact with the first gate and electrically connected to the first voltage input terminal; and a second conductive column, the second conductive column is in contact with the second gate and electrically connected to the second voltage input terminal.

[0011] In some embodiments, the lightly doped source and drain regions extend in a direction perpendicular to the symmetric transistor toward the asymmetric transistor and parallel to the surface of the substrate.

[0012] In some embodiments, an orthographic projection of the lightly doped source and drain region on the substrate surface partially overlaps with an orthographic projection of the second gate on the substrate surface.

[0013] In some embodiments, the symmetric transistor and the asymmetric transistor are of the same type, both being N-type transistors or P-type transistors.

[0014] According to some embodiments of the present disclosure, another aspect of the present disclosure further provides a memory, comprising the layout structure of the integrated circuit as described above.

[0015] The technical solution provided by the embodiments of the present disclosure has at least the following advantages: the layout structure of the integrated circuit includes symmetrical transistors and asymmetrical transistors, wherein the second source and drain regions of the symmetrical transistor are composed of a second doped region, and the asymmetrical transistor also includes a second doped region, that is, the symmetrical transistor and the asymmetrical transistor share a common source or a common drain, thereby reducing the layout area of ​​the layout structure of the integrated circuit; when a fourth doped region is present and the fourth doped region is connected to a first power supply, the fourth doped region can ensure the working state of the symmetrical transistor and the asymmetrical transistor, that is, the fourth doped region provides a bias voltage, and the common source and drain of the symmetrical transistor and the asymmetrical transistor can also reduce the leakage current passing through the fourth doped region, thereby improving the performance of the semiconductor structure corresponding to the integrated circuit layout structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0017] Figure 1 A schematic structural diagram of a semiconductor structure provided in one embodiment of the present disclosure;

[0018] Figure 2 A circuit diagram provided for an embodiment of the present disclosure;

[0019] Figure 3 A layout diagram of a layout structure of an integrated circuit provided in one embodiment of the present disclosure;

[0020] Figure 4 A schematic structural diagram of a semiconductor structure corresponding to a layout structure of an integrated circuit provided in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0021] As known from the background art, compared with symmetric transistors, asymmetric transistors have smaller leakage current. Therefore, theoretically, when two asymmetric transistors are connected in series, the leakage current of the two asymmetric transistors should be the smallest compared with the leakage current of two symmetric transistors connected in series.

[0022] refer to Figure 1In actual applications, when the fourth doped region 50 is present, the leakage current path is not only from the drain 11 of the first transistor 10 through the channel to the source 12 of the first transistor 10, then through the connection line between the two transistors to the drain 21 of the second transistor 20, then through the channel of the second transistor 20 to the source 22 of the second transistor 20, and finally flows to the power supply terminal 30, but the leakage current path also includes: from the lightly doped region 13 of the first transistor 10 through the substrate 40 and the fourth doped region 50 to the power supply terminal 30, resulting in a large leakage current in the structure formed by the two asymmetric transistors connected in series.

[0023] The present disclosure provides a layout structure of an integrated circuit. The layout structure of the integrated circuit includes a symmetric transistor and an asymmetric transistor, wherein the second source and drain regions of the symmetric transistor are formed by a second doped region, and the asymmetric transistor also includes a second doped region. That is, the symmetric transistor and the asymmetric transistor share a common source or drain. By sharing the same source or drain, the layout area of ​​the integrated circuit layout structure can be reduced. Moreover, by providing the integrated circuit layout structure with the symmetric transistor and the asymmetric transistor, one lightly doped source and drain region is reduced compared to two asymmetric transistors. Furthermore, by sharing the same source or drain, the symmetric transistor and the asymmetric transistor share a reduced leakage path from the lightly doped source and drain region of the asymmetric transistor through the substrate and the fourth doped region to the first power supply, thereby improving the performance of the semiconductor structure corresponding to the integrated circuit layout structure.

[0024] The following describes various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to facilitate a better understanding of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can still be implemented.

[0025] refer to Figures 2 to 4 , Figure 2 A circuit diagram corresponding to a layout structure of an integrated circuit provided in one embodiment of the present disclosure, Figure 3 A layout diagram corresponding to a layout structure of an integrated circuit provided in one embodiment of the present disclosure, Figure 4 A structural schematic diagram corresponding to the layout structure of an integrated circuit provided by an embodiment of the present disclosure.

[0026] refer to Figure 2The circuit diagram of the integrated circuit includes two transistors, and the two transistors are connected in series. Taking the two transistors as NMOS (N-Metal-Oxide-Semiconductor) tubes as an example, when the gates of the two transistors receive a high level, the transmission path between the source of one transistor and the drain of the other transistor is turned on.

[0027] refer to Figure 3 In some embodiments, the layout structure of the integrated circuit includes: a substrate 100 .

[0028] In some embodiments, the layout structure of the integrated circuit may further include: the symmetrical transistor 110 includes a first gate 111 located on the substrate 100 and a first source-drain region 112 and a second source-drain region 113 located within the substrate 100 and on opposite sides of the first gate 111, wherein the first source-drain region 112 is composed of a first doped region 114, and the second source-drain region 113 is composed of a second doped region 115.

[0029] In some embodiments, the layout structure of the integrated circuit may further include: the asymmetric transistor 120 includes a second gate 121 located on the substrate 100, a second doped region 115, and a third doped region 122 and a lightly doped source and drain region 123 located in the substrate 100 and on the side of the second gate 121 away from the second doped region 115.

[0030] In some embodiments, the layout structure of the integrated circuit may further include: a fourth doping region 130 located in the substrate 100 and connected to the first power source together with the third doping region 122 .

[0031] By providing an integrated circuit layout structure including a symmetric transistor 110 and an asymmetric transistor 120, wherein the second source and drain regions 113 of the symmetric transistor 110 are formed by the second doped region 115, and the asymmetric transistor 120 also includes the second doped region 115, that is, the symmetric transistor 110 and the asymmetric transistor 120 share a common source or drain. By having the symmetric transistor 110 and the asymmetric transistor 120 share a common source or drain, the layout area of ​​the integrated circuit layout structure can be reduced. Moreover, by providing the integrated circuit layout structure including the symmetric transistor 110 and the asymmetric transistor 120, one lightly doped source and drain region is eliminated compared to two asymmetric transistors. Furthermore, by having the symmetric transistor 110 and the asymmetric transistor 120 share a common source or drain, the leakage path from the lightly doped source and drain region 123 of the asymmetric transistor 120 through the substrate 100 and the fourth doped region 130 to the first power supply is reduced, thereby improving the performance of the semiconductor structure corresponding to the integrated circuit layout structure.

[0032] In some embodiments, the material of substrate 100 may include a semiconductor material, such as, but not limited to, silicon. In some embodiments, substrate 100 may include a base semiconductor, a compound semiconductor, or an alloy semiconductor. For example, base semiconductors include germanium; compound semiconductors include silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or Group III-V semiconductor materials; and alloy semiconductors include silicon germanium, silicon germanium carbide, germanium-tin, silicon-germanium-tin, gallium arsenic phosphide, gallium indium phosphide, gallium indium arsenide, indium gallium arsenide, aluminum indium arsenide, and / or aluminum gallium arsenide. In some embodiments, substrate 100 may also be a silicon-on-insulator (SOI) structure, a silicon-germanium-on-insulator (SGI) structure, a germanium-on-insulator (GOI) structure, or a combination thereof.

[0033] In addition, the substrate 100 can be doped according to design requirements (e.g., a P-type substrate or an N-type substrate). In some embodiments, the substrate 100 can be doped with P-type dopant ions (e.g., boron ions, aluminum ions) or N-type dopant ions (e.g., phosphorus ions, arsenic ions).

[0034] In some embodiments, the symmetrical transistor 110 may be a MOS (Metal Oxide Semiconductor) transistor, wherein the first gate 111 is used to control the conduction of a path between the first source-drain region 112 and the second source-drain region 113 of the symmetrical transistor 110. Taking the symmetrical transistor 110 as an NMOS transistor as an example, a positive voltage is applied to the first gate 111 of the symmetrical transistor 110. When the voltage received by the first gate 111 is higher than a certain value, carriers in the substrate 100 are attracted to the surface of the substrate 100 under the first gate 111, forming an inversion layer. The first source-drain region 112 and the second source-drain region 113 are then conducted through the inversion layer.

[0035] In some embodiments, the asymmetric transistor 120 can be a MOS (Metal Oxide Semiconductor) tube, wherein the second gate 121 is used to control the path conduction between the second doping region 115 and the third doping region 122 of the asymmetric transistor 120. Taking the asymmetric transistor 120 as an NMOS tube as an example, a positive voltage is applied to the second gate 121 of the asymmetric transistor 120. When the voltage received on the second gate 121 is higher than a certain value, the carriers in the substrate 100 are attracted to the surface of the substrate 100 under the second gate 121, forming an inversion layer, and the second doping region 115 and the third doping region 122 are conductive through the inversion layer.

[0036] It should be noted that the symmetric transistor 110 has symmetric source and drain. That is, the process for forming the first source-drain region 112 and the process for forming the second source-drain region 113 are the same, and the corresponding structures are the same. Even if the first source-drain region 112 and the second source-drain region 113 of the symmetric transistor are swapped, it will not affect the performance of the symmetric transistor 110. The asymmetric transistor 120 has asymmetric source and drain. For example, the asymmetric transistor 120 includes a third source-drain region and a fourth source-drain region, wherein the third source-drain region may include the second doped region 115, and the fourth source-drain region may include the third doped region 122 and the lightly doped source-drain region 123. That is, the process for forming the third source-drain region and the process for forming the fourth source-drain region of the asymmetric transistor are different, and the morphologies of the formed third source-drain region and the fourth source-drain region are also different. Swapping the third source-drain region and the fourth source-drain region of the asymmetric transistor 120 will change the performance of the asymmetric transistor 120.

[0037] In some embodiments, the lightly doped source and drain regions 123 are located on a side of the third doped region 122 close to the second gate 121 . The lightly doped source and drain regions 123 can reduce the peak electric field intensity near the second gate 121 and weaken the hot carrier effect.

[0038] It should be noted that hot carriers are carriers with high energy. The hot carrier effect is caused by the injection of high-energy carriers into the gate dielectric layer. During the injection process, interface states will be generated and the gate dielectric layer will be damaged. As the degree of damage to the gate dielectric layer increases, the current and voltage characteristics of the transistor will change. When the characteristics of the device change beyond a certain limit, the transistor will fail, and this process is called the hot carrier effect.

[0039] In some embodiments, the lightly doped source and drain regions 123 extend in a direction perpendicular to the symmetrical transistor 110 and toward the asymmetrical transistor 120 and parallel to the surface of the substrate 100. Figure 3 , the extension direction of the lightly doped source and drain region 123 is the same as the extension direction of the second gate 121, that is, Figure 3 In the illustrated layout plane, the direction extends perpendicular to the symmetrical transistor 110 and toward the asymmetrical transistor 120 .

[0040] By arranging the lightly doped source and drain regions 123 to extend in a direction perpendicular to the symmetric transistor 110 toward the asymmetric transistor 120 and parallel to the surface of the substrate 100 , the lightly doped source and drain regions 123 can withstand more voltage, thereby further reducing the hot carrier effect.

[0041] In some embodiments, in a direction perpendicular to the symmetric transistor 110 toward the asymmetric transistor 120 and parallel to the surface of the substrate 100, the length of the lightly doped source and drain region 123 is equal to the length of the substrate 100 in that direction. In other words, in the layout structure of the integrated circuit, in a direction perpendicular to the symmetric transistor 110 toward the asymmetric transistor 120 and parallel to the surface of the substrate 100, the lightly doped source and drain region 123 penetrates the substrate 100.

[0042] In some embodiments, in a direction perpendicular to the symmetric transistor 110 and toward the asymmetric transistor 120 and parallel to the surface of the substrate 100, the length of the lightly doped source and drain region 123 may be greater than or equal to the length of the second gate 121. It will be appreciated that when the asymmetric transistor 120 is operating, a channel is typically formed below the second gate 121. By providing a length of the lightly doped source and drain region 123 that is greater than or equal to the length of the second gate 121, damage to the gate dielectric layer below the second gate 121 can be reduced.

[0043] In some embodiments, the orthographic projection of the lightly doped source / drain region 123 on the surface of the substrate 100 partially overlaps with the orthographic projection of the second gate 121 on the surface of the substrate 100. In other words, a portion of the lightly doped source / drain region 123 is located directly below the second gate 121. By arranging for the orthographic projection of the lightly doped source / drain region 123 on the surface of the substrate 100 to partially overlap with the orthographic projection of the second gate 121 on the surface of the substrate 100, the hot carrier effect is further reduced, thereby improving the reliability of the semiconductor structure corresponding to the layout structure of the integrated circuit.

[0044] It should be noted that the “directly below” here refers to the portion of the second gate 121 that can overlap with the substrate 100 after being extended in the direction along the second gate 121 pointing to the substrate 100 . The position corresponding to this overlapping portion is directly below the second gate 121 .

[0045] In some embodiments, the symmetric transistor 110 and the asymmetric transistor 120 are of the same type, either N-type transistors or P-type transistors. By setting the symmetric transistor 110 and the asymmetric transistor 120 to be of the same type, no additional processing is required on the substrate 100. In other words, there is no need to consider the source and drain doping issues between the symmetric transistor 110 and the asymmetric transistor 120, thereby reducing the difficulty of subsequently forming a semiconductor structure corresponding to the layout structure of the integrated circuit.

[0046] In some embodiments, the symmetric transistor 110 and the asymmetric transistor 120 are both NMOS transistors, the substrate 100 may be doped with P-type dopant ions, the first doping region 114 and the second doping region 115 may be doped with N-type dopant ions, and the doping concentrations of the doping ions in the first doping region 114 and the second doping region 115 may be the same, and the third doping region 122 and the lightly doped source and drain region 123 may be doped with N-type dopant ions.

[0047] In some embodiments, the symmetrical transistor 110 and the asymmetrical transistor are both PMOS transistors, the substrate 100 can be doped with N-type dopant ions, the first doping region 114 and the second doping region 115 can be doped with P-type dopant ions, and the doping concentrations of the doping ions in the first doping region 114 and the second doping region 115 can be the same, and the third doping region 122 and the lightly doped source and drain region 123 can be doped with P-type dopant ions.

[0048] It is understandable that when the circuit is operating, the potential in the substrate 100 of each asymmetric transistor 120 is constantly changing. If the potential in the substrate 100 is not controlled, then the potential difference between the substrate 100 and the source of the asymmetric transistor 120 may not be zero, that is, the bias effect of the substrate 100 occurs. The bias effect of the substrate 100 will further widen the depletion layer thickness of the field-induction junction of the asymmetric transistor 120 and increase the space charge density in the depletion layer, resulting in an increase in the threshold voltage of the device and an increase in the channel resistance of the asymmetric transistor 120.

[0049] In order to improve the bias effect of the substrate 100 , a fourth doped region 130 is usually set in the substrate 100 , and the fourth doped region 130 is connected to the first power supply to stabilize the potential of the substrate 100 through the first power supply, thereby improving the bias effect in the asymmetric transistor 120 .

[0050] In some embodiments, the first doped region 114, the second doped region 115, the third doped region 122, and the lightly doped source / drain region 123 have a first conductivity type; and the substrate 100 and the fourth doped region 130 have a second conductivity type. It should be noted that the first doped region 114, the second doped region 115, the third doped region 122, and the lightly doped source / drain region 123 having the first conductivity type may mean that the majority carriers in the first doped region 114, the second doped region 115, the third doped region 122, and the lightly doped source / drain region 123 are one of holes and electrons, and the substrate 100 and the fourth doped region 130 having the second conductivity type may mean that the majority carriers in the substrate 100 and the fourth doped region 130 are the other of holes and electrons.

[0051] In other words, in some embodiments, the first doping region 114, the second doping region 115, the third doping region 122 and the lightly doped source and drain region 123 may be doped with N-type doping ions, and the substrate 100 and the fourth doping region 130 may be doped with P-type doping ions; in some embodiments, the first doping region 114, the second doping region 115, the third doping region 122 and the lightly doped source and drain region 123 may be doped with P-type doping ions, and the substrate 100 and the fourth doping region 130 may be doped with N-type doping ions.

[0052] By setting the first doping region 114 and the second doping region 115 to have the first conductivity type and the substrate 100 to have the second conductivity type, a PN junction of the symmetrical transistor 110 is formed; by setting the second doping region 115, the third doping region 122 and the lightly doped source and drain region 123 to have the first conductivity type and the substrate 100 to have the second conductivity type, a PN junction of the asymmetric transistor 120 is formed, and by setting the fourth doping region 130 to have the second conductivity type, the bias effect of the asymmetric transistor 120 can be improved.

[0053] In some embodiments, the doping ion concentration in the fourth doping region 130 may be greater than the doping ion concentration in the substrate 100. By setting the doping ion concentration in the fourth doping region 130 to be greater than the doping ion concentration in the substrate 100, the discharge effect of the accumulated charges in the channel can be effectively improved.

[0054] In some embodiments, the first doped region 114 is connected to a first node output terminal node; the first gate 111 is connected to a first voltage input terminal IN1; and the second gate 121 is connected to a second voltage input terminal IN2. A voltage signal is provided to the first source-drain region 112 of the symmetrical transistor 110 via the first node output terminal node. The first voltage input terminal IN1 is used to provide a voltage to the first gate 111, thereby controlling the operation of the first gate 111 and, in turn, controlling the operation of the symmetrical transistor 110. A voltage is provided to the second gate 121 via the second voltage input terminal IN2, thereby controlling the operation of the second gate 121 and, in turn, controlling the operation of the asymmetrical transistor 120.

[0055] In some embodiments, the first doping region 114 is connected to the first node output terminal node; the first gate 111 is connected to the first voltage input terminal IN1; the second gate 121 is connected to the second voltage input terminal IN2, the third doping region 122 and the fourth doping region 130 are connected to the ground, and the substrate 100 can be doped with P-type doping ions, the fourth doping region 130 can be doped with P-type doping ions, and the doping concentration of the fourth doping region 130 is greater than the doping concentration in the substrate 100, and the first doping region 114, the second doping region 115, the third doping region 122 and the lightly doped source and drain region 123 can be doped with N-type doping ions.

[0056] In some embodiments, the layout structure of the integrated circuit may further include: a first conductive plug 140, the first conductive plug 140 is in contact and electrically connected to the first doped region 114, and the top surface of the first conductive plug 140 is higher than the top surface of the substrate 100; a second conductive plug 150, the second conductive plug 150 is in contact and electrically connected to the second doped region 115, and the top surface of the second conductive plug 150 is higher than the top surface of the substrate 100; and a third conductive plug 160, the third conductive plug 160 is in contact and electrically connected to the third doped region 122, and the top surface of the third conductive plug 160 is higher than the top surface of the substrate 100. The first doping region 114 can be led out through the first conductive plug 140, so that an electrical signal can be provided to the first doping region 114 through the first conductive plug 140; the electrical signal of the second doping region 115 can be led out through the second conductive plug 150, so that an electrical signal can be provided to the second doping region 115 through the second conductive plug 150; the electrical signal of the third doping region 122 can be led out through the third conductive plug 160, so that an electrical signal can be provided to the third doping region 122 through the third conductive plug 160.

[0057] In some embodiments, the first conductive plug 140 , the second conductive plug 150 , and the third conductive plug 160 may be made of the same material, such as polysilicon, copper, or tungsten. In some embodiments, the first conductive plug 140 , the second conductive plug 150 , and the third conductive plug 160 may be made of different materials.

[0058] It can be understood that the first conductive plug 140, the second conductive plug 150 and the third conductive plug 160 are made of the same material, and the first conductive plug 140, the second conductive plug 150 and the third conductive plug 160 can be formed in the same process step in the subsequent process of forming the first conductive plug 140, the second conductive plug 150 and the third conductive plug 160.

[0059] In some embodiments, the layout structure of the integrated circuit may further include: a first wiring layer 170, the first wiring layer 170 is located on the top surface of the first conductive plug 140 and is insulated from the first gate 111 and the second gate 121, and the first node output terminal node is located in the first wiring layer 170; a second wiring layer 180, the second wiring layer 180 is located on the top surface of the second conductive plug 150 and is insulated from the first gate 111 and the second gate 121; a third wiring layer 190, the third wiring layer 190 is located on the top surface of the third conductive plug 160 and is insulated from the first gate 111 and the second gate 121, and the first power supply is located in the third wiring layer 190, and the first wiring layer 170, the second wiring layer 180 and the third wiring layer 190 are arranged on the same layer. The first wiring layer 170, the second wiring layer 180 and the third wiring layer 190 are the parts of the layout structure of the integrated circuit used for wiring and connecting various power supply terminals. The first wiring layer 170 is set to provide electrical signals to the first doping region 114, the second wiring layer 180 is set to provide electrical signals to the second doping region 115, and the third wiring layer 190 is set to provide electrical signals to the third doping region 122.

[0060] In some embodiments, the first wiring layer 170 , the second wiring layer 180 , and the third wiring layer 190 are spaced apart from each other.

[0061] In some embodiments, the materials of the first wiring layer 170 , the second wiring layer 180 , and the third wiring layer 190 may be the same, and may all be metal materials, such as copper or tungsten.

[0062] In some embodiments, the layout structure of the integrated circuit may further include: a first conductive pillar 200, the first conductive pillar 200 being in contact with the first gate 111 and electrically connected to the first voltage input terminal IN1; and a second conductive pillar 210, the second conductive pillar 210 being in contact with the second gate 121 and electrically connected to the second voltage input terminal IN2. The first conductive pillar 200 is provided to connect the first voltage input terminal IN1 to the first gate 111, so that the first voltage input terminal IN1 provides a voltage signal to the first gate 111 through the first conductive pillar 200. The second conductive pillar 210 is provided to connect the second voltage input terminal IN2 to the second gate 121, so that the first voltage input terminal IN1 provides a voltage signal to the second gate 121 through the second conductive pillar 210.

[0063] In some embodiments, the first conductive pillar 200 and the second conductive pillar 210 may be made of the same material, such as polysilicon, copper, tungsten, or other conductive materials. In some embodiments, the first conductive pillar 200 and the second conductive pillar 210 may be made of different materials.

[0064] In some embodiments, the first conductive pillar 200 , the second conductive pillar 210 , the first conductive plug 140 , the second conductive plug 150 , and the third conductive plug 160 may be made of the same material.

[0065] In some embodiments, the first conductive pillar 200 , the second conductive pillar 210 , the first conductive plug 140 , the second conductive plug 150 , and the third conductive plug 160 may be formed using the same process.

[0066] In some embodiments, the substrate 100 may further include a gate dielectric layer, which is located at least between the first gate 111 and the substrate 100 and also at least between the second gate 121 and the substrate 100. The gate dielectric layer prevents carriers in the substrate 100 from flowing directly into the first gate 111 and the second gate 121.

[0067] It should be noted that in the present disclosure, a high level refers to, for example, a state greater than or equal to the power supply voltage, and a low level refers to a state less than or equal to the ground voltage. Here, the terms high and low levels are relative, and the specific voltage ranges included need to be determined based on the specific device. For example, for an N-type field-effect transistor, a high level refers to the gate voltage range that can turn it on, and a low level refers to the gate voltage range that can turn it off. For a P-type field-effect transistor, a low level refers to the gate voltage range that can turn it on, and a high level refers to the gate voltage range that can turn it off.

[0068] It is worth noting that all units involved in this embodiment are logical units. In actual applications, a logical unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. In addition, to highlight the innovation of this disclosure, this embodiment does not include units that are not closely related to solving the technical problems proposed by this disclosure. However, this does not mean that other units do not exist in this embodiment.

[0069] Another embodiment of the present disclosure further provides a memory, including the layout structure of all or part of the integrated circuit in the above embodiment. It should be noted that the same or corresponding parts as the above embodiment can refer to the corresponding description of the above embodiment and will not be repeated below.

[0070] It should be noted that the memory may be a storage unit or device based on a semiconductor device or component. For example, the memory may be a volatile memory, such as dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), low power double data rate synchronous dynamic random access memory (LPDDR SDRAM), graphic double data rate synchronous dynamic random access memory (GDDR SDRAM), double data rate type dual synchronous dynamic random access memory (DDR2 SDRAM), double data rate type triple synchronous dynamic random access memory (DDR3 SDRAM), double data rate fourth generation synchronous dynamic random access memory (DDR4 SDRAM), thyristor random access memory (TRAM), etc.; or it may be a non-volatile memory, such as phase change random access memory (PRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), etc.

[0071] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present disclosure, and in actual applications, various changes may be made to them in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure. Therefore, the scope of protection of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A layout structure of an integrated circuit, characterized in that: The integrated circuit includes a symmetrical transistor and an asymmetrical transistor connected in series with the symmetrical transistor, and the layout structure of the integrated circuit includes: substrate; The symmetrical transistor includes a first gate located on the substrate, and a first source-drain region and a second source-drain region located in the substrate and on opposite sides of the first gate, wherein the first source-drain region is formed by a first doped region, and the second source-drain region is formed by a second doped region; The asymmetric transistor includes a second gate located on the substrate, the second doped region, and a third doped region and a lightly doped source and drain region located in the substrate and on a side of the second gate away from the second doped region; The fourth doping region is located in the substrate and is connected to a first power source together with the third doping region.

2. The layout structure of the integrated circuit according to claim 1, wherein: The first doping region, the second doping region, the third doping region and the lightly doped source and drain region have a first conductivity type; the substrate and the fourth doping region have a second conductivity type.

3. The layout structure of the integrated circuit according to claim 1, wherein: The first doped region is connected to a first node output terminal; the first gate is connected to a first voltage input terminal; and the second gate is connected to a second voltage input terminal.

4. The layout structure of the integrated circuit according to claim 3, wherein: Also includes: a first conductive plug, wherein the first conductive plug is in electrical contact with the first doped region, and a top surface of the first conductive plug is higher than a top surface of the substrate; a second conductive plug, the second conductive plug being in electrical contact with the second doped region, and a top surface of the second conductive plug being higher than a top surface of the substrate; A third conductive plug is in contact and electrically connected with the third doped region, and a top surface of the third conductive plug is higher than a top surface of the substrate.

5. The layout structure of the integrated circuit according to claim 4, wherein: Also includes: a first wiring layer, the first wiring layer being located on a top surface of the first conductive plug and being insulated from the first gate and the second gate, the first node output end being located in the first wiring layer; a second wiring layer, the second wiring layer being located on a top surface of the second conductive plug and being insulated from the first gate and the second gate; A third wiring layer is located on a top surface of the third conductive plug and is insulated from the first gate and the second gate. The first power supply is located in the third wiring layer. The first wiring layer, the second wiring layer and the third wiring layer are arranged on the same layer.

6. The layout structure of the integrated circuit according to claim 3, wherein: Also includes: The first conductive column, A first conductive column is in contact with the first gate and electrically connected to the first voltage input terminal; A second conductive column is in contact with the second gate and electrically connected to the second voltage input terminal.

7. The layout structure of the integrated circuit according to claim 1, wherein: The lightly doped source and drain regions extend in a direction perpendicular to the symmetrical transistor toward the asymmetrical transistor and parallel to the surface of the substrate.

8. The layout structure of the integrated circuit according to claim 1, wherein: The orthographic projection of the lightly doped source and drain regions on the substrate surface partially overlaps with the orthographic projection of the second gate on the substrate surface.

9. The layout structure of the integrated circuit according to claim 1, wherein: The symmetrical transistor and the asymmetrical transistor are of the same type, both being N-type transistors or P-type transistors.

10. A memory, characterized in that: A layout structure comprising an integrated circuit as claimed in any one of claims 1 to 9.

Images