Display panel and display device

Abstract

The application provides a display panel and a display device. By providing at least one compensation hole in at least one pixel driving circuit in a second direction, the compensation hole is arranged on the side of the active pattern of the driving transistor close to the active pattern of the switching transistor, and the projection of the compensation hole and the active pattern of the switching transistor on the substrate does not overlap. The compensation hole is arranged above the active pattern of the driving transistor, the number of holes above the active pattern of the driving transistor is similar to the number of holes below the active pattern of the driving transistor, and thus, when the display panel has defects, the holes can also produce the effect of dehydrogenation, the influence of the defects on the dehydrogenation effect can be reduced, the influence of the defects on the electrical property of the driving transistor can be reduced, the electrical property of the driving transistor in each pixel is similar, and thus, display unevenness can be avoided and the display effect is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] With the development of display devices, the requirements of existing display devices for power consumption and screen ratio are higher and higher. In order to reduce power consumption and improve screen ratio, the existing display devices will adopt low temperature polysilicon oxide (LTPO) technology. The LTPO technology refers to the use of low temperature polysilicon thin film transistor and oxide thin film transistor at the same time, so that the driving circuit takes into account the advantages of low temperature polysilicon thin film transistor and oxide thin film transistor, thereby reducing power consumption and reducing leakage current. In the display device using the LTPO technology, a punching space needs to be reserved for the oxide thin film transistor. Therefore, when the first time is punched to the polysilicon layer, the first gate layer and the second gate layer, the number of holes above the channel of the driving transistor is less than the number of holes below the channel of the driving transistor, which will cause the uneven distribution of holes in the upper and lower areas of the driving transistor, and further cause the electrical property of the driving transistor to be greatly affected by defects, and the problem of bright and dark spots is prone to occur during display.

[0003] Therefore, the existing display device has the technical problem of display abnormality caused by the uneven hole density on the upper and lower sides of the driving transistor. SUMMARY

[0004] The embodiments of the present application provide a display panel and a display device to solve the technical problem of display abnormality caused by the uneven hole density on the upper and lower sides of the driving transistor in the existing display device.

[0005] The embodiments of the present application provide a display panel, which comprises:

[0006] a substrate;

[0007] a driving circuit layer arranged on one side of the substrate, the driving circuit layer comprising a first active layer, the driving circuit layer further comprising a pixel driving circuit, the pixel driving circuit comprising a switching transistor, a driving transistor, a compensation transistor and a first initialization transistor, the switching transistor and the driving transistor being connected to a first node; one electrode of the compensation transistor and one electrode of the first initialization transistor being connected to a second node with the driving transistor, and the other electrode of the compensation transistor being connected to a third node with the driving transistor;

[0008] The first active layer includes an active pattern of the driving transistor and an active pattern of the switching transistor, the active pattern of the driving transistor is arranged along a first direction, the active pattern of the switching transistor is arranged along a second direction, at least one compensation hole is arranged in the at least one pixel driving circuit in the second direction, the compensation hole is arranged on a side of the active pattern of the driving transistor close to the active pattern of the switching transistor, the compensation hole does not overlap with a projection of the active pattern of the switching transistor on the substrate, and an included angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees.

[0009] Meanwhile, the display device provided by the embodiment of the present application includes the display panel as described in any one of the above embodiments.

[0010] Beneficial effects: the display panel and the display device provided by the present application can increase the compensation hole above the active pattern of the driving transistor, so that the number of holes above the active pattern of the driving transistor is close to the number of holes below the active pattern of the driving transistor, thereby reducing the influence of defects on the dehydrogenation effect when the display panel has defects, reducing the influence of defects on the electrical properties of the driving transistor, making the electrical properties of the driving transistor in each pixel similar, thereby avoiding display unevenness and improving display effect. BRIEF DESCRIPTION OF DRAWINGS

[0011] The technical solutions and other beneficial effects of the present application will be apparent from the following detailed description of the specific embodiments of the present application in conjunction with the accompanying drawings.

[0012] Figure 1 The present application provides a comparative display device.

[0013] Figure 2 The present application provides a comparative display device.

[0014] Figure 3 The present application provides a comparative display device.

[0015] Figure 4 The present application provides a comparative display device.

[0016] Figure 5 The present application provides a comparative display device.

[0017] Figure 6 A first stack diagram of a first active layer and a first gate layer provided for an embodiment of the present application.

[0018] Figure 7 A first stack diagram of a first active layer, a first gate layer and a second gate layer provided for an embodiment of the present application.

[0019] Figure 8 A first stack diagram of a first active layer, a first gate layer, a second gate layer and a second active layer provided for an embodiment of the present application.

[0020] Figure 9 A first stack diagram of a first active layer, a first gate layer, a second gate layer, a second active layer and a third gate layer provided for an embodiment of the present application.

[0021] Figure 10 A first stack diagram of a first active layer, a first gate layer, a second gate layer, a second active layer, a third gate layer and a first type of via provided for an embodiment of the present application.

[0022] Figure 11 A first stack diagram of a first active layer, a first gate layer, a second gate layer, a second active layer, a third gate layer, a first type of via and a second type of via provided for an embodiment of the present application.

[0023] Figure 12 A first stack diagram of a first active layer, a first gate layer, a second gate layer, a second active layer, a third gate layer, a first type of via, a second type of via and a first source / drain layer provided for an embodiment of the present application.

[0024] Figure 13 A first stack diagram of a first active layer, a first gate layer, a second gate layer, a second active layer, a third gate layer, a first type of via, a second type of via, a first source / drain layer and a third type of via provided for an embodiment of the present application.

[0025] Figure 14 A first stack diagram of a first active layer, a first gate layer, a second gate layer, a second active layer, a third gate layer, a first type of via, a second type of via, a first source / drain layer, a third type of via and a second source / drain layer provided for an embodiment of the present application.

[0026] Figure 15 A first stack diagram of a first active layer and a first type of via provided for an embodiment of the present application.

[0027] Figure 16 A second exploded diagram of a first active layer provided for an embodiment of the present application.

[0028] Figure 17A second stack diagram of the first active layer and the first gate layer provided by the embodiment of the present application.

[0029] Figure 18 A second stack diagram of the first active layer, the first gate layer and the second gate layer provided by the embodiment of the present application.

[0030] Figure 19 A second stack diagram of the first active layer, the first gate layer, the second gate layer and the second active layer provided by the embodiment of the present application.

[0031] Figure 20 A second stack diagram of the first active layer, the first gate layer, the second gate layer, the second active layer and the third gate layer provided by the embodiment of the present application.

[0032] Figure 21 A second stack diagram of the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer and the first via provided by the embodiment of the present application.

[0033] Figure 22 A second stack diagram of the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, the first via and the second via provided by the embodiment of the present application.

[0034] Figure 23 A second stack diagram of the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, the first via, the second via and the first source / drain layer provided by the embodiment of the present application.

[0035] Figure 24 A second stack diagram of the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, the first via, the second via, the first source / drain layer and the third via provided by the embodiment of the present application.

[0036] Figure 25 A second stack diagram of the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, the first via, the second via, the first source / drain layer, the third via and the second source / drain layer provided by the embodiment of the present application.

[0037] Figure 26 A second stack diagram of the first active layer and the first via provided by the embodiment of the present application.

[0038] Figure 27 A timing diagram of the pixel driving circuit provided by the embodiment of the present application. DETAILED DESCRIPTION

[0039] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0040] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present application, "multiple" means two or more, unless otherwise clearly and specifically defined.

[0041] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections, electrical connections, or mutual communication; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal communication between two components or the interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0042] In this application, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature between them. Moreover, a first feature being "above," "above," and "above" a second feature may include the first feature being directly above or obliquely above the second feature, or may simply mean that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature may include the first feature being directly below or obliquely below the second feature, or may simply mean that the first feature is lower in level than the second feature.

[0043] The following disclosure provides many different embodiments, or examples, for implementing different structures of the present application. For the purpose of simplifying the present application, the components and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeatedly refer to numbers and / or letters in different examples, and such repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed. In addition, the present application provides examples of various specific processes and materials, but those of ordinary skill in the art can realize the application of other processes and / or the use of other materials.

[0044] Figure 1 The stack diagram of the film layers of the display device is provided for the embodiments of the present application. Figure 2 The stack diagram of the polysilicon film and the connecting hole is provided for the embodiments of the present application.

[0045] As an introduction to the embodiments of the present application, a display device is provided to illustrate the principle of the technical problem to be solved by the embodiments of the present application. As shown in Figure 1 , Figure 2 The display device includes a polysilicon film 11, a first gate film 12, a second gate film 13, a metal oxide film 14 and a third gate film 15 arranged in sequence, each metal film forms an electrode and a signal line of each transistor, and each semiconductor film forms an active pattern of each transistor. In the display device, in order to make the oxide thin film transistor exist a punching space, the channels of a plurality of low-temperature polysilicon thin film transistors are arranged on one side of the channel of the driving transistor, so that the display device is punched for the first time to the polysilicon film 11, the first gate film 12 and the second gate film 13, and the display device is punched for the second time to the third gate film 15, so that the channels of the low-temperature polysilicon thin film transistors are arranged on the other side of the channel of the driving transistor. Figure 2 As can be seen from the above, the number of the connecting holes 16 located below the channel 111 of the driving transistor is more than the number of the connecting holes 16 above the channel 111 of the driving transistor. When a defect occurs in a certain pixel in the display device, the hydrogen inside the pixel will be released outward through the defect, resulting in a decrease in hydrogen, and the electrical properties of the driving transistor will be offset, thereby causing a difference in electrical properties between two adjacent pixels, and a display uneven problem occurs during display. Therefore, the existing display device has the technical problem that the hole density on the upper and lower sides of the driving transistor is uneven, resulting in display abnormalities.

[0046] The embodiments of the present application aim at the above technical problems, and provide a display panel and a display device to solve the above technical problems.

[0047] Figure 3 The film layer schematic diagram of the display panel is provided for the embodiments of the present application. Figure 4 The circuit diagram of the pixel driving circuit of the display panel is provided for the embodiments of the present application. Figure 5 The first kind of exploded view of the first active layer is provided for the embodiments of the present application. Figure 6 A first stack diagram of a first active layer and a first gate layer provided for an embodiment of the present application. Figure 7 A first stack diagram of a first active layer, a first gate layer and a second gate layer provided for an embodiment of the present application. Figure 8 A first stack diagram of a first active layer, a first gate layer, a second gate layer and a second active layer provided for an embodiment of the present application. Figure 9 A first stack diagram of a first active layer, a first gate layer, a second gate layer, a second active layer and a third gate layer provided for an embodiment of the present application.

[0048] Figure 10 A first stack diagram of a first active layer, a first gate layer, a second gate layer, a second active layer, a third gate layer and a first type of via provided for an embodiment of the present application. Figure 11 A first stack diagram of a first active layer, a first gate layer, a second gate layer, a second active layer, a third gate layer, a first type of via and a second type of via provided for an embodiment of the present application. Figure 12 A first stack diagram of a first active layer, a first gate layer, a second gate layer, a second active layer, a third gate layer, a first type of via, a second type of via and a first source / drain layer provided for an embodiment of the present application. Figure 13 A first stack diagram of a first active layer, a first gate layer, a second gate layer, a second active layer, a third gate layer, a first type of via, a second type of via, a first source / drain layer and a third type of via provided for an embodiment of the present application. Figure 14 A first stack diagram of a first active layer, a first gate layer, a second gate layer, a second active layer, a third gate layer, a first type of via, a second type of via, a first source / drain layer, a third type of via and a second source / drain layer provided for an embodiment of the present application. Figure 15 A first stack diagram of a first active layer and a first type of via provided for an embodiment of the present application. Figure 16 A second exploded diagram of a first active layer provided for an embodiment of the present application. Figure 17 A second stack diagram of a first active layer and a first gate layer provided for an embodiment of the present application. Figure 18 A second stack diagram of a first active layer, a first gate layer and a second gate layer provided for an embodiment of the present application. Figure 19 A second stack diagram of a first active layer, a first gate layer, a second gate layer and a second active layer provided for an embodiment of the present application. Figure 20 A second stack diagram of a first active layer, a first gate layer, a second gate layer, a second active layer and a third gate layer provided for an embodiment of the present application. Figure 21 A second stack diagram of a first active layer, a first gate layer, a second gate layer, a second active layer, a third gate layer and a first type of via provided for an embodiment of the present application.

[0049] Figure 22 A second kind of stack diagram of the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, the first kind of via hole and the second kind of via hole provided by the embodiment of the present application. Figure 23 A second kind of stack diagram of the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, the first kind of via hole, the second kind of via hole and the first source-drain layer provided by the embodiment of the present application. Figure 24 A second kind of stack diagram of the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, the first kind of via hole, the second kind of via hole, the first source-drain layer and the third kind of via hole provided by the embodiment of the present application. Figure 25 A second kind of stack diagram of the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, the first kind of via hole, the second kind of via hole, the first source-drain layer, the third kind of via hole and the second source-drain layer provided by the embodiment of the present application. Figure 26 A second kind of stack diagram of the first active layer and the first kind of via hole provided by the embodiment of the present application. Figure 27 A timing diagram of the pixel driving circuit provided by the embodiment of the present application.

[0050] As shown in Figures 3 to 26 The display panel 2 includes a substrate 21 and a driving circuit layer 22, the driving circuit layer 22 is arranged on one side of the substrate 21, the driving circuit layer 22 includes a first active layer 224, the first active layer 224 is arranged on one side of the substrate 21, the driving circuit layer 22 further includes a pixel driving circuit 31, the pixel driving circuit 31 includes a switching transistor T2, a driving transistor T1, a compensation transistor T3 and a first initialization transistor T4, the switching transistor T2 and the driving transistor T1 are connected to a first node A; one electrode of the compensation transistor T3 and one electrode of the first initialization transistor T4 are connected to a second node Q, the other electrode of the compensation transistor T3 and the driving transistor T1 are connected to a third node B.

[0051] The first active layer 224 includes an active pattern T1A of the driving transistor T1 and an active pattern T2A of the switching transistor T2, the active pattern T1A of the driving transistor T1 is arranged along a first direction X, the active pattern T2A of the switching transistor T2 is arranged along a second direction Y, at least one compensation hole 311a is arranged in at least one of the pixel driving circuits 31 in the second direction Y, the compensation hole 311a is arranged on a side of the active pattern T1A of the driving transistor T1 close to the active pattern T2A of the switching transistor T2, the compensation hole 311a and the projection of the active pattern T2A of the switching transistor T2 on the substrate 21 do not overlap, and the angle between the first direction X and the second direction Y is greater than 0 and less than or equal to 90 degrees.

[0052] An embodiment of the present application provides a display panel, which is configured such that at least one compensation hole is provided in at least one pixel driving circuit in a second direction. The compensation hole is provided on a side of the active pattern of the driving transistor close to the active pattern of the switching transistor, and the compensation hole does not overlap with the projection of the active pattern of the switching transistor on the substrate. Therefore, compensation holes can be added above the active pattern of the driving transistor so that the number of holes above the active pattern of the driving transistor is similar to the number of holes below the active pattern of the driving transistor. Therefore, when there are defects in the display panel, the holes can also produce a dehydrogenation effect, so that the influence of the defects on the dehydrogenation effect can be reduced, thereby reducing the influence of the defects on the electrical properties of the driving transistor, making the electrical properties of the driving transistors in each pixel similar, thereby avoiding display unevenness and improving the display effect.

[0053] Specifically, the embodiment of the present application adds compensation holes on the side of the active pattern of the driving transistor close to the active pattern of the switching transistor, so that the distribution of the compensation holes around the active pattern of the driving transistor is more uniform, thereby reducing the impact of defects on the electrical properties of the driving transistor and making the display uniformity of the display panel better. The compensation holes avoid the active pattern of the switching transistor to avoid affecting the active pattern of the switching transistor.

[0054] Specifically, the principle of improving the uniformity of the display panel by the embodiment of the present application compared to the current display device is as follows: defects are prone to occur during the preparation of the display panel, such as film breakdown or damage caused by particles, or film fracture. When a pixel in the display panel has a defect, the hydrogen in the pixel will be released outward through the defect, resulting in a decrease in hydrogen and a shift in the electrical properties of the transistor, thereby causing a difference in the electrical properties of the pixel and other pixels, resulting in a brightness difference during display and uneven display. The embodiment of the present application takes into account that the position where the hole is provided can also release hydrogen. When the defect occurs at a position with a high hole density, since the hole has already released hydrogen, the defect has less impact on the transistor of the pixel, thereby making the electrical difference between the defective pixel and the non-defective pixel, and the pixel with fewer defects and the pixel with more defects smaller. Therefore, by reducing the area with low hole density, the display unevenness caused by excessive electrical differences between pixels can be avoided. Therefore, the embodiment of the present application can increase the hole density above the active pattern of the driving transistor by providing at least one compensation hole above the active pattern of the driving transistor, reduce the impact of the defect on the electrical properties of the pixel, and improve display uniformity.

[0055] In some embodiments, the driving circuit layer 22 further comprises a first gate insulating layer 225, a second gate insulating layer 227, a first interlayer insulating layer 229, a third gate insulating layer 231, and a second interlayer insulating layer 233, the first gate insulating layer 225 is disposed on a side of the first active layer 224 away from the substrate 21, the second gate insulating layer 227 is disposed on a side of the first gate insulating layer 225 away from the first active layer 224, the first interlayer insulating layer 229 is disposed on a side of the second gate insulating layer 227 away from the first gate insulating layer 225, the third gate insulating layer 231 is disposed on a side of the first interlayer insulating layer 229 away from the second gate insulating layer 227, and the second interlayer insulating layer 233 is disposed on a side of the third gate insulating layer 231 away from the first interlayer insulating layer 229.

[0056] In some embodiments, the compensation hole 311a penetrates at least one of the first gate insulating layer 225, the second gate insulating layer 227, the first interlayer insulating layer 229, the third gate insulating layer 231, and the second interlayer insulating layer 233. By making the compensation hole penetrate at least one of the first gate insulating layer, the second gate insulating layer, the first interlayer insulating layer, the third gate insulating layer, and the second interlayer insulating layer, the compensation hole can release hydrogen, thereby reducing the impact of defects in the display panel on the electrical properties of the transistors in the pixel, improving the uniformity of the brightness of each pixel, and improving display uniformity.

[0057] In some embodiments, the pixel driving circuit 31 further comprises a storage capacitor Cst, one plate of the storage capacitor Cst is connected to a high potential power supply line VDD, and the other plate of the storage capacitor Cst is connected to the gate of the driving transistor T1 at a second node Q, the driving circuit layer 22 further comprises a first gate layer 226 and a second gate layer 228, the first gate layer 226 comprises a first plate Cst1 of the storage capacitor Cst, the second gate layer 228 comprises a second plate Cst2 of the storage capacitor Cst, and the second plate Cst2 of the storage capacitor Cst is provided with a first connecting portion L1, a projection of the first connecting portion L1 on the substrate 21 is located on a side of the active pattern of the driving transistor T1 close to the active pattern of the switching transistor T2. By disposing the first connecting portion of the storage capacitor on a side of the active pattern of the driving transistor close to the active pattern of the switching transistor, when the second plate of the storage capacitor is connected to the high potential power supply line through the metal in the compensation hole, the compensation hole can be located on a side of the active pattern of the driving transistor close to the first portion of the second scan line, thereby increasing the hole density above the active pattern of the driving transistor, reducing the impact of defects in the display panel on the electrical properties of the transistors in the pixel, improving the uniformity of the brightness of each pixel, and improving display uniformity.

[0058] In some embodiments, the compensation hole 311a penetrates the first interlayer insulating layer 229, the third gate insulating layer 231, and the second interlayer insulating layer 233, and the compensation hole 311a is arranged corresponding to the first connection portion L1. By making the compensation hole penetrate the first interlayer insulating layer, the third gate insulating layer, and the second interlayer insulating layer, and arranging the compensation hole corresponding to the first connection portion, the compensation hole corresponding to the first connection portion can be changed from being arranged below the active pattern of the drive transistor to being arranged above the active pattern of the drive transistor, without the need to increase the number of compensation holes, and the density of holes above the active pattern of the drive transistor is increased, thereby reducing the influence of defects in the display panel on the electrical properties of the transistors in the pixels, improving the uniformity of the brightness of each pixel, and improving the display uniformity.

[0059] In some embodiments, the pixel drive circuit 31 further includes a first light-emitting control transistor T5, the drive circuit layer 22 further includes a first source-drain layer 234, the first source-drain layer 234 includes a first electrode T5S of the first light-emitting control transistor T5 and a second connection portion L2, a projection of the second connection portion L2 on the substrate 21 is located on both sides of a projection of the active pattern T1A of the drive transistor T1 on the substrate 21, and the second connection portion L2 is connected to the first connection portion L1 through the compensation hole 311a.

[0060] In some embodiments, the drive circuit layer 22 further includes a second source-drain layer 236, the second source-drain layer 236 includes a high-potential power supply line VDD, and the high-potential power supply line VDD is connected to the second connection portion L2. By connecting the high-potential power supply line to the second connection portion, the high-potential power supply line can be connected to the first connection portion through the second connection portion, and the connection of the high-potential power supply line to the second plate of the storage capacitor is achieved.

[0061] In some embodiments, the first active layer 224 further includes a compensation active pattern T0A, the compensation active pattern T0A is arranged on a side of the active pattern T1A of the drive transistor T1 close to the active pattern T2A of the switch transistor T2, and a projection of the compensation active pattern T0A on the substrate 21 does not overlap with a projection of the active pattern T2A of the switch transistor T2 on the substrate 21. By arranging the compensation active pattern, the projection of the compensation active pattern on the substrate is located above the active pattern of the drive transistor, a compensation hole can be arranged on the compensation active pattern, the density of holes above the active pattern of the drive transistor is increased, thereby reducing the influence of defects in the display panel on the electrical properties of the transistors in the pixels, improving the uniformity of the brightness of each pixel, and improving the display uniformity.

[0062] In some embodiments, the gate of the switch transistor T2 is connected with the first scan signal line Pscan, the gate of the compensation transistor T3 is connected with the second scan signal line Nscanl, the gate of the first initialization transistor T4 is connected with the third scan signal line Nscan2, the driving circuit layer 22 further comprises a first gate layer 226 and a second gate layer 228, the first gate layer 226 comprises a first plate Cstl of the storage capacitor Cst, the second gate layer 228 comprises a first part Nscanla of the second scan signal line Nscanl, a first part Nscan2a of the third scan signal line Nscan2 and a second plate Cst2 of the storage capacitor Cst, the second plate Cst2 of the storage capacitor Cst is provided with a first connecting part Ll, a projection of the first connecting part Ll on the substrate 21 is located on a side of a projection of the active pattern of the driving transistor Tl on the substrate 21 away from a projection of the active pattern of the switch transistor T2 on the substrate 21. By arranging the first connecting part of the storage capacitor on the side of the active pattern of the driving transistor away from the active pattern of the switch transistor, when the second plate of the storage capacitor is connected with the high potential power supply line, the first electrode of the first light emitting control transistor can be connected with the high potential power supply line, and there is no need to arrange multiple connecting parts.

[0063] In some embodiments, the compensation hole 311a penetrates the first gate insulating layer 225, the second gate insulating layer 227, the first interlayer insulating layer 229, the third gate insulating layer 231 and the second interlayer insulating layer 233, and the compensation hole 311a is arranged corresponding to the compensation active pattern TOA. By making the compensation hole penetrate the first gate insulating layer, the second gate insulating layer, the first interlayer insulating layer, the third gate insulating layer and the second interlayer insulating layer, the hole density above the active pattern of the driving transistor can be increased, and the hole density below the active pattern of the driving transistor is not reduced, thereby reducing the influence of defects in the display panel on the electrical properties of the transistors in the pixels, improving the uniformity of the brightness of each pixel, and improving the display uniformity.

[0064] In some embodiments, a projection of the compensation hole 311a on the substrate 21 is located between a projection of the first part Nscanla of the second scan signal line Nscanl on the substrate 21 and a projection of the first part Nscan2a of the third scan signal line Nscan2 on the substrate 21.

[0065] In some embodiments, the pixel driving circuit 31 also includes a first light-emitting control transistor T5, and the driving circuit layer 22 also includes a first source-drain layer 234, the first source-drain layer 234 includes a first electrode T5S and a third connection part L3 of the first light-emitting control transistor T5, the first electrode T5S of the first light-emitting control transistor T5 is connected to the first connection part L1, and the third connection part L3 passes through the compensation hole 311a and is connected to the compensation active pattern T0A.

[0066] In some embodiments, the driving circuit layer 22 further includes a second source / drain layer 236. The second source / drain layer 236 includes a high-potential power line VDD, which is connected to the third connection portion L3. By connecting the high-potential power line to the third connection portion, the high-potential power line can be connected to the compensation active pattern through the third connection portion, thereby preventing the compensation active pattern from affecting other electrical signals and reducing the impedance of the high-potential power line.

[0067] In some embodiments, as Figures 4 to 26 As shown, the gate of the switching transistor T2 is connected to the first scanning signal line Pscan, the first electrode of the switching transistor T2 is connected to the data line DATA, and the second electrode of the switching transistor T2 is connected to the first electrode of the driving transistor T1 to the first node A; the gate of the compensation transistor T3 is connected to the second scanning signal line Nscan1, the first electrode of the compensation transistor T3 is connected to the gate of the driving transistor T1 to the second node Q, and the second electrode of the compensation transistor T3 is connected to the second electrode of the driving transistor T1; the gate of the first initialization transistor T4 is connected to the third scanning signal line Nscan2, the first electrode of the first initialization transistor T4 is connected to the first initialization signal line VI-G, and the second electrode of the first initialization transistor T4 is connected to the gate of the driving transistor T1 to the second node Q; the pixel driving circuit 31 further includes:

[0068] a first light-emitting control transistor T5, wherein a gate of the first light-emitting control transistor T5 is connected to the light-emitting control signal line EM, a first electrode of the first light-emitting control transistor T5 is connected to the high-potential power line VDD, and a second electrode of the first light-emitting control transistor T5 is connected to the first electrode of the driving transistor T1 and a first node A;

[0069] a second light emitting control transistor T6, wherein a gate of the second light emitting control transistor T6 is connected to the light emitting control signal line EM, and a first electrode of the second light emitting control transistor T6 and the second electrode of the driving transistor T1 are connected to a third node B;

[0070] a second initialization transistor T7 having a gate connected to the fourth scan signal line Pscan2, a first electrode connected to a second initialization signal line VI-ANO, and a second electrode connected to the second node C;

[0071] a third initialization transistor T8 having a gate connected to the fourth scan signal line Pscan2, a first electrode connected to a third initialization signal line VI3, and a second electrode connected to the first node A;

[0072] a storage capacitor Cst having one plate connected to the high potential power supply line VDD and the other plate connected to the gate of the drive transistor T1;

[0073] a boost capacitor Cboost having one plate connected to the first scan signal line Pscan and the other plate connected to the second electrode of the first initialization transistor T4.

[0074] Specifically, as shown in Figure 3 , Figure 4 the display panel 2 further includes a light emitting layer including a light emitting device LED connected to the pixel drive circuit, the anode of the light emitting device LED being connected to the second electrode of the second initialization transistor T7, and the cathode of the light emitting device LED being connected to the low potential power supply line VSS.

[0075] In some embodiments, as Figure 3As shown, the driving circuit layer 22 further comprises a first gate insulating layer 225, a first gate layer 226, a second gate insulating layer 227, a second gate layer 228, a first interlayer insulating layer 229, a second active layer 230, a third gate insulating layer 231, a third gate layer 232, a second interlayer insulating layer 233, a first source-drain layer 234, and a second source-drain layer 236. The first gate insulating layer 225 is disposed on the side of the first active layer 224 away from the substrate 21. The first gate layer 226 is disposed on the side of the first gate insulating layer 225 away from the first active layer 224. The second gate insulating layer 227 is disposed on the side of the first gate layer 226 away from the first gate insulating layer 225. The second gate layer 228 is disposed on the side of the second gate insulating layer 227 away from the first gate layer 226. The first interlayer insulating layer 229 is disposed on the side of the second gate layer 228 away from the second gate insulating layer 227. The second active layer 230 is disposed on the side of the first interlayer insulating layer 229 away from the second gate layer 228. The third gate insulating layer 231 is disposed on the side of the second active layer 230 away from the first interlayer insulating layer 229. The third gate layer 232 is disposed on the side of the third gate insulating layer 231 away from the second active layer 230. The second interlayer insulating layer 233 is disposed on the side of the third gate layer 232 away from the third gate insulating layer 231. The first source-drain layer 234 is disposed on the side of the second interlayer insulating layer 233 away from the third gate layer 232. The second source-drain layer 236 is disposed on the side of the first source-drain layer 234 away from the second interlayer insulating layer 233.

[0076] In the embodiment, the compensation hole 311a penetrates at least one of the first gate insulating layer 225, the second gate insulating layer 227, the first interlayer insulating layer 229, the third gate insulating layer 231, and the second interlayer insulating layer 233. By making the compensation hole penetrate at least one of the first gate insulating layer, the second gate insulating layer, the first interlayer insulating layer, the third gate insulating layer, and the second interlayer insulating layer, the compensation hole can release hydrogen, thereby reducing the influence of defects in the display panel on the electrical properties of the transistors in the pixels, improving the uniformity of the brightness of the pixels, and improving the display uniformity.

[0077] Specifically, it can be understood that the compensation hole can penetrate one of the first gate insulating layer, the second gate insulating layer, the first interlayer insulating layer, the third gate insulating layer, and the second interlayer insulating layer, or can penetrate two or more of the first gate insulating layer, the second gate insulating layer, the first interlayer insulating layer, the third gate insulating layer, and the second interlayer insulating layer.

[0078] Specifically, as shown in FIG. 3, the compensation hole 311a penetrates the first gate insulating layer 225, the second gate insulating layer 227, the first interlayer insulating layer 229, the third gate insulating layer 231, and the second interlayer insulating layer 233. Figure 3As shown, the driving circuit layer 22 further comprises a barrier layer 221, a light shielding layer 222, and a buffer layer 223, a first planarization layer 235, and a second planarization layer 237.

[0079] Specifically, as shown in FIG. 2, the first active layer 224 comprises an active pattern T1A of the driving transistor T1, an active pattern T2A of the switch transistor T2, an active pattern T3A of the first initialization transistor T3, and an active pattern T4A of the second initialization transistor T4. Figure 3 As shown, the light emitting layer comprises a pixel electrode layer 238, a pixel definition layer 239, a light emitting material layer, a common electrode layer, and a support column 240.

[0080] In some embodiments, as shown in FIG. 2, the first active layer 224 further comprises an active pattern T5A of the first light emitting control transistor T5, an active pattern T6A of the second light emitting control transistor T6, an active pattern T7A of the second initialization transistor T7, and an active pattern T8A of the third initialization transistor T8. Figure 3 , Figure 4 , Figure 5 As shown, the first active layer 224 further comprises an active pattern T5A of the first light emitting control transistor T5, an active pattern T6A of the second light emitting control transistor T6, an active pattern T7A of the second initialization transistor T7, and an active pattern T8A of the third initialization transistor T8, which are arranged along the second direction Y on the side of the active pattern T1A of the driving transistor T1 away from the active pattern T2A of the switch transistor T2, the side of the active pattern T1A of the driving transistor T1 connected with the active pattern T2A of the switch transistor T2 and the active pattern T5A of the first light emitting control transistor T5, the other side of the active pattern T1A of the driving transistor T1 connected with the active pattern T6A of the second light emitting control transistor T6, and the active pattern T6A of the second light emitting control transistor T6 connected with the active pattern T7A of the second initialization transistor T7. By arranging the active pattern T5A of the first light emitting control transistor T5, the active pattern T6A of the second light emitting control transistor T6, the active pattern T7A of the second initialization transistor T7, and the active pattern T8A of the third initialization transistor T8 along the second direction Y on the side of the active pattern T1A of the driving transistor T1 away from the active pattern T2A of the switch transistor T2, a space is left above the active pattern of the driving transistor for arranging the compensation transistor and the first initialization transistor.

[0081] Specifically, it can be understood that the specific positions of the active patterns of the transistors can be determined according to the specific positions of the gates of the transistors, for example, the specific position of the active pattern of the driving transistor can be determined according to the overlapping position of the active pattern of the driving transistor and the gate of the driving transistor.

[0082] In some embodiments, as shown in FIG. 2, the first active layer 224 further comprises an active pattern T5A of the first light emitting control transistor T5, an active pattern T6A of the second light emitting control transistor T6, an active pattern T7A of the second initialization transistor T7, and an active pattern T8A of the third initialization transistor T8. Figure 3 , Figure 4 , Figure 6As shown, the first gate layer 226 includes a first scan signal line Pscan, a first plate Cst1 of a storage capacitor Cst, an emission control signal line EM, a fourth scan signal line Pscan2, a gate T1G of the driving transistor T1, a gate T2G of the switching transistor T2, a gate T5G of the first emission control transistor T5, a gate T6G of the second emission control transistor T6, a gate T7G of the second initialization transistor T7, and a gate T8G of the third initialization transistor T8, which are sequentially and spaced apart along a second direction Y.

[0083] Specifically, as shown in Figure 5 , Figure 6 , Figure 6 is a laminated diagram of the first active layer 224 and the first gate layer 226 of the display panel in the embodiment of the present application, Figure 5 is an exploded diagram of the first active layer 224 of the display panel in the embodiment of the present application, in Figure 5 , the structures in the first active layer are identified, in order to clearly identify the structures of the first gate layer 226, and since the first active layer and the first gate layer are laminated, part of the structures of the first active layer are shielded by the first gate layer, in Figure 6 , the structures in the first active layer are not identified, and only the first active layer 224 and the structures of the first gate layer 226 are identified, it can be understood that Figure 6 , the specific structure of the first active layer 224 in Figure 5 may be referred to , and for the same reason, in other laminated diagrams, only the specific structures of the uppermost film layer or the compensation hole are identified, and the specific structures of the lower compensation hole and film layer can be referred to the specific identification in other drawings, which will not be described in the following embodiments.

[0084] Specifically, as shown in Figure 6As shown, the gate T2G of the switching transistor T2 is part of the first scanning signal line Pscan. It can be understood that since the gates T2G of all the switching transistors T2 in a row of pixel units are connected to the same first scanning signal line Pscan, when the first scanning signal line Pscan is formed, the portion of the first scanning signal line corresponding to the channel of the switching transistor T2 of each pixel unit serves as the gate of the switching transistor T2 of each pixel unit. Therefore, two reference numerals are used to identify the same structure. Similarly, the gate T1G of the driving transistor T1 serves as both the gate and the first plate Cst1 of the storage capacitor Cst. The light-emitting control signal line EM corresponds to the first light-emitting transistor. A portion of the channel of the control transistor T5 serves as the gate T5G of the first light-emitting control transistor T5, a portion of the channel of the light-emitting control signal line EM corresponding to the second light-emitting control transistor T6 serves as the gate T6G of the second light-emitting control transistor T6, a portion of the channel of the fourth scanning signal line Pscan2 corresponding to the second initialization transistor T7 serves as the gate T7G of the second initialization transistor T7, and a portion of the channel of the fourth scanning signal line Pscan2 corresponding to the third initialization transistor T8 serves as the gate T8G of the third initialization transistor T8. When multiple reference numerals are used to identify the same structure in other drawings, please refer to the above description and will not be repeated in the following embodiments.

[0085] Specifically, such as Figure 6 As shown, the first gate layer 226 further includes a first plate Cboost1 of the boost capacitor Cboost.

[0086] In some embodiments, as Figure 3 、 Figure 4 、 Figure 7As shown, the second gate layer 228 includes a first part Nscan1a of the second scan signal line Nscan1, a first part Nscan2a of the third scan signal line Nscan2, a second plate Cst2 of the storage capacitor Cst and the second initialization signal line VI-ANO, the first part Nscan2a of the third scan signal line Nscan2, the first part Nscan1a of the second scan signal line Nscan1, the second plate Cst2 of the storage capacitor Cst and the second initialization signal line VI-ANO are arranged along the second direction Y, the second plate Cst2 of the storage capacitor Cst is provided with a first connection portion L1, and the projection of the first connection portion L1 on the substrate 21 is located on the side of the active pattern T1A of the driving transistor T1 close to the first part Nscan1a of the second scan signal line Nscan1. By arranging the first connection portion of the storage capacitor on the side of the first portion of the active pattern of the driving transistor close to the second scanning signal line, when the second plate of the storage capacitor is connected to the high-potential power line through the metal in the compensation hole, the compensation hole can be located on the side of the first portion of the active pattern of the driving transistor close to the second scanning line, thereby increasing the hole density above the active pattern of the driving transistor, reducing the impact of defects in the display panel on the electrical properties of the transistor in the pixel, improving the uniformity of the brightness of each pixel, and improving display uniformity.

[0087] Specifically, such as Figure 7 As shown, a through hole is provided on the second plate Cst2 of the storage capacitor Cst, so that the first electrode of the compensation transistor can pass through the through hole of the second plate of the storage capacitor to be connected to the gate of the driving transistor, so that the pixel driving circuit works normally.

[0088] Specifically, such as Figure 7 As shown, the projection of the first connection portion L1 on the substrate 21 is located between the projection of the active pattern T1A of the driving transistor T1 on the substrate and the projection of the first portion Nscan1a of the second scan signal line Nscan1 on the substrate.

[0089] Specifically, such as Figure 7 As shown, the second gate layer 228 includes a first gate T3Ga of the compensation transistor T3 and a first gate T4Ga of the first initialization transistor T4.

[0090] In some embodiments, as Figure 3 、 Figure 4 、 Figure 8 As shown, the second active layer 230 includes an active pattern T3A of the compensation transistor T3 and an active pattern T4A of the first initialization transistor T4 , and the active pattern T3A of the compensation transistor T3 and the active pattern T4A of the first initialization transistor T4 are arranged along the second direction Y.

[0091] Specifically, as shown in Figure 8 The second active layer 230 further includes a second plate Cboost2 of the boost capacitor Cboost.

[0092] In some embodiments, as shown in Figure 3 , Figure 4 , Figure 9 The third gate layer 232 includes a second part Nscan1b of the second scan signal line Nscan1, a second part Nscan2b of the third scan signal line Nscan2, and the third initialization signal line VI3, the second part Nscan2b of the third scan signal line Nscan2, the second part Nscan1b of the second scan signal line Nscan1, and the third initialization signal line VI3 are arranged along the second direction Y, and a projection of the third initialization signal line VI3 on the substrate 21 overlaps with a projection of the fourth scan signal line Pscan2 on the substrate 21. By overlapping the projection of the third initialization signal line on the substrate with the projection of the fourth scan signal line on the substrate, the space occupied by the signal lines can be reduced, and the resolution of the display panel can be improved.

[0093] Specifically, as shown in Figure 9 The third gate layer 232 includes a second gate T3Gb of the compensation transistor T3 and a second gate T4Gb of the first initialization transistor T4.

[0094] Specifically, the second part Nscan1b of the second scan signal line Nscan1 is connected with the first part Nscan1a of the second scan signal line Nscan1, and the second part Nscan2b of the third scan signal line Nscan2 is connected with the first part Nscan2a of the third scan signal line Nscan2. Since the connection between the second part Nscan1b of the second scan signal line and the first part Nscan1a of the second scan signal line is located at the edge of the display area or in the non-display area, the connection between the two is not shown in the figure. Similarly, the connection between the second part Nscan2b of the third scan signal line Nscan2 and the first part Nscan2a of the third scan signal line Nscan2 is not shown.

[0095] In some embodiments, as shown in Figure 3 , Figure 10As shown, the display panel 2 includes first-type via holes 311, part of the first-type via holes 311 pass through the first gate insulating layer, the second gate insulating layer, the first interlayer insulating layer, the third gate insulating layer and the second interlayer insulating layer, part of the first-type via holes 311 pass through the second gate insulating layer, the first interlayer insulating layer, the third gate insulating layer and the second interlayer insulating layer, part of the first-type via holes 311 pass through the first interlayer insulating layer, the third gate insulating layer and the second interlayer insulating layer.

[0096] Specifically, when forming the connection holes on the display panel, part of the connection holes are formed by one process, and the first-type via holes 311 in the embodiments of the present application represent the connection holes formed by one process, and the first-type via holes 311 refer to the connection holes etched from the insulating layer under the first source-drain layer to one of the first active layer, the first gate layer and the second gate layer.

[0097] Specifically, the compensation hole is one of the first-type via holes 311. By making the compensation hole one of the first-type via holes, the process steps can be avoided, so that the process complexity is avoided when improving the display effect.

[0098] In some embodiments, as shown in Figure 3 , Figure 10 As shown, the compensation hole 311a passes through the first interlayer insulating layer 229, the third gate insulating layer 231 and the second interlayer insulating layer 233, and the compensation hole 311a is arranged corresponding to the first connection portion L1. By making the compensation hole pass through the first interlayer insulating layer, the third gate insulating layer and the second interlayer insulating layer, and the compensation hole corresponding to the first connection portion, the compensation hole corresponding to the first connection portion can be changed from below the active pattern of the drive transistor to above the active pattern of the drive transistor, without the need to increase the additional compensation hole, and the hole density above the active pattern of the drive transistor is increased, so that the influence of the defects in the display panel on the electrical properties of the transistors in the pixels is reduced, the uniformity of the brightness of each pixel is improved, and the display uniformity is improved.

[0099] In some embodiments, as shown in Figure 3 , Figure 11 As shown, the display panel 2 includes second-type via holes 312, part of the second-type via holes 312 pass through the third gate insulating layer and the second interlayer insulating layer, and part of the second-type via holes 312 pass through the second interlayer insulating layer.

[0100] Specifically, when forming the connection holes on the display panel, part of the connection holes are formed by one process, and the second-type via holes 312 in the embodiments of the present application represent the connection holes formed by one process, and the second-type via holes 312 refer to the connection holes etched from the insulating layer under the first source-drain layer to the second active layer or the third gate layer.

[0101] In some embodiments, as shown in Figure 3 , Figure 4 , Figure 12 the first source-drain layer 234 includes a first initialization signal line VI-G, a first electrode T2S of the switch transistor T2, a first electrode T3S of the compensation transistor T3, a second electrode T3D of the compensation transistor T3, a first electrode T4S of the first initialization transistor T4, a second electrode T4D of the first initialization transistor T4, a first electrode T5S of the first light-emitting control transistor T5, a second electrode T5D of the first light-emitting control transistor T5, a first electrode T6S of the second light-emitting control transistor T6, a second electrode T6D of the second light-emitting control transistor T6, a first electrode T7S of the second initialization transistor T7, a second electrode T7D of the second initialization transistor T7, a first electrode T8S of the third initialization transistor T8, a second electrode T8D of the third initialization transistor T8, and a second connection portion L2, a projection of the first electrode T5S of the first light-emitting control transistor T5 on the substrate 21 is located on both sides of a projection of the active pattern T1A of the drive transistor T1 on the substrate 21, and the second connection portion L2 is connected with the first connection portion L1 through the compensation hole 311a.

[0102] Specifically, it can be understood that due to the connection of the electrodes of some transistors, some electrodes are actually the same structure when the transistor is actually formed, for example, the first electrode T3S of the compensation transistor and the second electrode T4D of the first initialization transistor are actually the same structure, and similarly, the second electrode T6D of the second light-emitting control transistor T6 and the second electrode T7D of the second initialization transistor T7 are actually the same structure, and for the first electrode of the drive transistor T1 and the second electrode of the drive transistor T1, the first electrode of the drive transistor T1 is connected with the second electrode of the switch transistor T2 and the second electrode T5D of the first light-emitting control transistor T5, and in actual preparation, only one structure will be prepared, so the second electrode T5D of the first light-emitting control transistor T5 can be considered as the first electrode of the drive transistor T1 and the second electrode of the switch transistor T2 at the same time, and similarly, the first electrode T6S of the second light-emitting control transistor T6 can be considered as the second electrode of the drive transistor T1 at the same time.

[0103] In some embodiments, as shown in Figure 3 , Figure 13 the display panel 2 includes a third type of via hole 313, the third type of via hole 313 penetrates the first planarization layer 235, and one of the third type of via holes is arranged corresponding to the second connection portion.

[0104] In some embodiments, as shown in Figure 3 , Figure 4 , Figure 14 As shown, the second source-drain layer 236 includes a data line DATA and a high potential power line VDD, the data line DATA and the high potential power line VDD are arranged along the first direction X, and the high potential power line VDD is connected with the second connection portion L2. By connecting the high potential power line with the second connection portion, the high potential power line can be connected with the first connection portion through the second connection portion, and the connection of the high potential power line with the second plate of the storage capacitor is realized.

[0105] Specifically, as shown in FIG. 6, it can be seen that the data line DATA is connected with the first electrode of the switch transistor T2, and the high potential power line VDD is connected with the first electrode of the first light emitting control transistor T5. Figure 14

[0106] Specifically, as shown in FIG. 6, it can be seen that the data line DATA is connected with the first electrode of the switch transistor T2, and the high potential power line VDD is connected with the first electrode of the first light emitting control transistor T5. Figure 14

[0107] Specifically, as shown in FIG. 6, it can be seen that the data line DATA is connected with the first electrode of the switch transistor T2, and the high potential power line VDD is connected with the first electrode of the first light emitting control transistor T5. Figure 15 Figure 15 As shown in FIG. 6, a cross-sectional view of the first active layer 224 and the first type of via hole 311 is shown, and from the top view of the first active layer 224 and the first type of via hole 311, Figure 2 and Figure 15 As can be seen from the comparison, in the embodiment of the present application, the compensation hole located below the active pattern of the driving transistor is arranged above the active pattern of the driving transistor, without increasing the number of via holes, avoiding the reduction of the aperture ratio, and adjusting the design of other film layers accordingly, so that each pixel works normally, and the hole density above the active pattern of the driving transistor is increased, the influence of the defects in the display panel on the electrical properties of the transistor in the pixel is reduced, the uniformity of the brightness of each pixel is improved, and the display uniformity is improved.

[0108] In some embodiments, as shown in FIG. 1, Figure 3 , Figure 4 , Figure 16 ​​​As shown, the first active layer 224 further includes an active pattern T5A of a first light emitting control transistor T5, an active pattern T6A of a second light emitting control transistor T6, an active pattern T7A of a second initialization transistor T7, an active pattern T8A of a third initialization transistor T8, and a compensation active pattern T0A. The active pattern T5A of the first light emitting control transistor T5, the active pattern T6A of the second light emitting control transistor T6, the active pattern T7A of the second initialization transistor T7, and the active pattern T8A of the third initialization transistor T8 are arranged on a side of the active pattern T1A of the driving transistor T1 away from the active pattern T2A of the switch transistor T2 along the second direction Y. The side of the active pattern T1A of the driving transistor T1 is connected to the active pattern T2A of the switch transistor T2 and the active pattern T5A of the first light emitting control transistor T5, the other side of the active pattern T1A of the driving transistor T1 is connected to the active pattern T6A of the second light emitting control transistor T6, the active pattern T6A of the second light emitting control transistor T6 is connected to the active pattern T7A of the second initialization transistor T7, and the compensation active pattern T0A is arranged on a side of the active pattern T1A of the driving transistor T1 close to the active pattern T2A of the switch transistor T2, and a projection of the compensation active pattern T0A on the substrate 21 does not overlap with a projection of the active pattern T2A of the switch transistor T2 on the substrate 21. By arranging the compensation active pattern, the projection of the compensation active pattern on the substrate is arranged above the active pattern of the driving transistor, and a compensation hole can be arranged on the compensation active pattern, the hole density above the active pattern of the driving transistor is increased, and thus the influence of defects in the display panel on the electrical properties of the transistors in the pixel is reduced, the brightness uniformity of each pixel is improved, and the display uniformity is improved.

[0109] In some embodiments, as Figure 3 、 Figure 4 、 Figure 17As shown, the first gate layer 226 includes a first scan signal line Pscan, a first plate Cst1 of a storage capacitor Cst, a light-emitting control signal line EM, a fourth scan signal line Pscan2, a gate T1G of a driving transistor T1, a gate T2G of a switching transistor T2, a gate T5G of a first light-emitting control transistor T5, a gate T6G of a second light-emitting control transistor T6, a gate T7G of a second initialization transistor T7, and a gate T8G of a third initialization transistor T8. The first scan signal line Pscan, the first plate Cst1 of the storage capacitor Cst, the light-emitting control signal line EM, and the fourth scan signal line Pscan2 are sequentially spaced along the second direction Y, and a projection of the compensation active pattern T0A on the substrate 21 is located between a projection of the first plate Cst1 of the storage capacitor Cst on the substrate 21 and a projection of the first scan signal line Pscan on the substrate 21.

[0110] Specifically, such as Figure 17 As shown, the first gate layer 226 further includes a first plate Cboost1 of the boost capacitor Cboost.

[0111] In some embodiments, as Figure 3 、 Figure 4 、 Figure 18 As shown, the second gate layer 228 includes a first portion Nscan1a of the second scan signal line Nscan1, a first portion Nscan2a of the third scan signal line Nscan2, a second plate Cst2 of the storage capacitor Cst, and the second initialization signal line VI-ANO. The first portion Nscan2a of the third scan signal line Nscan2, the first portion Nscan1a of the second scan signal line Nscan1, the second plate Cst2 of the storage capacitor Cst, and the second initialization signal line VI-ANO are arranged along a second direction Y. The second plate Cst2 of the storage capacitor Cst has a first connection portion L1. The projection of the first connection portion L1 on the substrate 21 is located on a side of the active pattern T1A of the drive transistor T1 on the substrate 21 that is close to the projection of the second initialization signal line VI-ANO on the substrate 21. By arranging the first connection portion of the storage capacitor on the side of the active pattern of the drive transistor that is close to the second initialization signal line, when the second plate of the storage capacitor is connected to the high-potential power line, it can be connected to the first electrode of the first emission control transistor and then to the high-potential power line, eliminating the need for multiple connection points.

[0112] Specifically, such as Figure 18As shown, a through hole is provided on the second plate Cst2 of the storage capacitor Cst, so that the first electrode of the compensation transistor can pass through the through hole of the second plate of the storage capacitor to be connected to the gate of the driving transistor, so that the pixel driving circuit works normally.

[0113] Specifically, as shown in Figure 18 , the second gate layer 228 includes the first gate T3Ga of the compensation transistor T3 and the first gate T4Ga of the first initialization transistor T4.

[0114] Specifically, as shown in Figure 18 , in the second direction Y, the projection of the compensation active pattern T0A on the substrate 21 is located between the projection of the first scan signal line Pscan on the substrate and the projection of the first part of the second scan signal line Nscan on the substrate.

[0115] In some embodiments, as shown in Figure 3 , Figure 4 , Figure 19 , the second active layer 230 includes the active pattern T3A of the compensation transistor T3 and the active pattern T4A of the first initialization transistor T4, and the active pattern T3A of the compensation transistor T3 and the active pattern T4A of the first initialization transistor T4 are arranged along the second direction Y.

[0116] Specifically, as shown in Figure 19 , the second active layer 230 further includes the second plate Cboost2 of the boost capacitor Cboost.

[0117] Specifically, as shown in Figure 19 , in the first direction X, the projection of the compensation active pattern T0A on the substrate 21 is located between the active pattern of the switch transistor T2 and the active pattern of the compensation transistor T3.

[0118] In some embodiments, as shown in Figure 3 , Figure 4 , Figure 20 , the third gate layer 232 includes the second part Nscan1b of the second scan signal line Nscan1, the second part Nscan2b of the third scan signal line Nscan2, and the third initialization signal line VI3, the second part Nscan2b of the third scan signal line Nscan2, the second part Nscan1b of the second scan signal line Nscan1 and the third initialization signal line VI3 are arranged along the second direction Y, and the projection of the third initialization signal line VI3 on the substrate 21 overlaps with the projection of the fourth scan signal line Pscan2 on the substrate 21. By making the projection of the third initialization signal line on the substrate overlap with the projection of the fourth scan signal line on the substrate, the space occupied by the signal lines can be reduced, and the resolution of the display panel can be improved.

[0119] Specifically, as shown in Figure 20 , the third gate layer 232 includes a second gate T3Gb of the compensation transistor T3 and a second gate T4Gb of the first initialization transistor T4.

[0120] In some embodiments, as shown in Figure 3 , Figure 21 , the display panel 2 includes a first type of via hole 311, a part of the first type of via hole 311 penetrates through the first gate insulating layer, the second gate insulating layer, the first interlayer insulating layer, the third gate insulating layer and the second interlayer insulating layer, a part of the first type of via hole 311 penetrates through the second gate insulating layer, the first interlayer insulating layer, the third gate insulating layer and the second interlayer insulating layer, and a part of the first type of via hole 311 penetrates through the first interlayer insulating layer, the third gate insulating layer and the second interlayer insulating layer.

[0121] Specifically, when forming the connection hole of the display panel, part of the connection hole is formed by one process, and the embodiment of the present application represents the connection hole formed by one process as the first type of via hole 311, which refers to the connection hole etched from the insulating layer under the first source-drain layer to one layer of the first active layer, the first gate layer and the second gate layer.

[0122] Specifically, the compensation hole is one of the first type of via hole 311. By making the compensation hole one of the first type of via hole, the process step can be increased, thereby avoiding increasing the process complexity when improving the display effect.

[0123] In some embodiments, as shown in Figure 3 , Figure 21 , the compensation hole 311a penetrates through the first gate insulating layer 225, the second gate insulating layer 227, the first interlayer insulating layer 229, the third gate insulating layer 231 and the second interlayer insulating layer 233, and the compensation hole 311a is arranged corresponding to the compensation active pattern T0A. By making the compensation hole penetrate through the first gate insulating layer, the second gate insulating layer, the first interlayer insulating layer, the third gate insulating layer and the second interlayer insulating layer, the hole density above the active pattern of the driving transistor can be increased, and the hole density below the active pattern of the driving transistor is not reduced, thereby reducing the influence of defects in the display panel on the electrical properties of the transistor in the pixel, improving the uniformity of the brightness of each pixel, and improving the display uniformity.

[0124] In some embodiments, as shown in Figure 3 , Figure 22As shown, the display panel 2 includes second-type vias 312, part of the second-type vias 312 penetrating through the third gate insulating layer and the second interlayer insulating layer, and part of the second-type vias 312 penetrating through the second interlayer insulating layer.

[0125] Specifically, when forming the connecting holes in the display panel, part of the connecting holes are formed by one process, and the second-type via 312 in the embodiments of the present application represents the connecting hole formed by one process, which refers to the connecting hole etched from the insulating layer under the first source-drain layer to the second active layer or the third gate layer.

[0126] In some embodiments, as shown in Figure 3 , Figure 4 , Figure 23 As shown, the first source-drain layer 234 includes a first initialization signal line VI-G, a first electrode T2S of a switch transistor T2, a first electrode T3S of a compensation transistor T3, a second electrode T3D of the compensation transistor T3, a first electrode T4S of a first initialization transistor T4, a second electrode T4D of the first initialization transistor T4, a first electrode T5S of a first light-emitting control transistor T5, a second electrode T5D of the first light-emitting control transistor T5, a first electrode T6S of a second light-emitting control transistor T6, a second electrode T6D of the second light-emitting control transistor T6, a first electrode T7S of a second initialization transistor T7, a second electrode T7D of the second initialization transistor T7, a first electrode T8S of a third initialization transistor T8, a second electrode T8D of the third initialization transistor T8, and a third connecting portion L3, the first electrode T5S of the first light-emitting control transistor T5 is connected with the first connecting portion L1, and the third connecting portion L3 is connected with the compensation active pattern T0A through the compensation hole 311a.

[0127] In some embodiments, as shown in Figure 3 , Figure 24 As shown, the display panel 2 includes third-type vias 313, the third-type vias 313 penetrating through the first planarization layer 235, and one of the third-type vias is arranged corresponding to the third connecting portion.

[0128] In some embodiments, as shown in Figure 3 , Figure 4 , Figure 25 As shown, the second source-drain layer 236 includes a data line DATA and a high-potential power supply line VDD, the data line DATA and the high-potential power supply line VDD are arranged along the first direction X, and the high-potential power supply line VDD is connected with the third connecting portion L3. By connecting the high-potential power supply line with the third connecting portion, the high-potential power supply line can be connected with the compensation active pattern through the third connecting portion, the influence of the compensation active pattern on other electrical signals is avoided, and the impedance of the high-potential power supply line can be reduced.

[0129] Specifically, as shown in FIG. 6, it can be seen that the data line DATA is connected with the first electrode of the switching transistor T2, and the high potential power supply line VDD is connected with the first electrode of the first light emitting control transistor T5. Figure 25

[0130] Specifically, as shown in FIG. 6, it can be seen that the data line DATA is connected with the first electrode of the switching transistor T2, and the high potential power supply line VDD is connected with the first electrode of the first light emitting control transistor T5. Figure 25

[0131] Specifically, as shown in FIG. 6, it can be seen that the data line DATA is connected with the first electrode of the switching transistor T2, and the high potential power supply line VDD is connected with the first electrode of the first light emitting control transistor T5. Figure 26 Figure 26 FIG. 7 shows a cross-sectional view of the first active layer 224 and the first type of via hole 311, and FIG. 8 shows a cross-sectional view of the second active layer 226 and the second type of via hole 312. Figure 2 Figure 26 As can be seen from the comparison between FIG. 7 and FIG. 8, in the embodiment of the present application, a compensation active pattern is arranged above the active pattern of the driving transistor, and a compensation hole is arranged on the compensation active pattern, so that the hole density above the active pattern of the driving transistor can be increased without reducing the hole density below the active pattern of the driving transistor, thereby reducing the influence of defects in the display panel on the electrical properties of the transistors in the pixels, improving the uniformity of the brightness of each pixel, and improving the display uniformity.

[0132] Specifically, the above embodiment is described by taking the compensation active pattern connected with the high potential power supply line as an example, but the embodiment of the present application is not limited thereto, and the compensation active pattern can be connected with other signal lines of fixed potential, such as the first initialization signal line VI-G and the third initialization signal line VI3.

[0133] Specifically, the above embodiment is described by taking the compensation hole arranged above the active pattern of the driving transistor as an example, but the embodiment of the present application is not limited thereto, and a plurality of compensation holes can be arranged above the active pattern of the driving transistor.

[0134] Specifically, the above embodiment is described by taking the compensation hole penetrating through the first interlayer insulating layer, the third gate insulating layer and the second interlayer insulating layer, and the compensation hole being arranged corresponding to the first connection portion; the compensation hole penetrating through the first gate insulating layer, the second gate insulating layer, the first interlayer insulating layer, the third gate insulating layer and the second interlayer insulating layer, and the compensation hole being arranged corresponding to the compensation active pattern as an example, but it can be understood that two compensation holes can be arranged, one compensation hole penetrating through the first interlayer insulating layer, the third gate insulating layer and the second interlayer insulating layer, and the compensation hole being arranged corresponding to the first connection portion, and the other compensation hole penetrating through the first gate insulating layer, the second gate insulating layer, the first interlayer insulating layer, the third gate insulating layer and the second interlayer insulating layer, and the compensation hole being arranged corresponding to the compensation active pattern.

[0135] ​​​​Specifically, the first electrode of the transistor in the above embodiment is the source electrode, and the second electrode is the drain electrode; or the first electrode of the transistor in the above embodiment is the drain electrode, and the second electrode is the source electrode.

[0136] Specifically, the first scan signal line Pscan, the second scan signal line Nscan1, the third scan signal line Nscan2, the fourth scan signal line Pscan2 and the light-emitting control signal line EM can be connected to different gate drive circuits respectively, and specifically, five groups of gate drive circuits can be used to output signals to the first scan signal line Pscan, the second scan signal line Nscan1, the third scan signal line Nscan2, the fourth scan signal line Pscan2 and the light-emitting control signal line EM respectively, wherein the gate drive circuit connected to the first scan signal line Pscan can use double-side driving, and the other gate drive circuits use single-side driving.

[0137] Specifically, the material of the first active layer includes a silicon semiconductor material, and specifically can be low-temperature polysilicon.

[0138] Specifically, the material of the second active layer includes an oxide semiconductor material, and specifically can be a metal oxide semiconductor material, and more specifically can be indium gallium zinc oxide.

[0139] Specifically, the driving transistor, the switching transistor, the first light-emitting control transistor, the second light-emitting control transistor, the second initialization transistor and the third initialization transistor are P-type transistors, and the first initialization transistor and the compensation transistor are N-type transistors.

[0140] Specifically, in the above embodiment, when the transistor has a bottom gate and a top gate, the gate of the transistor refers to the first gate and the second gate of the transistor.

[0141] Specifically, as shown in FIG. 1, the first scan signal line Pscan, the second scan signal line Nscan1, the third scan signal line Nscan2, the fourth scan signal line Pscan2 and the light-emitting control signal line EM can be connected to different gate drive circuits respectively, and specifically, five groups of gate drive circuits can be used to output signals to the first scan signal line Pscan, the second scan signal line Nscan1, the third scan signal line Nscan2, the fourth scan signal line Pscan2 and the light-emitting control signal line EM respectively, wherein the gate drive circuit connected to the first scan signal line Pscan can use double-side driving, and the other gate drive circuits use single-side driving. Figure 4 , Figure 27As shown, the working process of the pixel driving circuit is explained. In a first stage t1, the second scan signal line Nscan1 is at a high potential, the compensation transistor T3 is turned on, the fourth scan signal line Pscan2 is at a low potential, the second initialization transistor T7 and the third initialization transistor T8 are turned on, and the first node A and the fourth node C are reset; in a second stage t2, the third scan signal line Nscan2 is at a high potential, the first initialization transistor T4 is turned on, and the second node Q is reset; in a third stage t3, the first scan signal line Pscan is at a low potential, the switch transistor T2 is turned on, the second scan signal line Nscan1 is at a high potential, the compensation transistor T3 is turned on, and the data line DATA writes a signal to the second node Q; in a fourth stage t4, the fourth scan signal line Pscan2 is at a low potential, the second initialization transistor T7 and the third initialization transistor T8 are turned on, and the first node A and the fourth node C are reset; in a fifth stage t5, the light-emitting control signal line EM is at a low potential, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on, and the light-emitting device emits light.

[0142] Specifically, the above embodiments respectively explain the display panel from the pixel driving circuit, the film layer structure, and the specific structure of each film layer in the display panel, and it can be understood that, when there is no conflict between the embodiments, the embodiments can be combined, for example, the material of the first active layer includes a silicon semiconductor material, and the material of the second active layer includes an oxide semiconductor material.

[0143] Meanwhile, the display device provided in the embodiments of the present application includes the display panel as described in any of the above embodiments.

[0144] In the above embodiments, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0145] The display panel and the display device provided in the embodiments of the present application are described in detail above, and the principle and implementation manner of the present application are described by applying specific examples in this paper, and the above embodiment is only used to help understand the technical solution and the core idea of the present application; the person skilled in the art should understand that: the technical solution recorded in the above embodiments can be modified, or some technical features can be replaced equivalently; and these modifications or replacements do not make the essence of the corresponding technical solution deviate from the scope of the technical solution of the embodiments of the present application.

Claims

1. A display panel, characterized in that: include: substrate; a driving circuit layer disposed on one side of the substrate, the driving circuit layer comprising a first active layer, the driving circuit layer further comprising a pixel driving circuit, the pixel driving circuit comprising a switching transistor, a driving transistor, a compensation transistor, and a first initialization transistor, the switching transistor and the driving transistor being connected at a first node; one electrode of the compensation transistor, one electrode of the first initialization transistor, and the driving transistor being connected at a second node, and the other electrode of the compensation transistor being connected to the driving transistor at a third node; In which, the first active layer includes an active pattern of the driving transistor and an active pattern of the switching transistor, the active pattern of the driving transistor is arranged along a first direction, and the active pattern of the switching transistor is arranged along a second direction. In the second direction, at least one pixel driving circuit is provided with at least one compensation hole, and the compensation hole is arranged on a side of the active pattern of the driving transistor close to the active pattern of the switching transistor, and the compensation hole does not overlap with the projection of the active pattern of the switching transistor on the substrate, so that the number of holes above the active pattern of the driving transistor is similar to the number of holes below the active pattern of the driving transistor, and the angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees.

2. The display panel according to claim 1, wherein The driving circuit layer further includes: a first gate insulating layer, disposed on a side of the first active layer away from the substrate; a second gate insulating layer, disposed on a side of the first gate insulating layer away from the first active layer; a first interlayer insulating layer, disposed on a side of the second gate insulating layer away from the first gate insulating layer; a third gate insulating layer, disposed on a side of the first interlayer insulating layer away from the second gate insulating layer; a second interlayer insulating layer, disposed on a side of the third gate insulating layer away from the first interlayer insulating layer; The compensation hole penetrates at least one of the first gate insulating layer, the second gate insulating layer, the first interlayer insulating layer, the third gate insulating layer and the second interlayer insulating layer.

3. The display panel according to claim 2, wherein: The pixel driving circuit also includes a storage capacitor, one plate of the storage capacitor is connected to the high-potential power line, and the other plate of the storage capacitor is connected to the gate of the driving transistor at a second node. The driving circuit layer also includes a first gate layer and a second gate layer. The first gate layer includes a first plate of the storage capacitor, and the second gate layer includes a second plate of the storage capacitor. The second plate of the storage capacitor is provided with a first connecting portion, and the projection of the first connecting portion on the substrate is located on the side of the active pattern of the driving transistor close to the active pattern of the switching transistor.

4. The display panel according to claim 3, wherein: The compensation hole penetrates the first interlayer insulating layer, the third gate insulating layer, and the second interlayer insulating layer, and the compensation hole is provided corresponding to the first connecting portion.

5. The display panel according to claim 4, wherein: The pixel driving circuit also includes a first light-emitting control transistor, and the driving circuit layer also includes a first source-drain layer. The first source-drain layer includes a first electrode and a second connecting portion of the first light-emitting control transistor. The projection of the second connecting portion and the first electrode of the first light-emitting control transistor on the substrate is located on both sides of the projection of the active pattern of the driving transistor on the substrate. The second connecting portion is connected to the first connecting portion through the compensation hole.

6. The display panel according to claim 5, wherein: The driving circuit layer further includes a second source-drain layer. The second source-drain layer includes a high-potential power line connected to the second connecting portion.

7. The display panel according to claim 2, wherein: The first active layer further includes a compensation active pattern, which is arranged on a side of the active pattern of the driving transistor close to the active pattern of the switching transistor, and a projection of the compensation active pattern on the substrate does not overlap with a projection of the active pattern of the switching transistor on the substrate.

8. The display panel according to claim 7, wherein: The gate of the switching transistor is connected to the first scanning signal line, the gate of the compensation transistor is connected to the second scanning signal line, and the gate of the first initialization transistor is connected to the third scanning signal line. The driving circuit layer also includes a first gate layer and a second gate layer. The first gate layer includes a first plate of a storage capacitor, and the second gate layer includes a first part of the second scanning signal line, a first part of the third scanning signal line and a second plate of the storage capacitor. The second plate of the storage capacitor is provided with a first connecting portion, and a projection of the first connecting portion on the substrate is located on a side of the projection of the active pattern of the driving transistor on the substrate away from the projection of the active pattern of the switching transistor on the substrate.

9. The display panel according to claim 8, wherein: The compensation hole penetrates the first gate insulating layer, the second gate insulating layer, the first interlayer insulating layer, the third gate insulating layer, and the second interlayer insulating layer, and the compensation hole is arranged corresponding to the compensation active pattern.

10. The display panel according to claim 9, wherein: A projection of the compensation hole on the substrate is located between a projection of the first portion of the second scan signal line on the substrate and a projection of the first portion of the third scan signal line on the substrate.

11. The display panel according to claim 10, wherein: The pixel driving circuit also includes a first light-emitting control transistor, and the driving circuit layer also includes a first source-drain layer. The first source-drain layer includes a first electrode and a third connection portion of the first light-emitting control transistor. The first electrode of the first light-emitting control transistor is connected to the first connection portion, and the third connection portion passes through the compensation hole and is connected to the compensation active pattern.

12. The display panel according to claim 11, wherein: The driving circuit layer further includes a second source-drain layer. The second source-drain layer includes a high-potential power line. The high-potential power line is connected to the third connection portion.

13. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 12.

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