Flip-chip LED chip and preparation method thereof

Abstract

The invention discloses a flip-chip LED chip and a preparation method thereof, and relates to the field of semiconductor photoelectric devices. The preparation method of the LED chip includes the following steps: S1, providing an epitaxial wafer; S2, forming a bonding layer; S3, bonding with a permanent substrate; S4, forming a first through hole; S5, forming a first P electrode in the first through hole to obtain an intermediate; wherein the first P electrode includes a first ohmic contact metal layer, a padding layer and a metal protection layer sequentially stacked on the P-type semiconductor layer; the height of the first P electrode is the same as the depth of the first through hole; S6, annealing; S7, simultaneously forming a first metal electrode layer and a second metal electrode layer on the N-type semiconductor layer and the metal protection layer, respectively, the first metal electrode layer and the second metal electrode layer both including a second ohmic contact metal layer and an etching barrier layer; S8, annealing; S9, forming a DBR layer, and etching to form a second through hole and a third through hole in the area where the first metal electrode layer and the second metal electrode layer are located; S10, forming an N electrode and a second P electrode; the N electrode is electrically connected to the first metal electrode layer through the second through hole, and the second P electrode is electrically connected to the first P electrode through the third through hole; the height of the N electrode and the second P electrode is the same; S11, cutting. The implementation of the present invention can improve the reliability of flip-chip LED chips.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor optoelectronic devices, and in particular to a flip-chip LED chip and a preparation method thereof. Background Art

[0002] As LED packaging continues to advance towards smaller size, higher power density, and better heat dissipation, flip chips with transparent substrates have become an important development direction for Mini-LED chips due to their advantages of no solder wires during packaging, high light extraction efficiency, small packaging size, and high reliability.

[0003] US Patent No. 7018859B2 discloses a flip-chip AlGaInP-based LED structure and manufacturing method based on a transparent substrate. The technical solution is as follows: growing an AlGaInP-based LED epitaxial wafer on a GaAs substrate, roughening the epitaxial wafer surface, bonding the epitaxial wafer to a transparent substrate using BCB, removing the GaAs substrate, etching out a P-type AlGaInP mesa, coating both the P-type AlGaInP mesa and the N-type AlGaInP surface with a metal reflective layer and a barrier layer, and finally fabricating P / N-type electrodes. Figure 1 There is a large height difference between the P-type electrode 200 and the N-type electrode 100. This height difference is not conducive to forming a good eutectic bond in the flip-chip LED chip solid crystal process. It is difficult to make the LED chip parallel to the bracket base. The chip is prone to tilting and forming a cold solder joint, which leads to a reduction in the shear force that the chip can withstand. As a result, when there is mechanical vibration or thermal expansion and contraction of the packaging colloid, the LED chip is at risk of falling off, breaking the circuit and causing the lamp to die.

[0004] In order to improve the problem of height difference between the P-electrode and the N-electrode, one way is to set only part of the P-type electrode 200 in the P-type area 400 and the rest in the light-emitting area 300. However, this design still has some recessed areas, which is still prone to cold solder joints, and the chip reliability is still low. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a flip-chip LED chip and a preparation method thereof, which can prevent the flip-chip LED chip from tilting during packaging, reduce cold solder joints, and improve the reliability of the chip.

[0006] In order to solve the above technical problems, the present invention provides a method for preparing a flip-chip LED chip, which specifically comprises the following steps:

[0007] S1. Providing an epitaxial wafer, wherein the epitaxial wafer includes a temporary substrate and an N-type semiconductor layer, an active layer, and a P-type semiconductor layer sequentially stacked on the temporary substrate;

[0008] S2, forming a bonding layer on the P-type semiconductor layer;

[0009] S3, bonding the epitaxial wafer obtained in step S2 to a permanent substrate, and removing the temporary substrate;

[0010] S4, forming a first through hole, wherein the first through hole is etched to the P-type semiconductor layer;

[0011] S5. Forming a first P-electrode in the first through-hole to obtain an intermediate; wherein the first P-electrode comprises a first ohmic contact metal layer, a spacer layer, and a metal protection layer sequentially stacked on the P-type semiconductor layer; and the height of the first P-electrode is the same as the depth of the first through-hole;

[0012] S6, annealing the intermediate obtained in step S5, so that the first ohmic contact metal layer forms an ohmic contact with the P-type semiconductor layer;

[0013] S7. Simultaneously forming a first metal electrode layer and a second metal electrode layer on the N-type semiconductor layer and the metal protection layer, respectively, wherein the first metal electrode layer and the second metal electrode layer both include a second ohmic contact metal layer and an etching stop layer;

[0014] S8, annealing the intermediate obtained in step S7, so that the second ohmic contact metal layer of the first metal electrode layer forms an ohmic contact with the N-type semiconductor layer;

[0015] S9, forming a DBR layer on the intermediate obtained in step S8, and etching to form a second through hole and a third through hole in the area where the first metal electrode layer and the second metal electrode layer are located;

[0016] S10, forming an N electrode and a second P electrode to obtain an LED wafer; wherein the N electrode is electrically connected to the first metal electrode layer through the second through hole, and the second P electrode is electrically connected to the first P electrode through the third through hole; and the N electrode and the second P electrode have the same height;

[0017] S11, cutting the LED wafer to obtain flip-chip LED chips.

[0018] As an improvement of the above technical solution, the first ohmic contact metal layer is one or more of an Au layer, an AuBe layer or an AuZn layer, and has a thickness of 0.5 μm to 1 μm; and / or

[0019] The cushioning layer is one or more of a Ti layer, an Al layer, a Ni layer, a Cr layer, a TiW layer, and an AlCu layer, and has a thickness of 3 μm to 5 μm;

[0020] The metal protective layer is a Pt layer and / or an Au layer, and its thickness is 1 μm to 4 μm; and / or

[0021] The second ohmic contact metal layer is one or more of an Au layer, a Ni layer, an AuGe layer or an AuGeNi layer, and has a thickness of 0.5 μm to 1 μm; and / or

[0022] The etching stop layer is one or more of a Ti layer, a Pt layer, a TiW layer, and a Ni layer, and has a thickness of 0.5 μm to 3 μm; and / or

[0023] The bonding layer is an Al2O3 layer and / or a SiO2 layer, and its thickness is 500nm to 3000nm.

[0024] As an improvement of the above technical solution, the first ohmic contact metal layer is an Au layer or an AuBe layer, and its thickness is 0.5 μm to 0.8 μm; and / or

[0025] The cushioning layer is a stacked structure consisting of a Ti layer and an Al layer, and its thickness is 4 μm to 5 μm;

[0026] The metal protective layer is a Pt layer and / or an Au layer, and its thickness is 1 μm to 3 μm; and / or

[0027] The second ohmic contact metal layer is an Au layer or an AuGeNi layer, and its thickness is 0.5 μm to 0.8 μm; and / or

[0028] The etching stop layer is a Ti layer or a TiW layer, and its thickness is 1 μm to 2 μm; and / or

[0029] The bonding layer is a SiO2 layer with a thickness of 500nm to 1000nm.

[0030] As an improvement to the above technical solution, the sidewall of the first through hole is inclined, and the inclination angle thereof is ≤70°; and / or

[0031] The first P-electrode is in a prism shape, with a sidewall inclination angle of ≤70°, and the metal protection layer covers the first ohmic contact metal layer and the padding layer.

[0032] As an improvement of the above technical solution, in step S6, the annealing temperature is 300°C to 550°C;

[0033] In step S8, the annealing temperature is 300°C to 400°C.

[0034] As an improvement of the above technical solution, the N-type semiconductor layer includes an N-type GaAs ohmic contact layer, an N-type AlGaInP current spreading layer and an N-type AlGaInP confinement layer sequentially stacked on the substrate; and / or

[0035] The P-type semiconductor layer includes a P-type AlGaInP confinement layer and a P-type GaP window layer sequentially stacked on the active layer; and / or

[0036] A GaAs buffer layer and a GaInP etching stop layer are sequentially provided between the temporary substrate and the N-type semiconductor layer; and / or

[0037] The temporary substrate is a GaAs substrate; and / or

[0038] The permanent substrate is a sapphire substrate, a silicon substrate or a silicon carbide substrate; and / or

[0039] The N electrode and the second P electrode have the same or different compositions, and both are stacked structures formed by at least two of a Cr layer, a Ti layer, an Al layer, a Ni layer, an Au layer, and a Pt layer.

[0040] As an improvement to the above technical solution, step S2 includes:

[0041] S21, roughening the P-type GaP window layer;

[0042] S22 , forming a bonding layer on the roughened P-type GaP window layer.

[0043] As an improvement to the above technical solution, step S3 includes:

[0044] S31, bonding the epitaxial wafer obtained in step S2 to a permanent substrate;

[0045] S32, removing the temporary substrate, the GaAs buffer layer and the GaInP etching stop layer.

[0046] As an improvement to the above technical solution, step S8 includes:

[0047] S81, using the first metal electrode layer as a mask, etching and removing the N-type GaAs ohmic contact layer around the first metal electrode layer;

[0048] S82, etching to form an etched groove that is etched to the permanent substrate;

[0049] S83 , annealing the intermediate obtained in step S82 so that the second ohmic contact metal layer of the first metal electrode layer forms an ohmic contact with the N-type GaAs ohmic contact layer.

[0050] Correspondingly, the present invention also discloses a flip-chip LED chip, which includes a permanent substrate, a bonding layer, a P-type semiconductor layer, an active layer, an N-type semiconductor layer, a first metal electrode layer, a DBR layer and an N-electrode sequentially stacked on the back of the permanent substrate;

[0051] The first metal electrode layer includes a second ohmic contact metal layer and an etch stop layer sequentially stacked on the N-type semiconductor layer; the second ohmic contact metal layer forms an ohmic contact with the N-type semiconductor layer through annealing; the N electrode is provided on the DBR layer and is electrically connected to the first metal electrode layer through a second through hole provided in the DBR layer;

[0052] The flip-chip LED chip further includes a first through-hole etched into the P-type semiconductor layer, a first P-electrode provided in the first through-hole, a second metal layer and a second P-electrode provided on the first P-electrode; the DBR layer covers the sidewalls and bottom of the first through-hole and the first P-electrode and the second metal electrode layer; the second P-electrode is provided on the DBR layer and is electrically connected to the first P-electrode via a third through-hole provided in the DBR layer; the third through-hole is provided above the second metal electrode layer;

[0053] The first P-electrode includes a first ohmic contact metal layer, a spacer layer, and a metal protection layer sequentially stacked on the P-type semiconductor layer, wherein the first ohmic contact metal layer forms an ohmic contact with the P-type semiconductor layer through annealing; the height of the first P-electrode is the same as the depth of the first through-hole; the second metal electrode layer includes a second ohmic contact metal layer and an etch stop layer sequentially stacked on the metal protection layer;

[0054] The N-electrode and the second P-electrode have the same height.

[0055] The implementation of the present invention has the following beneficial effects:

[0056] 1. In the method for preparing a flip-chip LED chip of the present invention, a first ohmic contact metal layer, a spacer layer, and a metal protective layer are sequentially stacked during the preparation of the first P-electrode, ensuring that the height of the first P-electrode is the same as the depth of the first through-hole. Subsequently, a first metal electrode layer and a second metal electrode layer of identical composition and height are formed on the surfaces of the N-type semiconductor layer and the metal protective layer, as well as a fully covered DBR layer, an N-electrode, and a first P-electrode of equal height. This ensures that the N-electrode and the first P-electrode are of equal height, thereby alleviating the problems of conventional flip-chip LED chips prone to side tilting and solder joint defects and improving the reliability of the flip-chip LED chip. Furthermore, both the first and second metal electrode layers of the present invention include an etch stop layer, which ensures that the underlying electrode structure is not damaged during etching of the DBR layer and lays a good foundation for achieving equal electrode heights.

[0057] 2. During the preparation of the flip-chip LED chip of the present invention, the first through hole and the first P electrode both adopt an inclined sidewall structure, which can effectively prevent cracks in the DBR layer from causing chip failure, thereby improving reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] Figure 1 This is a schematic diagram of the structure of a flip-chip LED chip in the prior art;

[0059] Figure 2 This is a schematic diagram of the structure of another flip-chip LED chip in the prior art;

[0060] Figure 3 1 is a schematic structural diagram of an epitaxial wafer in one embodiment of the present invention;

[0061] Figure 4 This is a schematic structural diagram of a flip-chip LED chip according to an embodiment of the present invention;

[0062] Figure 5 1 is a schematic diagram of a top view of a flip-chip LED chip according to an embodiment of the present invention;

[0063] In the figure, 100 is an N-type electrode, 200 is a P-type electrode, 300 is a light-emitting area, 400 is a P-type area, 1 is an epitaxial wafer, 11 is a temporary substrate, 12 is an N-type semiconductor layer, 121 is an N-type GaAs ohmic contact layer, 122 is an N-type AlGaInP current spreading layer, 123 is an N-type AlGaInP confinement layer, 13 is an active layer, 14 is a P-type semiconductor layer, 141 is a P-type AlGaInP confinement layer, 142 is a P-type GaP window layer, and 15 is a GaAs ohmic contact layer. As buffer layer, 16 is GaInP corrosion stop layer, 17 is preset area, 2 is bonding layer, 3 is permanent substrate, 4 is first through hole, 5 is first P electrode, 51 is first ohmic contact metal layer, 52 is padding layer, 53 is metal protection layer, 61 is first metal electrode layer, 62 is second metal electrode layer, 63 is second ohmic contact metal layer, 64 is etching barrier layer, 7 is DBR layer, 71 is second through hole, 72 is third through hole, 8 is N electrode, 9 is second P electrode. DETAILED DESCRIPTION

[0064] In order to make the objectives, technical solutions and advantages of the present invention more clear, the present invention is described in further detail below.

[0065] The present invention provides a method for preparing a horizontal structure LED chip, which comprises the following steps:

[0066] S1: Provide epitaxial wafers;

[0067] See also Figure 3The epitaxial wafer 1 includes a temporary substrate 11, and an N-type semiconductor layer 12, an active layer 13, and a P-type semiconductor layer 14 sequentially arranged on the temporary substrate 11. Specifically, the LED chip of the present invention can be a red, green, yellow, or violet LED chip. Based on the control of the emission wavelength, different types of semiconductor layers and active layers can be selected. For example, in one embodiment, when the LED chip is a blue LED chip or a green LED chip, the N-type semiconductor layer 12 can be an N-type GaN layer, the active layer 13 can be an InGaN-GaN type multi-quantum well layer, and the P-type semiconductor layer 14 can be a P-type GaN layer and a P-type InGaN layer, but is not limited thereto. In another embodiment, when the LED chip is a violet LED chip, the N-type semiconductor layer 12 can be an N-type AlGaN layer, the active layer 13 can be an AlGaN-AlGaN type multi-quantum well layer, and the P-type semiconductor layer 14 can be a P-type AlGaN layer and a P-type GaN layer, but is not limited thereto.

[0068] Preferably, in one embodiment, the LED chip is a red LED chip, and the epitaxial wafer 1 includes a GaAs buffer layer 15, a GaInP etching stop layer 16, an N-type semiconductor layer 12, an active layer 13, and a P-type semiconductor layer 14, which are sequentially disposed on a temporary substrate 11. Temporary substrate 11 is a GaAs substrate. The N-type semiconductor layer 12 includes an N-type GaAs ohmic contact layer 121, an N-type AlGaInP current spreading layer 122, and an N-type AlGaInP confinement layer 123, which are sequentially disposed on the GaInP etching stop layer 16. The P-type semiconductor layer 14 includes a P-type AlGaInP confinement layer 141 and a P-type GaP window layer 142, which are sequentially stacked on the active layer 13. The following steps are described using a red LED chip, but the technical solutions of the present invention are not limited to the red LED chip described herein.

[0069] S2: forming a bonding layer on the P-type semiconductor layer;

[0070] Depending on the subsequent bonding process, the bonding layer 2 can be formed of different materials. For example, when a eutectic bonding process is used, an Au layer, a Cu layer, an In layer, a Pb layer, or a Sn layer can be used, but the material is not limited thereto. For another example, when a hot compression bonding process is used, an Au layer, a Cu layer, an Ag layer, or an Al layer can be used as the bonding layer 2, but the material is not limited thereto.

[0071] Preferably, in one embodiment, a thermal compression bonding process is used, and the bonding layer 2 can be an Al2O3 layer and / or a SiO2 layer, which not only achieves good bonding but also improves light extraction efficiency. Specifically, the thickness of the bonding layer 2 is 500nm to 3000nm. More preferably, the bonding layer 2 is a SiO2 layer with a thickness of 500nm to 1000nm.

[0072] Preferably, in one embodiment, when the flip-chip LED chip is a red LED chip, step S2 includes:

[0073] S21: roughening the P-type GaP window layer;

[0074] S22: forming a bonding layer on the roughened P-type GaP window layer.

[0075] Roughening the P-type GaP window layer 142 can, firstly, remove impurities on the surface of the P-type GaP window layer 142 and improve the crystal quality of subsequent layers. Secondly, it can enhance the adhesion between the bonding layer 2 and the P-type GaP window layer 142. Thirdly, it can improve light extraction efficiency.

[0076] S3: bonding the epitaxial wafer obtained in step S2 to a permanent substrate;

[0077] The epitaxial wafer and the permanent substrate 3 may be bonded by eutectic bonding, thermocompression bonding, or other bonding methods, but are not limited thereto. Preferably, thermocompression bonding is employed. The bonding temperature is 360° C. to 550° C., and the bonding pressure is 8,000 kgf to 15,000 kgf.

[0078] The permanent substrate 3 may be a sapphire substrate, a silicon substrate or a silicon carbide substrate, but is not limited thereto, and is preferably a sapphire substrate.

[0079] Specifically, after bonding, the temporary substrate 11 is peeled off. The temporary substrate 11 may be peeled off by laser peeling, wet etching or other methods, but is not limited thereto.

[0080] Preferably, in one embodiment, when the flip-chip LED chip is a red LED chip, step S3 includes:

[0081] S31: bonding the epitaxial wafer obtained in step S2 to a permanent substrate;

[0082] S32: removing the temporary substrate, the GaAs buffer layer and the GaInP etching stop layer.

[0083] S4: forming a first through hole;

[0084] Specifically, the first through hole 4 can be formed by dry or wet etching. The depth of the first through hole 4 is greater than the combined thickness of the N-type semiconductor layer 12 and the active layer 13, so that the first P-electrode 5 forms a good ohmic contact with the P-type semiconductor layer 14. Preferably, in one embodiment, the sidewalls of the first through hole 4 are inclined, with an inclination angle of ≤70°. The inclined sidewalls can improve the tightness of the subsequent DBR layer 7 and prevent cracks. Preferably, the inclination angle is 50° to 60°. If the inclination angle is too small, the light-emitting area will be reduced, thereby reducing the light-emitting efficiency.

[0085] S5: forming a first P electrode in the first through hole to obtain an intermediate;

[0086] The first P-electrode 5 can be formed by evaporation, sputtering, etc., but is not limited thereto. Preferably, in one embodiment, the first P-electrode 5 is formed by photolithography, evaporation, and lift-off processes.

[0087] Specifically, the first P electrode 5 includes a first ohmic contact metal layer 51, a padding layer 52 and a metal protective layer 53 stacked in sequence on the P-type semiconductor layer 14. By introducing the padding layer 52 and the metal protective layer 53, the height of the first P electrode 5 can be increased to the same depth as the first through hole 4, laying the foundation for the subsequent N electrode 8 and the second P electrode 9 to be at the same height. The metal protective layer 53 can prevent the padding layer 52 from collapsing during the annealing process, affecting the height.

[0088] Specifically, the first ohmic contact metal layer 51 is one or more of, but not limited to, an Au layer, an AuBe layer, or an AuZn layer. The first ohmic contact metal layer 51 can form a good ohmic contact with the P-type semiconductor layer 14. Preferably, the first ohmic contact metal layer 51 is an Au layer or an AuBe layer. Specifically, the thickness of the first ohmic contact metal layer 51 is 0.5 μm to 1 μm, preferably 0.5 μm to 0.8 μm.

[0089] Specifically, the padding layer 52 is one or more of, but not limited to, a Ti layer, an Al layer, a Ni layer, a Cr layer, a TiW layer, and an AlCu layer. Preferably, the padding layer 52 is a stacked structure consisting of a Ti layer and an Al layer. Specifically, the padding layer 52 has a thickness of 3 μm to 5 μm, preferably 4 μm to 5 μm.

[0090] Specifically, the metal protective layer 53 is a Pt layer and / or an Au layer, which has good fluidity and can form a good wrapping around the first ohmic contact metal layer 51 and the padding layer 52, thereby providing protection. Specifically, the thickness of the metal protective layer 53 is 1 μm to 4 μm, preferably 1 μm to 3 μm.

[0091] The first P-electrode 5 is shaped like a prism, a cylinder, or a prism, but is not limited thereto. Preferably, in one embodiment, the first P-electrode 5 is shaped like a prism, with its sidewalls tilted at an angle of ≤70°, so that the metal protection layer 53 can better cover the first ohmic contact metal layer 51 and the spacer layer 52. More preferably, the sidewalls of the first P-electrode 5 have a tilt angle of 50° to 60°.

[0092] S6: annealing the intermediate obtained in step S5;

[0093] Annealing can form a good ohmic contact between the first ohmic contact metal layer 51 and the P-type semiconductor layer 14. Specifically, the annealing temperature is 300°C to 550°C, preferably 450°C to 500°C.

[0094] S7: simultaneously forming a first metal electrode layer and a second metal electrode layer on the N-type semiconductor layer and the metal protection layer respectively;

[0095] The first metal electrode layer 61 and the second metal electrode layer 62 can be formed by evaporation, sputtering, or other processes, but are not limited thereto. Preferably, in one embodiment, the first metal electrode layer 61 and the second metal electrode layer 62 are formed by photolithography, evaporation, and lift-off processes.

[0096] Specifically, the first metal electrode layer 61 and the second metal electrode layer 62 each include a second ohmic contact metal layer 63 and an etch stop layer 64 stacked in sequence. The second ohmic contact metal layer 63 can form a good ohmic contact with the N-type semiconductor layer 12, and the etch stop layer 64 can provide a good barrier during the subsequent etching of the DBR layer 7, allowing the DBR layer 7 to be completely etched and prevented from affecting the height of the N-electrode 8 and the second P-electrode 9.

[0097] Specifically, the second ohmic contact metal layer 63 is one or more of, but not limited to, an Au layer, a Ni layer, an AuGe layer, or an AuGeNi layer. The second ohmic contact metal layer 63 can form a good ohmic contact with the N-type semiconductor layer 12. Preferably, the second ohmic contact metal layer 63 is an Au layer or an AuGeNi layer. Specifically, the thickness of the second ohmic contact metal layer 63 is 0.5 μm to 1 μm, preferably 0.5 μm to 0.8 μm.

[0098] Specifically, the etch stop layer 64 is one or more of, but not limited to, a Ti layer, a Pt layer, a TiW layer, and a Ni layer. Preferably, it is a Ti layer or a TiW layer. Specifically, the thickness of the etch stop layer is 0.5 μm to 3 μm, preferably 1 μm to 2 μm.

[0099] S8: annealing the intermediate obtained in step S7;

[0100] Annealing can form a good ohmic contact between the second ohmic contact metal layer 63 and the N-type semiconductor layer 12. Specifically, the annealing temperature is 300°C to 400°C, preferably 300°C to 380°C.

[0101] Preferably, in one embodiment of the present invention, when the flip-chip LED chip is a red LED chip, step S8 includes:

[0102] S81: Using the first metal electrode layer as a mask, etching and removing the N-type GaAs ohmic contact layer around the first metal electrode layer;

[0103] Specifically, etching and removing the N-type GaAs ohmic contact layer can reduce its light absorption, so that more light is reflected by the DBR layer 7, thereby improving the luminous efficiency.

[0104] S82: etching to form an etched groove that is etched to the permanent substrate;

[0105] Specifically, through the etched groove (not shown in the figure), electrical insulation between multiple flip-chip LED chips can be achieved through the DBR layer 7.

[0106] S83: Annealing the intermediate obtained in step S82.

[0107] S9: forming a DBR layer on the intermediate obtained in step S8, and etching to form a second through hole and a third through hole in the area where the first metal electrode layer and the second metal electrode layer are located;

[0108] Specifically, the DBR layer 7 can be formed by MOCVD or PECVD, but is not limited thereto. The DBR layer 7 covers the entire surface of the intermediate body, which can achieve light reflection on the one hand and form passivation protection on the other hand.

[0109] Specifically, the DBR layer 7 can be etched by a dry etching process or a wet etching process to form the second through hole 71 and the third through hole 72. Since the present invention forms an etching stopper layer 64, the underlying structure is not damaged during the etching process, so complete etching can be achieved, laying a good foundation for equal-height electrodes.

[0110] S10: forming an N electrode and a second P electrode to obtain an LED wafer;

[0111] Specifically, the N electrode 8 and the second P electrode 9 can be formed by evaporation, sputtering, etc., but are not limited thereto. Preferably, in one embodiment, the N electrode 8 and the second P electrode 9 are formed by photolithography, evaporation, and lift-off processes.

[0112] The specific compositions of the N-electrode 8 and the second P-electrode 9 are the same or different. Preferably, they are the same, so that the N-electrode 8 and the second P-electrode 9 can be formed through a single evaporation process, thereby improving efficiency.

[0113] Specifically, both the N electrode 8 and the second P electrode 9 are stacked structures formed of at least two of a Cr layer, a Ti layer, an Al layer, a Ni layer, an Au layer, and a Pt layer, but the present invention is not limited thereto.

[0114] Specifically, the N-electrode 8 is electrically connected to the first metal electrode layer 61 through the second through hole 71 , and the second P-electrode 9 is electrically connected to the first P-electrode 5 through the third through hole 72 .

[0115] S11: cutting the LED wafer to obtain flip-chip LED chips;

[0116] Specifically, the permanent substrate is first ground and thinned, and then laser cut and split to obtain the flip-chip LED chip.

[0117] Correspondingly, the present invention also discloses a flip-chip LED chip, see Figure 4 and Figure 5 , which includes a permanent substrate 3, a bonding layer 2, a P-type semiconductor layer 14, an active layer 13, an N-type semiconductor layer 12, a first metal electrode layer 61, a DBR layer 7 and an N-electrode 8 sequentially stacked on the back side of the permanent substrate 3;

[0118] The first metal electrode layer 61 includes a second ohmic contact metal layer 63 and an etch stop layer 64 sequentially stacked on the N-type semiconductor layer 12; the second ohmic contact metal layer 63 forms an ohmic contact with the N-type semiconductor layer 12 through annealing; the N-electrode 8 is provided on the DBR layer 7 above the first metal electrode layer 61 and is electrically connected to the first metal electrode layer 61 through a second through hole 71 provided in the DBR layer 7;

[0119] The flip-chip LED chip further includes a first through hole 4 etched into the P-type semiconductor layer 14, a first P-electrode 5 disposed in the first through hole 4, a second metal electrode layer 62 disposed on the first P-electrode 5, and a second P-electrode 9; the N-electrode 8 and the second P-electrode 9 have the same height;

[0120] The first P-electrode 5 includes a first ohmic contact metal layer 51, a padding layer 52 and a metal protective layer 53 sequentially stacked on the P-type semiconductor layer 14, and the first ohmic contact metal layer 51 forms an ohmic contact with the P-type semiconductor layer 14 through annealing; the height of the first P-electrode 5 is the same as the depth of the first through hole 4; the second metal electrode layer 62 includes a second ohmic contact metal layer 63 and an etching barrier layer 64 sequentially stacked on the metal protective layer 53.

[0121] The DBR layer 7 covers the sidewalls and bottom of the first through-hole 4, as well as the first P-electrode 5 and the second metal electrode layer 62. The second P-electrode 9 is provided on the DBR layer 7 and is electrically connected to the first P-electrode 5 via a third through-hole 72 provided in the DBR layer 7. The third through-hole 72 is provided above the second metal electrode layer 62. The flip-chip LED chip based on this structure ensures that the N-electrode and the first P-electrode are at the same height, improving the problems of tilting and solder joint defects that are common in traditional flip-chip LED chips and enhancing the reliability of the flip-chip LED chip.

[0122] The above is a preferred embodiment of the invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the invention. These improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A method for preparing a flip-chip LED chip, characterized in that: The following steps are involved: S1. Providing an epitaxial wafer, wherein the epitaxial wafer includes a temporary substrate and an N-type semiconductor layer, an active layer, and a P-type semiconductor layer sequentially stacked on the temporary substrate; S2, forming a bonding layer on the P-type semiconductor layer; S3, bonding the epitaxial wafer obtained in step S2 to a permanent substrate, and removing the temporary substrate; S4, forming a first through hole, wherein the first through hole is etched to the P-type semiconductor layer; S5. Forming a first P-electrode in the first through-hole to obtain an intermediate; wherein the first P-electrode comprises a first ohmic contact metal layer, a spacer layer, and a metal protection layer sequentially stacked on the P-type semiconductor layer; and the height of the first P-electrode is the same as the depth of the first through-hole; S6, annealing the intermediate obtained in step S5, so that the first ohmic contact metal layer forms an ohmic contact with the P-type semiconductor layer; S7. Simultaneously forming a first metal electrode layer and a second metal electrode layer on the N-type semiconductor layer and the metal protection layer, respectively, wherein the first metal electrode layer and the second metal electrode layer both include a second ohmic contact metal layer and an etching stop layer; S8, annealing the intermediate obtained in step S7, so that the second ohmic contact metal layer of the first metal electrode layer forms an ohmic contact with the N-type semiconductor layer; S9, forming a DBR layer on the intermediate obtained in step S8, and etching to form a second through hole and a third through hole in the area where the first metal electrode layer and the second metal electrode layer are located; S10, forming an N electrode and a second P electrode to obtain an LED wafer; wherein the N electrode is electrically connected to the first metal electrode layer through the second through hole, and the second P electrode is electrically connected to the first P electrode through the third through hole; and the N electrode and the second P electrode have the same height; S11, cutting the LED wafer to obtain flip-chip LED chips.

2. The method for preparing a flip-chip LED chip according to claim 1, wherein: The first ohmic contact metal layer is one or more of an Au layer, an AuBe layer or an AuZn layer, and has a thickness of 0.5 μm to 1 μm; The cushioning layer is one or more of a Ti layer, an Al layer, a Ni layer, a Cr layer, a TiW layer, and an AlCu layer, and has a thickness of 3 μm to 5 μm; The metal protective layer is a Pt layer and / or an Au layer, and its thickness is 1 μm to 4 μm; The second ohmic contact metal layer is one or more of an Au layer, a Ni layer, an AuGe layer or an AuGeNi layer, and has a thickness of 0.5 μm to 1 μm; The etching stop layer is one or more of a Ti layer, a Pt layer, a TiW layer, and a Ni layer, and has a thickness of 0.5 μm to 3 μm; The bonding layer is an Al2O3 layer and / or a SiO2 layer, and its thickness is 500nm~3000nm.

3. The method for preparing a flip-chip LED chip according to claim 1 or 2, wherein: The first ohmic contact metal layer is an Au layer or an AuBe layer, and its thickness is 0.5 μm to 0.8 μm; The cushioning layer is a stacked structure consisting of a Ti layer and an Al layer, and its thickness is 4 μm to 5 μm; The metal protective layer is a Pt layer and / or an Au layer, and its thickness is 1 μm to 3 μm; The second ohmic contact metal layer is an Au layer or an AuGeNi layer, and its thickness is 0.5 μm to 0.8 μm; The etching stop layer is a Ti layer or a TiW layer, and its thickness is 1 μm to 2 μm; The bonding layer is a SiO2 layer with a thickness of 500nm-1000nm.

4. The method for preparing a flip-chip LED chip according to claim 1, wherein: The sidewall of the first through hole is inclined, and the inclination angle thereof is ≤70°; and / or The first P-electrode is in a prism shape, with a sidewall inclination angle of ≤70°, and the metal protection layer covers the first ohmic contact metal layer and the padding layer.

5. The method for preparing a flip-chip LED chip according to claim 1, wherein: In step S6, the annealing temperature is 300°C to 550°C; In step S8, the annealing temperature is 300°C to 400°C.

6. The method for preparing a flip-chip LED chip according to claim 1, wherein: The N-type semiconductor layer includes an N-type GaAs ohmic contact layer, an N-type AlGaInP current spreading layer and an N-type AlGaInP confinement layer sequentially stacked on the substrate; The P-type semiconductor layer includes a P-type AlGaInP confinement layer and a P-type GaP window layer sequentially stacked on the active layer; A GaAs buffer layer and a GaInP etching stop layer are sequentially provided between the temporary substrate and the N-type semiconductor layer; The temporary substrate is a GaAs substrate; The permanent substrate is a sapphire substrate, a silicon substrate or a silicon carbide substrate; The N electrode and the second P electrode are both stacked structures formed by at least two of a Cr layer, a Ti layer, an Al layer, a Ni layer, an Au layer, and a Pt layer.

7. The method for preparing a flip-chip LED chip according to claim 6, wherein: Step S2 includes: S21, roughening the P-type GaP window layer; S22 , forming a bonding layer on the roughened P-type GaP window layer.

8. The method for preparing a flip-chip LED chip according to claim 6, wherein: Step S3 includes: S31, bonding the epitaxial wafer obtained in step S2 to a permanent substrate; S32, removing the temporary substrate, the GaAs buffer layer and the GaInP etching stop layer.

9. The method for preparing a flip-chip LED chip according to claim 6, wherein: Step S8 includes: S81, using the first metal electrode layer as a mask, etching and removing the N-type GaAs ohmic contact layer around the first metal electrode layer; S82, etching to form an etched groove that is etched to the permanent substrate; S83 , annealing the intermediate obtained in step S82 so that the second ohmic contact metal layer of the first metal electrode layer forms an ohmic contact with the N-type GaAs ohmic contact layer.

10. A flip-chip LED chip, characterized in that: It includes a permanent substrate, a bonding layer, a P-type semiconductor layer, an active layer, an N-type semiconductor layer, a first metal electrode layer, a DBR layer and an N-electrode sequentially stacked on the back of the permanent substrate; The first metal electrode layer includes a second ohmic contact metal layer and an etch stop layer sequentially stacked on the N-type semiconductor layer; the second ohmic contact metal layer forms an ohmic contact with the N-type semiconductor layer through annealing; the N electrode is provided on the DBR layer and is electrically connected to the first metal electrode layer through a second through hole provided in the DBR layer; The flip-chip LED chip further includes a first through-hole etched into the P-type semiconductor layer, a first P-electrode provided in the first through-hole, a second metal electrode layer and a second P-electrode provided on the first P-electrode; the DBR layer covers the sidewalls and bottom of the first through-hole and the first P-electrode and the second metal electrode layer; the second P-electrode is provided on the DBR layer and is electrically connected to the first P-electrode via a third through-hole provided in the DBR layer; the third through-hole is provided above the second metal electrode layer; The first P-electrode includes a first ohmic contact metal layer, a spacer layer, and a metal protection layer sequentially stacked on the P-type semiconductor layer, wherein the first ohmic contact metal layer forms an ohmic contact with the P-type semiconductor layer through annealing; the height of the first P-electrode is the same as the depth of the first through-hole; the second metal electrode layer includes a second ohmic contact metal layer and an etch stop layer sequentially stacked on the metal protection layer; The N-electrode and the second P-electrode have the same height.

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