Adaptive process layer data dynamic detection and identification method

Abstract

The present invention relates to the field of digital information transmission technology, and in particular to an adaptive process layer data dynamic detection and identification method, comprising the following steps: (S1) firstly generating a configuration file for a device to be tested; (S2) dividing into SV sending, GOOSE sending and GOOSE receiving according to the needs of the device to be tested, and dividing into different processing modes according to different needs. The method has the technical effects of low cost, sufficient number of optical ports, convenient matching of interfaces and tooling, and high degree of automation.

Description

Technical Field

[0001] The present invention relates to the technical field of digital information transmission, and in particular to a method for dynamic detection and identification of adaptive process layer data. Background Art

[0002] At present, smart substations and new generation high-reliability substations have been widely promoted, and the detection of process layer data, which is the core data of protection and measurement and control devices, must be completed entirely by digital testers. Digital testers have many disadvantages, such as: (1) high cost, the price of ordinary digital relay protection testers is about 200,000 yuan; (2) small number of optical ports, ordinary digital relay protection testers can only provide eight optical ports, which cannot meet the requirement of 24 optical ports for the device under test; (3) difficult to match the interface with the detection system. During the automatic detection work, the system needs to retrieve and process the information reflecting the test results. The tester cannot automatically retrieve and match, and the corresponding configuration needs to be manually modified; (4) the degree of automation is low, which cannot meet the needs of automatic testing.

[0003] Based on this, a new method needs to be designed to replace the digital tester to complete the detection of data layer data. Summary of the Invention

[0004] In order to overcome the deficiencies in the prior art, the present invention provides an adaptive process layer data dynamic detection and identification method.

[0005] To achieve the above objectives, the present invention discloses an adaptive process layer data dynamic detection and identification method, comprising the following steps:

[0006] (S1) Connecting the device under test to the acquisition execution unit module in the adaptive process layer data dynamic monitoring and identification system through virtual terminals, generating a CCD configuration file for the device under test and the acquisition execution unit module, importing the configuration file into the tooling configuration tool module, and the tooling configuration tool module confirms the configuration information required for the test and generates an XML configuration file.

[0007] (S2) When the automatic test starts, the XML configuration file generated in step (S1) is imported into the adaptive process layer data dynamic detection and identification system, the CPU of the execution unit module parses the XML configuration file transmitted by the tooling configuration tool module, and stores each data set information according to the state sequence; according to the needs of the device under test, it is divided into SV sending, GOOSE sending and GOOSE receiving; if the need of the device under test is SV sending, jump to step (S3); if the need of the device under test is GOOSE sending, jump to step (S4); if the need of the device under test is GOOSE receiving, jump to step (S5).

[0008] (S3) In terms of the SV sending function, the FPGA module of the acquisition and execution unit module allocates two memory blocks, namely FPGA memory A and FPGA memory B, to store the control block information of the two SV state sequences. The CPU of the acquisition and execution unit module initially sends the contents of the two state sequences as well as the enable flag and timer trigger time of the timer trigger to the FPGA module. The timer trigger function is only for state sequence 1. The FPGA module forms a sine wave based on the waveform amplitude, frequency, and phase in the data set sent by the CPU to form a high-quality SV message. At the same time, based on the initial and final values ​​of the amplitude, it determines whether it is necessary to complete the power data transition according to the step size and step time. Then, according to the timed trigger time, an SV message is output from a specific network port. After the state duration expires, the SV message for the next state sequence is output. If the duration reaches 0, the current state is maintained. If there are two or more state sequences, after the FPGA completes processing the second sequence, it sends a CAN network interrupt to the CPU. Upon receiving the interrupt, the CPU sends the configuration information for state sequence 3 to FPGA memory A. After the FPGA control sends the contents of state sequence 3, it continues to send CAN network interrupts to the CPU. The CPU sends the configuration information for state sequence 4 to FPGA memory B, and so on, until the state persists in the last state sequence. At the same time, the tooling configuration tool detects and records in real time the DUT's related SV reception anomalies and the series of DUT actions caused by the digital values ​​of the SV messages sent by the execution unit module, thereby verifying the normal functioning of the DUT.

[0009] (S4) In the GOOSE transmission function, the FPGA module of the acquisition and execution unit module allocates a block of memory, defined as FPGA memory C, to store the control information for the GOOSE state sequence. When the telesignaling, telemetry, and other information in the state sequence changes, the CPU will package the GOOSE message according to the control block information and the change in the CCD file. At the same time, the GOOSE destination MAC address, network card output configuration, and state duration of the current state sequence will be sent to the FPGA. The FPGA will output the above GOOSE message from the specific network card according to the configuration sent by the CPU. When the state duration is 0, the current sequence is maintained. If it is not 0, the CAN network interrupt will continue to call the CPU for new state sequence content and perform the GOOSE message transmission function until the state continues in the last state sequence. At the same time, the tooling configuration tool module will detect GOOSE reception anomalies of the device under test in real time, as well as a series of actions of the device under test caused by changes in the telesignaling, telemetry, and other content in the GOOSE messages sent by the acquisition and execution unit module, and record them, thereby detecting whether the relevant functions of the device under test are normal.

[0010] (S5) In terms of the GOOSE receiving function, the FPGA module of the acquisition execution unit module allocates a piece of memory, defined as FPGA memory D, to store GOOSE receiving related information. The CPU determines the data set information to be received through the CCD file. The CPU sends the destination MAC address, APPID, and receiving port information of the first data set to the FPGA to receive the GOOSE message of the device under test. After a delay of 25 seconds, the CPU searches the GOOSE reception of the acquisition execution unit module to determine whether the GOOSE reception anomalies such as broken links have been eliminated to determine whether the reception is successful. At the same time, the result is returned to the tooling configuration tool module for recording, thereby detecting whether the GOOSE sending function of the relevant optical port of the device under test is normal. Then, it is determined whether data set 1 has multiple ports for reception. If so, the CPU sends the destination MAC address, APPID, and second receiving port information of the first data set to the FPGA. After a delay of 25 seconds, the result is judged and recorded. If not, the CPU performs the same processing on the second data set until all data set information is transmitted.

[0011] Preferably, the configuration information confirmed by the tooling configuration tool module in step (S1) includes the number of state sequences, the duration of the state sequence, the timing trigger enable and time, the data set module selection, the message output network port sequence number, and the data set content.

[0012] The present invention has the following technical effects:

[0013] (1) A sufficient number of optical ports. Due to the automation requirements of the detection process, optical ports can only be connected one-to-one through optical fibers. An ordinary digital relay protection tester can only provide 8 optical ports, which cannot meet the detection requirements of the maximum 24 optical ports required by the device under test. The acquisition execution unit module of the present invention can provide 24 optical ports for automatic identification and detection, which can basically meet the requirements of all types of test devices.

[0014] (2) The interface is easy to match with the tooling. During the automatic testing process, the system needs to retrieve and process the information reflecting the test results. The acquisition execution unit module in the present invention can provide an interface to adapt to the automatic testing tooling.

[0015] (3) High degree of automation

[0016] The detection system of the present invention can meet the needs of one-key adaptive recognition and detection. With only one instruction, it can automatically complete the automatic recognition and detection of the device function according to the detection steps and content without any human operation.

[0017] (4) The unique processing method of the integrated execution unit saves space loss and has strong applicability. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1This is the structural principle diagram of the adaptive process layer data dynamic monitoring and identification system;

[0019] Figure 2 Send a flow chart for SV;

[0020] Figure 3 Send a flow chart to GOOSE;

[0021] Figure 4 This is a schematic diagram of the GOOSE receiving process. DETAILED DESCRIPTION

[0022] The following is combined with Figure 1 To the attached Figure 4 The principles and features of the present invention are described, and the examples given are only used to explain the present invention and are not used to limit the scope of the present invention.

[0023] An adaptive process layer data dynamic detection and identification method comprises the following steps:

[0024] (S1) Connect the device to be tested to the acquisition execution unit module in the adaptive process layer data dynamic monitoring and identification system through virtual terminals, generate a CCD configuration file for the device to be tested and the acquisition execution unit module, import the configuration file into the tooling configuration tool module, the tooling configuration tool module confirms the configuration information required for the test and generates an XML configuration file; the configuration information confirmed by the tooling configuration tool module includes the number of state sequences, state sequence duration, timing trigger enable and time, data set module selection, message output network port serial number, data set content, etc.

[0025] (S2) When the automatic test starts, the XML configuration file generated in step (S1) is imported into the adaptive process layer data dynamic detection and identification system, the CPU of the execution unit module parses the XML configuration file transmitted by the tooling configuration tool module, and stores each data set information according to the state sequence; according to the needs of the device under test, it is divided into SV sending, GOOSE sending and GOOSE receiving; if the need of the device under test is SV sending, jump to step (S3); if the need of the device under test is GOOSE sending, jump to step (S4); if the need of the device under test is GOOSE receiving, jump to step (S5).

[0026] (S3) In the SV sending function, the FPGA module of the acquisition execution unit module allocates two memories, defining FPGA memory A and FPGA memory B respectively, which are used to store the control block information of the two SV state sequences. The CPU of the acquisition execution unit module initially sends the contents of the two state sequences and the enable flag and timing trigger time of the timing trigger to the FPGA module. The timing trigger function is only for state sequence 1; the FPGA module forms a sine wave according to the waveform amplitude, frequency, and phase in the data set sent by the CPU to form a high-quality SV message. At the same time, it determines whether it is necessary to complete the transition of the power data according to the step size and step time based on the initial and final values ​​of the amplitude, and then outputs the SV message from the specific network port according to the timing trigger time. After the state duration, it outputs the next state sequence. SV message, when the duration is 0, the current state is maintained; if the number of state sequences is more than two, after the FPGA processes the second sequence, it will send a CAN network interrupt to the CPU. After receiving the interrupt, the CPU will send the configuration information of state sequence 3 to FPGA memory A. When the FPGA control sends the content of state sequence 3, it will continue to send CAN network interrupts to the CPU. The CPU will send the configuration information of state sequence 4 to FPGA memory B, and so on, until the state continues in the last state sequence; the tooling configuration tool module will retrieve the SV reception abnormality information related to the device under test in real time, and collect a series of actions of the device under test caused by the digital quantity of the SV message sent by the execution unit module, and record them, so as to detect whether the relevant functions of the device under test are normal.

[0027] The SV sending control block configuration information is shown in Table 1, the SV sending data configuration information is shown in Table 2, and the SV timing trigger function configuration information is shown in Table 3. Among them, the SV sending data configuration content: each control block can support up to 48 sending data (excluding rated delay), and each sending data needs to be configured separately.

[0028] Table 1SV sends control block configuration information

[0029] Serial number Data Item Data Type 1 Status duration 4 bytes (unsigned) 2 Destination MAC address 6 bytes (unsigned) 3 APPID 2 bytes (unsigned) 4 DataNum 2 bytes (unsigned) 5 smvID_len 2 bytes (unsigned) 6 smvID 64 bytes (string) 7 ConfRev 2 bytes (unsigned) 8 Number of Asdu 2 bytes (unsigned) 9 DelayTime 2 bytes (unsigned) 10 priority_o,vid 2 bytes (unsigned)

[0030] Table 2 Sending data configuration information

[0031]

[0032]

[0033] Table 3SV timing trigger function configuration information

[0034] Serial number Data Item Data Type 1 Scheduled sending enable 1 byte (unsigned) 2 Second 1 byte (unsigned) 3 point 1 byte (unsigned) 4 hour 1 byte (unsigned)

[0035] (S4) For the GOOSE transmission function, the FPGA module of the acquisition and execution unit module allocates a block of memory, designated as FPGA memory C, to store control information for the GOOSE state sequence. When telesignaling, telemetry, and other information within the state sequence changes, the CPU packages the GOOSE message based on the control block information and the change in the CCD file. Simultaneously, the FPGA sends the GOOSE destination MAC address, network card output configuration, and state duration for the current state sequence to the FPGA. The FPGA then outputs the GOOSE message from the specified network card based on the configuration sent by the CPU. If the state duration is 0, the current sequence remains. If not, the CAN network interrupt continues to request new state sequence content from the CPU, performing the GOOSE message transmission function until the state remains in the last state sequence. The tooling configuration tool searches for GOOSE reception anomalies in the device under test in real time, as well as the series of actions of the device under test caused by changes in telesignaling, telemetry, and other content within the GOOSE messages sent by the acquisition and execution unit module, and records these information to verify that the relevant functions of the device under test are functioning properly. Table 4 shows the GOOSE transmission block configuration information.

[0036] Table 4 GOOSE sending block configuration information

[0037]

[0038]

[0039] (S5) For the GOOSE reception function, the FPGA module of the acquisition and execution unit module allocates a block of memory, defined as FPGA memory D, to store GOOSE reception-related information. The CPU determines the data set information to be received through the CCD file. The CPU sends the destination MAC address, APPID, and receiving port information of the first data set to the FPGA to receive the GOOSE message sent by the device under test. After a 25-second delay, the CPU checks whether the GOOSE reception of the acquisition and execution unit module has eliminated GOOSE reception anomalies such as link breakage to determine whether reception is successful. The result is returned to the tool configuration tool module for recording, thereby verifying the normal GOOSE transmission function of the relevant optical port of the device under test. It then determines whether data set 1 has multiple ports for reception. If so, the CPU sends the destination MAC address, APPID, and second receiving port information of the first data set to the FPGA. After a 25-second delay, the CPU determines and records the result. If not, the CPU performs the same process for the second data set until all data set information is transmitted. The GOOSE reception control block configuration information is shown in Table 5.

[0040] Table 5 GOOSE receiving control block configuration information

[0041] Serial number Data Item Data Type 1 GOOSE receiving destination MAC 1-64 6 bytes (unsigned) 2 APPID 1-64 2 bytes (unsigned) 3 Strobe Configuration 1-64 4 bytes (unsigned) 4 Accept configuration end flag 1 byte (unsigned)

[0042] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. An adaptive process layer data dynamic detection and identification method, characterized in that: The following steps are involved: (S1) connecting the device under test to the acquisition execution unit module in the adaptive process layer data dynamic monitoring and identification system through virtual terminals, generating a CCD configuration file for the device under test and the acquisition execution unit module, importing the configuration file into the tooling configuration tool module, the tooling configuration tool module confirms the configuration information required for the test, and generates an XML configuration file; (S2) When the automatic test starts, the XML configuration file generated in step (S1) is imported into the adaptive process layer data dynamic detection and identification system, the XML configuration file transmitted by the CPU parsing tool configuration tool module of the execution unit module is collected, and each data set information is stored according to the state sequence; according to the needs of the device under test, it is divided into SV sending, GOOSE sending and GOOSE receiving; if the demand of the device under test is SV sending, jump to step (S3); if the demand of the device under test is GOOSE sending, jump to step (S4); if the demand of the device under test is GOOSE receiving, jump to step (S5); (S3) In the SV sending function, the FPGA module of the acquisition execution unit module allocates two memories, defining FPGA memory A and FPGA memory B respectively, which are used to store the control block information of the two SV state sequences. The CPU of the acquisition execution unit module initially sends the contents of the two state sequences and the enable flag and timing trigger time of the timing trigger to the FPGA module. The timing trigger function is only for state sequence 1; the FPGA module forms a sine wave according to the waveform amplitude, frequency, and phase in the data set sent by the CPU to form a high-quality SV message. At the same time, according to the initial and final values ​​of the amplitude, it determines whether it is necessary to complete the change of the power data according to the step length and step time, and then outputs the SV message from the specific network port according to the timing trigger time. After the state duration, the next state sequence is output. SV message, when the duration is 0, the current state is maintained; if the number of state sequences is more than two, after the FPGA processes the second sequence, it will send a CAN network interrupt to the CPU. After the CPU receives the interrupt, it will send the configuration information of state sequence 3 to FPGA memory A. When the FPGA control sends the content of state sequence 3, it will continue to send CAN network interrupts to the CPU. The CPU will send the configuration information of state sequence 4 to FPGA memory B, and so on, until the state continues in the last state sequence; the tooling configuration tool module will retrieve the SV reception abnormal information related to the device under test in real time, and collect a series of actions of the device under test caused by the digital quantity of the SV message sent by the execution unit module, and record them, so as to detect whether the relevant functions of the device under test are normal; (S4) In the GOOSE sending function, the FPGA module of the acquisition execution unit module allocates a memory, defined as FPGA memory C, to store the control information of the GOOSE sending state sequence. When the telesignaling and telemetry information in the state sequence changes, the CPU will package the GOOSE message according to the control block information and the change in the CCD file, and at the same time send the GOOSE sending destination MAC address, network card output configuration and state duration of the current state sequence to the FPGA. The FPGA will output the above GOOSE message from a specific network card according to the configuration sent by the CPU. When the state duration is 0, it remains in the current sequence. If it is not 0, it will continue to call the new state sequence content to the CPU through the CAN network interrupt, and perform the GOOSE message sending function until the state continues in the last state sequence. At the same time, the tooling configuration tool module will retrieve the GOOSE reception abnormality of the device under test in real time, as well as a series of actions of the device under test caused by a series of telesignaling and telemetry content changes in the GOOSE message sent by the acquisition execution unit module, and record them, so as to detect whether the relevant functions of the device under test are normal; (S5) In the GOOSE receiving function, the FPGA module of the acquisition execution unit module allocates a piece of memory, defined as FPGA memory D, to store GOOSE receiving related information. The CPU determines the data set information to be received through the CCD file. The CPU sends the destination MAC address, APPID and receiving port information of the first data set to the FPGA to receive the GOOSE message sent by the device under test. After a delay of 25 seconds, the acquisition execution unit module GOOSE reception is retrieved to determine whether the broken GOOSE reception abnormality is eliminated to determine whether the reception is successful. At the same time, the result is returned to the tooling configuration tool module for recording, so as to detect whether the GOOSE function of the relevant optical port of the device under test is normal; then determine whether data set 1 has multiple ports for receiving. If so, the CPU sends the destination MAC address, APPID and second receiving port information of the first data set to the FPGA. After a delay of 25 seconds, the result is judged and recorded. If not, the CPU performs the same processing on the second data set until all data set information is transmitted.

2. The adaptive process layer data dynamic detection and identification method according to claim 1 is characterized in that: In step (S1), the configuration information confirmed by the tooling configuration tool module includes the number of state sequences, the duration of the state sequence, the timing trigger enable and time, the data set module selection, the message output network port number, and the data set content.

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