Semiconductor structure, memory and method for manufacturing memory

Abstract

Embodiments of the present disclosure relate to the semiconductor field and provide a semiconductor structure, memory, and memory manufacturing method. The semiconductor structure includes a transistor, including a gate structure and a first source / drain region, a first lightly doped region, a channel region, a second lightly doped region, and a second source / drain region arranged sequentially in a first direction; in a second direction, opposite sides of the first lightly doped region and the second lightly doped region are both protruded relative to opposite sides of the channel region, the first source / drain region, and the second source / drain region; the gate structure is located between the protruding first lightly doped region and the second lightly doped region, and on opposite sides of the channel region in the second direction; the first direction intersects the second direction. Embodiments of the present disclosure can at least improve the performance of the semiconductor structure.

Description

Technical Field

[0001] The present disclosure belongs to the field of semiconductors, and particularly relates to a semiconductor structure, a memory, and a method for manufacturing the memory. Background Art

[0002] 3D memory, which consists of multiple layers of stacked transistors, can effectively increase memory integration and storage capacity. However, as transistor size continues to shrink, hot carrier effects and short channel effects are becoming increasingly important factors affecting device reliability.

[0003] Therefore, a new type of semiconductor structure and memory is urgently needed to avoid hot carrier effects and short channel effects, thereby ensuring device performance. Summary of the Invention

[0004] The embodiments of the present disclosure provide a semiconductor structure that is at least beneficial in improving the performance of the semiconductor structure.

[0005] According to some embodiments of the present disclosure, on one hand, an embodiment of the present disclosure provides a semiconductor structure, wherein the semiconductor structure includes: a transistor, including: a gate structure and a first source and drain region, a first lightly doped region, a channel region, a second lightly doped region and a second source and drain region arranged in sequence in a first direction; in a second direction, the relative sides of the first lightly doped region and the second lightly doped region are both protruding relative to the relative sides of the channel region, the first source and drain region and the second source and drain region; the gate structure is located between the protruding first lightly doped region and the second lightly doped region, and is located on the relative sides of the channel region in the second direction; the first direction intersects with the second direction.

[0006] According to some embodiments of the present disclosure, on the other hand, embodiments of the present disclosure further provide a memory, the memory including the aforementioned semiconductor structure, and the memory also including: a substrate, the substrate having a plurality of transistor groups arranged in the second direction, the transistor group including a plurality of transistors arranged in a third direction; a plurality of the gate structures of the same transistor group are connected and extend along the third direction; a support structure, including a first supporting structure and a second supporting structure connected, the first supporting structure being located between adjacent transistor groups, and being arranged relative to the first lightly doped region, the second lightly doped region and the gate structure in the second direction; the second supporting structure being located between adjacent first lightly doped regions arranged in the third direction, and also between adjacent second lightly doped regions arranged in the third direction; the first direction and the second direction are both parallel to the upper surface of the substrate, and the third direction is perpendicular to the upper surface of the substrate.

[0007] According to some embodiments of the present disclosure, another aspect of the present disclosure further provides a method for manufacturing a memory, the manufacturing method comprising: providing a substrate; forming a plurality of active groups arranged in a second direction on the substrate; the active groups comprising a plurality of active structures arranged in a third direction, the active structures comprising a first active structure, a second active structure, a third active structure, a fourth active structure and a fifth active structure arranged in sequence in the first direction; in the second direction, the second active structure and the fourth active structure have opposite sides that are protruding relative to the first active structure, the third active structure and the fifth active structure; forming a supporting structure on the substrate, the supporting structure comprising a first supporting structure and a second supporting structure connected to each other. structure, the first supporting structure is located between adjacent active groups and is arranged opposite to the second active structure to the fourth active structure; the second supporting structure is located between adjacent second active structures arranged in the third direction, and is also located between adjacent fourth active structures arranged in the third direction; the active structures are doped so that the first active structure to the fifth active structure are respectively transformed into a first source and drain region, a first lightly doped region, a channel region, a second lightly doped region and a second source and drain region; a gate structure extending in the third direction is formed, the gate structure is located between the first lightly doped region and the second lightly doped region protruding in the second direction, and is located on opposite sides of the channel region in the second direction.

[0008] The technical solution provided by the embodiments of the present disclosure has at least the following advantages: a first lightly doped region and a second lightly doped region are added on opposite sides of the channel region along the first direction, and the first lightly doped region and the second lightly doped region can suppress the short channel effect and the hot carrier effect. In addition, in the second direction, the opposite sides of the first lightly doped region and the second lightly doped region are both protruded relative to the opposite sides of the channel region and the first source and drain region and the second source and drain region, and the gate structure is located between the protruding first lightly doped region and the second lightly doped region. Therefore, the first lightly doped region and the second lightly doped region have a larger width in the second direction, which is beneficial to reducing the series resistance between the first source and drain region and the second source and drain region. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0010] Figure 1 A local top view of a semiconductor structure provided by an embodiment of the present disclosure is shown.

[0011] Figure 2 A three-dimensional diagram of a semiconductor structure provided by an embodiment of the present disclosure is shown.

[0012] Figure 3-Figure 19 A structural schematic diagram corresponding to each step in a method for manufacturing a memory provided in another embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0013] As the background technology indicates, as transistor size continues to shrink, hot carrier effects and short channel effects are increasingly becoming significant factors affecting device reliability. While a lightly doped drain (LDD) structure can suppress these two effects to a certain extent, the width of the LDD structure is typically less than or equal to the width of the first and second source / drain regions. Consequently, the LDD's resistance is relatively high, affecting the series resistance between the first and second source / drain regions, leading to degradation of the semiconductor structure's electrical performance.

[0014] An embodiment of the present disclosure provides a semiconductor structure including a transistor, wherein opposite sides of a first lightly doped region and a second lightly doped region are both protruded relative to opposite sides of a channel region and a first source / drain region and a second source / drain region in a second direction; and a gate structure is located between the protruding first and second lightly doped regions. In other words, the widths of the first and second lightly doped regions in the second direction are greater than the widths of the channel region and the first and second source / drain regions in the second direction. This facilitates reducing the resistance of the first and second lightly doped regions, thereby reducing the series resistance between the first and second source / drain regions.

[0015] The following describes various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to help readers better understand the embodiments of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the embodiments of the present disclosure can be implemented.

[0016] refer to Figure 1-Figure 2 The semiconductor structure includes a transistor T, which includes a gate structure 7 and a first source / drain region SD1, a first lightly doped region L1, a channel region C, a second lightly doped region L2, and a second source / drain region SD2 arranged in sequence in a first direction X. In a second direction Y, opposite sides of the first lightly doped region L1 and the second lightly doped region L2 are protruded relative to opposite sides of the channel region C, the first source / drain region SD1, and the second source / drain region SD2. The gate structure 7 is located between the protruding first lightly doped region L1 and the second lightly doped region L2, and is located on opposite sides of the channel region C in the second direction Y. The first direction X intersects the second direction Y.

[0017] For example, the first direction X may be perpendicular to or close to the second direction Y. Figure 2 The semiconductor structure may further include a third direction Z, and the third direction Z may be perpendicular to both the first direction X and the second direction Y.

[0018] refer to Figure 1-Figure 2 The gate structure 7 includes a gate dielectric layer 72 and a gate layer 71. The gate dielectric layer 72 covers the sidewalls of the gate layer 71 facing the channel region C, the first lightly doped region L1, and the second lightly doped region L2. In some embodiments, the material of the gate layer 71 may include a conductive material such as tungsten, titanium, or polysilicon. Figure 1 The gate dielectric layer 72 may be a double-layer structure, for example, including a silicon oxide layer 721 and a high dielectric constant material layer 722, and the high dielectric constant material layer 722 may include at least one of zirconium oxide, aluminum oxide, or niobium oxide. Figure 2 The gate dielectric layer 72 may also be a single-layer structure, for example, including a silicon oxide layer 721 or a high dielectric constant material layer 722 .

[0019] refer to Figure 1-Figure 2 The widths of the first source / drain region SD1, the second source / drain region SD2, and the channel region C in the second direction Y may be equal, which can improve the uniformity of the semiconductor structure, reduce the series resistance between the first source / drain region SD1 and the second source / drain region SD2, and simplify the production process.

[0020] refer to Figure 1-Figure 2 The width of the first lightly doped region L1 in the second direction Y is equal to the total width of the channel region C and the gate structure 7 in the second direction Y, and the width of the second lightly doped region L2 in the second direction Y is equal to the total width of the channel region C and the gate structure 7 in the second direction Y. This simplifies the production process and fully utilizes the spatial position of the gate structure 7 on two opposite sides in the first direction X, ensuring that the first lightly doped region L1 and the second lightly doped region L2 have a large width in the second direction Y. At the same time, the opposite sides of the first lightly doped region L1 and the second lightly doped region L2 in the second direction Y are flush with the opposite sides of the gate structure 7 in the second direction Y, avoiding space waste.

[0021] In some embodiments, the first source / drain region SD1, the second source / drain region SD2, the side of the first lightly doped region L1 facing the first source / drain region SD1, and the side of the second lightly doped region L2 facing the second source / drain region SD2 all have first conductivity type dopant ions. The channel region C, the side of the first lightly doped region L1 facing the channel region C, and the side of the second lightly doped region L2 facing the channel region C all have second conductivity type dopant ions.

[0022] For example, the first conductivity type dopant ions are N-type, such as phosphorus, arsenic, antimony, etc. The second conductivity type dopant ions are P-type, such as boron, aluminum, and gallium. In other embodiments, the first conductivity type dopant ions may also be P-type, and the second conductivity type dopant ions may also be N-type.

[0023] In other embodiments, the first lightly doped region L1 and the second lightly doped region L2 may have only one conductive type of doping ions, for example, the conductive type of the doping ions in the two regions is the same as the conductive type of the doping ions in the first source / drain region SD1 and the second source / drain region SD2.

[0024] In the direction from the first source and drain region SD1 to the channel region C, the concentration of the first conductive type doped ions in the first lightly doped region L1 gradually decreases, and the concentration of the second conductive type doped ions in the first lightly doped region L1 gradually increases; in the direction from the second source and drain region SD2 to the channel region C, the concentration of the first conductive type doped ions in the second lightly doped region L2 gradually decreases, and the concentration of the second conductive type doped ions in the second lightly doped region L2 gradually increases.

[0025] A graded junction may be formed at the first lightly doped region L1 and the second lightly doped region L2. Compared to an abrupt junction, a graded junction can reduce the on-resistance of the transistor, reduce the threshold voltage, and improve the control capability of the gate structure 7. For example, the concentration of the first conductive type dopant ions in the first source / drain region SD1 and the second source / drain region SD2 is 7.5E20 / cm 3 ~8.5E20 / cm 3 , for example 8E20 / cm 3 The concentration of the second conductivity type doping ions in the channel region C is 1.5E20 / cm 3 ~2.5E20 / cm 3 , for example 2E20 / cm 3 .

[0026] The concentration of the first conductive type dopant ions on the side of the first lightly doped region L1 facing the first source / drain region SD1 is lower than the concentration of the first conductive type dopant ions in the first source / drain region SD1, for example, lower than 8.5E20 / cm 3 The concentration of the first conductive type dopant ions on the side of the second lightly doped region L2 facing the second source / drain region SD2 is lower than the doping concentration of the second source / drain region SD2, for example, lower than 8.5E20 / cm 3 The concentration of the second conductive type dopant ions on the side of the first lightly doped region L1 facing the channel region C and the concentration of the second conductive type dopant ions on the side of the second lightly doped region L2 facing the channel region C are both lower than the doping concentration of the channel region C, for example, lower than 2.5E20 / cm 3 .

[0027] When the concentrations of the first source and drain region SD1, the channel region C, the first lightly doped region L1, the second lightly doped region L2 and the second source and drain region SD2 are within the above range, it is beneficial to improve the breakdown voltage and can also ensure that the on-resistance between the first source and drain region SD1 and the second source and drain region SD2 remains within a small range.

[0028] refer to Figure 1-Figure 2 The length of the first lightly doped region L1 in the first direction X is shorter than the lengths of the first source and drain regions SD1, the second source and drain regions SD2, and the channel region C in the first direction X. The length of the second lightly doped region L2 in the first direction X is shorter than the lengths of the first source and drain regions SD1, the second source and drain regions SD2, and the channel region C in the first direction X. The shorter lengths of the first and second lightly doped regions L1 and L2 help reduce the series resistance between the first and second source and drain regions SD1 and SD2, thereby preventing performance degradation of the semiconductor structure.

[0029] In summary, the first lightly doped region L1 and the second lightly doped region L2 can improve the hot carrier effect and the short channel effect, and their larger width in the second direction Y is conducive to reducing the series resistance between the first source and drain region SD1 and the second source and drain region SD2, thereby ensuring the performance of the semiconductor structure.

[0030] Another embodiment of the present disclosure further provides a memory, which includes the semiconductor structure in the aforementioned embodiment. For detailed description of the semiconductor structure, reference may be made to the aforementioned embodiment.

[0031] refer to Figure 2 The memory also includes: a substrate 1, on which are provided a plurality of transistor groups T0 arranged in a second direction Y, the transistor group T0 including a plurality of transistors T arranged in a third direction Z; a plurality of gate structures 7 of the same transistor group T0 are connected and extend along the third direction Z; a support structure 5, including a first support structure 51 and a second support structure 52 connected to each other, the first support structure 51 being located between adjacent transistor groups T0 and being arranged opposite to the first lightly doped region L1, the second lightly doped region L2 and the gate structure 7 in the second direction Y; the second support structure 52 being located between adjacent first lightly doped regions L1 arranged in the third direction Z, and also between adjacent second lightly doped regions L2 arranged in the third direction Z; the first direction X and the second direction Y are both parallel to the upper surface of the substrate 1, and the third direction Z is perpendicular to the upper surface of the substrate 1.

[0032] That is to say, the memory is a 3D memory, which includes multiple layers of transistors T. The support structure 5 can support and isolate the multiple layers of transistors T. Among them, the first support structure 51 isolates the first lightly doped region L1, the gate structure 7 and the second lightly doped region L2 of the adjacent transistor group T0 in the second direction Y. The second support structure 52 mainly plays the role of supporting the first lightly doped region L1 and the second lightly doped region L2, and can also isolate the two adjacent layers of the first lightly doped region L1 and the two adjacent layers of the second lightly doped region L2 in the third direction Z. In addition, since the first support structure 51 and the second support structure 52 are connected, the first support structure 51 can also provide a supporting force to the first lightly doped region L1 and the second lightly doped region L2 through the second support structure 52, thereby improving the stability of the memory.

[0033] For example, the material of the support structure 5 can be an insulating material such as silicon nitride, silicon oxynitride, or silicon carbonitride. The first support structure 51 and the second support structure 52 can be an integrated structure, that is, they can be formed in the same process step. In this way, the two have a greater connection strength, which can improve the reliability of the memory.

[0034] Continue to refer Figure 2 The memory further includes: a plurality of bit lines 82 arranged in a third direction Z, the bit lines 82 extending along the second direction Y and connected to the plurality of first source and drain regions SD1 in the second direction Y. The memory further includes: a plurality of capacitors 81, the capacitors 81 being connected to the second source and drain regions SD2. Among them, a capacitor 81 and a transistor T can constitute a basic memory cell, and the word line and the bit line 82 can control the read and write process of the memory cell. The material of the bit line 82 can be tungsten, titanium, copper, or other metals. The capacitor 81 includes an upper electrode, a lower electrode, and a dielectric layer, wherein the lower electrode is in contact with the second source and drain region SD2.

[0035] The memory further includes a third isolation structure 64, which is located between two adjacent layers of transistors T and is used to isolate the transistors T in a third direction Z. The memory further includes a second isolation structure 66 (refer to Figure 19 ), the second isolation structure 66 is located between the first source and drain regions SD1 adjacent to each other in the second direction Y, and is also located between the second source and drain regions SD2 adjacent to each other in the second direction Y. In order to illustrate the memory more clearly, Figure 2 The second isolation structure 66 is not shown.

[0036] In summary, the disclosed embodiment utilizes the space on opposite sides of the gate structure 7 in the first direction X to extend the lengths of the first lightly doped region L1 and the second lightly doped region L2, and disposes the second support structure 52 there. This simplifies the support structure 5 while ensuring good electrical performance of the transistor T.

[0037] Another embodiment of the present disclosure further provides a method for manufacturing a memory, which can be used to manufacture the memory provided by the aforementioned embodiment. For detailed description of the memory, please refer to the aforementioned embodiment and will not be repeated here.

[0038] refer to Figure 3 A substrate 1 is provided, and multiple layers of alternating sacrificial layers 41 and active layers 20 are formed on the substrate 1. For example, the substrate 1 may be made of silicon, the active layers 20 may be made of the same material as the substrate 1, and the sacrificial layers 41 may be made of silicon germanium. The sacrificial layers 41 and the active layers 20 may be formed by an epitaxial growth process.

[0039] The semiconductor structure may include a sixth region f, a first region a, a second region b, a third region c, a fourth region d, and a fifth region e sequentially arranged in the first direction X.

[0040] refer to Figure 4 A first mask layer 31 and a second mask layer 32 are stacked on the active layer 20 and the sacrificial layer 41. For example, the first mask layer 31 may be made of silicon oxide or silicon oxynitride, and the second mask layer 32 may be made of silicon nitride or silicon carbide. The first and second mask layers 31 and 32 may be formed using a chemical vapor deposition process. A double mask layer improves the accuracy of subsequent pattern transfer. In other embodiments, a single mask layer may be used.

[0041] refer to Figure 5 The active layer 20 and sacrificial layer 41 are subjected to a first patterning process. Specifically, the first mask layer 31 and the second mask layer 32 are etched, and the patterns of the first mask layer 31 and the second mask layer 32 are transferred to the active layer 20 and the sacrificial layer 41. This means that portions of the active layer 20 and the sacrificial layer 41 in the first region a, the third region c, and the fifth region e are etched away, leaving the remaining active layer 20 and the sacrificial layer 41 in a grid pattern. The remaining active layer 20 in the sixth region f, the second region b, and the fourth region d extends along the second direction Y. The remaining active layer 20 in the first region a, the third region c, and the fifth region e extends along the first direction X, and the active layers 20 in these three regions are also spaced apart in the second direction Y. In this way, the active layers 20 in the first region a to the sixth region f can be arranged in an intersecting pattern, thereby forming a grid area. The orthographic projections of the sacrificial layer 41 and the active layer 20 on the substrate 1 are the same.

[0042] refer to Figure 6 A filling layer 61 is formed in the first region a, the third region c, and the fifth region e. That is, the filling layer 61 is located where the portions of the active layer 20 and the sacrificial layer 41 were removed during the first patterning process. For example, a chemical vapor deposition process is used to deposit silicon oxide as the filling layer 61 in the grid area surrounded by the remaining active layer 20 and the remaining sacrificial layer 41.

[0043] Figure 8 Shown Figure 7 The top view of the active structure 2 in FIG. Figure 7-Figure 8 A second patterning process is performed to form an isolation trench 68 extending through the active layer 20, the sacrificial layer 41, and the filling layer 61 in the third direction Z. The isolation trench 68 divides the active layer 20 into the active structure 2 and the sacrificial layer 41 into the sacrificial structure 42. The isolation trench 68 also extends in the first direction X and is located from the second region b to the fourth region d. Exemplarily, a dry etching process is used to form the isolation trench 68.

[0044] The active structure 2 includes a first active structure 21, a second active structure 22, a third active structure 23, a fourth active structure 24, and a fifth active structure 25 arranged in sequence in the first direction X. The active structure 2 may further include a sixth active structure 26, which is located in the sixth region f and extends in the second direction Y. The sixth active structure 26 will be removed later to form the bit line 82. In other embodiments, the sixth active structure 26 may not be formed.

[0045] Continue to refer Figure 8 The sacrificial structures 42 and the active structures 2 are alternately arranged in the third direction Z, and the orthographic projections of the sacrificial structures 42 and the active structures 2 on the substrate 1 coincide with each other.

[0046] So far, based on Figure 3-Figure 8 The steps shown can form a plurality of active groups 200 arranged in the second direction Y on the substrate 1; the active group 200 includes a plurality of active structures 2 arranged in the third direction Z; in the second direction Y, the opposing sides of the second active structure 22 and the fourth active structure 24 are both protruding relative to the opposing sides of the first active structure 21, the third active structure 23, and the fifth active structure 25. It should be noted that performing a double patterning process on the active layer 20 can improve patterning accuracy and ensure that the active structure 2 has a good morphology. In other embodiments, the active layer 20 can be directly patterned once to form the active structure 2.

[0047] refer to Figure 9 , the sacrificial structures 42 between the adjacent second active structures 22 in the third direction Z, and the sacrificial structures 42 between the adjacent fourth active structures 24 in the third direction Z are removed. That is, the sacrificial structures 42 in the second region b and the fourth region d are removed. For example, a wet etching process is used to remove the sacrificial structures 42 in the aforementioned positions. In other embodiments, the sacrificial structures 42 in the second region b and the fourth region d may not be completely removed. For example, only the sacrificial structures 42 in the second region b and the fourth region d that protrude relative to the first active structure 21 in the second direction Y are removed, and the sacrificial structures 42 that do not protrude may be removed together with the sacrificial structures 42 in the subsequent first region a, the third region c, and the fifth region e.

[0048] During the process of removing part of the sacrificial structure 42 , the filling layer 61 can support the second active structure 22 and the fourth active structure 24 to avoid collapse.

[0049] refer to Figure 10 , a support structure 5 is formed on the substrate 1, and the support structure 5 includes a first support structure 51 and a second support structure 52 connected (refer to Figure 11 ), the first support structure 51 is located between adjacent active groups 200 and is disposed opposite the second through fourth active structures 22, 24; the second support structure 52 is located between adjacent second active structures 22 arranged in the third direction Z, and is also located between adjacent fourth active structures 24 arranged in the third direction Z. In other words, the second support structure 52 is located where the sacrificial structures 42 have been removed, and the first support structure 51 is filled in the isolation trench 68.

[0050] For example, a chemical vapor deposition process is used to deposit insulating materials such as silicon nitride and silicon oxynitride as the support structure 5 .

[0051] refer to Figure 11 , the filling layer 61 is removed to expose the sacrificial structure 42. For example, the filling layer 61 is removed by a wet etching process.

[0052] refer to Figure 12 , remove the remaining sacrificial structures 42. Specifically, the sacrificial structures 42 in the first region a, the third region c, the fifth region e, and the sixth region f are removed. During the removal of the remaining sacrificial structures 42, the support structure 5 can support the active structure 2 and prevent the active structure 2 from collapsing. For example, a wet etching process is used to remove the remaining sacrificial structures 42.

[0053] In addition, since the second active structure 22 and the fourth active structure 24 are protruding relative to the first active structure 21, the third active structure 23 and the fifth active structure 25 in the second direction Y, there is a large spacing between adjacent first active structures 21, adjacent third active structures 23 and adjacent fifth active structures 25 in the second direction Y, thereby providing a larger process window for removing the remaining sacrificial structure 42, thereby reducing residues and improving removal efficiency.

[0054] refer to Figure 13Insulating materials such as silicon oxide or silicon oxycarbide are deposited using a chemical vapor deposition process in the first region a, the third region c, the fifth region e, and the sixth region f to form initial isolation structures 62. Part of the initial isolation structure 62 is located between adjacent first active structures 21 in the second direction Y, between adjacent third active structures 23 in the second direction Y, and between adjacent fifth active structures 25 in the second direction Y. Part of the initial isolation structure 62 is located between adjacent active structures 2 in the third direction Z.

[0055] It should be noted that the material of the initial isolation structure 62 can be different from that of the support structure 5, because a portion of the initial isolation structure 62 will be removed later. Using different materials can avoid damaging the support structure 5, thereby providing the support structure 5 with a better morphology. For example, the support structure 5 can be made of a harder material, which will make etching of the support structure 5 more difficult and help improve the stability of the support.

[0056] refer to Figure 14 , a portion of the initial isolation structure 62 between the adjacent first active structures 21 in the second direction Y and a portion of the initial isolation structure 62 between the adjacent fifth active structures 25 in the second direction Y are removed. The remaining initial isolation structures 62 between the adjacent third active structures 23 in the second direction Y serve as first isolation structures 65. The remaining initial isolation structures 62 between the adjacent active structures 2 in the third direction Z serve as third isolation structures 64.

[0057] So far, based on Figure 13-14 In the steps shown, a first isolation structure 65 can be formed between the third active structure 23 and the first support structure 51. The first isolation structure 65 is also located between the second active structure 22 and the fourth active structure 24 that protrude in the second direction Y. Furthermore, the first isolation structure 65 can be formed between adjacent third active structures 23 in the second direction Y. In other words, the first isolation structure 65 and the third isolation structure 64 can be formed in the same process step, thereby simplifying the production process. In other embodiments, the first isolation structure 65 and the third isolation structure 64 can also be formed in different process steps.

[0058] Continue to refer Figure 14 , performing a first doping treatment on the active structure 2. The first doping treatment includes: implanting first conductive type dopant ions into the first active structure 21 and the fifth active structure 25 to form a first source / drain region SD1 and a second source / drain region SD2; some of the first conductive type dopant ions are also implanted into the second active structure 22 on a side facing the first active structure 21, and into the fourth active structure 24 on a side facing the fifth active structure 25.

[0059] That is, under the shielding of the first isolation structure 65, only the side of the second active structure 22 facing the first region a is exposed, and only the side of the fourth active structure 24 facing the fifth region e is exposed. Therefore, dopant ions can enter the exposed sides of the second active structure 22 and the fourth active structure 24. In addition, the first doping process also implants first conductivity type dopant ions into the sixth active structure 26.

[0060] Since only one side surface of the second active structure 22 and the fourth active structure 24 is exposed, the concentration of the first conductive type dopant ions in the second active structure 22 and the fourth active structure 24 is lower than that in the first source / drain region SD1 and the second source / drain region SD2 .

[0061] In some embodiments, the first doping treatment may be performed by a diffusion process, which causes fewer defects in the active structure 2 and is beneficial for improving the electrical performance of the memory. In other embodiments, the first doping treatment may also be performed by an ion implantation process.

[0062] refer to Figure 15 , forming a second isolation structure 66, the second isolation structure 66 is located between the first source and drain regions SD1 adjacent to each other in the second direction Y, and is also located between the second source and drain regions SD2 adjacent to each other in the second direction Y. Thereafter, the first isolation structure 65 is removed (refer to Figure 14 ), so as to expose the third active structure 23 at two opposite sides in the second direction Y, and expose the side of the second active structure 22 facing the third region c and the side of the fourth active structure 24 facing the third region c.

[0063] The material of the second isolation structure 66 may be the same as that of the third isolation structure 64 . For example, both may be made of silicon oxide, silicon oxynitride, or silicon oxycarbide.

[0064] The active structure 2 is subjected to a second doping treatment, which includes implanting second conductivity type dopant ions into the third active structure 23 to form a channel region C. Some of the second conductivity type dopant ions are also implanted into a side of the second active structure 22 facing the third active structure 23 and a side of the fourth active structure 24 facing the third active structure 23, thereby transforming the second active structure 22 into the first lightly doped region L1 and transforming the fourth active structure 24 into the second lightly doped region L2.

[0065] For example, the second doping treatment may be performed by a diffusion process to reduce defects in the active structure 2. In other embodiments, the second doping treatment may also be performed by an ion implantation process.

[0066] Since only one side surface of the second active structure 22 and the fourth active structure 24 is exposed, the concentration of the second conductive type dopant ions in the second active structure 22 and the fourth active structure 24 is lower than the concentration of the second conductive type dopant ions in the channel region C.

[0067] So far, based on Figure 14-15 In the steps shown, the active structure 2 can be doped. The doping treatment includes a first doping treatment and a second doping treatment, so that the first active structure 21 to the fifth active structure 25 are transformed into the first source and drain region SD1, the first lightly doped region L1, the channel region C, the second lightly doped region L2, and the second source and drain region SD2, respectively. In the aforementioned example, the first doping treatment is performed before the second doping treatment, which saves process steps and allows the gate structure 7 to be formed directly in the third region c. In other embodiments, the second doping treatment can be performed first and then the first doping treatment. In other words, the second isolation structure 66 needs to be formed first and then the first isolation structure 65.

[0068] It should be noted that in the steps illustrated above, the doping process is performed after the support structure 5 is formed. Therefore, the support structure 5 can cover the upper and lower surfaces of the second active structure 22 and the fourth active structure 24, thereby preventing excessive dopant ions from entering the second active structure 22 and the fourth active structure 24, that is, preventing the ion concentration in the first lightly doped region L1 and the second lightly doped region L2 from being too high.

[0069] The doping process of the first active structure 21, the third active structure 23 and the fifth active structure 25 can be used to complete the doping of the second active structure 22 and the fourth active structure 24. Therefore, the production process is simpler and the production efficiency is higher. In other embodiments, the doping process of the second active structure 22 and the fourth active structure 24 can also be carried out separately. For example, in Figure 9 In the steps shown, after removing part of the sacrificial structure 42, the second active structure 22 and the fourth active structure 24 may be doped. Thereafter, the first active structure 21, the fifth active structure 25, and the third active structure 23 may be doped.

[0070] In some embodiments, the doping process further includes an annealing process to activate doping ions and repair defects, so that the second lightly doped region L2 and the first lightly doped region L1 form a graded junction.

[0071] refer to Figure 16 After doping treatment, a gate structure 7 extending in the third direction Z is formed. The gate structure 7 is located between the first lightly doped region L1 and the second lightly doped region L2 protruding in the second direction Y, and is located on opposite sides of the channel region C in the second direction Y.

[0072] For example, a chemical vapor deposition process is first used to form a gate dielectric layer 72. The gate dielectric layer 72 covers the sidewalls of the channel region C in the second direction Y, the sidewalls of the first lightly doped region L1 facing the third region C, and the sidewalls of the second lightly doped region L2 facing the third region C. Thereafter, a chemical vapor deposition process is used to form a gate layer 71. The gate layer 71 fills the area enclosed by the first support structure 51, the first lightly doped region L1, the second lightly doped region L2, and the channel region C.

[0073] refer to Figure 17 , removing the sixth active structure 26 , illustratively, using a wet etching process to remove the sixth active structure 26 .

[0074] refer to Figure 18 A bit line 82 is formed in the sixth region f. Bit line 82 extends along the second direction Y and connects to the plurality of first source and drain regions SD1 on the same layer. That is, bit line 82 is located at the spatial location of the original sixth active structure 26. For example, a chemical vapor deposition process is used to deposit a metal such as tungsten, titanium, or copper as bit line 82.

[0075] refer to Figure 19 , remove part of the second source and drain region SD2, the second isolation structure 66 and the third isolation structure 64 of the fifth region e, that is, shorten the length of the second source and drain region SD2, the second isolation structure 66 and the third isolation structure 64 in the first direction X, thereby providing a spatial position for manufacturing the capacitor 81.

[0076] Continue to refer Figure 19 , forming a capacitor 81, the capacitor 81 includes a lower electrode, a dielectric layer and an upper electrode. The lower electrode is connected to the second source and drain region SD2.

[0077] refer to Figure 2 The third isolation structure 64 and the bit line 82 of the sixth region f are patterned to form a step, so as to facilitate the subsequent leading of the bit line 82 in a direction back to the substrate 1, thereby electrically connecting to the peripheral circuit.

[0078] In summary, in the embodiment of the present disclosure, the shape of the active structure 2 is changed to make it more compatible with the process, and a support structure 5 is formed to support the active structure 2, thereby avoiding irregular morphology caused by simple hole opening or lateral etching of the sacrificial structure 42, thereby improving the performance of the semiconductor structure.

[0079] In the description of this specification, the reference terms "some embodiments", "exemplarily", etc. mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0080] Although the embodiments of the present disclosure have been shown and described above, it is understood that the above embodiments are illustrative and cannot be understood as limitations on the present disclosure. A person skilled in the art may change, modify, replace and modify the above embodiments within the scope of the present disclosure. Therefore, any changes or modifications made in accordance with the claims and description of the present disclosure shall fall within the scope of the patent of the present disclosure.

Claims

1. A semiconductor structure, characterized in that include: Transistors, including: A gate structure and a first source and drain region, a first lightly doped region, a channel region, a second lightly doped region and a second source and drain region arranged in sequence in a first direction; In the second direction, the relative sides of the first lightly doped region and the second lightly doped region are both protruded relative to the relative sides of the channel region, the first source and drain region, and the second source and drain region; the gate structure is located between the protruding first lightly doped region and the second lightly doped region, and is located on the relative sides of the channel region in the second direction; the first direction intersects with the second direction.

2. The semiconductor structure according to claim 1, wherein: The width of the first lightly doped region in the second direction is equal to the total width of the channel region and the gate structure in the second direction; A width of the second lightly doped region in the second direction is equal to a total width of the channel region and the gate structure in the second direction.

3. The semiconductor structure according to claim 1, wherein: The first source and drain region, the second source and drain region, a side of the first lightly doped region facing the first source and drain region, and a side of the second lightly doped region facing the second source and drain region all have dopant ions of the first conductivity type; The channel region, a side of the first lightly doped region facing the channel region, and a side of the second lightly doped region facing the channel region all have second conductivity type doping ions.

4. The semiconductor structure according to claim 3, wherein: In a direction from the first source / drain region to the channel region, the concentration of the first conductive type dopant ions in the first lightly doped region gradually decreases, and the concentration of the second conductive type dopant ions in the first lightly doped region gradually increases; In a direction from the second source and drain region to the channel region, the concentration of the first conductive type dopant ions in the second lightly doped region gradually decreases, and the concentration of the second conductive type dopant ions in the second lightly doped region gradually increases.

5. The semiconductor structure according to claim 3 or 4, characterized in that: The doping concentration of the first source and drain regions and the second source and drain regions is 7.5E20 / cm 3 ~8.5E20 / cm 3 ; The doping concentration of the channel region is 1.5E20 / cm 3 ~2.5E20 / cm 3 ; The concentration of the first conductive type dopant ions on the side of the first lightly doped region facing the first source and drain regions is less than 8.5E20 / cm 3 The concentration of the first conductive type dopant ions on the side of the second lightly doped region facing the second source and drain regions is less than 8.5E20 / cm 3 ; The concentration of the second conductive type dopant ions on the side of the first lightly doped region facing the channel region is less than 2.5E20 / cm 3 The concentration of the second conductive type dopant ions on the side of the second lightly doped region facing the channel region is less than 2.5E20 / cm 3 . The semiconductor structure according to claim 1 , wherein: The gate structure includes a gate dielectric layer and a gate layer, wherein the gate dielectric layer covers side walls of the gate layer facing the channel region, the first lightly doped region, and the second lightly doped region.

7. A memory, characterized in that: include: The semiconductor structure according to any one of claims 1 to 6, wherein the memory further comprises: a substrate having a plurality of transistor groups arranged in the second direction, the transistor groups including a plurality of transistors arranged in a third direction; the plurality of gate structures of the same transistor group are connected and extend along the third direction; a support structure comprising a first support structure and a second support structure connected to each other, wherein the first support structure is located between adjacent transistor groups and is arranged opposite to the first lightly doped region, the second lightly doped region, and the gate structure in the second direction; and the second support structure is located between adjacent first lightly doped regions arranged in the third direction and also between adjacent second lightly doped regions arranged in the third direction; The first direction and the second direction are both parallel to the upper surface of the substrate, and the third direction is perpendicular to the upper surface of the substrate.

8. The memory according to claim 7, wherein: The memory further includes: a plurality of bit lines arranged in the third direction, the bit lines extending along the second direction and connected to the plurality of first source and drain regions in the second direction.

9. A method for manufacturing a memory, characterized in that: include: providing a substrate; forming a plurality of active groups arranged in a second direction on the substrate; The active group includes a plurality of active structures arranged in a third direction, wherein the active structures include a first active structure, a second active structure, a third active structure, a fourth active structure, and a fifth active structure arranged in sequence in the first direction; in the second direction, opposite sides of the second active structure and the fourth active structure are both protruded relative to opposite sides of the first active structure, the third active structure, and the fifth active structure; forming a support structure on the substrate, the support structure comprising a first support structure and a second support structure connected to each other, the first support structure being located between adjacent active groups and arranged opposite to the second to fourth active structures; the second support structure being located between adjacent second active structures arranged in the third direction and also between adjacent fourth active structures arranged in the third direction; performing a doping process on the active structures so as to transform the first active structure to the fifth active structure into a first source-drain region, a first lightly doped region, a channel region, a second lightly doped region, and a second source-drain region, respectively; A gate structure extending in the third direction is formed, the gate structure is located between the first lightly doped region and the second lightly doped region protruding in the second direction, and is located on two opposite sides of the channel region in the second direction.

10. The method for manufacturing a memory according to claim 9, wherein: The doping process includes a first doping process and a second doping process; The first doping process includes: implanting first conductive type dopant ions into the first active structure and the fifth active structure to form the first source / drain region and the second source / drain region; and implanting part of the first conductive type dopant ions into a side of the second active structure facing the first active structure and a side of the fourth active structure facing the fifth active structure. The second doping treatment includes: implanting second conductive type dopant ions into the third active structure to form the channel region; part of the second conductive type dopant ions is also implanted into the side of the second active structure facing the third active structure, and into the side of the fourth active structure facing the third active structure.

11. The method for manufacturing a memory according to claim 10, wherein: Before the first doping process, the method further includes: forming a first isolation structure between the third active structure and the first supporting structure, wherein the first isolation structure is also located between the second active structure protruding in the second direction and the fourth active structure; Before the second doping process, the method further includes: forming a second isolation structure, wherein the second isolation structure is located between the first source and drain regions adjacent to each other in the second direction, and is also located between the second source and drain regions adjacent to each other in the second direction; The first isolation structure is removed, and the gate structure is formed after the second doping process.

12. The method for manufacturing a memory according to claim 11, wherein: The first doping treatment and the second doping treatment both include a diffusion process, and the doping treatment further includes an annealing process.

13. The method for manufacturing a memory according to claim 9, wherein: Before forming the support structure, the method further includes: forming a sacrificial structure, wherein the sacrificial structure and the active structure are alternately arranged in the third direction; removing the sacrificial structure between the second active structures adjacent to each other in the third direction, and removing the sacrificial structure between the fourth active structures adjacent to each other in the third direction; After forming the support structure and before the doping process, the method further includes: The remaining sacrificial structure is removed.

14. The method for manufacturing a memory according to claim 13, wherein: After removing the remaining sacrificial structure and before the doping process, the method further includes: A third isolation structure is formed, where the third isolation structure is located between the active structures adjacent to each other in the third direction.

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