Semiconductor structure and preparation method thereof

Abstract

The present disclosure relates to a semiconductor structure and a method for preparing the same. The semiconductor structure includes a substrate, a first gate structure, a channel layer, a source / drain structure, and a buffer layer. The first gate structure is located on the top surface of the substrate; the channel layer is located on a side of the first gate structure away from the substrate along a first direction; the source / drain structure is located on opposite sides of the channel layer along a second direction; the buffer layer is located on opposite sides of the channel layer along the second direction and between the channel layer and the source / drain structure; and the first direction intersects the second direction. The above structure can reduce device damage, reduce contact resistance, and increase device service life, thereby improving the overall performance of the semiconductor device.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a preparation method thereof. Background Art

[0002] With the development of the chip market, dynamic random access memory (DRAM) has a trend of further miniaturization, integration and low power consumption. DRAM, which has one transistor and one capacitor (1Transistor 1Capacitor, abbreviated as 1T1C) in its storage unit, needs to use capacitors for data storage. The preparation process and storage performance of capacitors restrict the development of DRAM.

[0003] The 2T0C structure, in which a memory cell consists of two transistors for data storage, can circumvent the problems associated with using capacitors for data storage. However, the structure of the 2T0C cell still needs further optimization and adjustment to improve DRAM storage performance. Summary of the Invention

[0004] Based on this, the present disclosure provides a semiconductor structure and a method for manufacturing the same to optimize the structural layout of a 2T0C memory cell and further improve the overall performance of the memory.

[0005] According to various embodiments of the present disclosure, a semiconductor structure is provided, comprising a substrate, a first gate structure, a channel layer, a source / drain structure, and a buffer layer. The first gate structure is located on a top surface of the substrate; the channel layer is located on a side of the first gate structure away from the substrate along a first direction; the source / drain structure is located on opposite sides of the channel layer along a second direction; and the buffer layer is located on opposite sides of the channel layer along the second direction and between the channel layer and the source / drain structure. The first direction intersects the second direction.

[0006] In the semiconductor structure of the above embodiment, by arranging the buffer layer between the channel layer and the source / drain structure to isolate the channel layer from the source / drain structure, the problem of large contact resistance between the channel layer and the source / drain structure can be solved, thereby improving the overall performance of the device; it can also prevent the metal material molecules in the source / drain structure from diffusing into the channel layer, and avoid the surface damage of the channel layer caused by contact between the channel layer and the source / drain structure, thereby extending the service life of the semiconductor structure. In conventional technology, the channel and the source / drain are usually directly in contact, which will cause the contact surface between the channel and the source / drain to be damaged, and due to the mismatch between the work functions of the two, the contact resistance between the two will also increase, thereby affecting the conductive performance of the semiconductor device and reducing its working efficiency. The present disclosure arranges the buffer layer between the channel layer and the source / drain structure, thereby avoiding the occurrence of the above problems. While reducing the contact resistance between the channel layer and the source / drain structure, it can also reduce damage to the channel layer, increase the service life of the channel layer, and thus improve the yield of the semiconductor structure.

[0007] In some embodiments, the work function of the buffer layer is greater than the work function of the source / drain structure and less than the work function of the channel layer.

[0008] In some embodiments, the work function of the buffer layer is in the range of (4.5 eV, 5.7 eV).

[0009] In some embodiments, the material of the buffer layer is selected from palladium, cadmium, titanium, aluminum, silver, and combinations thereof.

[0010] In some embodiments, the first gate structure includes a first gate dielectric layer and a first gate conductive layer. The first gate dielectric layer is located between the substrate and the channel layer, between the substrate and the source / drain structure, and between the substrate and the buffer layer. The first gate conductive layer is located on the top surface of the substrate and within the first gate dielectric layer.

[0011] In some embodiments, a length of the first gate conductive layer along the second direction is greater than or equal to a length of the channel layer along the second direction.

[0012] In some embodiments, the semiconductor structure further includes a second gate structure located on a side of the channel layer away from the first gate structure along the first direction; wherein the first gate structure and the second gate structure share the channel layer.

[0013] In some embodiments, the second gate structure includes a second gate dielectric layer and a second gate conductive layer. The second gate dielectric layer is located on a side of the channel layer away from the first gate structure along the first direction and covers the channel layer, the source / drain structure, and the top surface of the buffer layer; and the second gate conductive layer is located on a side of the second gate dielectric layer away from the first gate structure along the first direction.

[0014] In some embodiments, a length of the second gate conductive layer along the second direction is greater than or equal to a length of the channel layer along the second direction.

[0015] In some embodiments, the material of the channel layer is selected from indium gallium zinc oxide, indium zinc oxide, transition metals, transition metal oxides, and combinations thereof.

[0016] According to some embodiments of the present disclosure, the present disclosure provides a method for preparing a semiconductor structure on another aspect, including: providing a substrate; forming a first gate structure on the top surface of the substrate; forming a channel layer on a side of the first gate structure away from the substrate along a first direction; forming a buffer layer on opposite sides of the channel layer along a second direction; forming a source / drain structure on a side of the buffer layer away from the channel layer along the second direction; the buffer layer is located between the channel layer and the source / drain structure; wherein the first direction intersects with the second direction.

[0017] In the method for preparing the semiconductor structure in the above-mentioned embodiment, a source / drain structure is formed on a side of the buffer layer away from the channel layer along the second direction, so that the buffer layer is located between the channel layer and the source / drain structure to isolate the channel layer from the source / drain structure. This can solve the problem of high contact resistance between the channel layer and the source / drain structure and reduce the problem of internal damage to the channel layer caused by contact between the two, thereby improving the overall performance of the semiconductor structure. Compared with the traditional technology of directly contacting the channel with the source / drain, the present disclosure arranges the buffer layer between the channel layer and the source / drain structure, thereby reducing the contact resistance between the channel layer and the source / drain structure while also reducing the damage caused to the channel layer by the source / drain structure, thereby improving the overall performance of the semiconductor structure.

[0018] In some embodiments, the work function of the buffer layer is greater than the work function of the source / drain structure and less than the work function of the channel layer.

[0019] In some embodiments, the work function of the buffer layer is in the range of (4.5 eV, 5.7 eV).

[0020] In some embodiments, the material of the buffer layer is selected from palladium, cadmium, titanium, aluminum, silver, and combinations thereof.

[0021] In some embodiments, after forming the source / drain structure, the method further includes forming a second gate structure on a side of the channel layer away from the first gate structure along the first direction; wherein the first gate structure and the second gate structure share the channel layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0023] Figure 1 Shown is a schematic cross-sectional view of a semiconductor structure provided in the related art according to an embodiment of the present disclosure;

[0024] Figure 2 Shown is a circuit diagram of a memory cell provided in the related art according to an embodiment of the present disclosure;

[0025] Figure 3 Shown is a circuit diagram of a memory array provided in the related art according to an embodiment of the present disclosure;

[0026] Figure 4 Shown is a schematic cross-sectional view of a semiconductor structure provided in the related art according to another embodiment of the present disclosure;

[0027] Figure 5 Shown is a circuit diagram of a memory cell provided in the related art according to another embodiment of the present disclosure;

[0028] Figure 6 Shown is a circuit diagram of a memory array provided in the related art according to another embodiment of the present disclosure;

[0029] Figure 7 A schematic cross-sectional view of a semiconductor structure provided by an embodiment of the present disclosure is shown;

[0030] Figure 8 A schematic cross-sectional view of a semiconductor structure provided by another embodiment of the present disclosure is shown;

[0031] Figure 9 A schematic diagram showing a process of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0032] Figure 10 A schematic cross-sectional view showing a method for preparing a semiconductor structure according to an embodiment of the present disclosure, wherein a first gate conductive layer is formed on a substrate;

[0033] Figure 11 A method for preparing a semiconductor structure provided by an embodiment of the present disclosure is shown as follows: Figure 10 A cross-sectional schematic diagram of forming a first gate dielectric layer on the structure shown;

[0034] Figure 12 A method for preparing a semiconductor structure provided by an embodiment of the present disclosure is shown as follows: Figure 11 A schematic cross-sectional view of a channel layer formed on the structure shown;

[0035] Figure 13 A method for preparing a semiconductor structure provided by an embodiment of the present disclosure is shown as follows: Figure 12 Schematic cross-sectional view of forming a buffer layer on the structure shown.

[0036] Description of reference numerals:

[0037] 10. Base; 11. First gate; 12. First insulating layer; 13. Source / drain; 14. Channel; 15. Second insulating layer; 16. Second gate; 20. Substrate; 21. First gate structure; 211. First gate conductive layer; 212. First gate dielectric layer; 22. Channel layer; 23. Source / drain structure; 24. Buffer layer; 25. Second gate structure; 251. Second gate dielectric layer; 252. Second gate conductive layer. DETAILED DESCRIPTION

[0038] To facilitate understanding of the present disclosure, a more comprehensive description of the present disclosure will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present disclosure. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0040] It should be understood that when an element or layer is referred to as being “on,” “adjacent,” “connected to,” or “coupled to” another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly adjacent to,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers present.

[0041] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0042] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0043] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present disclosure. Although the illustrations only show components related to the present disclosure and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation can be changed arbitrarily, and the component layout type may also be more complex.

[0044] Memory is a component used to store programs and various data. It can be categorized by usage type into ROM (Read-Only Memory) and RAM (Random Access Memory). Based on the operating principles of the memory cell, RAM is divided into SRAM (Static RAM) and DRAM. Compared to SRAM, DRAM offers advantages such as high integration, low power consumption, and low price, making it widely used in large-capacity memory. The basic memory cell in DRAM consists of two components: a transistor and a capacitor. The transistor is used to charge and discharge the capacitor, and both charging and discharging are accomplished through word lines and bit lines.

[0045] It should be noted that, in some embodiments of the present disclosure, the first direction may be the oy direction, the oy direction may be the thickness / height direction, and the second direction may be the ox direction.

[0046] See also Figure 1 、 Figure 2 and Figure 3 , Figure 1 In the semiconductor structure shown, a first gate 11 is located on the top surface of a substrate 10, a first insulating layer 12 covers the side and top surface of the first gate 11, a channel 14 is provided on one side of the first insulating layer 12 away from the substrate along a first direction (e.g., the oy direction), and source / drain electrodes 13 are provided on opposite sides of the channel 14 along a second direction (e.g., the ox direction). The above structure can be used to form a memory cell. Figure 2 In the memory cell circuit shown, data 1 or 0 is stored in the storage node SN through the write word line WWL and the write bit line WBL, and then the stored data in the storage node SN is read out through the read word line RWL and the read bit line RBL. Figure 3 The circuit shown is Figure 2 However, in the circuit constructed with the aforementioned structure, the use of a write bit line (WBL) and a read bit line (RBL) in a single memory cell limits the high-density design of the memory device and presents a serious voltage drop (IR drop) problem. IR drop refers to the phenomenon of voltage drops and rises on the power and ground networks in an integrated circuit. With the continuous evolution of semiconductor processes, the width of metal interconnects has become narrower, the resistance has continued to increase, and the power supply voltage has become smaller and smaller. The IR drop effect has become increasingly significant, causing the activated read word line (RWL) to accumulate current during operation, limiting the number of memory cells per row in the memory array.

[0047] See also Figure 4 、 Figure 5 and Figure 6 , Figure 4 In the semiconductor structure shown, a first gate 11 is located on a substrate 10, a first insulating layer 12 covers the side and top surface of the first gate 11, a channel 14 is provided on the side of the first insulating layer 12 away from the substrate along a first direction (e.g., the oy direction), a source / drain 13 is provided on opposite sides of the channel 14 along a second direction (e.g., the ox direction), a second insulating layer 15 and a second gate 16 are provided on the side of the channel 14 and the source / drain 13 away from the substrate along the first direction (e.g., the oy direction), wherein the second gate 16 is provided on the side of the second insulating layer 15 away from the substrate along the first direction (e.g., the oy direction). The above structure can be used to form a memory cell with a dual-gate structure. Figure 5 In the memory cell circuit shown, data 1 or 0 is stored in the storage node SN through the write word line WWL and the bit line BL, and then the stored data in the storage node SN is read out through the read word line RWL and the bit line BL. Figure 6 The circuit shown is Figure 2The memory array is composed of memory cells shown in FIG. The dual-gate structure allows for flexible control of read operations and uses only one bit line BL, facilitating high-density design of memory devices. Current in the memory cells can flow to ground GND via the bit line BL, making the current in the read word line RWL negligible, thereby alleviating the IR drop problem.

[0048] See also Figures 1-6 However, in both of the above-mentioned semiconductor structures, the source / drain 13 is directly in contact with the channel 14. Carriers need to overcome energy barriers to transport between the thin films. Excessive barriers can lead to voltage loss, reduce energy conversion efficiency, increase operating voltage, and reduce device life. Especially at the electrode interface, the Fermi level of the conductor metal and the carrier transport energy level of the organic semiconductor are usually quite different. Therefore, how to reduce the contact resistance at the electrode interface through interface engineering has always been one of the focuses of device research. Through research, it has been found that the metal material in the source / drain 13, such as tungsten, will diffuse into the channel 14, thereby damaging the channel 14. Electrochemical reactions will also occur at the contact interface between the two, forming a defective mixed layer at the interface, causing device instability and affecting its service life. In addition, the work function of the source / drain 13 and the channel 14 does not match, making it difficult for the two to form a good ohmic contact, resulting in problems such as poor current spreading and high voltage in the device, and increasing the contact resistance, affecting the conductive performance of the semiconductor device.

[0049] Based on the above technical problems, the present disclosure provides a semiconductor structure and a method for manufacturing the same to optimize the structural layout of a 2T0C memory cell and further improve the overall performance of the memory.

[0050] As an example, see Figure 7 The present disclosure provides a semiconductor structure, including a substrate 20, a first gate structure 21, a channel layer 22, a source / drain structure 23, and a buffer layer 24. The first gate structure 21 is located on the top surface of the substrate 20; the channel layer 22 is located on a side of the first gate structure 21 away from the substrate 20 along a first direction (e.g., the oy direction); the source / drain structure 23 is located on opposite sides of the channel layer 22 along a second direction (e.g., the ox direction); the buffer layer 24 is located on opposite sides of the channel layer 22 along the second direction (e.g., the ox direction) and between the channel layer 22 and the source / drain structure 23; and the first direction (e.g., the oy direction) intersects with the second direction (e.g., the ox direction).

[0051] In the semiconductor structure of the above embodiment, by disposing a buffer layer 24 between the channel layer 22 and the source / drain structure 23 to isolate the channel layer 22 from the source / drain structure 23, the problem of large contact resistance between the channel layer 22 and the source / drain structure 23 can be solved, thereby improving the overall performance of the device; it can also prevent the metal material molecules in the source / drain structure 23 from diffusing into the channel layer 22, and avoid the channel layer 22 from contacting the source / drain structure 23 and causing surface damage to the channel layer 22, thereby extending the service life of the semiconductor structure. In traditional technology, the channel is usually directly contacted with the source / drain, which will cause the contact surface between the channel and the source / drain to be damaged. Due to the mismatch in the work function of the two, the contact resistance between the two will also increase, thereby affecting the conductive performance of the semiconductor device and reducing its working efficiency. The present disclosure sets the buffer layer 24 between the channel layer 22 and the source / drain structure 23, so as to avoid the occurrence of the above-mentioned problems. While reducing the contact resistance between the channel layer 22 and the source / drain structure 23, it can also reduce the damage to the channel layer 22 and increase the service life of the channel layer 22, thereby improving the yield of the semiconductor structure.

[0052] As an example, the substrate 20 can be made of a semiconductor material, an insulating material, a conductor material, or any combination thereof. The substrate 20 can be a single-layer structure or a multi-layer structure. For example, the substrate 20 can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 20 can be a layered substrate including Si / SiGe, Si / SiC, silicon on insulator (SOI), or silicon germanium on insulator. Those skilled in the art can select the type of substrate 20 according to the type of transistor formed on the substrate 20. Therefore, the type of substrate 20 should not limit the scope of protection of this application.

[0053] As an example, see Figure 7 The work function of the buffer layer 24 is greater than the work function of the source / drain structure 23 and less than the work function of the channel layer 22. Since the work function of the channel layer 22 does not match the work function of the source / drain structure 23, and the work function of the channel layer 22 is greater than the work function of the source / drain structure 23, setting the work function of the buffer layer 24 between the work functions of the source / drain structure 23 can improve the work function mismatch problem, reduce contact resistance, and improve conductive performance.

[0054] As an example, see Figure 7, the work function range of the buffer layer 24 is (4.5eV, 5.7eV). For example, the work function of the buffer layer 24 can be 3.6eV, 4.0eV, 4.5eV, 5.0eV or 5.7eV, etc. Since the work function of the source / drain structure 23 is generally about 4.5eV and the work function of the channel layer 22 is generally about 5.7eV, the work function range of the buffer layer 24 is set to (4.5eV, 5.7eV), so that the buffer layer 24 can form a good ohmic contact with the channel layer 22 and the source / drain structure 23, respectively, thereby reducing the contact resistance. Usually, when a semiconductor material contacts a metal material, a barrier layer is often formed. However, when the semiconductor doping concentration is very high, electrons can pass through the barrier by the tunnel effect, thereby forming a low-resistance ohmic contact. Ohmic contact is very important for semiconductor devices. The formation of a good ohmic contact is conducive to the input and output of current. Ohmic contact is related to the work function of the metal and semiconductor materials. The work function, also known as the work function, represents the energy required to move an electron from the Fermi level of the material into the vacuum outside the material, where it remains stationary. This energy is equivalent to the energy required to reduce the kinetic energy to zero. The closer the work function of the metal and semiconductor materials, the lower the ohmic contact resistance and the better the device's conductivity. The present disclosure can reduce the contact resistance between the channel layer 22 and the source / drain structure 23, thereby improving the overall performance of the memory device.

[0055] As an example, see Figure 7 , the material of the buffer layer 24 is selected from palladium, cadmium, titanium, aluminum, silver and a combination thereof. It should be noted that the materials of the buffer layer 24 include but are not limited to the above materials, and other materials can be selected as needed, but it is necessary to ensure that the work function of the buffer layer 24 is greater than the work function of the source / drain structure 23 and less than the work function of the channel layer 22, and it can prevent the material molecules in the channel layer 22 and the source / drain structure 23 from diffusing into each other, so as to reduce the contact resistance while extending the service life of the semiconductor structure and improving the yield of the semiconductor device. It should be noted that the materials of the buffer layer 24 include but are not limited to the above materials, and other materials can be selected as needed, but it is necessary to ensure that the work function of the buffer layer 24 is greater than the work function of the source / drain structure 23 and less than the work function of the channel layer 22, and it can prevent the material molecules in the channel layer 22 or the source / drain structure 23 from diffusing into each other.

[0056] In this embodiment, graphene is used as the material of the buffer layer 24. Graphene has rich electronic states and good mechanical properties, and can replace carbon nanotubes in many fields. Atom-thick graphene sheets with a two-dimensional planar geometry are more conducive to electron transmission than carbon nanotubes. Graphene can be used as a conductive coating and interface barrier layer to enhance the corrosion resistance and electrochemical properties of the metal current collector, and serve as a buffer layer 24 between the channel layer 22 and the source / drain structure 23 to prevent material molecules in the source / drain structure 23 from diffusing into the channel layer 22.

[0057] As an example, see Figure 7 The first gate structure 21 includes a first gate dielectric layer 212 and a first gate conductive layer 211. The first gate dielectric layer 212 is located between the substrate 20 and the channel layer 22, between the substrate 20 and the source / drain structure 23, and between the substrate 20 and the buffer layer 24. The first gate conductive layer 211 is located on the top surface of the substrate 20 and inside the first gate dielectric layer 212.

[0058] As an example, see Figure 7 The material of the first gate conductive layer 211 can be a conductive material such as polysilicon, titanium (Titanium, Ti), titanium nitride (TiN), tungsten silicide (Tungsten silicide, Si2W), tungsten (Tungsten, W) (TaN) or (TiSiN). Furthermore, for P-type metal-oxide-semiconductor (PMOS) transistors, materials that can be used for the first gate conductive layer 211 include but are not limited to ruthenium, palladium, platinum, cobalt, nickel and conductive metal oxides, such as ruthenium oxide. The P-type metal layer will enable the formation of a PMOS gate electrode with a work function between approximately 4.5 eV and approximately 5.7 eV; for N-type metal-oxide-semiconductor (NMOS) transistors, materials that can be used for the first gate conductive layer 211 include but are not limited to hafnium, zirconium, titanium, tantalum, aluminum and their alloys and carbides, such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide and aluminum carbide. The N-type metal layer will enable the formation of an NMOS gate electrode with a work function between approximately 3.9 eV and approximately 4.5 eV.

[0059] As an example, see Figure 7 The material of the first gate dielectric layer 212 can be an insulating material with a low dielectric constant such as silicon oxide or silicon nitride, or an insulating material with a high dielectric constant such as hafnium oxide (HfO2), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), aluminum oxide (Al2O3) or strontium titanium oxide (SrTiO3).

[0060] As an example, see Figure 7 The length of the first gate conductive layer 211 along the second direction (for example, the ox direction) is greater than or equal to the length of the channel layer 22 along the second direction (for example, the ox direction), so that during the operation of the semiconductor device, the voltage of the first gate conductive layer 211 can better control the conductivity of the channel layer 22.

[0061] As an example, see Figure 8 The semiconductor structure further includes a second gate structure 25 located on a side of the channel layer 22 that is away from the first gate structure 21 along a first direction (e.g., the oy direction). The first gate structure 21 and the second gate structure 25 share the channel layer 22. The dual-gate structure in the above structure allows for more flexible control of read operations and improves IR drop issues.

[0062] As an example, see Figure 8 The second gate structure 25 includes a second gate dielectric layer 251 and a second gate conductive layer 252. The second gate dielectric layer 251 is located on a side of the channel layer 22 away from the first gate structure 21 along the first direction (e.g., the oy direction), and covers the top surfaces of the channel layer 22, the source / drain structure 23, and the buffer layer 24; the second gate conductive layer 252 is located on a side of the second gate dielectric layer 251 away from the first gate structure 21 along the first direction (e.g., the oy direction).

[0063] As an example, see Figure 8 The material of the second gate conductive layer 252 can be a conductive material such as polysilicon, titanium (Titanium, Ti), titanium nitride (TiN), tungsten silicide (Tungsten silicide, Si2W), tungsten (Tungsten, W) (TaN) or (TiSiN). Furthermore, for P-type metal-oxide-semiconductor (PMOS) transistors, materials that can be used for the second gate conductive layer 252 include but are not limited to ruthenium, palladium, platinum, cobalt, nickel and conductive metal oxides, such as ruthenium oxide. The P-type metal layer will enable the formation of a PMOS gate electrode with a work function between approximately 4.5 eV and approximately 5.7 eV; for N-type metal-oxide-semiconductor (NMOS) transistors, materials that can be used for the second gate conductive layer 252 include but are not limited to hafnium, zirconium, titanium, tantalum, aluminum and their alloys and carbides, such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide and aluminum carbide. The N-type metal layer will enable the formation of an NMOS gate electrode with a work function between approximately 3.9 eV and approximately 4.5 eV.

[0064] As an example, see Figure 8 The material of the second gate dielectric layer 251 can be an insulating material with a low dielectric constant such as silicon oxide or silicon nitride, or an insulating material with a high dielectric constant such as hafnium oxide (HfO2), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), aluminum oxide (Al2O3) or strontium titanium oxide (SrTiO3).

[0065] As an example, see Figure 8 The length of the second gate conductive layer 252 along the second direction (for example, the ox direction) is greater than or equal to the length of the channel layer 22 along the second direction (for example, the ox direction), so that during operation of the semiconductor device, the voltage of the second gate conductive layer 252 can be combined with the voltage of the first gate conductive layer 211 to better control the conductivity of the channel layer 22.

[0066] As an example, see Figure 8 The material of the channel layer 22 is selected from indium gallium zinc oxide, indium zinc oxide, transition metal, transition metal oxide and a combination thereof. In this embodiment, the material of the channel layer 22 is indium gallium zinc oxide, namely IGZO (Indium Gallium Zinc Oxide), which is a channel layer material used in the new generation of thin film transistor technology and a type of metal oxide (Oxide) panel technology. Using IGZO crystal as the channel layer material makes the device size smaller, makes the device thinner, and can increase the aperture ratio of the component, improve brightness, and reduce power consumption; in addition, in terms of electron mobility, IGZO is about 10cm 2 / Vs, the critical voltage drift is almost the same, which is 20 to 50 times higher than that of traditional materials.

[0067] As an example, see Figure 9 In another aspect, the present disclosure provides a method for preparing a semiconductor structure, comprising:

[0068] Step S2: providing a substrate;

[0069] Step S4: forming a first gate structure on the top surface of the substrate;

[0070] Step S6: forming a channel layer on a side of the first gate structure away from the substrate along the first direction;

[0071] Step S8: forming a buffer layer on two opposite sides of the channel layer along the second direction;

[0072] Step S10: forming a source / drain structure on a side of the buffer layer away from the channel layer along the second direction; the buffer layer is located between the channel layer and the source / drain structure; wherein the first direction (eg, oy direction) intersects with the second direction.

[0073] In the method for preparing the semiconductor structure in the above embodiment, a source / drain structure 23 is formed on a side of the buffer layer 24 away from the channel layer 22 along a second direction (e.g., the ox direction); that is, the buffer layer 24 is located between the channel layer 22 and the source / drain structure 23 to isolate the channel layer 22 from the source / drain structure 23, thereby solving the problem of large contact resistance between the channel layer 22 and the source / drain structure 23 and reducing the internal damage of the channel layer 22 caused by the contact between the two, thereby improving the overall performance of the semiconductor structure. Compared with the conventional technology of directly contacting the channel with the source / drain, the present disclosure arranges the buffer layer 24 between the channel layer 22 and the source / drain structure 23, thereby reducing the contact resistance between the channel layer 22 and the source / drain structure 23 while reducing the damage caused to the channel layer 22 by the source / drain structure 23, thereby improving the overall performance of the semiconductor structure.

[0074] In step S4, see Figure 9 Step S4 in Figure 10 and Figure 11 , also includes:

[0075] Step S41: forming a first gate conductive layer 211 on the top surface of the substrate 20;

[0076] Step S42 : forming a first gate dielectric layer 212 on the top surface and side surfaces of the first gate conductive layer 211 .

[0077] In step S41, the length of the first gate conductive layer 211 along the second direction (eg, ox direction) is greater than or equal to the channel layer 22 (see Figure 12 ) along the second direction (e.g., the ox direction), so that during operation of the semiconductor device, the voltage of the first gate conductive layer 211 can better control the conductivity of the channel layer 22. Specifically, the material of the first gate conductive layer 211 can be a conductive material such as polysilicon, titanium (Ti), titanium nitride (TiN), tungsten silicide (Si2W), tungsten (W) (TaN) or (TiSiN).

[0078] In step S42, the first gate dielectric layer 212 covers the side and top surfaces of the first gate conductive layer 211 to isolate the first gate conductive layer 211 from the channel layer 22 (see FIG. Figure 12 Specifically, the material of the first gate dielectric layer 212 can be an insulating material with a low dielectric constant, such as silicon oxide or silicon nitride, or an insulating material with a high dielectric constant, such as hafnium oxide (HfO2), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), aluminum oxide (Al2O3) or strontium titanium oxide (SrTiO3).

[0079] In step S6, refer to Figure 9 Step S6 and Figure 12 A channel layer 22 is formed on a side of the first gate structure 21 away from the substrate 20 along a first direction (eg, oy direction). The material of the channel layer 22 is selected from indium gallium zinc oxide, indium zinc oxide, transition metal, transition metal oxide, and combinations thereof.

[0080] In step S8, refer to Figure 9 Step S8 and Figure 13 , forming a buffer layer 24 on opposite sides of the channel layer 22 along the second direction (eg, ox direction), the buffer layer 24 completely covers the surface of the channel layer 22 on opposite sides along the second direction (eg, ox direction), so that the channel layer 22 and the source / drain structure 23 (see Figure 7 ) phase isolation, which can reduce the contact resistance between the channel layer 22 and the source / drain structure 23 and prevent the mutual diffusion of materials.

[0081] As an example, see Figure 13 The work function of the buffer layer 24 is greater than the work function of the source / drain structure 23 and less than the work function of the channel layer 22. Since the work function of the channel layer 22 does not match the work function of the source / drain structure 23, and the work function of the channel layer 22 is greater than the work function of the source / drain structure 23, setting the work function of the buffer layer 24 between the work functions of the source / drain structure 23 can improve the work function mismatch problem, reduce contact resistance, and improve conductive performance.

[0082] As an example, see Figure 13, the work function range of the buffer layer 24 is (4.5eV, 5.7eV). For example, the work function of the buffer layer 24 can be 3.6eV, 4.0eV, 4.5eV, 5.0eV or 5.7eV, etc. Since the work function of the source / drain structure 23 is generally about 4.5eV and the work function of the channel layer 22 is generally about 5.7eV, the work function range of the buffer layer 24 is set to (4.5eV, 5.7eV), so that the buffer layer 24 can form good contact with the channel layer 22 and the source / drain structure 23 respectively, thereby reducing the contact resistance. Usually, when a semiconductor material contacts a metal material, a barrier layer is often formed. However, when the semiconductor doping concentration is very high, electrons can pass through the barrier by the tunnel effect, thereby forming a low-resistance ohmic contact. Ohmic contact is very important for semiconductor devices. The formation of a good ohmic contact is conducive to the input and output of current. Ohmic contact is related to the work function of the metal and semiconductor materials. The work function, also known as the work function, represents the energy required to move an electron from the Fermi level of the material into the vacuum outside the material, where it remains stationary. This energy is equivalent to the energy required to reduce the kinetic energy to zero. The closer the work function of the metal and semiconductor materials, the lower the ohmic contact resistance and the better the device's conductivity. The present disclosure can reduce the contact resistance between the channel layer 22 and the source / drain structure 23, thereby improving the overall performance of the memory device.

[0083] As an example, see Figure 13 The material of the buffer layer 24 is selected from palladium, cadmium, titanium, aluminum, silver, and combinations thereof, and also includes cobalt, copper, indium tin oxide (ITO), and the like. The work function of graphene is 4.5 eV, the work function of cadmium is 4.07 eV, the work function of titanium is 4.3 eV, the work function of aluminum is 4.28 eV, the work function of silver is 4.26 eV, the work function of cobalt is 5.0 eV, the work function of copper is 4.65 eV, and the work function of indium tin oxide is 4.8 eV. The work functions of the above materials are all between the work function of the channel layer 22 and the work function of the source / drain structure 23, and can prevent the material molecules in the source / drain structure 23 from diffusing into the channel layer 22. It should be noted that the materials of the buffer layer 24 include but are not limited to the above-mentioned materials, and other materials can be selected according to needs, but it is necessary to ensure that the work function of the buffer layer 24 is greater than the work function of the source / drain structure 23 and less than the work function of the channel layer 22, and it can prevent the material molecules in the channel layer 22 or the source / drain structure 23 from diffusing into each other, so as to reduce the contact resistance while extending the service life of the semiconductor structure and improving the yield of the semiconductor device.

[0084] In step S10, refer to Figure 9 Step S10 and Figure 7, a source / drain structure 23 is formed on the side of the buffer layer 24 away from the channel layer 22 along the second direction (for example, the ox direction); the buffer layer 24 is located between the channel layer 22 and the source / drain structure 23, serving as a connecting layer and a barrier layer therebetween, thereby improving the problem of work function mismatch between the source / drain structure 23 and the channel layer 22, resulting in a large contact resistance. At the same time, the introduction of the buffer layer 24 material can also prevent material molecules in the source / drain structure 23 from diffusing into the channel layer 22, thereby extending the service life of the device.

[0085] As an example, see Figure 8 After forming the source / drain structure 23 in step S10, the method may further include:

[0086] Step S12 : forming a second gate structure 25 on a side of the channel layer 22 away from the first gate structure 21 along a first direction (eg, oy direction); wherein the first gate structure 21 and the second gate structure 25 share the channel layer 22 .

[0087] In step S12, the following steps may also be included:

[0088] Step S121 : forming a second gate dielectric layer 251 on a side of the channel layer 22 away from the first gate structure 21 along a first direction (eg, oy direction);

[0089] Step S122 : forming a second gate conductive layer 252 on a side of the second gate dielectric layer 251 away from the first gate structure 21 along the first direction (eg, the oy direction).

[0090] In step S121, please continue to refer to Figure 8 The second gate dielectric layer 251 may cover the channel layer 22 , the buffer layer 24 and the source / drain structure 23 away from the surface of the substrate 20 along the first direction (eg, oy direction) to isolate the second gate conductive layer 252 from the channel layer 22 .

[0091] In step S122, please continue to refer to Figure 8 The length of the second gate conductive layer 252 along the second direction (for example, the ox direction) is greater than or equal to the length of the channel layer 22 along the second direction (for example, the ox direction), so that during operation of the semiconductor device, the voltage of the second gate conductive layer 252 can jointly control the conductivity of the channel layer 22 with the voltage of the first gate conductive layer 211.

[0092] It should be understood that, unless otherwise expressly stated herein, the steps described are not strictly limited in order of execution, and the steps may be executed in other orders. Furthermore, at least a portion of the steps described may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but may be executed at different times. The sub-steps or stages are not necessarily executed sequentially, but may be executed in rotation or alternation with other steps or at least a portion of the sub-steps or stages of other steps.

[0093] In the semiconductor structure and preparation method thereof in the above-mentioned embodiment, by arranging the buffer layer between the channel layer and the source / drain structure in a single-gate or double-gate structure, not only the problem of large contact resistance between the channel layer and the source / drain structure can be improved, but also the metal material molecules in the source / drain structure can be blocked from diffusing into the channel layer, and the channel layer can be prevented from contacting the source / drain structure, thereby reducing or even eliminating the interface damage of the channel layer. The above-mentioned structure improves the problem of direct contact between the channel and the source / drain in the traditional technology, which causes the contact surface between the channel and the source / drain to be damaged, reduces the damage to the channel layer, and improves the service life of the channel layer. In addition, in the traditional technology, due to the mismatch between the work function of the channel and the source / drain, the contact resistance between the two will also increase. The present disclosure can reduce the contact resistance between the channel layer and the source / drain structure, thereby improving the yield of the semiconductor structure.

[0094] Please note that the above embodiments are for illustrative purposes only and are not intended to limit the present disclosure.

[0095] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0096] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0097] The above embodiments merely illustrate several implementations of the present disclosure, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the disclosed patent. It should be noted that a person of ordinary skill in the art would be able to make numerous variations and improvements without departing from the scope of the present disclosure, all of which fall within the scope of protection of the present disclosure. Therefore, the scope of protection of the disclosed patent shall be determined by the appended claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate; forming a first gate structure on a top surface of the substrate; forming a channel layer on a side of the first gate structure away from the substrate along a first direction; forming a buffer layer on two opposite sides of the channel layer along the second direction; A source / drain structure is formed on a side of the buffer layer away from the channel layer along the second direction; the buffer layer is located between the channel layer and the source / drain structure; wherein the first direction intersects with the second direction.

2. The method for preparing a semiconductor structure according to claim 1, wherein: The work function of the buffer layer is greater than the work function of the source / drain structure and smaller than the work function of the channel layer.

3. The method for preparing a semiconductor structure according to claim 2, wherein: The work function range of the buffer layer is (4.5 eV, 5.7 eV).

4. The method for preparing a semiconductor structure according to claim 3, wherein: The material of the buffer layer is selected from palladium, cadmium, titanium, aluminum, silver and combinations thereof.

5. The method for preparing a semiconductor structure according to any one of claims 1 to 4, wherein: After forming the source / drain structure, the method further includes: A second gate structure is formed on a side of the channel layer away from the first gate structure along the first direction; wherein the first gate structure and the second gate structure share the channel layer.

6. A semiconductor structure, prepared by the preparation method according to any one of claims 1 to 5, characterized in that: include: substrate; a first gate structure, located on the top surface of the substrate; a channel layer, located on a side of the first gate structure away from the substrate along a first direction; a source / drain structure located on two opposite sides of the channel layer along the second direction; The buffer layer is located on two opposite sides of the channel layer along the second direction and between the channel layer and the source / drain structure; wherein the first direction intersects with the second direction.

7. The semiconductor structure according to claim 6, wherein: The work function of the buffer layer is greater than the work function of the source / drain structure and smaller than the work function of the channel layer.

8. The semiconductor structure according to claim 7, wherein: The work function range of the buffer layer is (4.5 eV, 5.7 eV).

9. The semiconductor structure according to claim 8, wherein: The material of the buffer layer is selected from palladium, cadmium, titanium, aluminum, silver and combinations thereof.

10. The semiconductor structure according to any one of claims 6 to 9, characterized in that: The first gate structure includes: a first gate dielectric layer, located between the substrate and the channel layer, between the substrate and the source / drain structure, and between the substrate and the buffer layer; The first gate conductive layer is located on the top surface of the substrate and inside the first gate dielectric layer.

11. The semiconductor structure according to claim 10, wherein: A length of the first gate conductive layer along the second direction is greater than or equal to a length of the channel layer along the second direction.

12. The semiconductor structure according to claim 10, wherein: Also includes: The second gate structure is located on a side of the channel layer away from the first gate structure along the first direction; wherein the first gate structure and the second gate structure share the channel layer.

13. The semiconductor structure according to claim 12, wherein: The second gate structure includes: a second gate dielectric layer, located on a side of the channel layer away from the first gate structure along the first direction, and covering a top surface of the channel layer, the source / drain structure, and the buffer layer; The second gate conductive layer is located on a side of the second gate dielectric layer away from the first gate structure along the first direction.

14. The semiconductor structure according to claim 13, wherein: A length of the second gate conductive layer along the second direction is greater than or equal to a length of the channel layer along the second direction.

15. The semiconductor structure according to any one of claims 6 to 9, characterized in that: The material of the channel layer is selected from indium gallium zinc oxide, indium zinc oxide, transition metal, transition metal oxide and a combination thereof.

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