Semiconductor device and method for manufacturing the same

Abstract

An embodiment of the present disclosure provides a semiconductor device and a method for preparing the same, wherein the semiconductor device includes: a substrate; the substrate includes at least a device region, and a stacking structure is formed on the surface of the substrate; a plurality of gates located in the device region; the stacking structure is penetrated along a third direction and arranged in an array along a first direction and a second direction; a plurality of isolation structures extending along the first direction and arranged at intervals along the second direction; the isolation structure is located between every two adjacent gates along the second direction; a plurality of first metal wires are arranged at intervals along the first direction and the second direction; each first metal wire is connected to two gates located on both sides of the isolation structure along the second direction; a plurality of second metal wires extend along the second direction and are arranged at intervals along the first direction; every two second metal wires arranged along the first direction are correspondingly connected to a column of first metal wires arranged in sequence along the second direction, and two adjacent first metal wires arranged in sequence along the second direction are connected to different second metal wires.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to, but not limited to, a semiconductor device and a method for manufacturing the same. Background Art

[0002] Flash memory devices can be categorized as NOR or NAND flash memory devices. NOR flash memory devices typically provide faster programming and reading speeds by connecting one terminal of each memory cell to ground and the other terminal to a bit line.

[0003] Using traditional fabrication methods, NOR and NAND flash memory devices are two-dimensional, with memory cells arranged in a two-dimensional array on a silicon substrate. However, two-dimensional structures have shown limitations, such as scaling constraints due to process and device limitations. Therefore, there is a need for increased research in the field of three-dimensional NOR devices. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same.

[0005] In a first aspect, an embodiment of the present disclosure provides a semiconductor device, including:

[0006] A substrate; the substrate includes at least a device region, and a stacked structure is formed on the surface of the substrate;

[0007] A plurality of gates are located in the device region, penetrate the stack structure along the third direction, and are arranged in an array along the first direction and the second direction;

[0008] a plurality of isolation structures extending along the first direction and arranged at intervals along the second direction; the isolation structure being located between every two adjacent gates along the second direction;

[0009] a plurality of first metal lines arranged at intervals along the first direction and the second direction; each of the first metal lines is connected to two gates located on both sides of the isolation structure along the second direction;

[0010] a plurality of second metal lines extending along the second direction and arranged at intervals along the first direction; every two second metal lines arranged along the first direction are connected to a row of first metal lines arranged sequentially along the second direction, and two adjacent first metal lines arranged sequentially along the second direction are connected to different second metal lines;

[0011] The first direction intersects with the second direction and is parallel to the plane where the substrate is located. The third direction intersects with the plane where the substrate is located.

[0012] In some embodiments, the substrate further includes a step region located on at least one side of the device region along the first direction, and the plurality of isolation structures extend into the step region along the first direction; the stacked structure includes at least insulating layers and conductive layers alternately arranged in a third direction; and the semiconductor device further includes:

[0013] A step structure is located in the step area; the step structure exposes each conductive layer.

[0014] In some embodiments, the gate includes a control layer and a charge storage layer located on a sidewall of the control layer; the semiconductor device further includes: a plurality of channel layers;

[0015] The channel layer is located at the bottom and sidewall of the charge storage layer; the channel layer, the charge storage layer and the control layer form a storage unit.

[0016] In some embodiments, further comprising a second mask layer, a first connection structure, and a second connection structure;

[0017] The second mask layer covers the step area and the device area;

[0018] The first connecting structure penetrates the second mask layer of the step region and is connected to the conductive layer exposed in the step region between any two adjacent isolation structures along the second direction;

[0019] The second connection structure passes through the second mask layer of the device region and is connected to the control layer and the first metal line.

[0020] In some embodiments, the method further includes: a third connection structure; the third connection structure is connected between the first metal line and the second metal line.

[0021] In a second aspect, an embodiment of the present disclosure provides a method for manufacturing a semiconductor device, the method comprising:

[0022] Providing a substrate, wherein the substrate includes at least a device region;

[0023] forming an initial stacking structure on the substrate, and a plurality of gates penetrating the initial stacking structure along a third direction and located in the device region; the plurality of gates are arranged in an array along the first direction and the second direction;

[0024] forming a plurality of isolation structures extending along the first direction and spaced apart in the second direction; wherein the isolation structure is located between every two adjacent gates along the second direction;

[0025] forming a plurality of first metal lines spaced apart along the first direction and the second direction; each of the first metal lines is connected to the two gates located on both sides of the isolation structure along the second direction;

[0026] forming a plurality of second metal lines extending along the second direction and arranged at intervals along the first direction; wherein every two second metal lines arranged along the first direction are correspondingly connected to a column of first metal lines arranged sequentially along the second direction, and two adjacent first metal lines arranged sequentially along the second direction are connected to different second metal lines;

[0027] The first direction intersects with the second direction and is parallel to the plane where the substrate is located. The third direction intersects with the plane where the substrate is located.

[0028] In some embodiments, the substrate further includes a step region located on at least one side of the device region along the first direction; the initial stack includes sacrificial layers and conductive layers alternately arranged along the third direction; after forming the initial stack structure and before forming the gate, the method includes:

[0029] forming a first mask layer on the initial stacked structure;

[0030] A multi-step etching process is adopted to etch the first mask layer and the step region along the third direction to form a step structure in the step region; the step structure exposes each conductive layer.

[0031] In some embodiments, forming a plurality of gates penetrating the initial stack structure includes:

[0032] forming a second mask layer covering the step area and the device area;

[0033] patterning the device region based on the second mask layer to form a plurality of first trenches extending along the third direction in the device region;

[0034] A charge storage layer and a control layer are sequentially formed in the first trench to form the gate.

[0035] In some embodiments, before forming the charge storage layer, a channel layer is formed on the inner wall and bottom of the first trench;

[0036] The channel layer, the charge storage layer, and the control layer form the memory cell.

[0037] In some embodiments, after forming the memory cell, the method further includes:

[0038] patterning the step region based on the second mask layer to form a first connection structure connected to each of the conductive layers between any two adjacent isolation structures along the second direction;

[0039] The device region is patterned based on the second mask layer to form a second connection structure connected to each of the control layers.

[0040] In some embodiments, forming a plurality of first metal lines spaced apart along the first direction and the second direction includes:

[0041] forming a first metal strip extending along the second direction; and connecting the first metal strip to a row of the second connection structures arranged in sequence along the second direction;

[0042] The first metal strip is etched to remove a portion of the first metal strip between every two second connection structures adjacent to each other along the second direction to form the first metal line.

[0043] In some embodiments, the method further comprises:

[0044] A plurality of third conductive pillars connected to the first metal line and the second metal line are formed; wherein the third conductive pillars spaced apart along the second direction are located on the same straight line extending along the second direction.

[0045] In some embodiments, the plurality of isolation structures extend along the first direction into the step region; forming a plurality of isolation structures extending along the first direction and spaced apart in the second direction, comprises:

[0046] patterning the device region and the step region based on the second mask layer to form a plurality of second trenches penetrating the second mask layer and the initial stacked structure; wherein the second trenches extend along the first direction and are arranged at intervals along the second direction;

[0047] The isolation structure is formed in the second trench.

[0048] In some embodiments, after forming the second trench, the method further includes:

[0049] removing the sacrificial layer through the second trench to form a third trench;

[0050] An insulating layer is formed in the third trench to form a stacked structure consisting of the conductive layer and the insulating layer; wherein the isolation structure and the insulating layer are formed in a one-step process.

[0051] In some embodiments, the step region located on one side of the device region includes i sub-regions arranged sequentially along the first direction; i is greater than or equal to 2; and a multi-step etching process is used to etch the first mask layer and the step region along the third direction to form a step structure in the step region, including:

[0052] forming a photoresist layer on the surface of the first mask layer; wherein the photoresist layer exposes a portion of the first mask layer on a side of the step region away from the device region;

[0053] The exposed first mask layer and the exposed sub-regions are etched through the photoresist layer so that after the i-th etching, the first conductive layer from top to bottom in the i-th sub-region is exposed, and the j+1-th conductive layer from top to bottom in the ij-th sub-region is exposed to form the step structure; wherein j=i-1; before the i-th etching, the photoresist layer used for the i-1-th time is trimmed so that the photoresist layer exposes the first i sub-regions.

[0054] The semiconductor device provided by the embodiment of the present disclosure includes at least a substrate in a device region; a stacked structure formed on the surface of the substrate; a plurality of gates located in the device region; a plurality of isolation structures extending along the first direction and spaced apart along the second direction; an isolation structure located between each two adjacent gates along the second direction; a plurality of first metal lines spaced apart along the first direction and the second direction; each first metal line connected to two gates located on either side of the isolation structure along the second direction; a plurality of second metal lines extending along the second direction and spaced apart along the first direction; each two second metal lines arranged along the first direction are connected to a row of first metal lines arranged in sequence along the second direction, and two adjacent first metal lines arranged in sequence along the second direction are connected to different second metal lines. Since the gate can be selected by the first metal lines and the second metal lines in the embodiment of the present disclosure, no additional top select gate needs to be prepared. This can increase the process window of the semiconductor device and reduce the manufacturing cost. The resistance at the interface between the top select gate and the gate can also be reduced, thereby reducing the power consumption of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In the accompanying drawings (which are not necessarily drawn to scale), like reference numerals may describe similar components in different views. Like reference numerals with different letter suffixes may represent different examples of similar components. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation.

[0056] Figure 1 A schematic flow chart of a method for forming a semiconductor device according to an embodiment of the present disclosure;

[0057] Figures 2 to 29 A schematic structural diagram of the semiconductor device during the formation process provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0058] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0059] In the following description, numerous details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0060] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0061] It should be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Thus, a first element, component, region, layer, or portion discussed below could be represented as a second element, component, region, layer, or portion without departing from the teachings of the present disclosure. And when a second element, component, region, layer, or portion is discussed, it does not necessarily mean that the first element, component, region, layer, or portion is present.

[0062] The terminology used herein is for the purpose of describing specific embodiments only and is not intended to be limiting of the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, identify the presence of stated features, integers, steps, operations, elements and / or parts, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0063] As process nodes continue to shrink, two-dimensional NOR flash memory devices have shown their limitations, such as scaling limitations due to process and device limitations. Therefore, there is a need in the art to increase research on three-dimensional NOR devices.

[0064] Based on this, an embodiment of the present disclosure provides a semiconductor device and a preparation method thereof, wherein the semiconductor device includes: a substrate including at least a device area; a stacking structure formed on the surface of the substrate; a plurality of gates located in the device area; the stacking structure is penetrated along a third direction and arranged in an array along a first direction and a second direction; a plurality of isolation structures extending along the first direction and arranged at intervals along the second direction; the isolation structure is located between every two adjacent gates along the second direction; a plurality of first metal wires are arranged at intervals along the first direction and the second direction; each first metal wire is connected to two gates located on both sides of the isolation structure along the second direction; a plurality of second metal wires extend along the second direction and are arranged at intervals along the first direction; every two second metal wires arranged along the first direction are correspondingly connected to a column of first metal wires arranged in sequence along the second direction, and two adjacent first metal wires arranged in sequence along the second direction are connected to different second metal wires. The embodiments of the present disclosure can realize the preparation of a three-dimensional semiconductor device with high storage density; in addition, since the gate can be selected by the first metal wire and the second metal wire in the embodiments of the present disclosure, there is no need to prepare an additional top selection gate, thus increasing the process window of the semiconductor device and reducing the preparation cost; and reducing the resistance at the interface between the top selection gate and the gate, thereby reducing the power consumption of the semiconductor device.

[0065] Hereinafter, the semiconductor device and the method for forming the same in the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0066] Before introducing the embodiments of the present disclosure, the three directions for describing the three-dimensional structure that may be used in the following embodiments are defined. Taking the Cartesian coordinate system as an example, the three directions may include the X-axis, Y-axis, and Z-axis directions. The thickness direction of the substrate is defined as the third direction. In the plane where the substrate is located, two directions that intersect with each other (for example, perpendicular to each other) are defined as the first direction and the second direction. For example, the arrangement direction of the step area and the device area can be defined as the first direction. Here, the first direction can be, for example, the X-axis direction, the second direction can be, for example, the Y-axis direction, and the third direction can be, for example, the Z-axis direction. In the embodiments of the present disclosure, the first direction, the second direction, and the third direction can be perpendicular to each other in pairs. In other embodiments, the first direction, the second direction, and the third direction may not be perpendicular.

[0067] Figure 1 A schematic flow chart of a method for forming a semiconductor device according to an embodiment of the present disclosure is provided. Figures 2 to 29 This is a schematic diagram of the structure of the semiconductor device during the formation process provided by the embodiment of the present disclosure. Figures 2 to 29 The formation process of the semiconductor device provided by the embodiment of the present disclosure is described in detail.

[0068] like Figure 1 As shown, the method for forming a semiconductor device includes the following steps S101 to S105:

[0069] First, refer to Figure 1 and Figure 2 , perform step S101, provide a substrate 301, the substrate 301 includes at least a device area A.

[0070] The substrate 301 may be a silicon substrate, a germanium substrate, a silicon-germanium substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate. The substrate 301 may also include other elemental semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide, or silicon carbide. In other embodiments, the substrate 301 may also be an ion-doped substrate, such as a P-type doped substrate or an N-type doped substrate.

[0071] It should be noted that the device region A is used to form functional structures of the semiconductor device, such as channels, word lines and other structures.

[0072] In some embodiments, the substrate 301 further includes a step region S located on at least one side of the device region A along the X-axis. The step region S is used to implement the extraction of electrical signals from the device region A. The number of step regions S can be one, two, or more. In the embodiment of the present disclosure, two step regions S are used as an example for subsequent description.

[0073] Next, continue to refer to Figure 1、 Figures 3 to 18 , perform step S102 to form an initial stacking structure 303 and a plurality of gates 600 penetrating the initial stacking structure 303 along a third direction and located in the device area A on the substrate 301; the plurality of gates 600 are arranged in an array along the first direction and the second direction.

[0074] In some embodiments, the initial stacked structure 303 includes sacrificial layers 3031 and conductive layers 3032 alternately arranged along the Z-axis direction.

[0075] During implementation, sacrificial material and conductive material are sequentially and cyclically deposited on the surface of substrate 301 to form a cyclically alternating stack of sacrificial layer 3031 and conductive layer 3032. The sacrificial material can be any material that is easier to remove than the conductive material, such as SiGe; and the conductive material can be any material with good conductivity, such as polysilicon.

[0076] In the embodiment of the present disclosure, the sacrificial layer 3031 and the conductive layer 3032 can be formed by a chemical vapor deposition process (CVD), a physical vapor deposition process (PVD), an atomic layer deposition (ALD), a spin coating process, a coating process or a furnace tube process.

[0077] It should be noted that the conductive layer 3032 can serve as a source or drain of a transistor in a semiconductor device, and the sacrificial layer 3031 can be removed later to form an isolation structure that isolates adjacent conductive layers 3032 to prevent transistor short circuit.

[0078] It should also be noted that Figure 3 The initial stacking structure 303 shown in FIG. 3 includes five layers of cyclically stacked sacrificial layers 3031 and conductive layers 3032 . In actual manufacturing, the initial stacking structure 303 may include more layers of cyclically stacked sacrificial layers 3031 and conductive layers 3032 .

[0079] In some embodiments, see Figure 3 After forming the initial stacking structure 303 , the method for preparing the semiconductor device further includes: sequentially forming an initial top spacer layer 304 a and an initial top sacrificial layer 305 a on the surface of the initial stacking structure 303 .

[0080] In some embodiments, the method for forming a semiconductor device further includes patterning the initial top sacrificial layer 305a and the initial top spacer layer 304a to form Figure 5 A top sacrificial layer 305 and a top spacer layer 304 are shown.

[0081] During implementation, a layer such as the following is formed on the surface of the initial top sacrificial layer 305a: Figure 4 The first photoresist layer 306 is shown, and the first photoresist layer 306 exposes the step area S. The initial top sacrificial layer 305a and the initial top spacer 304a are etched through the first photoresist layer 306 to remove the initial top sacrificial layer 305a and the initial top spacer 304a on the surface of the step area S. The remaining initial top sacrificial layer 305a and the initial top spacer 304a are formed as shown in FIG. Figure 5 A top sacrificial layer 305 and a top spacer layer 304 are shown.

[0082] In some embodiments, after forming the top sacrificial layer 305 and the top spacer layer 304 , the method for preparing a semiconductor device further includes: removing the first photoresist layer 306 , for example, by wet etching.

[0083] In some embodiments, after forming the top sacrificial layer 305 and the top spacer layer 304 , the method for preparing a semiconductor device further includes the following steps:

[0084] Step 1: Form the following on the initial stacking structure 303: Figure 5 and Figure 6 A first mask layer 400 is shown.

[0085] It should be noted that the first mask layer 400 is formed on the surface of the top sacrificial layer 305 and covers both the step region S and the device region A. The first mask layer 400 is used as a mask for etching the initial stacked structure 303 to form a step structure 500 in the step region S in subsequent processes.

[0086] The material of the first mask layer 400 may be a spin-on hard mask.

[0087] It should also be noted that the embodiments of the present disclosure Figure 5 It is a schematic diagram of a three-dimensional structure during the formation of a semiconductor device, and all XZ plane diagrams shown in the drawings of this disclosure are cross-sectional views along aa' in the three-dimensional view.

[0088] Step 2: A multi-step etching process is used to etch the first mask layer 400 and the step region S along the Z-axis direction to form a step structure 500 in the step region S; the step structure 500 exposes each conductive layer 3032 .

[0089] In some embodiments, the step region S located on one side of the device region A includes i sub-regions sequentially arranged along the X-axis direction; i is a positive integer greater than or equal to 2.

[0090] It should be noted that the specific value of i is related to the number of layers of the cyclically stacked sacrificial layer 3031 and the conductive layer 3032 in the initial stacking structure 303. For example, when the initial stacking structure 303 includes 5 layers of cyclically stacked sacrificial layers 3031 and the conductive layer 3032, i can be 5. Figure 7 The five sub-areas shown in FIG are sub-area X1, sub-area X2, sub-area X3, sub-area X4 and sub-area X5.

[0091] In some embodiments, step 2 may include the following steps:

[0092] On the surface of the first mask layer 400, a Figure 7 The photoresist layer 307 is shown; the photoresist layer 307 exposes a portion of the first mask layer 400 on the side of the step region S away from the device region A.

[0093] It can be understood that the photoresist layer 307 also exposes a portion of the sub-region under the first mask layer 400 .

[0094] The exposed first mask layer 400 and the exposed sub-regions are etched through the photoresist layer 307 so that after the i-th etching, the first conductive layer 3032 from top to bottom in the i-th sub-region is exposed, and the j+1-th conductive layer 3032 from top to bottom in the ij-th sub-region is exposed, forming a step structure 500; wherein j=i-1.

[0095] Specifically, during the first etching process, the photoresist layer 307 exposes the first sub-region X1 (eg, Figure 7 As shown), and the first mask layer 400 on the surface of the first sub-region X1, the first mask layer 400 and the first sub-region X1 exposed by etching the photoresist layer 307, exposing the first conductive layer 3032 from top to bottom in the first sub-region X1 (as shown Figure 8 and Figure 9 shown).

[0096] In some embodiments, before the i-th etching, the photoresist layer 307 used for the (i-1)th etching is trimmed so that the first i sub-regions of the photoresist layer 307 are exposed.

[0097] For example, before the second etching, the photoresist layer 307 used in the first etching process is trimmed along the X-axis direction so that the photoresist layer 307 after the first trimming exposes the first two sub-regions (sub-region X1 and sub-region X2) of the step area S away from the device area A, and the first mask layer 400 located on the surface of the first two sub-regions. Next, the exposed first mask layer 400 and the first two sub-regions are etched for the second time using the photoresist layer 307 after the first trimming to expose the first conductive layer 3032 from top to bottom in the second sub-region (X2) and expose the second conductive layer 3032 from top to bottom in the first sub-region (X1). Next, the photoresist layer 307 used in the second etching process is trimmed along the X-axis direction, so that the photoresist layer 307 after the second trimming exposes the first three sub-regions (sub-region X1, sub-region X2 and sub-region X3) of the step region S away from the device region A, and the first mask layer 400 located on the surface of the first three sub-regions. Next, the exposed first mask layer 400 and the first three sub-regions are etched for the third time using the photoresist layer 307 after the second trimming, exposing the first conductive layer 3032 from top to bottom in the third sub-region (X3), exposing the second conductive layer 3032 from top to bottom in the second sub-region (X2), and exposing the third conductive layer 3032 from top to bottom in the first sub-region (X1), and so on, until a Figure 8 and Figure 9 A stepped structure 500 is shown.

[0098] It should be noted that, in order to more clearly illustrate the specific structure of the step structure 500, Figure 9 Only the step region S and the step structure 500 located on one side of the device region A are shown.

[0099] In some embodiments, after forming the stepped structure 500 , the method for forming a semiconductor device includes: removing the first mask layer 400 , and forming silicon dioxide on surfaces of the device region A and the stepped region S.

[0100] In some embodiments, forming a plurality of gates 600 penetrating the initial stack structure 303 may include the following steps:

[0101] Step 1: forming a second mask layer 308 covering the step region S and the device region A.

[0102] During implementation, silicon dioxide ( Figure 10 The second mask material is deposited on the surface of the film (not shown) to form a Figure 10Next, the second initial mask layer 308a and the top sacrificial layer 305 are subjected to chemical mechanical polishing (CMP) until the top surface of the top spacer layer 304 is exposed; Next, a second mask material is continuously deposited on the surface of the exposed top spacer layer 304 and the second initial mask layer 308a to form a second mask layer as shown in FIG. Figure 11 The second mask layer 308 is shown covering the step region S and the device region A. Here, the second mask material may be silicon dioxide.

[0103] It should be noted that, in the embodiment of the present disclosure, for example, a high-density plasma (HDP) process may be used to deposit the second mask material to form the second mask layer, so as to achieve higher film coverage quality.

[0104] It should also be noted that the top spacer layer 304 can serve as a part of the second mask layer 308 , and the top spacer layer 304 will not be shown separately in subsequent drawings.

[0105] Step 2: Patterning the device region A based on the second mask layer 308 to form a plurality of first trenches B in the device region A extending along the Z-axis direction.

[0106] During implementation, a film is formed on the surface of the second mask layer 308. Figure 12 and Figure 13 The second photoresist layer 309 is shown, wherein the second photoresist layer 309 includes a plurality of sub-patterns arranged in an array, each sub-pattern exposing a portion of the device area A; Next, the second mask layer 308 and the initial stacked structure 303 are sequentially etched through the second photoresist layer 309 until the substrate 301 is exposed, forming a Figure 14 The first trench B shown penetrates the initial stack structure 303 and extends along the Z-axis direction.

[0107] In some embodiments, after forming the first trench B, the second photoresist layer 309 is removed.

[0108] Step 3: In the first trench B, the following are formed in sequence: Figure 17 The charge storage layer 61 and the control layer 62 are shown to form a gate 600 .

[0109] In some embodiments, before forming the charge storage layer 61, the method for forming a semiconductor device further includes: forming a plurality of layers on the inner wall and bottom of the first trench B as shown in FIG. Figure 16 The channel layer 700 shown; the channel layer 700, the charge storage layer 61 and the control layer 62 form a memory cell.

[0110] During implementation, a channel material is deposited on the inner wall of the first trench B and the surface of the second mask layer 308 to form a channel material. Figure 15 The initial channel layer 700a is shown; the initial channel layer 700a is etched to remove the initial channel layer 700a located on the surface of the second mask layer 308, forming Figure 16 The channel layer 700 is shown located on the sidewalls and bottom of the first trench B. Here, the channel material can be polysilicon or metal oxide.

[0111] In some embodiments, please refer to Figure 17 and Figure 18 The charge storage layer 61 includes a tunneling layer 611, a storage layer 612, a first blocking layer 613, and a second blocking layer 614 stacked in sequence along the surface of the channel layer 700. The tunneling layer 611, the storage layer 612, the first blocking layer 613, and the second blocking layer 614 can be divided into a silicon dioxide layer, a silicon nitride layer, a silicon dioxide layer, and an HK dielectric layer. The control layer 62 fills the gap within the first trench B.

[0112] It should be noted that Figure 18 for Figure 17 Magnified view of the structure within the square dashed box.

[0113] During implementation, a tunneling material, a storage material, a first barrier material, a second barrier material, and a gate electrode material are sequentially deposited on the surface of the channel layer 700 in the first trench B to form a tunneling layer 611, a storage layer 612, a first barrier layer 613, a second barrier layer 614, and a control layer 62, respectively. Here, the tunneling material can be silicon dioxide; the storage material can be silicon nitride; the first barrier material can be silicon dioxide; and the second barrier material can be a high dielectric constant material (HK), such as lanthanum oxide (La2O3), aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), hafnium silicate (HfSiO x ) or zirconium oxide (ZrO2) or any combination thereof; the gate electrode material can be any material with good conductivity, such as cobalt, titanium, tungsten, titanium nitride, etc.

[0114] In other embodiments, the gate 600 may further include a gate dielectric layer (not shown) located between the second barrier layer 614 and the control layer 62 .

[0115] It should be noted that the channel layer 700 , the charge storage layer 61 and the control layer 62 form a memory cell, and the memory cell in the embodiment of the present disclosure is a charge trapping memory cell.

[0116] Next, refer to Figure 1 、 Figures 19 to 21, executing step S103 to form a plurality of isolation structures 310 extending along the first direction and spaced apart in the second direction; the isolation structure 310 is located between every two adjacent gates 600 along the second direction.

[0117] In some embodiments, step S103 may include the following steps:

[0118] The device region A and the step region S are patterned based on the second mask layer 308 to form a plurality of second trenches C penetrating the second mask layer 308 and the initial stacking structure 303 ; wherein the second trenches C extend along the X-axis direction and are spaced apart along the Y-axis direction.

[0119] During implementation, a film is formed on the surface of the second mask layer 308. Figure 19 The third photoresist layer 311 shown in FIG. 3 includes a plurality of sub-patterns spaced apart along the Y-axis direction and extending along the X-axis direction. Each sub-pattern exposes the device area A and the step area S. The second mask layer 308 and the initial stacked structure 303 are sequentially etched through the third photoresist layer 311 to form a device region A and a step region S. Figure 19 and Figure 20 The second groove C is shown.

[0120] An isolation structure 310 is formed in the second trench C.

[0121] During implementation, an isolation material is deposited in the second trench C to form Figure 21 The isolation structure 310 is shown. The isolation material can be any insulating material, such as silicon dioxide.

[0122] It should be noted that all YZ planes shown in the drawings of this disclosure are Figure 19 The three-dimensional view shown is a cross-sectional view along c-c' and will not be specifically described later.

[0123] In some embodiments, after forming the second trench C, the method for forming a semiconductor device further includes:

[0124] The sacrificial layer 3031 is removed through the second trench C to form Figure 20 The third groove D shown;

[0125] In the third trench D, a Figure 21 The insulating layer 3033 is shown to form a stacked structure consisting of the conductive layer 3032 and the insulating layer 3033; wherein the isolation structure 310 and the insulating layer 3033 are formed in a one-step process.

[0126] It should be noted that since the formed second trench C passes through the initial stacking structure 303, the second trench C exposes the side wall of the sacrificial layer 3031 in the initial stacking structure 303. Therefore, the sacrificial layer 3031 can be removed by lateral wet etching of the second trench C to form a third trench D.

[0127] It should also be noted that the insulating layer 3033 and the isolation structure 310 are formed in a one-step deposition process, that is, the isolation material is deposited in the second trench C and the third trench D at the same time, forming the isolation structure 310 located in the second trench C and the insulating layer 3033 located in the third trench D.

[0128] In some embodiments, the plurality of isolation structures 310 extend into the step region S along the X-axis direction.

[0129] Next, refer to Figure 1 、 Figures 22 to 27 and Figure 29 , step S104 is performed to form a plurality of first metal lines 81 spaced apart along the first direction and the second direction; each first metal line 81 is connected to two gates 600 located on both sides of the isolation structure 310 along the second direction.

[0130] In some embodiments, before forming the first metal line 81 , the method for forming a semiconductor device further includes:

[0131] Based on the patterned step area S of the second mask layer 308, a first connection structure 81 connected to each conductive layer 3032 is formed between any two adjacent isolation structures 310 along the Y-axis direction; based on the patterned device area A of the second mask layer 308, a second connection structure 82 connected to each control layer 62 is formed.

[0132] It should be noted that the first connection structure 81 and the second connection structure 82 are formed simultaneously in the same process step.

[0133] During implementation, a third mask layer 314 and a fourth photoresist layer 315 are formed on the surface of the second mask layer 308. The fourth photoresist layer 315 includes a plurality of sub-patterns arranged in an array along the X-axis and Y-axis directions. Each sub-pattern exposes the third mask layer 312 of the device area A or the step area S. Next, the third mask layer 314 and the second mask layer 308 are sequentially etched through the fourth photoresist layer 315 to form a Figure 22 The first etching hole 81 a exposing the conductive layer 3032 and the second etching hole 82 a exposing the control layer 62 are shown.

[0134] The conductive layer 3032 exposed by the first etching hole 81a can be used as the source and drain of the transistor in the memory cell later. It can be understood that in the embodiment of the present disclosure, two adjacent memory cells arranged in sequence along the Z-axis share the source and drain (or conductive layer 3032).

[0135] Next, the following are formed at the bottoms of the first etching hole 81a and the second etching hole 82a: Figure 24 The metal silicide 316 shown is, for example, cobalt silicide (CoSi). Since the metal silicide 316 has a low resistance, it can reduce the contact resistance between the subsequently formed first connecting structure 81 and the conductive layer 3032, or between the second connecting structure 82 and the control layer 62, thereby reducing the power consumption of the semiconductor device.

[0136] Finally, a conductive material is deposited in the first etching hole 81a and the second etching hole 82a having the metal silicide 316 to form a Figure 24 The first connecting structure 81 and the second connecting structure 82 are shown. Here, the conductive material can be metal copper, cobalt, tungsten or titanium nitride.

[0137] In some embodiments, step S104 may include the following steps:

[0138] A first metal strip 90 a extending along the second direction is formed; the first metal strip 90 a is connected to the second connection structures 82 sequentially arranged along the second direction.

[0139] It should be noted that the first metal strip 90a is located on the surface of the second connection structure 82 and the second mask layer 308 in the device area A. During implementation, a metal material can be deposited on the top surface of the second mask layer 308 and the second connection structure 82 to form a first initial metal layer (not shown). Next, the first initial metal layer is patterned to form a Figure 25 The first metal strip 90a shown extends along the Y-axis direction; the first metal strip 90a is connected to a row of second connection structures 82 arranged in sequence along the Y-axis direction. Here, the metal material can be copper, tungsten, cobalt, nickel, etc.

[0140] The first metal strip 90a is etched to remove a portion of the first metal strip 90a between every two second connection structures 82 adjacent along the second direction, forming Figure 26 and Figure 29 A first metal line 90 is shown.

[0141] It should be noted that each first metal line 90 is connected to two gates 600 (ie, two second connection structures 82 ) located on both sides of the isolation structure 310 along the Y-axis direction.

[0142] In some embodiments, after forming the first metal line 90 , the method for forming a semiconductor device further includes:

[0143] A plurality of third conductive pillars 83 connected to the first metal line 90 are formed; wherein the third conductive pillars 83 arranged at intervals along the second direction are located on the same straight line extending along the second direction.

[0144] During implementation, a first dielectric layer is formed on the surface of the first metal line 90 and the second mask layer 308, and the first dielectric layer is patterned to form an etched hole exposing each first metal line 90, wherein the etched holes spaced apart along the Y-axis direction are located on the same straight line extending along the Y-axis direction; then, a conductive material is deposited in the etched holes to form a structure as shown in FIG. Figure 27 and Figure 29 The third conductive column 83 is shown.

[0145] Finally, reference Figure 1 、 Figure 28 and Figure 29 , execute step S105 to form a plurality of second metal wires 91 extending along the second direction and arranged at intervals along the first direction; every two second metal wires 91 arranged along the first direction are correspondingly connected to a column of first metal wires 90 arranged in sequence along the second direction, and two adjacent first metal wires 91 arranged in sequence along the second direction are connected to different second metal wires 92.

[0146] During implementation, a second initial metal layer is formed on the surface of the first dielectric layer and the third conductive pillar 83, and the second initial metal layer is patterned to form the following Figure 28 and Figure 29 A plurality of second metal lines 91 are shown extending along the Y-axis direction and arranged at intervals along the X-axis direction.

[0147] It should be noted that in the embodiment of the present disclosure, a row of first metal wires 90 arranged at intervals along the Y-axis direction can be connected through a second metal wire 91, and the first metal wire 90 is electrically connected to the gate 600 located on both sides of the isolation structure 310 along the Y-axis direction. In this way, a gate can be located through the second metal wire 91 and the first metal wire 90, and the gate 600 can be selected.

[0148] In some embodiments, while forming the first metal line 90 , a third metal line connected to the first connection structure 81 may also be formed. The third metal line may be a bit line or a source line.

[0149] The method for forming a semiconductor device provided in the embodiment of the present disclosure can realize the preparation of a three-dimensional semiconductor device with high storage density; in addition, since the gate can be selected by the first metal wire and the second metal wire in the embodiment of the present disclosure, there is no need to prepare an additional top selection gate, thus increasing the process window of the semiconductor device and reducing the preparation cost; and reducing the resistance at the interface between the top selection gate and the gate, thereby reducing the power consumption of the semiconductor device.

[0150] Another embodiment of the present disclosure also provides a Figures 24 to 29 The semiconductor device shown in FIG. 1 may be a three-dimensional NOR gate flash memory device. Figures 24 to 29 , semiconductor devices include:

[0151] Substrate 301; the substrate 301 includes at least a device region A, and a stacked structure is formed on the surface of the substrate 301;

[0152] A plurality of gates 600 are located in the device region A, penetrate the stacked structure along the Z-axis direction, and are arranged in an array along the X-axis and the Y-axis directions;

[0153] A plurality of isolation structures 310 extending along the X-axis direction and spaced apart along the Y-axis direction; the isolation structure 310 is located between every two adjacent gates 600 along the Y-axis direction;

[0154] A plurality of first metal lines 90 are arranged at intervals along the X-axis and the Y-axis; each first metal line 91 is connected to two gates 600 located on both sides of the isolation structure 310 along the Y-axis;

[0155] Multiple second metal wires 91 extend along the Y-axis direction and are arranged at intervals along the X-axis direction; every two second metal wires 92 arranged along the X-axis direction are correspondingly connected to a row of first metal wires 90 arranged in sequence along the Y-axis direction, and two adjacent first metal wires 90 arranged in sequence along the Y-axis direction are connected to different second metal wires 91.

[0156] In some embodiments, see Figures 24 to 29 The substrate 301 also includes a step region S located on at least one side of the device region A along the first direction, and multiple isolation structures 310 extend into the step region S along the X-axis direction; the stacked structure includes at least insulating layers 3031 and conductive layers 3032 alternately arranged in the Z-axis direction; the semiconductor device also includes: a step structure 500, located in the step region S; the step structure 500 exposes each layer of the conductive layer 3032.

[0157] In some embodiments, see Figure 24The gate 600 includes a control layer 62 and a charge storage layer 61 located on the sidewalls of the control layer 62; the semiconductor device further includes: a plurality of channel layers 700; the channel layer 700 is located at the bottom and sidewalls of the charge storage layer 61; the channel layer 700, the charge storage layer 61 and the control layer 62 form a storage unit.

[0158] In some embodiments, see Figure 18 The charge storage layer 61 includes a tunneling layer 611 , a storage layer 612 , a first blocking layer 613 and a second blocking layer 614 stacked in sequence along the surface of the channel layer 700 .

[0159] In some embodiments, see Figure 24 The semiconductor device also includes a second mask layer 308, a first connection structure 81 and a second connection structure 82; the second mask layer 308 covers the step area S and the device area A; the first connection structure 81 penetrates the second mask layer 308 of the step area S and is connected to the conductive layer 3032 exposed in the step area S between any two adjacent isolation structures 310 along the Y-axis direction; the second connection structure 82 penetrates the second mask layer 308 of the device area A and is connected to the control layer 62 and the first metal wire 90.

[0160] In some embodiments, see Figures 27 to 29 The semiconductor device further includes: a third connection structure 83 ; the third connection structure 83 is connected between the first metal wire 91 and the second metal wire 91 .

[0161] It should be noted that the second metal line 91 and the first metal line 90 in the embodiment of the present disclosure can be regarded as word lines for realizing gate selection.

[0162] In some embodiments, the semiconductor device further includes a third metal line connected to the first connection structure 81 , where the third metal line may be a bit line or a source line.

[0163] It should be noted that the semiconductor device in the embodiment of the present disclosure is prepared by the preparation method of the semiconductor device in the above embodiment, and has a structure similar to the semiconductor device in the above embodiment. For the technical features not fully disclosed in the embodiment of the present disclosure, please refer to the above embodiment for understanding, and no further details will be given here.

[0164] The semiconductor device provided by the embodiment of the present disclosure has a high storage density on the one hand, and on the other hand, since there is no top selection gate in the semiconductor device, the resistance at the interface between the top selection gate and the gate can be reduced, thereby making the power consumption of the formed semiconductor device smaller.

[0165] In the several embodiments provided in this disclosure, it should be understood that the disclosed structures and methods can be implemented in non-targeted ways. The structural embodiments described above are merely illustrative. For example, the division of units is merely a logical functional division. In actual implementation, there may be other division methods, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the components shown or discussed are coupled or directly coupled to each other.

[0166] The features disclosed in several method or structural embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments or structural embodiments.

[0167] The above are only some embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by any person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A semiconductor device, characterized in that: include: A substrate; the substrate includes at least a device region, and a stacked structure is formed on the surface of the substrate; a plurality of gates located in the device region; penetrating the stacked structure along the third direction and arranged in an array along the first direction and the second direction; a plurality of isolation structures extending along the first direction and arranged at intervals along the second direction; The isolation structure is located between every two adjacent gates along the second direction; a plurality of first metal wires arranged at intervals along the first direction and the second direction; Each of the first metal lines is connected to two of the gates located on both sides of the isolation structure along the second direction; a plurality of second metal lines extending along the second direction and arranged at intervals along the first direction; every two second metal lines arranged along the first direction are connected to a row of first metal lines arranged sequentially along the second direction, and two adjacent first metal lines arranged sequentially along the second direction are connected to different second metal lines; The first direction intersects with the second direction and is parallel to the plane where the substrate is located. The third direction intersects with the plane where the substrate is located.

2. The semiconductor device according to claim 1, wherein The substrate further includes a step region located on at least one side of the device region along the first direction, and the plurality of isolation structures extend into the step region along the first direction; the stacked structure includes at least insulating layers and conductive layers alternately arranged in a third direction; The semiconductor device further includes: A step structure is located in the step area; the step structure exposes each conductive layer.

3. The semiconductor device according to claim 2, wherein The gate includes a control layer and a charge storage layer located on a sidewall of the control layer; the semiconductor device further includes: a plurality of channel layers; The channel layer is located at the bottom and sidewall of the charge storage layer; the channel layer, the charge storage layer and the control layer form a storage unit.

4. The semiconductor device according to claim 3, wherein Also comprising a second mask layer, a first connection structure and a second connection structure; The second mask layer covers the step area and the device area; The first connecting structure penetrates the second mask layer of the step region and is connected to the conductive layer exposed in the step region between any two adjacent isolation structures along the second direction; The second connection structure passes through the second mask layer of the device region and is connected to the control layer and the first metal line.

5. The semiconductor device according to any one of claims 1 to 4, wherein: Also includes: a third connecting structure; The third connection structure is connected between the first metal line and the second metal line.

6. A method for preparing a semiconductor device, characterized in that: The method comprises: Providing a substrate, wherein the substrate includes at least a device region; forming an initial stacking structure on the substrate, and a plurality of gates penetrating the initial stacking structure along a third direction and located in the device region; the plurality of gates are arranged in an array along the first direction and the second direction; forming a plurality of isolation structures extending along the first direction and spaced apart in the second direction; wherein the isolation structure is located between every two adjacent gates along the second direction; forming a plurality of first metal lines spaced apart along the first direction and the second direction; each of the first metal lines is connected to the two gates located on both sides of the isolation structure along the second direction; forming a plurality of second metal lines extending along the second direction and arranged at intervals along the first direction; wherein every two second metal lines arranged along the first direction are correspondingly connected to a column of first metal lines arranged sequentially along the second direction, and two adjacent first metal lines arranged sequentially along the second direction are connected to different second metal lines; The first direction intersects with the second direction and is parallel to the plane where the substrate is located. The third direction intersects with the plane where the substrate is located.

7. The method according to claim 6, characterized in that The substrate further includes a step region located on at least one side of the device region along the first direction; the initial stack includes sacrificial layers and conductive layers alternately arranged along the third direction; After forming the initial stack structure and before forming the gate, the method includes: forming a first mask layer on the initial stacked structure; A multi-step etching process is adopted to etch the first mask layer and the step region along the third direction to form a step structure in the step region; the step structure exposes each conductive layer.

8. The method according to claim 7, characterized in that forming a plurality of gates penetrating the initial stack structure, comprising: forming a second mask layer covering the step area and the device area; patterning the device region based on the second mask layer to form a plurality of first trenches extending along the third direction in the device region; A charge storage layer and a control layer are sequentially formed in the first trench to form the gate.

9. The method according to claim 8, characterized in that Before forming the charge storage layer, forming a channel layer on the inner wall and bottom of the first trench; The channel layer, the charge storage layer, and the control layer form a memory cell.

10. The method according to claim 9, characterized in that After forming the memory cell, the method further includes: patterning the step region based on the second mask layer to form a first connection structure connected to each of the conductive layers between any two adjacent isolation structures along the second direction; The device region is patterned based on the second mask layer to form a second connection structure connected to each of the control layers.

11. The method according to claim 10, characterized in that Forming a plurality of first metal lines spaced apart along the first direction and the second direction, comprising: forming a first metal strip extending along the second direction; and connecting the first metal strip to a row of the second connection structures arranged in sequence along the second direction; The first metal strip is etched to remove a portion of the first metal strip between every two second connection structures adjacent to each other along the second direction to form the first metal line.

12. The method according to claim 11, characterized in that The method further comprises: A plurality of third conductive pillars connected to the first metal line and the second metal line are formed; wherein the third conductive pillars spaced apart along the second direction are located on the same straight line extending along the second direction.

13. The method according to any one of claims 8 to 12, characterized in that The plurality of isolation structures extend along the first direction into the step area; forming a plurality of isolation structures extending along the first direction and spaced apart in the second direction, including: patterning the device region and the step region based on the second mask layer to form a plurality of second trenches penetrating the second mask layer and the initial stacked structure; wherein the second trenches extend along the first direction and are arranged at intervals along the second direction; The isolation structure is formed in the second trench.

14. The method according to claim 13, characterized in that After forming the second trench, the method further includes: removing the sacrificial layer through the second trench to form a third trench; An insulating layer is formed in the third trench to form a stacked structure consisting of the conductive layer and the insulating layer; wherein the isolation structure and the insulating layer are formed in a one-step process.

15. The method according to claim 7, characterized in that The step region located on one side of the device region includes i sub-regions arranged sequentially along the first direction; i is greater than or equal to 2; and a multi-step etching process is used to etch the first mask layer and the step region along the third direction to form a step structure in the step region, including: forming a photoresist layer on the surface of the first mask layer; wherein the photoresist layer exposes a portion of the first mask layer on a side of the step region away from the device region; The exposed first mask layer and the exposed sub-regions are etched through the photoresist layer so that after the i-th etching, the first conductive layer from top to bottom in the i-th sub-region is exposed, and the j+1-th conductive layer from top to bottom in the ij-th sub-region is exposed to form the step structure; wherein j=i-1; before the i-th etching, the photoresist layer used for the i-1-th time is trimmed so that the photoresist layer exposes the first i sub-regions.

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