A power distribution circuit using an external PNP connector for integrated high voltage and high current.

Abstract

This invention discloses an integrated high-voltage, high-current power distribution circuit using an external PNP transistor, belonging to the field of analog circuit design. It includes a high-voltage LDO module, a current detector, a digital controller, a digital current converter, and an external PNP transistor. The output of the error amplifier is simultaneously connected to the gates of MOSFET PM1 and PM2. The drain of MOSFET PM2 is connected to the input of the current detector, which is connected to a rise-fall counter in the digital controller. The rise-fall counter is connected to a digital-to-analog converter in the digital current converter, which is connected to a transconductance amplifier. The output of the transconductance amplifier is connected to the gate of MOSFET NM1, and the drain of MOSFET NM1 is connected to the base of transistor Q1 in the external PNP transistor. This invention achieves an integrated power distribution scheme by connecting an external PNP transistor and an LDO chip in parallel, achieving optimal results in power distribution and board area optimization. It has a simple structure, low cost, and well meets current needs.

Description

Technical Field

[0001] This invention relates to the field of analog circuit design, specifically to a power distribution circuit that uses an external PNP connector to integrate high voltage and high current. Background Technology

[0002] High-voltage, high-current LDOs are voltage regulator chips that employ linear control methods. Compared to switching-mode regulators, they offer advantages such as low output voltage noise, fast response to load changes, and strong EMI immunity. However, for high-input-voltage applications, increased load current drastically increases power consumption. On one hand, high power consumption necessitates larger packages, occupying more PCB area, which contradicts the miniaturization demands of electronic devices. On the other hand, higher power consumption means higher chip surface temperatures, which severely impact chip reliability and lifespan. Typically, these chips include over-temperature protection circuits. Excessive internal temperature triggers this protection, causing the chip to lose its voltage regulation function. While the chip itself may not be damaged, this severely compromises the safe and reliable operation of the entire system.

[0003] In scenarios where high-voltage, high-current LDO chips are prone to over-temperature protection, system designers often need to use multiple chips operating in parallel, and also need to use power distribution chips. This will greatly increase the system's BOM cost and occupy more board space. Therefore, a technical solution that can achieve power distribution through integrated high-voltage, high-current circuitry is needed to meet the current requirements. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, the present invention aims to provide a power distribution circuit that integrates an external PNP connector with high voltage and high current, thereby solving the problems mentioned in the background art.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] A power distribution circuit using an external PNP to an integrated high-voltage, high-current circuit includes a high-voltage LDO module, a current detector, a digital controller, a digital current converter, and an external PNP. The high-voltage LDO module includes a built-in power generation circuit LDO, a reference voltage generation circuit Ref, a current generation circuit Bias, an error amplifier, MOSFETs PM1 and PM2, and resistors Rfb1 and Rfb2. The input terminal of the built-in power generation circuit LDO is connected to the power supply VIN, and the output terminal of the built-in power generation circuit LDO is connected to the input terminals of the reference voltage generation circuit Ref and the current generation circuit Bias. The output terminal of the current generation circuit Bias is connected to the input terminal of the error amplifier. The source input terminal is connected, and the output terminal of the reference voltage generation circuit Ref is connected to the positive input terminal of the error amplifier; the output terminal of the reference voltage generation circuit Ref outputs the reference voltage VREF; the output terminal of the error amplifier is simultaneously connected to the gate of MOSFET PM1 and the gate of MOSFET PM2, and the sources of MOSFET PM1 and PM2 are both connected to the power supply VIN; the drain of MOSFET PM1 is connected to one end of resistor Rfb1, and the other end of resistor Rfb1 is simultaneously connected to the negative input terminal of the error amplifier and one end of resistor Rfb2, with the other end of resistor Rfb2 grounded; the negative input terminal of the error amplifier is the voltage feedback VFB; the drain of MOSFET PM1 is the output voltage VOUT;

[0007] The drain of MOSFET PM2 is connected to the input terminal of the current detector, and the power input terminal of the current detector is connected to the reference voltage VREF; the current detector uses the sampled current ISEN to generate a logic control signal.

[0008] The digital controller includes a ramp counter; the two output terminals of the current detector are connected to the input terminals D_UP and D_DOWN of the ramp counter, respectively.

[0009] The digital current converter includes a digital-to-analog converter, a transconductance amplifier, a MOSFET NM1, and a resistor R3. The output terminal D2A_PDC of the boost counter is connected to the input terminal of the digital-to-analog converter. The output terminal VDAC of the digital-to-analog converter is connected to the positive input terminal of the transconductance amplifier. The negative input terminal of the transconductance amplifier is connected to the source of the MOSFET NM1. The negative input terminal of the transconductance amplifier is the voltage feedback VFB2. The output terminal of the transconductance amplifier is connected to the gate of the MOSFET NM1. The source of the MOSFET NM1 is connected to one end of the resistor R3, and the other end of the resistor R3 is grounded.

[0010] The external PNP transistor includes transistor Q1, the drain of MOSFET NM1 is connected to the base of transistor Q1, and the emitter of transistor Q1 is connected to the power supply VIN. The collector of transistor Q1 is connected to one end of resistor R5, the other end of resistor R5 is connected to the drain of MOSFET PM1, one end of capacitor Cout is connected to the drain of MOSFET PM1, the other end of capacitor Cout is grounded, and resistor Rload is connected in parallel across capacitor Cout.

[0011] As a further aspect of the present invention: the error amplifier includes MOS transistors M1, M2, M3, M4, M5, M6, PMR, and resistor Rka; the gate of MOS transistor M1 is connected to the reference voltage VREF, and the gate of MOS transistor M2 is connected to the voltage feedback VFB; the gate of MOS transistor M1 is the positive input terminal of the error amplifier, and the gate of MOS transistor M2 is the negative input terminal of the error amplifier; the sources of both MOS transistors M1 and M2 are connected to the output terminal of the current generation circuit Bias.

[0012] The drain of MOSFET M1 is connected to the drain, gate, and gate of MOSFET M3 and MOSFET M4. The drain of MOSFET M4 is connected to the drain and gate of MOSFET M2 and MOSFET M5. The drain of MOSFET M5 is connected to the source of MOSFET M6. The gate of MOSFET M6 is connected to the input terminal of the current generation circuit Bias. The drain of MOSFET M6 is connected to the drain and gate of MOSFET PMR and one end of resistor Rka. The other end of resistor Rka is connected to the power supply VIN. The source of MOSFET PMR is also connected to the power supply VIN. The gate of MOSFET PMR is the output terminal of the error amplifier.

[0013] As a further aspect of the present invention: the sources of MOS transistors M3, M4, and M5 in the error amplifier are all grounded.

[0014] As a further embodiment of the present invention: the current detector includes a first comparator CMP1, a second comparator CMP2, resistors R1 and R2. The negative input terminal of the first comparator CMP1 is connected to the drain of the MOSFET PM2, the positive input terminal of the first comparator CMP1 is connected to the reference voltage VREF, and the output terminal of the first comparator CMP1 is connected to the input terminal D_DOWN of the up-down counter. One end of resistor R1 is connected to the negative input terminal of the first comparator CMP1, and the other end of resistor R1 is connected to the positive input terminal of the second comparator CMP2 and one end of resistor R2. The negative input terminal of the second comparator CMP2 is connected to the reference voltage VREF, and the output terminal of the second comparator CMP2 is connected to the input terminal D_UP of the up-down counter. The other end of resistor R2 is grounded.

[0015] As a further aspect of the present invention: the ramp counter is a 4-bit ramp counter.

[0016] As a further aspect of the present invention: the digital-to-analog converter is a resistor divider formed by 15 resistors connected in series.

[0017] As a further aspect of the present invention: the transconductance amplifier includes MOSFETs PM11, PM12, PM13, PM14, NM11, NM12, NM13, and NM14; the gate of MOSFET PM11 is connected to the source of MOSFET NM1, and the gate of MOSFET PM11 is the negative input terminal of the transconductance amplifier; the gate of MOSFET PM12 is connected to the output terminal VDAC of the digital-to-analog converter, and the gate of MOSFET PM12 is the positive input terminal of the transconductance amplifier;

[0018] The source of MOSFET PM11 and the source of MOSFET PM12 are connected to the power supply VCC; the drain of MOSFET PM11 is also connected to the drain of MOSFET NM11, the gate of MOSFET NM11, and the gate of MOSFET NM13; the drain of MOSFET PM12 is also connected to the drain of MOSFET NM12, the gate of MOSFET NM12, and the gate of MOSFET NM14.

[0019] The drain of MOSFET NM13 is connected to the drain of MOSFET PM13, the gate of MOSFET PM13, and the gate of MOSFET PM14. The drain of MOSFET NM14 is connected to the drain of MOSFET PM14. The drain of MOSFET NM14 is connected to the gate of MOSFET NM1. The drain of MOSFET NM14 is the output terminal of the transconductance amplifier.

[0020] The source of MOSFET PM13 and the source of MOSFET PM14 are both connected to the power supply VCC.

[0021] As a further aspect of the present invention: the sources of MOS transistors NM11, NM12, NM13, and NM14 in the transconductance amplifier are all grounded.

[0022] Compared with the prior art, the beneficial effects of the present invention are:

[0023] This invention provides an integrated power distribution solution by connecting an external PNP transistor and an LDO chip in parallel. The core control functions are integrated into the LDO chip, requiring only one external PNP chip. This achieves optimal results in power distribution and board area optimization, with a simple structure and low cost, which well meets current needs. Attached Figure Description

[0024] Figure 1 The present invention discloses a system block diagram of a high-voltage, high-current power distribution circuit using an external PNP.

[0025] Figure 2 The present invention discloses a circuit schematic of an error amplifier in an integrated high-voltage, high-current power distribution circuit using an external PNP transistor.

[0026] Figure 3 This is a circuit diagram of a current detector in an integrated high-voltage, high-current power distribution circuit using an external PNP pin, as disclosed in an embodiment.

[0027] Figure 4 The present invention discloses a circuit schematic of a transconductance amplifier in an integrated high-voltage, high-current power distribution circuit using an external PNP pin.

[0028] Figure 5 The following is a waveform timing diagram of an embodiment of a power distribution circuit that uses an external PNP to integrate high voltage and high current.

[0029] The attached figures are labeled as follows: 1. Error amplifier; 2. Current detector; 3. Rise-fall counter; 4. Digital-to-analog converter; 5. Transconductance amplifier. Detailed Implementation

[0030] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0031] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installed," "equipped with," "connected," and "linked" should be interpreted broadly; for example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0032] Please see Figure 1-5 A power distribution circuit using an external PNP to integrate high voltage and high current includes a high voltage LDO module, a current detector 2, a digital controller, a digital current converter, and an external PNP.

[0033] The high-voltage LDO module includes a built-in power generation circuit LDO, a reference voltage generation circuit Ref, a current generation circuit Bias, an error amplifier 1, MOSFETs PM1 and PM2, resistors Rfb1 and Rfb2; the input terminal of the built-in power generation circuit LDO is connected to the power supply VIN, the output terminal of the built-in power generation circuit LDO is connected to the input terminals of the reference voltage generation circuit Ref and the current generation circuit Bias, the output terminal of the current generation circuit Bias is connected to the power input terminal of the error amplifier 1, and the output terminal of the reference voltage generation circuit Ref is connected to the positive input terminal of the error amplifier 1; the reference voltage generation circuit Ref... The output terminal outputs a reference voltage VREF; the output terminal of error amplifier 1 is simultaneously connected to the gate of MOSFET PM1 and the gate of MOSFET PM2, and the sources of MOSFET PM1 and PM2 are both connected to the power supply VIN; the drain of MOSFET PM1 is connected to one end of resistor Rfb1, and the other end of resistor Rfb1 is simultaneously connected to the negative input terminal of error amplifier 1 and one end of resistor Rfb2, with the other end of resistor Rfb2 grounded; the negative input terminal of error amplifier 1 is the voltage feedback VFB; the drain of MOSFET PM1 is the output voltage VOUT; MOSFET PM2 is the current sampling MOSFET; MOSFET PM1 is the main power MOSFET.

[0034] The drain of MOSFET PM2 is connected to the input terminal of current detector 2, and the power input terminal of current detector 2 is connected to the reference voltage VREF; current detector 2 uses the sampled current ISEN to generate a logic control signal.

[0035] The digital controller includes a ramp counter 3; the two output terminals of the current detector 2 are connected to the input terminals D_UP and D_DOWN of the ramp counter 3, respectively.

[0036] The digital current converter includes a digital-to-analog converter 4, a transconductance amplifier 5, a MOSFET NM1, and a resistor R3; the output terminal D2A_PDC of the rise-fall counter 3 is connected to the input terminal of the digital-to-analog converter 4, the output terminal VDAC of the digital-to-analog converter 4 is connected to the positive input terminal of the transconductance amplifier 5, the negative input terminal of the transconductance amplifier 5 is connected to the source of the MOSFET NM1, and the negative input terminal of the transconductance amplifier 5 is the voltage feedback VFB2; the output terminal of the transconductance amplifier 5 is connected to the gate of the MOSFET NM1, the source of the MOSFET NM1 is connected to one end of the resistor R3, and the other end of the resistor R3 is grounded;

[0037] The external PNP transistor includes transistor Q1, the drain of MOSFET NM1 is connected to the base of transistor Q1, and the emitter of transistor Q1 is connected to the power supply VIN. The collector of transistor Q1 is connected to one end of resistor R5, the other end of resistor R5 is connected to the drain of MOSFET PM1, one end of capacitor Cout is connected to the drain of MOSFET PM1, the other end of capacitor Cout is grounded, and resistor Rload is connected in parallel across capacitor Cout. The specific principle of the external PNP base drive circuit is as follows: the digital code in the digital controller is converted into an analog voltage (VDAC) through a digital-to-analog converter (DAC), and then the VDAC voltage is converted into the drive current (IDRV) of the external PNP base through an analog voltage-to-current converter (V2I).

[0038] The drain current of MOSFET PM1 is I LDO The drain current of MOSFET PM2 is I. SEN The drain input current of MOSFET NM1 is I. DRV The collector output current of transistor Q1 is I. PNP The current received at one end of capacitor Cout is I. load The output voltage of error amplifier 1 is Vg, and the output voltage of transconductance amplifier 5 is Vo2;

[0039] The power distribution control loop between the external PNP and LDO is implemented using a 4-bit (the number of bits can be increased to improve control accuracy) ramp-up counter. Each counter clock cycle is 64µs. The specific control principle is as follows: when the LDO load current reaches the PNP activation threshold (I... th(act)PNP When the external PNP transistor is in the ON state, the counter in the internal PNP controller starts counting up, and the internal digital current converter increases the PNP base current, thereby gradually increasing the output current of the external PNP transistor. When the external PNP current equals I... load - I th(act)PNP When the counter stops counting, the LDO and PNP currents remain constant, thus achieving power distribution between the LDO and the external PNP; as the external load current gradually decreases, the LDO output current exceeds I. th(deact)PNP At that time, the PNP current remains at I. load - I th(act)PNP The LDO output current gradually decreases following the decrease of the external load; when the LDO output current equals I... th(deact)PNP At that time, the LDO output current begins to maintain at I. th(deact)PNPAs the load current decreases, the counter in the PNP controller starts counting down, the internal digital current converter reduces the PNP base current, and thus the external PNP current begins to decrease in line with the decrease in load current. When the external PNP current equals I... load -I th(deact)PNP The internal counter stops counting, and the PNP output current remains unchanged; when the load current is lower than the PNP shutdown threshold (I... th(deact)PNP When the external PNP transistor is off, the output current of the LDO chip remains constant at I during periods of significant variation in the external load. th(deact)PNP ~I th(act)PNP Within this range, typically set at 30-60mA, the LDO chip's internal power consumption will remain low for high-voltage scenarios, with the main power consumption being handled by an external PNP device. Generally, the β of a PNP chip exhibits some variability, typically ranging from 50-500, which is suitable for this technical solution. Because the internal controller has limited current output capability, with a maximum current of only 4mA, when β is only 50, the external PNP's current output can only reach 200mA. A larger β results in a higher output current capability for the external PNP.

[0040] like Figure 2 As shown, the error amplifier 1 includes MOSFETs M1, M2, M3, M4, M5, M6, PMR, and resistor Rka; the gate of MOSFET M1 is connected to the reference voltage VREF, and the gate of MOSFET M2 is connected to the voltage feedback VFB; the gate of MOSFET M1 is the positive input terminal of error amplifier 1, and the gate of MOSFET M2 is the negative input terminal of error amplifier 1; the sources of MOSFETs M1 and M2 are both connected to the output terminal of the current generation circuit Bias.

[0041] The drain of MOSFET M1 is connected to the drain, gate, and gate of MOSFET M3 and MOSFET M4. The drain of MOSFET M4 is connected to the drain and gate of MOSFET M2 and MOSFET M5. The drain of MOSFET M5 is connected to the source of MOSFET M6. The gate of MOSFET M6 is connected to the input terminal of the current generation circuit Bias. The drain of MOSFET M6 is connected to the drain and gate of MOSFET PMR and one end of resistor Rka. The other end of resistor Rka is connected to the power supply VIN. The source of MOSFET PMR is also connected to the power supply VIN. The gate of MOSFET PMR is the output terminal of error amplifier 1. The sources of MOSFETs M3, M4, and M5 are all grounded.

[0042] Error amplifier 1 is used to detect the difference between the reference voltage VREF and the feedback voltage VFB to control the output adjustment transistor PM1. Sampling transistors PM2 and PM1 have the same gate-source connection, thus allowing the acquisition of the power transistor sampling current I. SEN The output voltage obtains the feedback voltage VFB through the resistor divider Rfb1 and Rfb2. The emitter of the external PNP transistor is at the same potential as the source of PM1. The collector is connected to the drain of the power transistor PM1 through the resistor RS to realize a parallel structure with the power transistor. The base of the external PNP transistor is provided with the base drive current through the internal VPNPDRV of the chip.

[0043] The current detector 2 includes a first comparator CMP1, a second comparator CMP2, resistors R1 and R2. The negative input terminal of the first comparator CMP1 is connected to the drain of the MOSFET PM2, the positive input terminal of the first comparator CMP1 is connected to the reference voltage VREF, and the output terminal of the first comparator CMP1 is connected to the input terminal D_DOWN of the boost counter 3. One end of resistor R1 is connected to the negative input terminal of the first comparator CMP1, and the other end of resistor R1 is connected to the positive input terminal of the second comparator CMP2 and one end of resistor R2. The negative input terminal of the second comparator CMP2 is connected to the reference voltage VREF, and the output terminal of the second comparator CMP2 is connected to the input terminal D_UP of the boost counter 3. The other end of resistor R2 is grounded.

[0044] Current detector 2 implements the power transistor current detection logic output. The sampling current generated by the high voltage LDO generates sampling voltages Vsen1 and Vsen2 through resistors R1 and R2. The first comparator CMP1 compares VREF and Vsen1. The output of the first comparator CMP1 is D_DOWN. A high level indicates that the load current (ILOAD) is lower than the PNP turn-off threshold (Ith(deact)PNP). The second comparator CMP2 compares Vsen2 and VREF. The output of the second comparator CMP2 is D_UP. A high level indicates that the load current is higher than the PNP turn-on threshold (Ith(act)PNP).

[0045] Ramp-up counter 3 is a 4-bit ramp-up counter that outputs the digital code D2A_PDC<3:0>. When D_UP=1 and D_DOWN=0, the counter is configured in asynchronous ramp-up mode, incrementing the counter output by 1 on each rising edge of the clock. When D_UP=0 and D_DOWN=1, the counter is configured in asynchronous ramp-down mode, decrementing the counter output by 1 on each rising edge of the clock. When D_UP=0 and D_DOWN=0, the counter clock is locked, counting stops, and the counter output retains its current state. Additionally, D_UP=1 and D_DOWN=1 indicate a system disabled state.

[0046] The digital-to-analog converter 4 is a resistor divider formed by 15 resistors connected in series, which divides the reference voltage into 16 reference voltages, and then generates the final output voltage VDAC through a 4-bit analog multiplexer.

[0047] The transconductance amplifier 5 includes MOSFETs PM11, PM12, PM13, PM14, NM11, NM12, NM13, and NM14; the gate of MOSFET PM11 is connected to the source of MOSFET NM1, and the gate of MOSFET PM11 is the negative input terminal of transconductance amplifier 5; the gate of MOSFET PM12 is connected to the output terminal VDAC of digital-to-analog converter 4, and the gate of MOSFET PM12 is the positive input terminal of transconductance amplifier 5;

[0048] The source of MOSFET PM11 and the source of MOSFET PM12 are connected to the power supply VCC; the drain of MOSFET PM11 is also connected to the drain of MOSFET NM11, the gate of MOSFET NM11, and the gate of MOSFET NM13; the drain of MOSFET PM12 is also connected to the drain of MOSFET NM12, the gate of MOSFET NM12, and the gate of MOSFET NM14.

[0049] The drain of MOSFET NM13 is connected to the drain of MOSFET PM13, the gate of MOSFET PM13, and the gate of MOSFET PM14. The drain of MOSFET NM14 is connected to the drain of MOSFET PM14. The drain of MOSFET NM14 is connected to the gate of MOSFET NM1. The drain of MOSFET NM14 is the output terminal of transconductance amplifier 5.

[0050] The source of MOSFET PM13 and the source of MOSFET PM14 are both connected to the power supply VCC.

[0051] The sources of MOSFETs NM11, NM12, NM13, and NM14 are all grounded.

[0052] Transconductance amplifier 5 locks the VFB2 voltage to VDAC, so the base drive current becomes the current on resistor R3, i.e., VDAC / R3. At this time, the collector current of the external PNP amplifies the base drive circuit by β times, realizing the power distribution between the power transistor and the external PNP.

[0053] Figure 5 In the power distribution timing diagram shown, when the load increases, I load > I th(act)PNP After, I LDO =I th(act)PNP The additional load current is provided by the PNP; when the load decreases, the PNP current remains constant, ILDO The current begins to decrease, when I LDO = I th(deact)PNP After, I LDO = I th(deact)PNP And remain unchanged, at which point the additional load current is provided by the PNP, when I load < I th(deact)PNP After that, the PNP current is 0, and the load current is provided by the LDO.

[0054] This invention provides an integrated power distribution solution by connecting an external PNP transistor and an LDO chip in parallel. The core control functions are integrated into the LDO chip, requiring only one external PNP chip. This achieves optimal results in power distribution and board area optimization, with a simple structure and low cost, which well meets current needs.

[0055] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered exemplary and not restrictive in all respects. The scope of the invention is defined by the appended claims rather than the foregoing description, and therefore all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0056] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A power distribution circuit using external PNP for integrated high voltage and high current, characterized by, The application relates to a high-voltage LDO module, a current detector (2), a digital controller, a digital current converter and an external PNP; the high-voltage LDO module comprises a built-in power supply generating circuit LDO, a reference voltage generating circuit Ref, a current generating circuit Bias, an error amplifier (1), MOS tubes PM1 and PM2, resistors Rfb1 and Rfb2; the input end of the built-in power supply generating circuit LDO is connected with a power supply VIN, the output end of the built-in power supply generating circuit LDO is connected with the input end of the reference voltage generating circuit Ref and the input end of the current generating circuit Bias, the output end of the current generating circuit Bias is connected with the power supply input end of the error amplifier (1), and the output end of the reference voltage generating circuit Ref is connected with the input positive end of the error amplifier (1); the output end of the reference voltage generating circuit Ref outputs a reference voltage VREF; the output end of the error amplifier (1) is connected with the gate of the MOS tube PM1 and the gate of the MOS tube PM2, the source of the MOS tube PM1 and the source of the MOS tube PM2 are connected with the power supply VIN; the drain of the MOS tube PM1 is connected with one end of the resistor Rfb1, the other end of the resistor Rfb1 is connected with the input negative end of the error amplifier (1) and one end of the resistor Rfb2, and the other end of the resistor Rfb2 is grounded; the input negative end of the error amplifier (1) is a voltage feedback VFB; the drain of the MOS tube PM1 is an output voltage VOUT; the drain of the MOS tube PM2 is connected with the input end of the current detector (2), and the power supply input end of the current detector (2) is connected with the reference voltage VREF; the current detector (2) generates a logic control signal by using a sampling current ISEN; the digital controller comprises a up-down counter (3); two output ends of the current detector (2) are connected with the input end D_UP and the input end D_DOWN of the up-down counter (3) respectively; the digital current converter comprises a digital-analog converter (4), a transconductance amplifier (5), a MOS tube NM1 and a resistor R3; the output end D2A_PDC of the up-down counter (3) is connected with the input end of the digital-analog converter (4), the output end VDAC of the digital-analog converter (4) is connected with the input positive end of the transconductance amplifier (5), the input negative end of the transconductance amplifier (5) is connected with the source of the MOS tube NM1, and the input negative end of the transconductance amplifier (5) is a voltage feedback VFB2; the output end of the transconductance amplifier (5) is connected with the gate of the MOS tube NM1, the source of the MOS tube NM1 is connected with one end of the resistor R3, and the other end of the resistor R3 is grounded; the external PNP comprises a transistor Q1, the drain of the MOS tube NM1 is connected with the base of the transistor Q1, and the emitter of the transistor Q1 is connected with the power supply VIN; one end of the resistor R5 is connected with the collector of the transistor Q1, the other end of the resistor R5 is connected with the drain of the MOS tube PM1, one end of the capacitor Cout is connected with the drain of the MOS tube PM1, the other end of the capacitor Cout is grounded, and the resistor Rload is connected in parallel with the capacitor Cout.

2. The power distribution circuit using external PNP for integrated high voltage and high current according to claim 1, wherein, The error amplifier (1) comprises MOS tubes M1, M2, M3, M4, M5, M6, MOS tube PMR and resistor Rka; the gate of the MOS tube M1 is connected with reference voltage VREF, and the gate of the MOS tube M2 is connected with voltage feedback VFB; the gate of the MOS tube M1 is the positive input terminal of the error amplifier (1), and the gate of the MOS tube M2 is the negative input terminal of the error amplifier (1); the source of the MOS tube M1 and the source of the MOS tube M2 are both connected with the output terminal of the current generating circuit Bias; The drain of the MOS tube M1 is connected with the drain of the MOS tube M3, the gate of the MOS tube M3 and the gate of the MOS tube M4, the drain of the MOS tube M4 is connected with the drain of the MOS tube M2 and the gate of the MOS tube M5, the drain of the MOS tube M5 is connected with the source of the MOS tube M6, the gate of the MOS tube M6 is connected with the input terminal of the current generating circuit Bias, the drain of the MOS tube M6 is connected with the drain of the MOS tube PMR, the gate of the MOS tube PMR and one end of the resistor Rka, the other end of the resistor Rka is connected with power supply VIN, and the source of the MOS tube PMR is also connected with the power supply VIN; the gate of the MOS tube PMR is the output terminal of the error amplifier (1).

3. The power distribution circuit of claim 2, wherein, The source of the MOS tube M3, the source of the MOS tube M4 and the source of the MOS tube M5 in the error amplifier (1) are grounded.

4. The power distribution circuit using external PNP for integrated high voltage and high current according to claim 3, wherein, The current detector (2) comprises first comparator CMP1, second comparator CMP2, resistor R1 and resistor R2, the input negative terminal of the first comparator CMP1 is connected with the drain of the MOS tube PM2, the input positive terminal of the first comparator CMP1 is connected with reference voltage VREF, and the output terminal of the first comparator CMP1 is connected with the input terminal D_DOWN of the up-down counter (3); one end of the resistor R1 is connected with the input negative terminal of the first comparator CMP1, the other end of the resistor R1 is connected with the input positive terminal of the second comparator CMP2 and one end of the resistor R2, the input negative terminal of the second comparator CMP2 is connected with reference voltage VREF, and the output terminal of the second comparator CMP2 is connected with the input terminal D_UP of the up-down counter (3); the other end of the resistor R2 is grounded.

5. The power distribution circuit using external PNP for integrated high voltage and high current according to claim 4, wherein, The up-down counter (3) is a 4-bit up-down counter.

6. The power distribution circuit using external PNP for integrated high voltage and high current according to claim 5, wherein, The digital-to-analog converter (4) is a resistor divider formed by 15 resistors in series.

7. A power distribution circuit using an external PNP connector for integrated high voltage and high current as described in claim 6, characterized in that, The transconductance amplifier (5) comprises MOS tubes PM11, PM12, PM13, PM14, NM11, NM12, NM13 and NM14; the gate of the MOS tube PM11 is connected with the source of the MOS tube NM1, and the gate of the MOS tube PM11 is the negative input terminal of the transconductance amplifier (5); the gate of the MOS tube PM12 is connected with the output terminal VDAC of the digital-to-analog converter (4), and the gate of the MOS tube PM12 is the positive input terminal of the transconductance amplifier (5); The source of the MOS transistor PM11 and the source of the MOS transistor PM12 are connected to the power supply VCC; the drain of the MOS transistor PM11 is connected to the drain of the MOS transistor NM11, the gate of the MOS transistor NM11 and the gate of the MOS transistor NM13; the drain of the MOS transistor PM12 is connected to the drain of the MOS transistor NM12, the gate of the MOS transistor NM12 and the gate of the MOS transistor NM14; The drain of the MOS transistor NM13 is connected to the drain of the MOS transistor PM13, the gate of the MOS transistor PM13 and the gate of the MOS transistor PM14; the drain of the MOS transistor NM14 is connected to the drain of the MOS transistor PM14; the drain of the MOS transistor NM14 is connected to the gate of the MOS transistor NM1; the drain of the MOS transistor NM14 is the output terminal of the transconductance amplifier (5); The source of the MOS transistor PM13 and the source of the MOS transistor PM14 are connected to the power supply VCC.

8. The power distribution circuit using external PNP for integrated high voltage and high current according to claim 7, wherein, The source of the MOS transistor NM11, the source of the MOS transistor NM12, the source of the MOS transistor NM13 and the source of the MOS transistor NM14 in the transconductance amplifier (5) are grounded.

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