A frequency modulation method, apparatus, electronic device, chip, and medium

Abstract

This disclosure provides a frequency adjustment method, apparatus, electronic device, chip, and medium, relating to the field of artificial intelligence chips. The method includes: determining first data and second data for one or more first operators, wherein the first data includes at least the energy required to execute the first operator, and the second data includes at least the time delay for executing the first operator; adjusting a first operating frequency of the chip to a second operating frequency based on the first data and the second data, thereby improving the chip's operating efficiency and reducing power consumption by dynamically adjusting the chip's operating frequency for each operator.

Description

Technical Field

[0001] This disclosure relates to the field of artificial intelligence chips, and more particularly to a frequency adjustment method, apparatus, electronic device, chip, and medium. Background Technology

[0002] Artificial intelligence (AI) chips are a core component of AI server computing power. Specifically designed for the field of artificial intelligence, their architecture and instruction sets are optimized for various algorithms and applications within AI, efficiently supporting intelligent processing tasks such as vision, speech, natural language processing, and traditional machine learning. With technological advancements and the rapid growth of AI computing power, AI chips are becoming increasingly integrated and complex, with correspondingly more powerful functions. Designing efficient chips is crucial during the chip development process to achieve low power consumption. Summary of the Invention

[0003] This disclosure provides a frequency adjustment method, apparatus, electronic device, chip, and medium to solve problems in related technologies. By dynamically adjusting the operating frequency of the chip for each operator, the chip's operating efficiency is improved and power consumption is reduced.

[0004] A first aspect of this disclosure provides a frequency adjustment method executed by a chip. The method includes: determining first data and second data for one or more first operators, wherein the first data includes at least the energy required to execute the first operator and the second data includes at least the time delay for executing the first operator; and adjusting a first operating frequency of the chip to a second operating frequency based on the first data and the second data.

[0005] In some embodiments of this disclosure, determining the first data and second data of one or more first operators includes: obtaining a first operand and a first utilization rate of the first operator based on a first parameter, wherein the first utilization rate is the utilization rate of executing the first operator to perform a second operation, the first parameter including AI model parameters and / or hardware parameters corresponding to the AI ​​model, and the first operator being at least one of the AI ​​model operators; determining a second operand corresponding to the first operator based on the first operand and the first utilization rate, wherein the second operand is the operand used to execute the first operator to perform a second operation, and the second operand is greater than or equal to the first operand; determining a third operand within a preset time period based on the first parameter, wherein the third operand is the operand used to execute the first operator to perform a second operation within the preset time period; and determining the first data and second data of the first operator based on the second operand and the third operand.

[0006] In some embodiments of this disclosure, determining the first data of the first operator based on the second operand and the third operand includes: determining the operating period of the first operator based on the second operand and the third operand; determining the running time of the first operator based on the first operating frequency and the operating period; determining the power of the first operator based on the first operating frequency and a first correspondence, wherein the first correspondence is the relationship between the operating frequency and voltage of the first operator; and determining the first data based on the power and running time of the first operator.

[0007] In some embodiments of this disclosure, determining the second data of the first operator based on the second operand and the third operand includes: determining the second data of the first operator based on the first operand, the first utilization rate, the third operand, and the first operating frequency.

[0008] In some embodiments of this disclosure, adjusting the first operating frequency of a chip to a second operating frequency based on the first data and the second data includes: determining a target state of the chip, and determining a first preset coefficient and a second preset coefficient based on the target state, wherein the target state includes either target performance or target power consumption; determining a frequency adjustment value of the chip based on the first preset coefficient, the second preset coefficient, the first data, and the second data; and adjusting the first operating frequency of the chip to the second operating frequency using the frequency adjustment value.

[0009] In some embodiments of this disclosure, determining the target state of the chip includes: determining the target state of the chip based on a first operator.

[0010] In some embodiments of this disclosure, adjusting the first operating frequency of the chip to the second operating frequency based on the first data and the second data includes: in response to a received frequency modulation command, adjusting the first operating frequency of the chip to the second operating frequency based on the first data and the second data.

[0011] A second aspect of this disclosure provides a frequency adjustment device applied to a chip. The device includes: a determining unit for determining first data and second data for one or more first operators, wherein the first data includes at least the energy required to execute the first operator and the second data includes at least the time delay for executing the first operator; and an adjusting unit for adjusting a first operating frequency of the chip to a second operating frequency based on the first data and the second data.

[0012] A third aspect of this disclosure provides a chip including one or more interface circuits and one or more processors; the processors are configured to perform the methods described in the first aspect of this disclosure.

[0013] A fourth aspect of this disclosure provides an electronic device that includes the apparatus described in the second aspect of this disclosure or the chip described in the third aspect of this disclosure.

[0014] A fifth aspect of this disclosure provides a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause a computer to perform the methods described in the first aspect of this disclosure.

[0015] In summary, according to the frequency adjustment method proposed in this disclosure, first data and second data of one or more first operators are determined. The first data includes at least the energy required to execute the first operator, and the second data includes at least the time delay of executing the first operator. Based on the first data and the second data, the first operating frequency of the chip is adjusted to the second operating frequency. By dynamically adjusting the operating frequency of the chip for each operator, the chip's operating efficiency is improved and power consumption is reduced.

[0016] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure, and are not intended to unduly limit this disclosure.

[0018] Figure 1 A flowchart of a frequency adjustment method provided in an embodiment of this disclosure;

[0019] Figure 2 A flowchart of a frequency adjustment method provided in an embodiment of this disclosure;

[0020] Figure 3 This is a schematic diagram of the structure of a frequency adjustment device provided in an embodiment of the present disclosure;

[0021] Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0022] Embodiments of this disclosure are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments are described below with reference to the accompanying drawings.

[0023] The relevant technologies for chip frequency and voltage modulation mainly include the following:

[0024] Dynamic Voltage and Frequency Scaling (DVFS) technology:

[0025] This technology divides the chip's internal space into several different voltage zones, increasing the frequency and voltage as the workload increases and decreasing the frequency and voltage as the workload decreases. This method is simple to implement, using several fixed voltage levels and frequencies. However, DVFS (Distributed Voltage Filtering) limits the adjustable voltage levels and frequencies, thus restricting the range of power reduction.

[0026] Adaptive Voltage Frequency Scaling (AVFS) technology:

[0027] AVFS uses sensors to measure and detect data in real time, allowing for free adjustment of the system's power supply voltage and frequency within a certain range. This method can more precisely adjust voltage and frequency values ​​within a certain range. However, it significantly increases the difficulty of timing signoff verification, as it is difficult to cover all voltage and frequency combinations with a few PVT (Process, Voltage, Temperature) conditions. Furthermore, increasing PVT conditions may lead to too many signoff corners or incomplete timing libraries.

[0028] Frequency modulation and voltage regulation techniques are applied based on the complexity of neural network (NN) models (and their application scenarios).

[0029] This technique modulates frequency and voltage based on the overall complexity of the neural network model or the application scenario. This method can adjust voltage and frequency for different neural network models. However, adjusting the entire model as a unit results in a large granularity, which can easily lead to performance overkill during neural network inference.

[0030] Layer-by-layer dynamic frequency scaling technology:

[0031] This technique calculates the power behavior of each layer in the neural network based on the operation type and data size, and then dynamically scales the frequency. This technique allows for layer-by-layer adjustment of the neural network model, taking into account the varying operation types and data sizes at each layer, resulting in finer-grained adjustment. However, the algorithm is relatively complex; the NPU needs to generate an interrupt at each layer to notify its completion. Since the CPU inevitably experiences delays in processing interrupts and scaling frequencies during operation, and CPU wake-up also requires time, each layer incurs a certain execution time.

[0032] To address the problems existing in related technologies, this disclosure proposes a frequency adjustment method that can be applied to NPU chips or other chips running neural networks. The frequency adjustment method provided in this disclosure, from the perspectives of power consumption and performance, adjusts the operating frequency using operators as the adjustment granularity to find the optimal solution between power consumption and performance for the system.

[0033] The frequency adjustment method provided in this application will be described in detail below with reference to the accompanying drawings.

[0034] Figure 1 This is a flowchart of a frequency adjustment method provided in an embodiment of the present disclosure.

[0035] The frequency adjustment method provided in this disclosure can be executed by a chip, which may include a general-purpose chip or a dedicated chip. For example, a general-purpose chip may include a CPU or a GPU, and a dedicated chip may include, but is not limited to, an NPU or a video processing unit (VPU). The chip can run one or more AI models.

[0036] like Figure 1 As shown, the frequency adjustment method includes the following steps:

[0037] Step 101: Determine first data and second data for one or more first operators. The first data includes at least the energy required to execute the first operator, and the second data includes at least the delay required to execute the first operator.

[0038] In embodiments of this disclosure, the chip can run one or more AI models, each model including one or more operators. An operator is a mapping from one function space to another (or itself), and in this disclosure, operators can instruct one or more computational units of the AI ​​model. The operators in this disclosure can include any one of operators such as summation operators, convolution operators, deconvolution operators, and activation function operators, without specific limitations.

[0039] In the embodiments of this disclosure, the first data and second data of one or more first operators can be determined by a first parameter. The first parameter includes AI model parameters and / or hardware parameters corresponding to the AI ​​model. For example, the AI ​​model parameters may include the operation type and data size of each operator in the model, as well as other related parameters of the model. The hardware parameters corresponding to the AI ​​model may include information such as actual bandwidth and memory.

[0040] The first data may include the energy required to execute the first operator, and the second data may include the maximum latency required to complete the execution of the first operator.

[0041] Step 102: Based on the first data and the second data, adjust the first operating frequency of the chip to the second operating frequency.

[0042] In the embodiments of this disclosure, the first data, namely the energy required to execute the first operator, mainly considers the power consumption of the electronic device; the second data, namely the maximum latency for executing the first operator, mainly considers the performance of the electronic device. By combining the first data and the second data, an optimal solution that satisfies the balance between power consumption and performance can be obtained from the perspectives of power consumption and performance.

[0043] The first operating frequency refers to the current operating frequency corresponding to the first operator, i.e., the operating frequency before adjustment; the second operating frequency refers to the operating frequency of the first operator after adjustment based on the target state.

[0044] In summary, according to the frequency adjustment method proposed in this disclosure, first data and second data of one or more first operators are determined. The first data includes at least the energy required to execute the first operator, and the second data includes at least the time delay of executing the first operator. Based on the first data and the second data, the first operating frequency of the first operator is adjusted to the second operating frequency. By dynamically adjusting the operating frequency of the chip for each operator, the chip's operating efficiency is improved and power consumption is reduced.

[0045] based on Figure 1 The embodiment shown, Figure 2 A flowchart of a frequency adjustment method proposed in this disclosure is further shown. Figure 2 based on Figure 1 The illustrated embodiment further defines steps 101 and 102. Figure 2 In the illustrated embodiment, step 101 includes steps 201, 202, 203, and 204, and step 102 includes steps 205, 206, and 207. For example... Figure 2 As shown, the method includes the following steps:

[0046] Step 201: Based on the first parameter, obtain the first operand and the first utilization rate of the first operator. The first utilization rate is the utilization rate of executing the first operator to perform the second operation.

[0047] In the embodiments of this disclosure, the first parameter includes AI model parameters and / or hardware parameters corresponding to the AI ​​model, and the first operator is one of the AI ​​model operators. The first operand refers to the computational load required by the first operator, and the first utilization rate refers to the actual MAC utilization rate that can be obtained based on the first parameter after the hardware is determined. Here, MAC, MultiplyAccumulate (MAC), refers to the smallest unit of operation required during the execution of the first operator, and is a special operation in digital signal processors or some microprocessors. The hardware circuit unit that implements this operation can also be called a "multiplier accumulator".

[0048] Specifically, the chip can determine the computational cost (N) required for each operator based on the operation type, data size, other relevant parameters of the model, and / or the actual bandwidth, memory, and other primary parameters corresponding to the AI ​​model. need Because the computing power of a computing chip (such as an NPU) is limited by hardware resources, an NPU may only utilize a portion of its theoretical computing power. Therefore, once the hardware is determined, the chip can obtain the actual MAC utilization rate (MAC) based on the relevant hardware parameters. ratio ).

[0049] Step 202: Based on the first operand and the first utilization rate, determine the second operand corresponding to the first operator. The second operand is the operand used to perform the second operation by executing the first operator, and the second operand is greater than or equal to the first operand.

[0050] In the embodiments of this disclosure, the second operation refers to the multiplication, accumulation, and addition operation that the first operator needs to perform during hardware execution, and the second operand refers to the operand that the second operation actually needs to be performed when executing the first operator, obtained based on the first utilization rate.

[0051] Specifically, according to Formula 1, the number of MACs that the first operator needs to execute on the hardware can be obtained based on the MAC utilization rate, i.e., the number of MACs. hw-need .

[0052]

[0053] Among them, MAC hw-need This refers to the number of MACs that the first operator needs to execute in hardware, i.e., the second operand; N need This refers to the computational cost required for each operator, i.e., the first operand; MAC ratio This refers to MAC utilization, also known as primary utilization. ratio Between 0 and 1.

[0054] Step 203: Based on the first parameter, determine the third operand within a preset time period. The third operand is the operand used to execute the first operator to perform the second operation within the preset time period.

[0055] In the embodiments of this disclosure, the third operand refers to the operand in which multiplication and addition operations are actually performed within a preset time period.

[0056] It is understood that the third operand may be the same as or different from the second operand, and the third operand is limited by the actual hardware parameters, i.e., the first parameter. The preset time can be a unit of time, such as one second, one millisecond, etc., and the specific time is set according to actual needs, and is not limited in this embodiment.

[0057] Specifically, the actual computing power of the hardware per unit time can be obtained based on the actual hardware configuration parameters. Here, actual computing power refers to the actual number of MACs that can be computed, i.e., HW. C .

[0058] Step 204: Based on the second operand and the third operand, determine the first data and the second data of the first operator.

[0059] In the embodiments of this disclosure, the first data and the second data of the first operator are determined based on the second operand and the third operand, respectively. It should be noted that in this disclosure, the first data can be determined first, or the second data can be determined first; the order in which the first data and the second data are determined is not limited in the embodiments of this disclosure.

[0060] In one optional embodiment of this disclosure, determining the first data of the first operator based on the second operand and the third operand includes: determining the operating period of the first operator based on the second operand and the third operand; determining the running time of the first operator based on the first operating frequency and the operating period; determining the power of the first operator based on the first operating frequency and a first correspondence, wherein the first correspondence is the relationship between the operating frequency and voltage of the first operator; and determining the first data based on the power and running time of the first operator.

[0061] Specifically, according to Formula 2, this disclosure can obtain the number of operation cycles required for the hardware to execute the first operator based on the number of MACs that the hardware can actually execute per unit time, i.e., the third operand, and the number of MACs that the current first operator needs to execute on the hardware, i.e., the second operand.

[0062]

[0063] According to Formula 3, this disclosure can obtain the time t required to complete the execution of the first operator, i.e., the running time, based on the first operating frequency f before the first operator is adjusted and the operating cycle obtained from Formula 2 above.

[0064]

[0065] Since different frequencies f correspond to different voltages U in the first correspondence, the first voltage corresponding to the first operating frequency can be determined based on the first operating frequency of the first operator. At the same time, based on the current hardware environment of the first operator, the first resistance can be determined. Based on the first voltage and the first resistance, the first current I can be calculated.

[0066] Based on the relationship P=UI, and the first voltage and first current determined above, the correspondence between the first operating frequency f and the power P can be determined, that is...

[0067] P = F(f) (Formula 4)

[0068] The first correspondence table represents the relationship between operating frequency and voltage, that is, different operating frequencies f correspond to different voltage levels U. The first correspondence is preset, and it can be determined by looking up the first correspondence table, which is not limited in this embodiment.

[0069] Based on the power calculated above and the time t required to complete the first operator, the energy W required to execute the first operator can be obtained according to Formula 5. op That is, the first data.

[0070] W op =t*P (Formula 5)

[0071] In one optional embodiment of this disclosure, determining the second data of the first operator based on the second operand and the third operand includes: determining the second data of the first operator based on the first operand, the first utilization rate, the third operand, and the first operating frequency.

[0072] Specifically, according to Formula 6, this disclosure takes into account performance and operator-by-operator adjustments, and can determine the maximum latency required to complete the calculation of the first operator, i.e., the second data, based on the computational load required by the first operator, the number of MACs actually executed per unit time, the actual MAC utilization rate obtained based on the first parameter, and the first operating frequency f.

[0073]

[0074] Step 205: Determine the target state of the chip, and determine the first preset coefficient and the second preset coefficient based on the target state.

[0075] In this disclosure, the target state includes either the target performance or the target power consumption.

[0076] In the embodiments of this disclosure, the first preset coefficient and the second preset coefficient are determined based on the primary and secondary relationship of the optimization objectives, and both the first preset coefficient and the second preset coefficient are between 0 and 1.

[0077] The target state of the chip is determined based on the first parameter. Specifically, when the first operator has an operator with a memory access bottleneck, the target state is determined to be the target power consumption, that is, power consumption is given priority. In this case, the first preset coefficient is set to be larger and the second preset coefficient is set to be smaller, that is, the first operating frequency is lowered. When the first operator has an operator with high computational density, the target state is determined to be the target performance, that is, performance is given priority. In this case, the first preset coefficient is set to be smaller and the second preset coefficient is set to be larger, that is, the first operating frequency is increased.

[0078] It is understood that the first preset coefficient and the second preset coefficient are preset, and the specific values ​​are set according to actual needs, and are not limited in this embodiment.

[0079] Step 206: Determine the frequency adjustment value of the chip based on the first preset coefficient, the second preset coefficient, the first data, and the second data.

[0080] In the embodiments of this disclosure, as shown in Formula 7, the frequency adjustment value of the chip is determined based on the first preset coefficient and the second preset coefficient determined based on the target state, thereby minimizing the cost.

[0081] Minimize Cost = A * W op +B*Latency (Formula 7)

[0082] In this disclosure, A is the first preset coefficient and B is the second preset coefficient.

[0083] Step 207: Adjust the chip's first operating frequency to the second operating frequency using the frequency adjustment value.

[0084] In the embodiments of this disclosure, a second operating frequency is determined based on the frequency adjustment value determined above. Since the adjustment of the first operating frequency is based on a target state, the adjusted operating frequency can maximize chip efficiency while meeting the requirement of low power consumption.

[0085] Furthermore, in an optional embodiment of this disclosure, in response to the received frequency modulation command, the first operating frequency of the chip is adjusted to a second operating frequency based on the first data and the second data. In other words, a frequency modulation command is inserted before each first operator calculation to notify the frequency modulation module, i.e., to notify the chip to perform frequency modulation. The specific frequency adjustment value is obtained through step 206. In this disclosure, the frequency modulation command can be sent via the CPU or other control modules in the chip, and this is not limited in this embodiment.

[0086] For example, when the AI ​​model consists of 5 operators, this disclosure can first determine the second operating frequency table corresponding to these 5 operators, and use the second operating frequency table as a frequency modulation command. The frequency modulation command (i.e., the second operating frequency table) is then sent to the NPU or the corresponding AI processing chip, and the adjustment unit corresponding to the NPU or the corresponding AI processing chip performs the frequency modulation operation according to the frequency modulation command.

[0087] In summary, the method provided in this disclosure, based on the determined energy and delay of the first operator and according to the target state, adjusts the chip's first operating frequency to a second operating frequency. This frequency adjustment targeting the first operator is more suitable for computing chips (such as NPU chips) than the traditional DVFS method, and the frequency adjustment effect is better. Compared to the layer-by-layer frequency adjustment method, the operator-by-operator frequency adjustment method in this disclosure does not require setting breakpoints or layer-by-layer feedback to the CPU or other control modules; it can directly respond to frequency adjustment commands for frequency adjustment, making it easier to implement. Furthermore, the method of this disclosure can determine the target state based on the first operator, thereby dynamically adjusting the frequency to reduce power consumption while satisfying the target state.

[0088] Figure 3 This is a schematic diagram of the structure of a frequency adjustment device 300 provided in an embodiment of this disclosure. Figure 3 As shown, this device is applied to a chip, and the frequency adjustment device includes:

[0089] The determining unit 310 is used to determine first data and second data of one or more first operators, wherein the first data includes at least the energy required to execute the first operator, and the second data includes at least the time delay of executing the first operator;

[0090] The adjustment unit 320 is used to adjust the first operating frequency of the chip to the second operating frequency based on the first data and the second data.

[0091] In some embodiments, the determining unit 310 is configured to: obtain a first operand and a first utilization rate of a first operator based on a first parameter, wherein the first utilization rate is the utilization rate of executing the first operator to perform a second operation, the first parameter including AI model parameters and / or hardware parameters corresponding to the AI ​​model, and the first operator being at least one of the AI ​​model operators; determine a second operand corresponding to the first operator based on the first operand and the first utilization rate, wherein the second operand is the operand used to execute the first operator to perform a second operation, and the second operand is greater than or equal to the first operand; determine a third operand within a preset time based on the first parameter, wherein the third operand is the operand used to execute the first operator to perform a second operation within the preset time; and determine first data and second data of the first operator based on the second operand and the third operand.

[0092] In some embodiments, the determining unit 310 is configured to: determine the operating period of the first operator based on the second operand and the third operand; determine the running time of the first operator based on the first operating frequency and the operating period; determine the power of the first operator based on the first operating frequency and a first correspondence, wherein the first correspondence is the relationship between the operating frequency and voltage of the first operator; and determine the first data based on the power and running time of the first operator.

[0093] In some embodiments, the determining unit 310 is configured to: determine the second data of the first operator based on the first operand, the first utilization rate, the third operand, and the first operating frequency.

[0094] In some embodiments, the adjustment unit 320 is configured to: determine the target state of the chip, and determine a first preset coefficient and a second preset coefficient based on the target state, wherein the target state includes one of target performance or target power consumption; determine the frequency adjustment value of the chip based on the first preset coefficient, the second preset coefficient, the first data and the second data; and adjust the first operating frequency of the chip to the second operating frequency using the frequency adjustment value.

[0095] In some embodiments, the adjustment unit 320 is used to: determine the target state of the chip based on the first operator.

[0096] In some embodiments, the determining unit 320 is configured to: adjust the first operating frequency of the chip to a second operating frequency based on the first data and the second data in response to the received frequency modulation command.

[0097] In summary, by determining the first data and the second data of the first operator in the first module, the first data includes at least the energy required to execute the first operator, and the second data includes at least the time delay of executing the first operator; based on the first data and the second data, the first operating frequency of the chip is adjusted to the second operating frequency. By dynamically adjusting the operating frequency of the chip for each operator, the chip's operating efficiency is improved and power consumption is reduced.

[0098] Corresponding to the methods provided in the above embodiments, this disclosure also provides a frequency adjustment device. Since the device provided in this disclosure corresponds to the methods provided in the above embodiments, the implementation of the methods is also applicable to the device provided in this embodiment, and will not be described in detail in this embodiment.

[0099] The methods and apparatus provided in the embodiments of this application have been described above. To implement the functions of the methods provided in the embodiments of this application, the electronic device may include a hardware structure and software modules, and may implement the above functions in the form of a hardware structure, software modules, or a hardware structure plus software modules. One of the above functions may be executed in the form of a hardware structure, software modules, or a hardware structure plus software modules.

[0100] Figure 4 This is a block diagram illustrating an electronic device 400 for implementing the frequency adjustment method described above, according to an exemplary embodiment. For example, the electronic device 400 may be a mobile phone, computer, messaging device, game console, tablet device, medical device, fitness equipment, personal digital assistant, etc.

[0101] Reference Figure 4 The electronic device 400 may include one or more of the following components: processing component 402, memory 404, power supply component 406, multimedia component 408, audio component 410, input / output (I / O) interface 412, sensor component 414, and communication component 416.

[0102] Processing component 402 typically controls the overall operation of electronic device 400, such as operations associated with display, telephone calls, data communication, camera operation, and recording. Processing component 402 may include one or more processors 420 to execute instructions to perform all or part of the steps of the methods described above. Furthermore, processing component 402 may include one or more modules to facilitate interaction between processing component 402 and other components. For example, processing component 402 may include a multimedia module to facilitate interaction between multimedia component 408 and processing component 402.

[0103] Memory 404 is configured to store various types of data to support the operation of electronic device 400. Examples of this data include instructions for any application or method operating on electronic device 400, contact data, phonebook data, messages, pictures, videos, etc. Memory 404 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0104] Power supply component 406 provides power to various components of electronic device 400. Power supply component 406 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to electronic device 400.

[0105] Multimedia component 408 includes a screen that provides an output interface between electronic device 400 and a user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touchscreen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors may sense not only the boundaries of touch or swipe actions but also the duration and pressure associated with the touch or swipe operation. In some embodiments, multimedia component 408 includes a front-facing camera and / or a rear-facing camera. When electronic device 400 is in an operating mode, such as a shooting mode or video mode, the front-facing camera and / or rear-facing camera may receive external multimedia data. Each front-facing camera and rear-facing camera may be a fixed optical lens system or have focal length and optical zoom capabilities.

[0106] Audio component 410 is configured to output and / or input audio signals. For example, audio component 410 includes a microphone (MIC) configured to receive external audio signals when electronic device 400 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio signals may be further stored in memory 404 or transmitted via communication component 416. In some embodiments, audio component 410 also includes a speaker for outputting audio signals.

[0107] I / O interface 412 provides an interface between processing component 402 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, power buttons, and lock buttons.

[0108] Sensor assembly 414 includes one or more sensors for providing state assessments of various aspects of electronic device 400. For example, sensor assembly 414 may detect the on / off state of electronic device 400, the relative positioning of components such as the display and keypad of electronic device 400, changes in position of electronic device 400 or a component of electronic device 400, the presence or absence of user contact with electronic device 400, orientation or acceleration / deceleration of electronic device 400, and temperature changes of electronic device 400. Sensor assembly 414 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 414 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, sensor assembly 414 may also include an accelerometer, gyroscope, magnetometer, pressure sensor, or temperature sensor.

[0109] Communication component 416 is configured to facilitate wired or wireless communication between electronic device 400 and other devices. Electronic device 400 can access wireless networks based on communication standards, such as WiFi, 2G or 3G, 4G LTE, 5G NR (NewRadio), or combinations thereof. In one exemplary embodiment, communication component 416 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, communication component 416 also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, Infrared Data Association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0110] In an exemplary embodiment, the electronic device 400 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the methods described above.

[0111] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 404 including instructions, which can be executed by a processor 420 of an electronic device 400 to perform the above-described method. For example, the non-transitory computer-readable storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.

[0112] Embodiments of this disclosure also provide a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause a computer to perform the frequency adjustment method described in the above embodiments of this disclosure.

[0113] Embodiments of this disclosure also provide a computer program product, including a computer program that is executed by a processor using the frequency adjustment method described in the above embodiments of this disclosure.

[0114] Embodiments of this disclosure also propose a chip including one or more interface circuits and one or more processors. The interface circuits are used to receive signals from the memory of an electronic device and send signals to the processors. The signals include computer instructions stored in the memory. When the processor executes the computer instructions, it causes the electronic device to perform the frequency adjustment method described in the above embodiments of this disclosure. Furthermore, the interface circuits can also send signals to the electronic device, i.e., transmit information in reverse. For example, after processing a task, the chip transmits the result or status outward for use by other modules (such as a CPU or ISP). Here, "chip" refers to the computing chip of the AI ​​model, specifically an NPU chip.

[0115] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0116] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0117] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing a particular logical function or process, and the scope of the preferred embodiments of the invention includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as will be understood by those skilled in the art to which embodiments of the invention pertain.

[0118] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processing module, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (control method), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic device, and portable optical disc read-only memory (CDROM). Furthermore, computer-readable media can even be paper or other suitable media on which programs can be printed, because programs can be obtained electronically, for example, by optically scanning the paper or other media, followed by editing, interpreting, or otherwise processing as necessary, and then stored in computer memory.

[0119] It should be understood that various parts of the embodiments of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0120] Those skilled in the art will understand that all or part of the steps of the methods described in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.

[0121] Furthermore, the functional units in the various embodiments of the present invention can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. The storage medium mentioned above can be a read-only memory, a disk, or an optical disk, etc.

[0122] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A frequency adjustment method, characterized in that, The method is executed by the chip and includes: Determine first data and second data for one or more first operators, wherein the first data includes at least the energy required to execute the first operator, and the second data includes at least the delay in executing the first operator; Based on the first data and the second data, the first operating frequency of the chip is adjusted to the second operating frequency; The first and second data for determining one or more first operators include: Based on the first parameter, the first operand and the first utilization rate of the first operator are obtained. The first utilization rate is the utilization rate of executing the first operator to perform the second operation. The first parameter includes AI model parameters and / or hardware parameters corresponding to the AI ​​model. The first operator is at least one of the AI ​​model operators. Based on the first operand and the first utilization rate, a second operand corresponding to the first operator is determined. The second operand is the operand used to execute the first operator to perform the second operation. The second operand is greater than or equal to the first operand. Based on the first parameter, a third operand is determined within a preset time period. The third operand is the operand used to execute the first operator to perform the second operation within the preset time period. Based on the second operand and the third operand, the first data and the second data of the first operator are determined.

2. The method according to claim 1, characterized in that, Based on the second operand and the third operand, the first data of the first operator is determined as follows: The operation period of the first operator is determined based on the second operand and the third operand; The running time of the first operator is determined based on the first operating frequency and the operating cycle; Based on the first operating frequency and the first correspondence, the power of the first operator is determined, where the first correspondence is the relationship between the operating frequency of the first operator and the voltage. The first data is determined based on the power of the first operator and the running time.

3. The method according to claim 1, characterized in that, Based on the second operand and the third operand, the second data of the first operator is determined as follows: The second data of the first operator is determined based on the first operand, the first utilization rate, the third operand, and the first operating frequency.

4. The method according to claim 1, characterized in that, The step of adjusting the first operating frequency of the chip to a second operating frequency based on the first data and the second data includes: Determine the target state of the chip, and determine a first preset coefficient and a second preset coefficient based on the target state, wherein the target state includes either target performance or target power consumption; The frequency adjustment value of the chip is determined based on the first preset coefficient, the second preset coefficient, the first data, and the second data; The first operating frequency of the chip is adjusted to the second operating frequency using the frequency adjustment value.

5. The method according to claim 4, characterized in that, Determining the target state of the chip includes: Based on the first operator, the target state of the chip is determined.

6. The method according to claim 1, characterized in that, The step of adjusting the first operating frequency of the chip to a second operating frequency based on the first data and the second data to determine one or more first operators includes: In response to the received frequency modulation command, the first operating frequency of the chip is adjusted to the second operating frequency based on the first data and the second data.

7. A frequency adjustment device, characterized in that, The device is applied to a chip, and the device includes: A determining unit is configured to determine first data and second data for one or more first operators, wherein the first data includes at least the energy required to execute the first operator, and the second data includes at least the time delay required to execute the first operator; An adjustment unit is configured to adjust the first operating frequency of the chip to a second operating frequency based on the first data and the second data. The determining unit is further configured to obtain, based on the first parameter, the first operand and the first utilization rate of the first operator, wherein the first utilization rate is the utilization rate of executing the first operator to perform the second operation, the first parameter includes AI model parameters and / or hardware parameters corresponding to the AI ​​model, and the first operator is at least one of the AI ​​model operators; Based on the first operand and the first utilization rate, a second operand corresponding to the first operator is determined. The second operand is the operand used to execute the first operator to perform the second operation. The second operand is greater than or equal to the first operand. Based on the first parameter, a third operand is determined within a preset time period. The third operand is the operand used to execute the first operator to perform the second operation within the preset time period. Based on the second operand and the third operand, the first data and the second data of the first operator are determined.

8. A chip, characterized in that, It includes one or more interface circuits and one or more processors; the processors are used to perform the method according to any one of claims 1-6.

9. An electronic device, characterized in that, The electronic device includes the frequency adjustment device as described in claim 7, or the chip as described in claim 8.

10. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to perform the method according to any one of claims 1-6.

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