A method for optimizing memory and cache blocks

Abstract

The present invention provides a method for optimizing a memory and a cache block, wherein the memory includes: firmware, in which a free list, a write cache list and a read cache list are arranged; when performing a read and write operation, the main control unit is used to call a cache block from the write cache list and the free list to perform a write operation, and to call a cache block from the read cache list and the free list to perform a read operation; when performing a recycling operation, when the mapping relationship of the host data to be erased matches the mapping relationship of the host data stored in a certain cache block in the write cache list and the read cache list, the host data of the cache block is erased, and the relevant information of the cache block is stored in the free list. Through the method for optimizing a memory and a cache block provided by the present invention, the allocation mode of the cache block can be optimized, so that the cache blocks can be mixed in different scenarios.

Description

Technical Field

[0001] The present invention relates to the field of storage, and in particular to a method for optimizing a memory and a cache block. Background Art

[0002] In modern large-capacity storage products, NAND flash memory is one of the main storage media. When reading and writing data, the cache block (Buffer) in the random access memory unit (RAM) is usually used to temporarily store data. The size and allocation of the cache block directly affect the efficiency of data transmission and the overall performance of the storage system.

[0003] Currently, when the memory performs read and write operations, its internal cache blocks are isolated according to the type of read and write operations, and different types of cache blocks cannot be mixed. In actual usage scenarios, the memory may only perform read operations or write operations for a period of time, which will cause some cache blocks to be unable to be effectively used for a period of time, forming redundancy, which not only wastes system resources, but also may affect the stability and efficiency of the system. Therefore, how to optimize the allocation of cache blocks is an urgent problem to be solved. Summary of the invention

[0004] The object of the present invention is to provide a method for optimizing a memory and a cache block, which can optimize the allocation mode of the cache block so that the cache blocks can be mixed in different scenarios.

[0005] In order to solve the above technical problems, the present invention is achieved through the following technical solutions:

[0006] The present invention provides a memory, comprising: a main control unit for performing read and write operations and recycling operations;

[0007] A read-only storage unit, electrically connected to the main control unit, and having firmware therein;

[0008] a random access memory unit, electrically connected to the main control unit, and having a plurality of cache blocks therein; and

[0009] A storage unit, electrically connected to the random access storage unit, for storing host data;

[0010] The firmware is provided with a free list, a write cache list and a read cache list, wherein the free list is used to store relevant information of unused cache blocks, the write cache list is used to store relevant information of cache blocks for performing write operations, and the read cache list is used to store relevant information of cache blocks for performing read operations;

[0011] When performing a read or write operation, the main control unit is used to call a cache block from the write cache linked list and the free linked list to perform a write operation, and to call a cache block from the read cache linked list and the free linked list to perform a read operation;

[0012] When performing a recycling operation, when the mapping relationship of the host data to be erased matches the mapping relationship of the host data stored in a cache block in the write cache linked list and the read cache linked list, the host data of the cache block is erased and the relevant information of the cache block is saved in the free linked list.

[0013] In one embodiment of the present invention, the write cache linked list includes a first write cache linked list, a second write cache linked list and a third write cache linked list, and the read cache linked list includes a first read cache linked list, a second read cache linked list and a third read cache linked list;

[0014] The first write cache linked list is used to store relevant information of the cache block that is performing a write operation;

[0015] The second write cache linked list is used to store relevant information of cache blocks that have been filled with host data and have not been written to the storage unit;

[0016] The third write cache linked table is used to store relevant information of the cache blocks of the storage unit that have written the host data;

[0017] The first read cache linked list is used to store relevant information of the cache block that is performing a read operation;

[0018] The second read cache linked list is used to store relevant information of cache blocks that have been filled with host data and have not been read out to the host;

[0019] The third read cache linked list is used to store relevant information of the cache blocks of the host that have read the host data;

[0020] When performing a read / write operation, the main control unit writes the host data of the cache blocks in the second write cache linked list to the storage unit, reads the host data of the cache blocks in the second read cache linked list to the host, and reallocates the cache blocks when determining that the data amount of the allocated cache blocks is greater than the maximum concurrent read / write data amount;

[0021] When the main control unit determines that the data amount of the allocated cache block is less than or equal to the maximum read and write concurrent data amount, the cache block is called from the first write cache linked list, the third write cache linked list, and the free linked list to perform a write operation, and the cache block is called from the first read cache linked list, the third read cache linked list, and the free linked list to perform a read operation.

[0022] In one embodiment of the present invention, when performing a write operation, the cache blocks in the first write cache linked list are preferentially called to perform the write operation;

[0023] When the cache blocks in the first write cache linked list are filled, the cache blocks are stored in the second write cache linked list, and cache blocks are called from the free linked list to perform write operations in the first write cache linked list;

[0024] When there is no cache block in the free linked list, the cache blocks are sorted according to the cache block hit counts of each cache block in the third write cache linked list and the third read cache linked list, and the corresponding cache blocks are called in ascending order of the cache block hit counts to perform write operations.

[0025] In one embodiment of the present invention, when there are no cache blocks in the free list, the first write cache list, the third write cache list, and the third read cache list, the host data of the cache blocks in the second write cache list are written to the storage unit to store the relevant information of the corresponding cache blocks in the third write cache list, and at the same time, the host data of the cache blocks in the second read cache list are read out to the host to store the relevant information of the corresponding cache blocks in the third read cache list.

[0026] In one embodiment of the present invention, when performing a read operation, when the mapping relationship of the host data to be read matches the mapping relationship of the host data stored in a cache block in the first write cache linked list, the second write cache linked list, the third write cache linked list, the first read cache linked list, and the third read cache linked list, the corresponding host data is read from the cache block to the host, and the mapping table hit count and cache block hit count of the corresponding cache block are updated.

[0027] In one embodiment of the present invention, when performing a read operation, when performing a read operation, when the mapping relationship of the host data to be read does not match the mapping relationship of the host data stored in the cache blocks in the first write cache linked list, the second write cache linked list, the third write cache linked list, the first read cache linked list, and the third read cache linked list, the cache blocks in the first read cache linked list are preferentially called to perform the read operation.

[0028] In one embodiment of the present invention, when the cache blocks in the first read cache linked list are filled, they are stored in the second read cache linked list, and cache blocks are called from the free linked list to perform read operations in the first read cache linked list;

[0029] When there is no cache block in the free linked list, the cache blocks are sorted according to the cache block hit counts of each cache block in the third write cache linked list and the third read cache linked list, and the corresponding cache blocks are called in ascending order of the cache block hit counts to perform a read operation;

[0030] When there are no cache blocks in the free list, the third write cache list, and the third read cache list, the host data of the cache blocks in the second write cache list are written to the storage unit to store the relevant information of the corresponding cache blocks in the third write cache list, and at the same time, the host data of the cache blocks in the second read cache list are read out to the host to store the relevant information of the corresponding cache blocks in the third read cache list.

[0031] In one embodiment of the present invention, when performing a recycling operation, when the mapping relationship of the host data to be erased matches the mapping relationship of the host data stored in a cache block in the first write cache linked list, the second write cache linked list, the third write cache linked list, the first read cache linked list, and the third read cache linked list, the host data of the cache block is erased, and the mapping table hit count and cache block hit count of the corresponding cache block are updated, and the relevant information of the cache block that has completed the erase operation is saved in the free linked list.

[0032] In one embodiment of the present invention, at least one temperature sensor is further included, and the temperature sensor is installed at different positions of the memory to detect the real-time temperature of different positions inside the memory in real time;

[0033] When the main control unit determines that a certain real-time temperature is greater than a maximum value of a preset temperature range, the main control unit sequentially reduces the number of cache blocks that can be allocated when performing read and write operations until the real-time temperature is lower than a minimum value of the preset temperature range;

[0034] When the main control unit determines that the real-time temperature at different positions is less than the minimum value of the preset temperature range, it sequentially increases the allocatable number of cache blocks when performing read and write operations until a real-time temperature is greater than the minimum value of the preset temperature range.

[0035] The present invention also provides a method for optimizing a cache block of a memory, comprising:

[0036] A free list, a write cache list, and a read cache list are set in the firmware, wherein the free list is used to store relevant information of unused cache blocks, the write cache list is used to store relevant information of cache blocks that perform write operations, and the read cache list is used to store relevant information of cache blocks that perform read operations;

[0037] When performing read and write operations, calling cache blocks from the write cache linked list and the free linked list to perform write operations, and calling cache blocks from the read cache linked list and the free linked list to perform read operations;

[0038] When performing a recycling operation, when the mapping relationship of the host data to be erased matches the mapping relationship of the host data stored in a cache block in the write cache linked list and the read cache linked list, the host data of the cache block is erased and the relevant information of the cache block is saved in the free linked list.

[0039] As described above, the present invention provides a method for optimizing a memory and a cache block, which manages the state of the cache block in the reading and writing process in detail, and classifies the state of the cache block in different operations in detail, thereby optimizing the use and recovery strategy of the cache block, improving the utilization rate of the cache block, reducing unnecessary cache block replacement, and thus improving the overall read and write performance of the memory. By increasing the information records corresponding to the cache block, including the use frequency, hit count, and most recent access time of the cache block, a basis is provided for the priority sorting of the cache block, so that the memory can more intelligently decide which cache blocks should be retained first and which cache blocks can be recycled. At the same time, in combination with the information recorded by the cache block, the allocation and recovery of the cache block are prioritized to improve the cache hit probability when reading data. Through this priority sorting mechanism, the memory can give priority to retaining cache blocks with high hit rates, thereby improving the overall read performance and reducing the number of times data is read from the NAND memory. When the concurrent operation of multiple NAND chips causes the temperature to be too high, the read and write speed can be reduced by reducing the number of cache blocks allocated, thereby achieving the purpose of controlling the temperature. This controllable cache allocation mechanism not only helps prevent the device from overheating, but also prolongs the life of the memory and improves the reliability and durability of the product. By adjusting the number of cache blocks allocated and controlling the read and write speeds, the heat generated by the NAND chip during concurrent operations can be effectively reduced to prevent overheating.

[0040] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0042] Figure 1 A schematic diagram of a memory and a host in one embodiment of the present invention;

[0043] Figure 2The present invention is a flowchart of a method for optimizing a cache block of a memory according to an embodiment of the present invention.

[0044] In the figure: 100, host; 200, transmission interface; 300, main control unit; 400, random access memory; 410, cache block; 500, storage unit; 600, temperature sensor. DETAILED DESCRIPTION

[0045] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0046] See also Figure 1 The present invention discloses a memory, which can communicate with a host 100 through a transmission interface 200 to receive and execute different operation instructions, such as read, write, and erase instructions. The transmission interface 200 is a bridge for transmitting data and instructions between the memory and the host 100. Different types of transmission interfaces 200 have different performance characteristics and application scenarios.

[0047] In one embodiment, the memory may include a main control unit 300 , a random access memory 400 , a read-only memory (ROM), a storage unit 500 , a temperature sensor 600 , and the like.

[0048] In one embodiment, the main control unit 300 may be a microcontroller unit (MCU). The main control unit 300 may be used to perform specific control tasks, such as reading data, processing instructions from the host 100, etc. The processing core of the main control unit 300 may be designed based on the RISC-V architecture to perform various control and computing tasks.

[0049] In one embodiment, a random access memory 400 (RAM) may be electrically connected to the main control unit 300. The random access memory 400 may be used to temporarily store data so as to perform efficient read and write operations between different data transmission operations.

[0050] In one embodiment, a read-only memory unit (ROM) may be electrically connected to the main control unit 300. The read-only memory unit may be a non-volatile memory for long-term data storage. Firmware may be stored in the read-only memory unit. The firmware may be a set of pre-written programs that instruct the main control unit 300 on how to start and run. These instructions include device initialization, peripheral configuration, and a possible boot loader. The boot loader may be used to load updated programs or operating systems, etc.

[0051] In one embodiment, the storage unit 500 may be a logical unit (LUN) of the memory. A logical unit refers to a logical unit for parallel operation of a flash memory. A logical unit may consist of multiple planes. A plane may consist of multiple blocks, and the memory may support simultaneous operation of multiple blocks in a plane. A block may consist of multiple pages, and a page is a basic unit for the memory to perform read and write operations.

[0052] Furthermore, the memory can support the MultiPlane function, which refers to operating the Pages on multiple Planes in a LUN at the same time, thereby improving parallelism and data transmission efficiency. In order to make full use of the MultiPlane function, the random access memory 400 can be divided into a number of cache blocks 410 (Buffer) of fixed size. The size of the cache block 410 can be the unit size of the number of Planes in a LUN × Page. That is, one cache block 410 corresponds to the amount of data that can be read and written simultaneously by one LUN.

[0053] Specifically, the size of each cache block 410 can be determined according to the specific configuration of the NAND flash memory. For example, if there are 4 Planes in a LUN and the size of each Page is 8KB, the size of each cache block 410 is 4×8KB=32KB. According to the total cache size of the random access memory 400, a number of cache blocks 410 are divided. For example, if the total cache is 1GB, 1024×32 cache blocks can be divided.

[0054] In one embodiment, during the reading and writing process, in order to facilitate the management of the cache block 410, a free buffer queue, a write buffer queue, a read buffer queue, and a cache block mapping table (L2P[N / 4]) may be set in the firmware.

[0055] Among them, the free list can be used to store the relevant information of the unused cache blocks 410. The cache blocks 410 in the free list can be represented as unused cache blocks 410. After the memory is initialized, all cache blocks 410 have no data, and at this time all cache blocks 410 can be stored in the free list. The write cache list can be used to store the relevant information of the cache blocks 410 that perform write operations. The read cache list can be used to store the relevant information of the cache blocks 410 that perform read operations.

[0056] In one embodiment, the write buffer linked list may include a first write buffer linked list (Write Buffer Queue), a second write buffer linked list (Write Buffer Rcv Done Queue), and a third write buffer linked list (Write Buffer Prog Done Queue).

[0057] In one embodiment, the cache block 410 in the first write cache linked list can be represented as the relevant information of the cache block 410 that is performing a write operation. The cache block 410 in the linked list is used to receive the host data that needs to be written from the host 100, and is not fully written. There is at most one cache block 410 in the linked list.

[0058] In one embodiment, the second write cache linked list is used to store information related to cache blocks 410 that have been filled with host data and have not been written to the storage unit 500. The cache blocks 410 in the linked list represent cache blocks that have been filled with host data that needs to be written from the host but have not been written to the storage unit 500.

[0059] In one embodiment, the third write cache linked list is used to store information related to the cache blocks 410 that have written host data to the storage unit 500. The cache blocks 410 in the linked list indicate that the host data in the cache blocks 410 have been written to the storage unit 500.

[0060] In one embodiment, the read buffer linked list may include a first read buffer linked list (Read Buffer Queue), a second read buffer linked list (Read Buffer Rcv Done Queue), and a third read buffer linked list (Read Buffer SendDone Queue).

[0061] In one embodiment, the first read cache linked list is used to store information related to the cache block 410 that is performing a read operation. The cache block 410 in the linked list is used to store data read from the storage unit 500 and is not filled. There is at most one cache block 410 in the linked list.

[0062] In one embodiment, the second read cache linked list is used to store information about cache blocks 410 that have been filled with host data but have not been read out to the host 100. The cache blocks 410 in the linked list represent cache blocks that have been filled with data read out from the storage unit 500 but have not yet been sent to the host 100.

[0063] In one embodiment, the third read cache linked list is used to store information related to cache blocks 410 that have read host data to the host 100. The cache blocks 410 in the linked list indicate that the data in the cache blocks 410 have been read to the host 100.

[0064] In one embodiment, the cache block mapping table (L2P[N / 4]) is used to store the mapping relationship from the logical to the physical address of the data in the reading and writing process. N refers to the size of a cache block 410 (Buffer). Since each L2P entry corresponds to 4KB of data, N / 4 can represent the number of L2Ps that need to be recorded in a cache block. L2P refers to the mapping relationship from the logical address to the physical address. For example, if the size of a cache block 410 is 32KB, the number of L2Ps that need to be recorded is 8, that is, the cache block 410 has 8 L2P mapping relationships.

[0065] Furthermore, each L2P mapping entry corresponds to a mapping table hit count (HitCnt[N / 4]). The mapping table hit count can record the number of times the data corresponding to the entry is read. The cache block hit count (HitCntSum) can be expressed as the sum of the mapping table hit counts (HitCnt[N / 4]) of all data in the cache block 410. When the host data corresponding to each L2P mapping entry is read, the mapping table hit count needs to be increased by one, and the corresponding cache block hit count also needs to be increased by one.

[0066] In one embodiment, by setting a free linked list, a first write cache linked list, a second write cache linked list, a third write cache linked list, a first read cache linked list, a second read cache linked list, and a third read cache linked list in the firmware, relevant information of all cache blocks 410 can be stored in corresponding linked lists to facilitate management of cache blocks 410 during the reading and writing process.

[0067] In one embodiment, when the main control unit 300 performs a read / write operation, it is necessary to allocate and manage the cache block 410 based on the maximum concurrent read / write data volume (X) and the data volume (Y) of the host data in the allocated cache block 410, so as to improve the versatility and performance of the storage system. The maximum concurrent read / write data volume (X) can be expressed as the maximum concurrent processing capability of the storage.

[0068] Furthermore, in the read and write operations, each time a cache block 410 is allocated and used, the data volume of the allocated cache block 410 is recorded, which is recorded as Y. Before allocating a cache block 410, it is necessary to determine whether the total size Y of the allocated cache block 410 exceeds the maximum concurrent read and write data volume X.

[0069] In one embodiment, if the data volume Y of the allocated cache blocks 410 is greater than the maximum concurrent read and write data volume X, the allocation of new cache blocks 410 is suspended until enough cache blocks 410 are reclaimed to ensure that the maximum concurrent processing capability of the system is not exceeded.

[0070] When performing a write operation, when the main control unit 300 determines that the amount of data in the allocated cache block 410 is greater than the maximum concurrent read and write data amount, it can obtain relevant information of the cache block 410 that is filled with host data and has not been written to the storage unit 500 from the second write cache linked list of the write cache linked list, write the host data in the corresponding cache block 410 to the storage unit 500, and at the same time, store the relevant information of the corresponding cache block 410 in the third write cache linked list.

[0071] When performing a read operation, when the main control unit 300 determines that the amount of data in the allocated cache block 410 is greater than the maximum concurrent read and write data amount, it can obtain the cache block 410 that is filled with host data and has not been read out to the host 100 from the second read cache linked list of the read cache linked list, read the host data in the corresponding cache block 410 to the host 100, and at the same time, store the relevant information of the corresponding cache block 410 in the third read cache linked list.

[0072] In one embodiment, if the data volume Y of the allocated cache block 410 is less than or equal to the maximum concurrent read and write data volume X, a new cache block 410 may be allocated to perform read and write operations. At this time, the cache block 410 may be called from the write cache linked list and the free linked list to perform write operations, and the cache block 410 may be called from the read cache linked list and the free linked list to perform read operations.

[0073] In one embodiment, after the memory is initialized, all cache blocks 410 may be stored in the free list.

[0074] In one embodiment, after the memory is initialized, when performing a write operation, the main control unit 300 can apply for an unused cache block 410 from the free list, and store its related information in the first write cache list to perform the write operation. During the write operation, the data write amount (Write Buffer Offest) of the cache block 410 in the first write cache list can be updated according to the host data received from the host 100, and the mapping relationship corresponding to the host data is recorded in the mapping relationship table L2P, wherein the data write amount can be represented as the amount of host data in the cache block 410 that has been written to the storage unit 500.

[0075] Further, when the written host data does not fill up the cache block 410, the cache block 410 can continue to be stored in the first write cache linked list. When it is necessary to continue to receive new host data later, the cache block 410 can continue to be allocated and used to perform a write operation. When the cache block 410 is filled with host data, the cache block 410 can be taken out of the first write cache linked list and stored in the second write cache linked list to wait for the host data inside it to be written into the storage unit 500 later. In this way, the utilization rate of a single cache block 410 can be improved.

[0076] Furthermore, when the cache block 410 in the first write cache linked list is not filled with host data, and the host data in the cache block 410 needs to be immediately written into the storage unit 500, invalid data (Dummy) can be filled into the cache block 410 to fill the cache block 410. Subsequently, the relevant information of the cache block 410 can be taken out from the first write cache linked list and stored in the second write cache linked list to wait for the host data inside it to be written into the storage unit 500 later.

[0077] Furthermore, when the host data in the cache block 410 in the second write cache linked list is written into the storage unit 500, the data amount of the host data in the cache block 410 that has been written into the storage unit 500 can be recorded through the data reception amount (Write Buffer DMA Offest). When the data reception amount of a certain cache block 410 is equal to the data writing amount, it can be indicated that the host data in the cache block 410 has been completely written into the storage unit 500. At this time, the relevant information of the cache block 410 can be taken out from the second write cache linked list and stored in the third write cache linked list.

[0078] In one embodiment, after the memory is used for a period of time, the cache blocks 410 in the free linked list may be insufficient. In order to ensure that there are enough cache blocks 410 for use during the read and write process, while retaining data with a large number of cache hits and improving the overall read and write performance, the cache blocks 410 in different linked lists need to be prioritized and managed.

[0079] In one embodiment, when performing a write operation, it is necessary to first determine whether there is a cache block 410 in the first write cache linked list that is not filled with host data.

[0080] Further, when the main control unit 300 determines that there is a cache block 410 in the first write cache linked list that is not filled with host data, the cache block 410 can be preferentially called to perform a write operation. After the cache block 410 is filled with host data, the cache block 410 needs to be stored in the second write cache linked list.

[0081] Furthermore, when the main control unit 300 determines that there is no cache block 410 in the first write cache linked list that is not filled with host data, it can search the free list for unused cache blocks 410. When there is an unused cache block 410 in the free list, the main control unit 300 can store the cache block 410 in the first write cache linked list and continue to perform the write operation.

[0082] Furthermore, when the main control unit 300 determines that there is no unused cache block 410 in the free list, it is necessary to call the cache block 410 from the third write cache linked list and the third read cache linked list to perform the write operation. The data receiving amount of the cache block 410 in the third write cache linked list and the third read cache linked list is equal to the data writing amount.

[0083] Furthermore, since there may be multiple cache blocks 410 in the third write cache linked list and the third read cache linked list, it is necessary to sort the multiple cache blocks 410 so as to call them in sequence. Specifically, when sorting, the number of cache block hits of each cache block 410 can be obtained first. Afterwards, each cache block 410 can be sorted according to the size of the number of cache block hits. Finally, the relevant information of the corresponding cache block 410 is called from the third write cache linked list and the third read cache linked list in order from small to large according to the number of cache block hits to the first write cache linked list to perform a write operation. At the same time, it is necessary to clear the mapping relationship, mapping table hit count, and cache block hit count of the called cache block 410. By doing so, it can be ensured that the host data with a large number of cache block hits is kept in the cache block 410 as much as possible. By doing so, it is possible to achieve mixed use of cache blocks in different usage scenarios.

[0084] Furthermore, since the cache block 410 may not exist in the third write cache linked list and the third read cache linked list, the search for the available cache block 410 may be stopped first, and the host data in the cache block 410 in the first write cache linked list and the second write cache linked list may be written into the storage unit 500. At the same time, the host data in the cache block 410 in the first read cache linked list and the second read cache linked list may also be read out to the host 100. Subsequently, the relevant information of the corresponding cache block 410 in the first write cache linked list and the second write cache linked list needs to be stored in the third write cache linked list, and the relevant information of the corresponding cache block 410 in the first read cache linked list and the second read cache linked list needs to be stored in the third write cache linked list, so as to re-execute the write operation.

[0085] In one embodiment, during a read operation, the host data to be read may already exist in the used cache blocks 410. Reading the host data directly from these cache blocks 410 can skip the process of reading the host data from the storage unit 500, thereby improving the read performance. Therefore, when receiving a data read request from the host 100, the main control unit 300 first searches the cache block 410 to see if the required host data exists. If the required host data is found in the cache block 410 (called a cache hit), the data can be read directly from the cache block 410, thereby avoiding the delay of reading from the storage unit 500. This not only reduces the time for data reading, but also reduces the wear of the memory and prolongs its service life. If the required data is not found in the cache block 410 (called a cache miss), the system will read the host data from the storage unit 500. The read host data will be stored in the cache block 410 so that a faster response can be provided during subsequent access.

[0086] In one embodiment, during a read operation, the main control unit 300 needs to sequentially search the first write cache linked list, the second write cache linked list, the third write cache linked list, the first read cache linked list, and the cache block 410 inside the third read cache linked list to see whether the mapping relationship of the stored host data matches the mapping relationship of the host data that needs to be read.

[0087] Further, when the mapping relationship of the host data to be read matches the mapping relationship of the host data stored in a certain cache block 410 in the first write cache linked list, the second write cache linked list, the third write cache linked list, the first read cache linked list, and the third read cache linked list, the corresponding host data can be directly read from the cache block 410 and read to the host 100. At the same time, the mapping table hit count and the cache block hit count of the corresponding cache block 410 are updated.

[0088] Furthermore, when the mapping relationship of the host data to be read does not match the mapping relationship of the host data stored in a cache block 410 in the first write cache linked list, the second write cache linked list, the third write cache linked list, the first read cache linked list, and the third read cache linked list, a read operation can be performed according to the allocated cache block 410.

[0089] In one embodiment, after the memory is initialized, when performing a read operation, the main control unit 300 may apply for an unused cache block 410 from the free list and store it in the first read cache list to perform the read operation. During the read operation, the data read amount (Read Buffer Offest) of the cache block 410 in the first read cache list may be determined according to the host data read from the storage unit 500.

[0090] The host data is updated, and the mapping relationship corresponding to the host data is recorded in the mapping relationship table L2P, wherein the data read-out amount can be represented as the amount of host data read from the storage unit 500 in the cache block 410 .

[0091] Further, when the read host data does not fill up the cache block 410, the relevant information of the cache block 410 can continue to be stored in the first read cache linked list. When the host data needs to be read out from the storage unit 500 later, the cache block 410 can continue to be allocated and used to perform the read operation. When the cache block 410 is filled with host data, the relevant information of the cache block 410 can be taken out from the first read cache linked list and stored in the second read cache linked list to wait for the host data inside it to be read out to the host 100 later. In this way, the utilization rate of a single cache block 410 can be improved.

[0092] Furthermore, when the host data in the cache block 410 in the second read cache linked list is read out to the host 100, the data amount of the host data in the cache block 410 that has been read out to the host 100 can be recorded through the data transmission amount (Read Buffer DMA Offest). When the data reading amount of a certain cache block 410 is equal to the data transmission amount, it can be indicated that all the host data in the cache block 410 has been read out to the host 100. At this time, the relevant information of the cache block 410 can be taken out from the second read cache linked list and stored in the third read cache linked list.

[0093] In one embodiment, after the memory is used for a period of time, the cache blocks 410 in the free linked list may be insufficient. In order to ensure that there are enough cache blocks 410 for use during the read and write process, while retaining data with a large number of cache hits and improving the overall read and write performance, the cache blocks 410 in different linked lists need to be prioritized and managed.

[0094] In one embodiment, when performing a read operation, it is necessary to first determine whether there is a cache block 410 in the first read cache linked list that is not filled with host data.

[0095] Further, when the main control unit 300 determines that there is a cache block 410 in the first read cache linked list that is not filled with host data, the cache block 410 can be preferentially called to perform a read operation. After the cache block 410 is filled with host data, the relevant information of the cache block 410 needs to be stored in the second read cache linked list.

[0096] Furthermore, when the main control unit 300 determines that there is no cache block 410 in the first read cache linked list that is not filled with host data, it can search the free list for unused cache blocks 410. When there is an unused cache block 410 in the free list, the main control unit 300 can store the relevant information of the cache block 410 in the first read cache linked list and continue to perform the read operation.

[0097] Furthermore, when the main control unit 300 determines that there is no unused cache block 410 in the free list, it needs to call the cache block 410 from the third write cache linked list and the third read cache linked list to perform the read operation.

[0098] Furthermore, since there may be multiple cache blocks 410 in the third read cache linked list and the third write cache linked list, it is necessary to sort the multiple cache blocks 410 so as to call them in sequence. Specifically, when sorting, the number of cache block hits of each cache block 410 can be obtained first. Afterwards, each cache block 410 can be sorted according to the size of the number of cache block hits. Finally, the relevant information of the corresponding cache block 410 is called from the third read cache linked list and the third write cache linked list in the order of the number of cache block hits from small to large to the first read cache linked list to perform a read operation. At the same time, it is necessary to clear the mapping relationship, the number of mapping table hits, and the number of cache block hits of the called cache block 410. By doing so, it can be ensured that the host data with a large number of cache block hits is kept in the cache block 410 as much as possible. By doing so, it is possible to achieve mixed use of cache blocks in different usage scenarios.

[0099] Furthermore, since the cache block 410 may not exist in the third read cache linked list and the third write cache linked list, the search for the available cache block 410 may be stopped first, and the host data in the cache block 410 in the first read cache linked list and the second read cache linked list may be read out to the host 100. At the same time, the host data in the cache block 410 in the first write cache linked list and the second write cache linked list may also be written into the storage unit 500. Subsequently, the relevant information of the corresponding cache block 410 in the first read cache linked list and the second read cache linked list needs to be stored in the third read cache linked list, and the relevant information of the corresponding cache block 410 in the first write cache linked list and the second write cache linked list needs to be stored in the third write cache linked list, so as to re-execute the read operation.

[0100] In one embodiment, the main control unit 300 can also be used to perform a recycling operation. When the mapping relationship of the host data to be erased matches the mapping relationship of the host data stored in a cache block 410 in the first write cache linked list, the second write cache linked list, the third write cache linked list, the first read cache linked list, and the third read cache linked list, the host data in the cache block 410 is erased, and the mapping table hit count and cache block hit count of the corresponding cache block 410 are updated, and the relevant information of the cache block 410 that has completed the erase operation is saved in the free linked list.

[0101] Specifically, when the host 100 decides to erase certain host data, it will search for corresponding L2P records in the cache block 410 according to the L2P of the host data to be erased. If the corresponding L2P record is found in the cache block 410, the record is deleted from the cache block mapping table L2P. Each time an L2P record is deleted from the cache block mapping table, the mapping table hit count (HitCnt) of the cache block 410 corresponding to the L2P and the cache block hit count (HitCntSum) of the cache block 410 need to be updated. When all L2P records of the cache block mapping table records in the cache block 410 are deleted, it means that there is no valid data in the cache block 410. At this time, the cache block 410 can be considered to be free and can be recycled and reallocated, for example, its related information is saved in the free linked list. In this way, the memory can effectively manage the data and mapping relationship in the cache block 410 when erasing data, ensuring the effective use and timely recycling of the cache block 410.

[0102] In one embodiment, in the memory, multiple NAND chips are usually used to increase data storage capacity and read and write performance. When multiple NAND chips perform read and write operations simultaneously, the read and write speed and throughput of the overall system will increase. Since multiple NAND chips operate concurrently, a large amount of heat will be generated, causing the device temperature to rise. At the same time, excessively high temperatures may affect the performance of the flash memory chip and increase the data error rate. Furthermore, long-term high-temperature operation will accelerate the aging of the NAND chip and shorten its service life. Therefore, in order to control the temperature, the read and write speed of the NAND chip can be controlled by adjusting the number of cache block allocations.

[0103] See also Figure 1 In one embodiment, the number of temperature sensors 600 can be multiple. The temperature sensors 600 can be installed at different positions inside the memory to detect the real-time temperature of different positions inside the memory in real time. For example, one temperature sensor 600 can be installed on the main control unit 300 to detect the temperature of the main control unit 300 in real time. For another example, multiple temperature sensors 600 can be installed at different positions of the storage unit 500 to detect the real-time temperature of different positions of the storage unit 500.

[0104] In one embodiment, the temperature sensor 600 can be electrically connected to the main control unit 300, and the main control unit 300 can obtain the real-time temperature of different locations in the memory. The main control unit 300 can set a preset temperature range, and when the real-time temperature of different locations in the memory is within the preset temperature range, it can indicate that the memory can work normally.

[0105] In one embodiment, when the main control unit 300 determines that a certain real-time temperature is greater than the maximum value of the preset temperature range, it can be considered that the temperature of the memory is too high and needs to be cooled down. At this time, the heat generated by the concurrent operation of multiple NAND chips can be reduced by reducing the number of cache blocks 410 that can be allocated when performing read and write operations, thereby achieving the purpose of cooling down.

[0106] Specifically, when reducing the allocatable number of cache blocks 410 when performing read and write operations, the allocatable number of cache blocks 410 can be reduced in sequence according to a preset ratio. For example, the original allocatable number of cache blocks 410 can be expressed as M. After multiple reduction operations, the number of allocatable cache blocks 410 can be changed to M / 2, M / 4, M / 8, etc., until the number of allocatable cache blocks 410 is reduced to 1. For another example, in each reduction operation, the number of allocatable cache blocks 410 can also be reduced according to a fixed value, for example, 1, 2, or 3 are reduced each time. Among them, after each reduction operation, the memory needs to continue to run. After reaching the running time, if a real-time temperature is still greater than the maximum value of the preset temperature range, the number of cache blocks 410 with the allocated number can be reduced again. The preset time length can be 30s, 1Min, etc., and its specific size can be set according to actual needs.

[0107] In one embodiment, when the main control unit 300 determines that the real-time temperature of all positions is less than the minimum value of the preset temperature range, it can be considered that the memory read and write performance is poor. At this time, the read and write performance of the memory can be improved by increasing the number of cache blocks 410 that can be allocated when performing read and write operations.

[0108] Specifically, when increasing the allocatable number of cache blocks 410 when performing read and write operations, the allocatable number of cache blocks 410 can be increased in sequence according to a preset ratio. For example, the original allocatable number of cache blocks 410 can be expressed as K. After multiple increase operations, the number of allocatable cache blocks 410 can be changed to 2K, 4K, 8K, etc. in sequence. For another example, in each increase operation, the number of allocatable cache blocks 410 can also be increased according to a fixed value, such as increasing by 1, 2, or 3 each time. Among them, after each increase operation, the memory needs to continue to run. After reaching the running time, if a real-time temperature is greater than the minimum value of the preset temperature range, the increase in the number of cache blocks 410 with the allocated number can be stopped at this time.

[0109] It can be seen that in the above scheme, by finely managing the state of the cache block in the reading and writing process, the state of the cache block in different operations is classified in detail, thereby optimizing the use and recycling strategy of the cache block, improving the utilization rate of the cache block, reducing unnecessary cache block replacement, and thus improving the overall read and write performance of the memory. By increasing the information records corresponding to the cache block, including the use frequency, hit count, and recent access time of the cache block, a basis is provided for the priority sorting of the cache block, so that the memory can more intelligently decide which cache blocks should be retained first and which cache blocks can be recycled. At the same time, combined with the information recorded by the cache block, the allocation and recycling of the cache block are prioritized to improve the cache hit probability when reading data. Through this priority sorting mechanism, the memory can give priority to retaining cache blocks with high hit rates, thereby improving the overall read performance and reducing the number of times data is read from the NAND memory. When the concurrent operation of multiple NAND chips causes the temperature to be too high, the read and write speed can be reduced by reducing the number of cache blocks allocated, thereby achieving the purpose of controlling the temperature. This controllable cache allocation mechanism not only helps prevent the device from overheating, but also prolongs the life of the memory and improves the reliability and durability of the product. By adjusting the number of cache blocks allocated and controlling the read and write speeds, the heat generated by the NAND chip during concurrent operations can be effectively reduced to prevent overheating.

[0110] See also Figure 2 The present invention also provides a method for optimizing a cache block of a memory, which can be applied to the above-mentioned memory to manage and optimize the cache block 410 inside the memory. The optimization method may include the following steps:

[0111] Step S10, setting a free list, a write cache list, and a read cache list in the firmware, wherein the free list is used to store relevant information of unused cache blocks, the write cache list is used to store relevant information of cache blocks performing write operations, and the read cache list is used to store relevant information of cache blocks performing read operations;

[0112] Step S20: When performing read and write operations, cache blocks are called from the write cache linked list and the free linked list to perform write operations, and cache blocks are called from the read cache linked list and the free linked list to perform read operations;

[0113] Step S30: When executing the recycling operation, when the mapping relationship of the host data to be erased matches the mapping relationship of the host data stored in a cache block in the write cache linked list and the read cache linked list, the host data of the cache block is erased and the cache block is saved in the free linked list.

[0114] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A memory, characterized in that: include: A main control unit, used to perform read, write and recycle operations; A read-only storage unit, electrically connected to the main control unit, and having firmware therein; a random access memory unit, electrically connected to the main control unit, and having a plurality of cache blocks therein; and A storage unit, electrically connected to the random access storage unit, for storing host data; The firmware is provided with a free list, a write cache list and a read cache list, wherein the free list is used to store relevant information of unused cache blocks, the write cache list is used to store relevant information of cache blocks for performing write operations, and the read cache list is used to store relevant information of cache blocks for performing read operations; When performing a read or write operation, the main control unit is used to call a cache block from the write cache linked list and the free linked list to perform a write operation, and to call a cache block from the read cache linked list and the free linked list to perform a read operation; When performing a recycling operation, when the mapping relationship of the host data to be erased matches the mapping relationship of the host data stored in a certain cache block in the write cache linked list and the read cache linked list, the host data of the cache block is erased, and the relevant information of the cache block is saved in the free linked list; Also includes at least one temperature sensor, the temperature sensor is installed at different positions of the memory to detect the real-time temperature of different positions inside the memory in real time; When the main control unit determines that a certain real-time temperature is greater than a maximum value of a preset temperature range, the main control unit sequentially reduces the number of cache blocks that can be allocated when performing read and write operations until the real-time temperature is lower than a minimum value of the preset temperature range; When the main control unit determines that the real-time temperature at different positions is less than the minimum value of the preset temperature range, it sequentially increases the allocatable number of cache blocks when performing read and write operations until a real-time temperature is greater than the minimum value of the preset temperature range.

2. The memory according to claim 1, characterized in that: The write cache linked list includes a first write cache linked list, a second write cache linked list and a third write cache linked list, and the read cache linked list includes a first read cache linked list, a second read cache linked list and a third read cache linked list; The first write cache linked list is used to store relevant information of the cache block that is performing a write operation; The second write cache linked list is used to store relevant information of cache blocks that have been filled with host data and have not been written to the storage unit; The third write cache linked table is used to store relevant information of the cache blocks of the storage unit that have written the host data; The first read cache linked list is used to store relevant information of the cache block that is performing a read operation; The second read cache linked list is used to store relevant information of cache blocks that have been filled with host data and have not been read out to the host; The third read cache linked list is used to store relevant information of the cache blocks of the host that have read the host data; When performing a read / write operation, the main control unit writes the host data of the cache blocks in the second write cache linked list to the storage unit, reads the host data of the cache blocks in the second read cache linked list to the host, and reallocates the cache blocks when determining that the data amount of the allocated cache blocks is greater than the maximum concurrent read / write data amount; When the main control unit determines that the data amount of the allocated cache block is less than or equal to the maximum read and write concurrent data amount, the cache block is called from the first write cache linked list, the third write cache linked list, and the free linked list to perform a write operation, and the cache block is called from the first read cache linked list, the third read cache linked list, and the free linked list to perform a read operation.

3. The memory according to claim 2, characterized in that: When performing a write operation, the cache blocks in the first write cache linked list are preferentially called to perform the write operation; When the cache blocks in the first write cache linked list are filled, the cache blocks are stored in the second write cache linked list, and cache blocks are called from the free linked list to perform write operations in the first write cache linked list; When there is no cache block in the free linked list, the cache blocks are sorted according to the cache block hit counts of each cache block in the third write cache linked list and the third read cache linked list, and the corresponding cache blocks are called in ascending order of the cache block hit counts to perform write operations.

4. The memory according to claim 3, characterized in that: When there are no cache blocks in the free list, the first write cache list, the third write cache list, and the third read cache list, the host data of the cache blocks in the second write cache list are written to the storage unit to store the relevant information of the corresponding cache blocks in the third write cache list, and at the same time, the host data of the cache blocks in the second read cache list are read out to the host to store the relevant information of the corresponding cache blocks in the third read cache list.

5. The memory according to claim 2, characterized in that: When performing a read operation, when the mapping relationship of the host data to be read matches the mapping relationship of the host data stored in a cache block in the first write cache linked list, the second write cache linked list, the third write cache linked list, the first read cache linked list, and the third read cache linked list, the corresponding host data is read from the cache block to the host, and the mapping table hit count and cache block hit count of the corresponding cache block are updated.

6. The memory according to claim 5, characterized in that: When performing a read operation, when performing a read operation, when the mapping relationship of the host data to be read does not match the mapping relationship of the host data stored in the cache blocks in the first write cache linked list, the second write cache linked list, the third write cache linked list, the first read cache linked list, and the third read cache linked list, the cache blocks in the first read cache linked list are preferentially called to perform the read operation.

7. The memory according to claim 6, characterized in that: When the cache blocks in the first read cache linked list are filled, the cache blocks are stored in the second read cache linked list, and cache blocks are called from the free linked list to perform a read operation in the first read cache linked list; When there is no cache block in the free linked list, the cache blocks are sorted according to the cache block hit counts of each cache block in the third write cache linked list and the third read cache linked list, and the corresponding cache blocks are called in ascending order of the cache block hit counts to perform a read operation; When there are no cache blocks in the free list, the third write cache list, and the third read cache list, the host data of the cache blocks in the second write cache list are written to the storage unit to store the relevant information of the corresponding cache blocks in the third write cache list, and at the same time, the host data of the cache blocks in the second read cache list are read out to the host to store the relevant information of the corresponding cache blocks in the third read cache list.

8. The memory according to claim 2, characterized in that: When performing a recycling operation, when the mapping relationship of the host data to be erased matches the mapping relationship of the host data stored in a cache block in the first write cache linked list, the second write cache linked list, the third write cache linked list, the first read cache linked list, and the third read cache linked list, the host data of the cache block is erased, and the mapping table hit count and cache block hit count of the corresponding cache block are updated, and the relevant information of the cache block that has completed the erase operation is saved in the free linked list.

9. A method for optimizing a cache block of a memory, characterized in that: include: A free list, a write cache list, and a read cache list are set in the firmware, wherein the free list is used to store relevant information of unused cache blocks, the write cache list is used to store relevant information of cache blocks that perform write operations, and the read cache list is used to store relevant information of cache blocks that perform read operations; When performing read and write operations, calling cache blocks from the write cache linked list and the free linked list to perform write operations, and calling cache blocks from the read cache linked list and the free linked list to perform read operations; When performing a recycling operation, when the mapping relationship of the host data to be erased matches the mapping relationship of the host data stored in a certain cache block in the write cache linked list and the read cache linked list, the host data of the cache block is erased, and the relevant information of the cache block is saved in the free linked list; Real-time detection of the real-time temperature of different locations inside the storage; When it is determined that a certain real-time temperature is greater than a maximum value of a preset temperature range, the number of cache blocks that can be allocated when performing read and write operations is reduced in sequence until the real-time temperature is lower than a minimum value of the preset temperature range; When it is determined that the real-time temperature at different locations is less than the minimum value of the preset temperature range, the allocatable number of cache blocks when performing read and write operations is increased sequentially until a real-time temperature is greater than the minimum value of the preset temperature range.

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