Pixel driving circuit and display device

Abstract

The present disclosure provides a pixel driving circuit and a display device, and relates to the technical field of display, and comprises a pulse amplitude modulation circuit and a pulse width modulation circuit which are electrically connected, wherein the pulse amplitude modulation circuit is electrically connected with a light emitting element and is configured to provide a driving current to the light emitting element; the pulse amplitude modulation circuit is configured to control the amplitude of the driving current, and the pulse width modulation circuit is configured to control the pulse width of the driving current; the pulse amplitude modulation circuit comprises a light emitting branch connected with the light emitting element, the light emitting branch comprises a first driving transistor and at least one switching transistor, and at least one transistor in the light emitting branch is a double-gate double-channel transistor. The double-gate double-channel transistor is introduced in the light emitting branch, the output channel of the driving current is increased, and therefore the current transmission time is reduced, the power consumption of the pixel driving circuit is reduced, and the output capability of the pixel driving circuit for the driving current is improved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a pixel driving circuit and a display device. BACKGROUND

[0002] With the continuous development of science and technology, more and more display products, such as mobile phones, tablet computers, notebook computers and smart wearable devices, are widely used in people's daily life and work, bringing great convenience to people's daily life and work, and becoming an indispensable important tool for people today.

[0003] At present, how to reduce the power consumption of display products has become one of the technical problems to be solved. SUMMARY

[0004] In order to solve the above technical problems, the present disclosure provides a pixel driving circuit and a display device, aiming to reduce the power consumption of products.

[0005] In a first aspect, the present disclosure provides a pixel driving circuit, comprising a pulse amplitude modulation circuit and a pulse width modulation circuit electrically connected, wherein the pulse amplitude modulation circuit is electrically connected with a light emitting element, and is configured to provide a driving current to the light emitting element; the pulse amplitude modulation circuit is configured to control the amplitude of the driving current, and the pulse width modulation circuit is configured to control the pulse width of the driving current.

[0006] The pulse amplitude modulation circuit comprises a light emitting branch connected with the light emitting element, the light emitting branch comprising a first driving transistor and at least one switching transistor, and at least one transistor in the light emitting branch is a double-gate double-channel transistor.

[0007] In a second aspect, based on the same inventive concept, the present disclosure further provides a display device comprising the pixel driving circuit provided in the first aspect of the present disclosure.

[0008] The technical scheme provided by the embodiments of the present disclosure has the following advantages compared with the prior art:

[0009] The pixel driving circuit and the display device provided by the present disclosure include a pulse amplitude modulation circuit and a pulse width modulation circuit, wherein the output end of the pulse width modulation circuit is electrically connected with the pulse amplitude modulation circuit, and the output end of the pulse amplitude modulation circuit is electrically connected with the light emitting element. In the light emitting stage, the driving current provided by the pulse amplitude modulation circuit in the pixel driving circuit is transmitted to the light emitting element through a light emitting branch. The light emitting branch includes a driving transistor and a switching transistor, and the driving current is transmitted to the light emitting element through the driving transistor and the switching transistor. When the light emitting element is a light emitting diode such as a mini LED or a micro LED, the driving current required for driving the light emitting element is large. In the related art, when a general transistor such as a single-gate transistor is used as the driving transistor or the switching transistor, the output current capacity of the general transistor is insufficient, and a high Vgs and Vds voltage is required to reach the driving current required by the light emitting diode, which may cause the power consumption to increase. Therefore, in the present disclosure, at least one of the driving transistor and the switching transistor in the light emitting branch is set to a double-gate double-channel transistor. Compared with the general transistor, the double-gate double-channel transistor has two gates and two channels, and the driving current is transmitted through the channel region of the transistor. When the double-gate double-channel transistor is used, the output channel of the driving current is increased, the transmission time of the driving current is reduced, the transmission efficiency of the driving current is improved, and the power consumption of the pixel driving circuit is reduced. Moreover, by increasing the output channel of the driving current, the output current is also increased, thereby improving the brightness of the light emitting element, and when the pixel driving circuit is used in a display product, the overall brightness of the display product is improved. BRIEF DESCRIPTION OF DRAWINGS

[0010] The accompanying drawings, which are incorporated into and form a part of the specification, illustrate an embodiment consistent with the present disclosure and, together with the description, serve to explain the principles of the disclosure.

[0011] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the accompanying drawings required to be used in the embodiments or the prior art description will be briefly introduced. Obviously, for those skilled in the art, other drawings can also be obtained from these drawings without any creative labor.

[0012] Figure 1 A module schematic diagram of the pixel driving circuit provided by the present disclosure is shown.

[0013] Figure 2 A structure schematic diagram of the pixel driving circuit provided by the present disclosure is shown.

[0014] Figure 3Output current comparison chart of single gate structure transistor and double gate double channel transistor;

[0015] Figure 4 Connection diagram of double gate double channel transistor and light emitting element provided by the embodiment of the present disclosure;

[0016] Figure 5 First top view of double gate double channel transistor provided by the embodiment of the present disclosure;

[0017] Figure 6 Another structure diagram of pixel driving circuit provided by the embodiment of the present disclosure;

[0018] Figure 7 Another structure diagram of pixel driving circuit provided by the embodiment of the present disclosure;

[0019] Figure 8 Relationship chart of driving current and drain voltage corresponding to transistors with different width-length ratios;

[0020] Figure 9 Another structure diagram of pixel driving circuit provided by the embodiment of the present disclosure;

[0021] Figure 10 Another structure diagram of pixel driving circuit provided by the embodiment of the present disclosure;

[0022] Figure 11 Another structure diagram of pixel driving circuit provided by the embodiment of the present disclosure;

[0023] Figure 12 Another structure diagram of pixel driving circuit provided by the embodiment of the present disclosure;

[0024] Figure 13 Another structure diagram of pixel driving circuit provided by the embodiment of the present disclosure;

[0025] Figure 14 Connection diagram of pixel driving circuit and light emitting element in the present disclosure;

[0026] Figure 15 Structure diagram of pulse width modulation circuit in pixel driving circuit provided by the embodiment of the present disclosure;

[0027] Figure 16 Another structure diagram of pulse width modulation circuit in pixel driving circuit provided by the embodiment of the present disclosure;

[0028] Figure 17Fig. 2 shows another structural schematic diagram of the pulse width modulation circuit in the pixel driving circuit provided by the embodiment of the present disclosure;

[0029] Figure 18 Fig. 1 shows a schematic diagram of the pixel driving circuit provided by the embodiment of the present disclosure;

[0030] Figure 19 Fig. 3 shows a timing diagram corresponding to the pixel driving circuit shown in Fig. 1; Figure 18

[0031] Figure 20 Fig. 4 shows another schematic diagram of the pixel driving circuit provided by the embodiment of the present disclosure;

[0032] Figure 21 Fig. 5 shows a structural schematic diagram of the display device provided by the embodiment of the present disclosure. DETAILED DESCRIPTION

[0033] In order to enable a more clear understanding of the above-mentioned purposes, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0034] In the following description, a lot of specific details are set forth in order to facilitate a thorough understanding of the present disclosure, but the present disclosure can also be implemented in other different manners from those described herein; obviously, the embodiments described in the specification are only some of the embodiments of the present disclosure, not all the embodiments.

[0035] For the display panel of the inorganic light-emitting diode structure, the inorganic light-emitting diode is connected with the pixel driving circuit, and the driving current is obtained through the pixel driving circuit. The working current of the inorganic light-emitting diode is relatively high, and in the corresponding pixel driving circuit, the Vds (voltage between the source and the drain) and the Vgs (voltage between the gate and the source) required by the part of the transistors will be larger in order to provide a larger driving current, resulting in an increase in the power consumption of the pixel driving circuit.

[0036] In order to solve the problem of large power consumption of the pixel driving circuit, the structure of the pixel driving circuit is improved in the present disclosure, which will be described below in combination with the drawings and specific embodiments.

[0037] Figure 1 Fig. 6 shows a module schematic diagram of the pixel driving circuit provided by the embodiment of the present disclosure, Figure 2 Fig. 7 shows a structural schematic diagram of the pixel driving circuit provided by the embodiment of the present disclosure, Figure 2 The part of the structure of the pulse amplitude modulation circuit is refined. Please refer to Figure 1 and Figure 2 ​The present disclosure provides a pixel driving circuit 100, comprising a pulse amplitude modulation circuit 10 and a pulse width modulation circuit 20 electrically connected, wherein the pulse amplitude modulation circuit 10 is electrically connected with a light emitting element LD, for providing a driving current to the light emitting element LD; the pulse amplitude modulation circuit 10 is configured to control the amplitude of the driving current, and the pulse width modulation circuit 20 is configured to control the pulse width of the driving current; wherein the pulse width of the driving current is understood as the duration of the driving current, and the amplitude of the driving current is understood as the current value of the driving current. The pulse amplitude modulation circuit 10 comprises a light emitting branch 11 connected with the light emitting element LD, the light emitting branch 11 comprises a first driving transistor M0 and at least one switching transistor (for example, switching transistors M1 and M2 are taken as examples in the present disclosure), and at least one transistor in the light emitting branch 11 is a double-gate double-channel transistor. Optionally, the light emitting element LD can be a light-emitting diode (LED), such as a mini LED, a micro LED, etc. Figure 2

[0038] The light emitting branch 11 of the pulse amplitude modulation circuit 10 mentioned in the present disclosure refers to a branch turned on in the pulse amplitude modulation circuit 10 in the light emitting stage, and the light emitting branch 11 is essentially a branch providing the driving current to the light emitting element LD to make the light emitting element LD emit light. The light emitting branch 11 comprises a first driving transistor M0 and at least one switching transistor, and it needs to be explained that, Figure 2 The embodiments shown only show the light emitting branch 11 in the pulse amplitude modulation circuit 10, and do not show other structures in the pulse amplitude modulation circuit 10. In addition, Figure 2 The light emitting branch 11 is taken as an example to be explained, but it is not limited thereto, and in some other embodiments of the present disclosure, the light emitting branch 11 can only comprise one driving transistor and one switching transistor.

[0039] ​The pixel driving circuit provided by the present disclosure generates a driving current under the control of the pulse amplitude modulation circuit 10 and the pulse width modulation circuit 20, and provides the driving current to the light emitting element LD. The pulse amplitude modulation circuit 10 can be used to control the amplitude of the driving current, and the pulse width modulation circuit 20 can be used to adjust the pulse width of the driving current applied to the light emitting element LD. The pulse width modulation circuit 20 is used to adjust the pulse width of the voltage applied to the light emitting element LD, that is, the pulse width modulation circuit 20 adjusts the actual emission period of the driving current applied to the light emitting element LD; at the same time, the driving current applied to the light emitting element LD can be maintained at a constant level to adjust the gray scale or brightness displayed by the light emitting element LD, instead of adjusting the gray scale or brightness displayed by the light emitting element LD by adjusting the size of the driving current applied to the light emitting element LD. Therefore, the pulse amplitude modulation circuit 10 can provide the driving current to the light emitting element LD so that the light emitting element LD is driven with optimal light emitting efficiency, and the gray scale or brightness displayed by the light emitting element LD is adjusted by adjusting the light emitting duty cycle of the light emitting element LD (that is, the emission period of the light emitting element LD) through the pulse width modulation circuit 20.

[0040] In the light emitting stage, the driving current provided by the pulse amplitude modulation circuit 10 to the light emitting element LD is transmitted to the light emitting element LD through the light emitting branch 11. In order to Figure 2 For example, the light emitting branch 11 includes a first driving transistor M0 and a switch transistor, and the driving current is transmitted to the light emitting element LD through the first driving transistor M0 and the switch transistor. When the light emitting element LD is a light emitting diode such as a mini LED or a micro LED, the driving current required to drive the light emitting element LD to emit light is large. In the related art, when a general transistor is used as a driving transistor or a switch transistor, the general transistor, for example, a single-gate transistor, has insufficient output current capacity, and a higher Vgs and Vds voltage is required to reach the driving current required by the light emitting diode, which will cause the power consumption to increase. Figure 3The output current of the single-gate transistor and the double-gate double-channel transistor is shown in the figure, where Vd1 and Vgs1 represent the drain voltage and the gate-source voltage of the single-gate transistor respectively, Vd2 and Vgs2 represent the drain voltage and the gate-source voltage of the double-gate double-channel transistor respectively, ID represents the output driving current, and Vd represents the drain voltage. In order to achieve the same driving current, Vgs1 > Vgs2 and |Vd1| > |Vd2| in the single-gate transistor and the double-gate double-channel transistor. The power consumption P of the transistor is ID x |Vd|, when the value of the driving current ID is consistent, the greater |Vd| is, the greater the power consumption is, and vice versa. Since |Vd1| > |Vd2|, the power consumption of the double-gate double-channel transistor is smaller to achieve the same driving current. Therefore, in the embodiment of the present disclosure, at least one of the driving transistor and the switching transistor in the light-emitting branch 11 is set as a double-gate double-channel transistor. The double-gate double-channel transistor has two gates and two channels compared with the ordinary transistor. When the driving current is transmitted in the light-emitting branch, it will pass through the channel area of the transistor. When the double-gate double-channel transistor is used, it is equivalent to increasing the output channel of the driving current, reducing the transmission time of the driving current, which is beneficial to improve the transmission efficiency of the driving current and reduce the power consumption of the pixel driving circuit. Moreover, by increasing the output channel of the driving current, it is also beneficial to increase the output current, thereby improving the brightness of the light-emitting element. When the pixel driving circuit is used in a display product, it is beneficial to improve the overall brightness of the display product.

[0041] Figure 4 A connection diagram of the double-gate double-channel transistor M and the light-emitting element LD provided by the embodiment of the present disclosure is shown, Figure 5 A first top view of the double-gate double-channel transistor provided by the embodiment of the present disclosure is shown, please refer to Figure 4 and Figure 5 In an optional embodiment of the present disclosure, the double-gate double-channel transistor includes a substrate 00, an active layer P0, a bottom gate G1 and a top gate G2 located on the same side of the substrate 00. In the first direction, the bottom gate G1 and the top gate G2 are located on the two sides of the active layer P0 respectively, and the bottom gate G1 is located between the active layer P0 and the substrate 00. The first direction D1 is perpendicular to the plane where the substrate 00 is located. Optionally, the source s and the drain d of the double-gate double-channel transistor are located on the side of the top gate G2 away from the substrate 00. The outer edge of the orthographic projection of the bottom gate G1 on the plane where the active layer P0 is located is the first edge B1, and the outer edge of the orthographic projection of the top gate G2 on the plane where the active layer P0 is located is the second edge B2. The first edge B1 is outside the second edge B2.

[0042] Please continue to refer to Figure 4 and Figure 5For the double-gate double-channel transistor, it has two gates and two channels, the two gates are top gate G2 and bottom gate G1 respectively, the top gate G2 is located on the side of the active layer P0 away from the substrate, and the bottom gate G1 is located on the side of the active layer P0 towards the substrate. In the first direction, the region formed by the overlap of the top gate G2 and the active layer P0 is the first channel of the transistor, and the region formed by the overlap of the bottom gate G1 and the active layer P0 is the second channel of the transistor, and the first channel and the second channel overlap in the first direction to form a double-channel structure. When the double-gate double-channel transistor is turned on, the driving current is transmitted to the light emitting element LD through the first channel and the second channel respectively, so as to increase the transmission channel of the driving current, which is beneficial to reduce the power consumption. In the embodiment, the projection of the bottom gate G1 on the plane of the active layer P0 is the first edge B1, the projection of the top gate G2 on the plane of the active layer P0 is the second edge BE, and the first edge B1 is on the periphery of the second edge B2, that is, the area of the projection of the bottom gate G1 on the plane of the active layer P0 is greater than the area of the projection of the top gate G2 on the plane of the active layer P0, and the projection of the top gate G2 on the plane of the active layer P0 is located within the projection range of the bottom gate G1 on the plane of the active layer P0, which is beneficial to avoid the misalignment of the top gate G2 and the bottom gate G1, so as to ensure the double-gate and double-channel structure of the transistor.

[0043] Optionally, the distance between the first edge corresponding to the bottom gate G1 and the second edge corresponding to the top gate G2 in the foregoing embodiment is D0, and D0≥1μm. That is, the first edge B1 of the projection of the bottom gate G1 on the plane of the active layer P0 is expanded outward relative to the second edge B2 of the projection of the top gate G2 on the plane of the active layer P0 by at least 1μm, so that even considering the alignment deviation in the manufacturing process, the overlapping area of the bottom gate G1 and the top gate G2 can be ensured, and the double-gate and double-channel structure of the transistor can be ensured.

[0044] The structure of the double-gate double-channel transistor mentioned in the embodiments of the present disclosure can be referred to Figure 4 and Figure 5 , and the repeated parts will not be described again.

[0045] It should be noted that Figure 2 the embodiments shown only show the scheme that the driving transistor in the light emitting branch 11 is a double-gate double-channel transistor, and in some other embodiments of the present disclosure, other transistors in the light emitting branch 11 can also be provided with a double-gate double-channel structure. For example, please refer to Figure 6 and Figure 7 , Figure 6 and Figure 7 respectively show another structure schematic diagram of the pixel driving circuit provided by the embodiments of the present disclosure, Figure 6 and Figure 7 part of the structure of the pulse amplitude modulation circuit 10 is refined, and Figure 2The difference lies in the increased number of dual-gate dual-channel transistors in the light-emitting branch 11. Figure 6 In the illustrated embodiment, the switching transistors in the light-emitting branch 11 include a first switching transistor M1 and a second switching transistor M2. A first driving transistor M0 is connected in series between the first switching transistor M1 and the second switching transistor M2. The gate of the first switching transistor M1 is connected to the first switching control terminal EM1, and the gate of the second switching transistor M2 is connected to the second switching control terminal EM2. The second switching transistor M2 is connected in series between the first driving transistor M0 and the light-emitting element LD. The first switching transistor M1, the first driving transistor M0, and the second switching transistor M2 are all dual-gate dual-channel transistors. In this case, each transistor in the light-emitting branch 11 is a dual-gate dual-channel transistor, and each transistor has two channels. During the light-emitting stage, when the driving current passes through each transistor, it will pass through both channels of each transistor, thereby effectively increasing the transmission rate of the driving current and increasing the output current, which is more conducive to reducing the power consumption of the pixel driving circuit.

[0046] Figure 7 The illustrated embodiments and Figure 6 The difference lies in the type of the second switching transistor M2. Please refer to [link / reference]. Figure 7 In the light-emitting branch 11, the switching transistors include a first switching transistor M1 and a second switching transistor M2. A first driving transistor M0 is connected in series between the first switching transistor M1 and the second switching transistor M2. The gate of the first switching transistor M1 is connected to the first switching control terminal EM1, and the gate of the second switching transistor M2 is connected to the second switching control terminal EM2. The second switching transistor M2 is connected in series between the first driving transistor M0 and the light-emitting element LD. The first driving transistor M0 and the first switching transistor M1 are dual-gate dual-channel transistors, and the second switching transistor M2 is a four-gate four-channel transistor.

[0047] Specifically, Figure 7 The illustrated embodiment demonstrates another feasible implementation of the light-emitting branch 11, and... Figure 6Similar to the illustrated embodiment, the light-emitting branch 11 includes a first drive transistor M0 and two switch transistors, a first switch transistor M1 connected in series between the first power voltage terminal VDD_PAM and the first drive transistor M0, and a second switch transistor M2 connected in series between the light-emitting element LD and the first drive transistor M0. In the light-emitting branch 11, the second switch transistor M2 disposed close to the light-emitting element LD is a four-gate four-channel transistor, and the first drive transistor M0 and the first switch transistor M1 are double-gate double-channel transistors. The four-gate four-channel transistor can be regarded as the series connection of two double-gate double-channel transistors, further increasing the number of channels compared to the double-gate double-channel transistor, which is equivalent to further increasing the current transmission path. Since the second switch transistor M2 is closer to the light-emitting element LD than the first drive transistor M0, the four-gate four-channel second switch transistor M2 can further improve the transmission rate of the drive current and reduce the transmission time of the drive current, further improving the ability of the pixel drive circuit to output the drive current, thereby more effectively reducing the power consumption of the circuit. In addition, in the present embodiment, the first switch transistor M1 and the first drive transistor M0 are both double-gate double-channel transistors, and the second switch transistor M2 is a four-gate four-channel transistor. Compared to single-gate transistors, both the number of current output channels is increased, so the output power consumption of the first drive transistor M0, the first switch transistor M1, and the second switch transistor M2 is effectively reduced, thereby facilitating the reduction of the overall power consumption of the pixel drive circuit.

[0048] Please continue to refer to Figure 6 and Figure 7 In an optional embodiment of the present disclosure, the aspect ratio of the second switch transistor M2 is greater than the aspect ratio of the first switch transistor M1.

[0049] It should be noted that for a double-gate double-channel transistor, as described above, please refer to Figure 4 , along the first direction D1, its top gate G2 and bottom gate G1 overlap, and the two channels also overlap. The aspect ratio of the double-gate double-channel transistor can be regarded as the aspect ratio of one of the channels, such as the aspect ratio of the channel formed by the overlap of its top gate G2 and active layer P0. For a four-gate four-channel transistor, its aspect ratio can be regarded as the sum of the aspect ratios of the two double-gate double-channel transistors.

[0050] Please continue to refer to Figure 6 and Figure 7When the first switch transistor M1 and the second switch transistor M2 are both included in the light-emitting branch 11, the first switch transistor M1 is connected in series between the first drive transistor M0 and the first power voltage terminal VDD PAM, and the second switch transistor M2 is connected in series between the first drive transistor M0 and the light-emitting element LD, that is, the second switch transistor M2 is closer to the light-emitting element LD than the first switch transistor M1. The driving capability of a transistor is positively correlated with its width-length ratio, and the greater the width-length ratio, the stronger the driving capability and the stronger the output current capability. In the present embodiment, when the width-length ratio of the second switch transistor M2 close to the light-emitting element LD is set to be greater, it is beneficial to increase the output current capability of the transistor close to the light-emitting element LD, so that the required driving current can be output to the light-emitting element LD in a shorter time, which is beneficial to improve the overall output current capability of the pixel driving circuit and reduce the overall power consumption of the pixel driving circuit.

[0051] Please continue to refer to Figure 6 and Figure 7 When the width-length ratio of the second switch transistor M2 is greater than that of the first switch transistor M1, optionally, the width-length ratio of the first switch transistor M1 is A1, the width-length ratio of the second switch transistor M2 is A2, A2 = K x A1, and K ≥ 2.

[0052] Figure 8 A graph of the relationship between the driving current and the drain voltage of the transistor with different width-length ratios is shown, and A1 = 45 μm / 4 μm and A2 = 90 μm / 4 μm are taken as examples for illustration, at this time, K = 2, that is, the width-length ratio of the second switch transistor M2 is twice that of the first switch transistor M1. Please continue to refer to Figure 8When the driving current reaches 1.00E-04, the Vd corresponding to the first switch transistor M1 is about -0.55V, and the Vd corresponding to the second switch transistor M2 is about -0.25V, that is, to achieve the same driving current, the absolute value of the Vd of the second switch transistor M2 is smaller, and considering the power consumption P = ID x |Vd| of the transistor, the smaller the |Vd| is, the smaller the corresponding power consumption is, so the power consumption of the second switch transistor M2 will be smaller, when K = 2, the power consumption of the second switch transistor M2 can be reduced by at least 50% compared with the first switch transistor M1, when K > 2, the power consumption of the second switch transistor M2 can be reduced by more than 50% compared with the first switch transistor M1, therefore, when the width-length ratio of the second switch transistor M2 is set to be 2 times or more than 2 times the width-length ratio of the first switch transistor M1, the power consumption of the second switch transistor M2 can be effectively reduced. At the same time, since the width-length ratio of the transistor is positively correlated with the output current capacity, when the width-length ratio of the second switch transistor M2 is set to be 2 times or more than 2 times the width-length ratio of the first switch transistor M1, it is beneficial to greatly improve the ability of the second switch transistor M2 to output driving current to the light emitting element LD, thereby improving the ability of the pixel driving circuit as a whole to output driving current to the light emitting element LD.

[0053] Please refer to Figure 7 In an optional embodiment of the present disclosure, the first switch control end EM1 and the second switch control end EM2 are the same switch control end. The embodiment shows a scheme in which the gate of the first switch transistor M1 and the gate of the second switch transistor M2 in the light emitting branch 11 are connected to the same switch control end. In the light emitting stage, the first switch transistor M1 and the second switch transistor M2 are controlled to be turned on at the same time under the control of the switch control end, so as to facilitate reducing the number of switch control ends connected to the switch transistors and simplifying the circuit structure of the pixel driving circuit.

[0054] Of course, in some other embodiments of the present disclosure, the first switch control end EM1 and the second switch control end EM2 corresponding to the first switch transistor M1 and the second switch transistor M2 can also be different control ends according to needs, as long as the two different control ends can control the first switch transistor M1 and the second switch transistor M2 to be turned on in the light emitting stage.

[0055] In an optional embodiment of the present disclosure, please refer to Figure 2 , Figure 6 and Figure 7 , the output end OUT of the pulse width modulation circuit 20 is connected to the gate of the first driving transistor M0, or please refer to Figure 9 , the output end OUT of the pulse width modulation circuit 20 is connected to the gate of the first driving transistor M0 through the capacitor C, Figure 9Fig. 2 shows another structural schematic diagram of the pixel driving circuit provided by the embodiment of the present disclosure.

[0056] Please refer to Figure 2 , Figure 6 and Figure 7 When the output end OUT of the pulse width modulation circuit 20 is directly connected to the gate of the first driving transistor M0 in the pulse amplitude modulation circuit 10, the signal at the output end of the pulse width modulation circuit 20 directly acts on the gate of the first driving transistor M0 in the pulse amplitude modulation circuit 10. In this way, the signal at the output end of the pulse width modulation circuit 20 can directly control the potential change of the gate of the first driving transistor M0, so as to control the off state of the first driving transistor M0, thereby realizing the modulation of the pulse width of the driving current output by the pulse amplitude modulation circuit 10 to the light emitting element LD.

[0057] Please refer to Figure 9 When the output end OUT of the pulse width modulation circuit 20 is connected to the gate of the first driving transistor M0 through the capacitor C, it is assumed that, among the two plates of the capacitor C, the plate connected to the pulse width modulation circuit 20 is the first plate, and the plate connected to the pulse amplitude modulation circuit 10 is the second plate. The control current provided by the output end of the pulse width modulation circuit 20 causes the voltage of the first plate of the capacitor to change by△V, and the voltage of the second plate of the capacitor also changes by△V accordingly. Through the coupling effect of the capacitor, the gate voltage of the first driving transistor M0 in the pulse amplitude modulation circuit 10 changes by△V, which can control the first driving transistor M0 to be turned off, so that the pulse amplitude modulation circuit 10 stops providing the driving current to the light emitting element LD, thereby realizing the control of the driving current flow period. By introducing the capacitor, there is no direct correlation between the gate voltage of the first driving transistor M0 in the pulse amplitude modulation circuit 10 and the control current provided by the pulse width modulation circuit 20, which can more accurately control the turning off of the driving transistor and is conducive to improving the performance stability of the pixel driving circuit. Moreover, the voltage value of the signal at the output end of the pulse width modulation circuit 20 and the source voltage of the first driving transistor M0 do not necessarily have a size relationship, which can reduce the correlation between the signals required for the operation of the pulse amplitude modulation circuit 10 and the operation of the pulse width modulation circuit 20.

[0058] Figure 10 Fig. 2 shows another structural schematic diagram of the pixel driving circuit provided by the embodiment of the present disclosure. In an optional embodiment of the present disclosure, the light emitting branch 11 further includes a third transistor M3, which is connected in series between the first driving transistor M0 and the light emitting element LD, and the gate of the third transistor M3 is connected to the output end OUT of the pulse width modulation circuit 20.

[0059] The third transistor M3 is introduced in the light emitting branch 11, and the third transistor M3 is taken as an example to be connected in series between the first driving transistor M0 and the second switch transistor M2. In the light emitting stage, the first switch transistor M1, the first driving transistor M0, the second switch transistor M2 and the third transistor M3 in the light emitting branch 11 are all turned on, and the driving current is sent to the light emitting element LD via the light emitting branch 11. In this embodiment, the output end OUT of the pulse width modulation circuit 20 is connected to the gate of the third transistor M3, the change of the potential of the gate of the third transistor M3 is controlled by the output signal of the pulse width modulation circuit 20, the control of the off state of the third transistor M3 is realized, and the modulation of the pulse width of the driving current output by the pulse amplitude modulation circuit 10 to the light emitting element LD is realized.

[0060] Please continue to refer to Figure 10 In an optional embodiment of the present disclosure, the third transistor M3 is connected in series between the first driving transistor M0 and the second switch transistor M2; the width-length ratio of the third transistor M3 is A3, the width-length ratio of the first switch transistor M1 is A1, and the width-length ratio of the second switch transistor M2 is A2, wherein A1

[0061] When the third transistor M3 is introduced in the light emitting branch 11, and the third transistor M3 is connected in series between the first driving transistor M0 and the second switch transistor M2, among the first switch transistor M1, the third transistor M3 and the second switch transistor M2, the transistor directly connected with the light emitting element LD is the second switch transistor M2, along the flow direction of the driving current in the light emitting branch 11, the first switch transistor M1 is far away from the light emitting element LD, the third switch transistor M03 is located between the first switch transistor M1 and the second switch transistor M2, and the width-length ratio relationship of the three is set as A1

[0062] Please continue to refer to Figure 10Optionally, the third transistor M3 is a double-gate double-channel transistor. When the third transistor M3 is introduced between the first driving transistor M0 and the second switch transistor M2 in the light emitting branch 11, the third transistor M3 is set as a double-gate double-channel transistor, so that the third transistor M3 has two current transmission channels, and the driving current will pass through the two channels of the third transistor M3 when passing through the third transistor M3, thereby effectively increasing the transmission rate of the driving current and being beneficial to increasing the output current, and thus being more beneficial to reducing the power consumption of the pixel driving circuit.

[0063] As an optional embodiment, Figure 10 In the pixel driving circuit, the first switch transistor M1, the first driving transistor M0, the third transistor M3 and the second switch transistor M2 are all double-gate double-channel transistors.

[0064] As another optional embodiment, the second switch transistor M2 in Figure 10 is set as a four-gate four-channel transistor, and the first switch transistor M1, the first driving transistor and the third transistor M3 remain as double-gate double-channel transistors.

[0065] Figure 11 Another structure of the pixel driving circuit provided by the embodiment of the present disclosure is shown in FIG. 3, and the pixel driving circuit is composed of a first switch transistor M1, a first driving transistor M0, a third transistor M3 and a second switch transistor M2. Figure 11 In an optional embodiment of the present disclosure, the third transistor M3 is connected in series between the second switch transistor M2 and the light emitting element LD; the width-length ratio of the third transistor M3 is A3, the width-length ratio of the first switch transistor M1 is A1, and the width-length ratio of the second switch transistor M2 is A2, wherein A1 < A2 < A3.

[0066] The embodiment shows another possible connection mode when the third transistor M3 is introduced in the light emitting branch 11, specifically, the third transistor M3 is connected in series between the second switch transistor M2 and the light emitting element LD, the transistor directly connected with the light emitting element LD is the third transistor M3, in the light emitting branch 11, along the flow direction of the driving current in the light emitting branch 11, the third transistor M3 is closest to the light emitting element LD, the first switch transistor M1 is farthest from the light emitting element LD, and the second switch transistor M2 is between the first switch transistor M1 and the third transistor M3, at this time, the width-length ratio relationship of the three transistors is set as A1

[0067] Optionally, in the light emitting branch 11 of the embodiment, the first switch transistor M1, the first driving transistor M0, the second switch transistor M2 and the third transistor M3 are all double-gate double-channel transistors, so that each transistor in the light emitting branch 11 has two current transmission channels when transmitting the driving current, thereby more favorably improving the transmission rate of the driving current in the light emitting branch 11 and reducing the overall power consumption of the pixel driving circuit.

[0068] Figure 12 Another structure schematic diagram of the pixel driving circuit provided by the embodiment of the present disclosure is shown in FIG. 6, and details are Figure 12 In an optional embodiment of the present disclosure, the third transistor M3 is a four-gate four-channel transistor.

[0069] The light emitting branch 11 of the embodiment is the same as Figure 11 The difference between the embodiment shown in FIG. 6 and the embodiment shown in FIG. 5 is that the type of the third transistor M3 is different, and the others are the same, and the width-length ratio relationship still satisfies A1

[0070] Figure 13 Another structure schematic diagram of the pixel driving circuit provided by the embodiment of the present disclosure is shown in FIG. 6, and details are Figure 13In an optional embodiment of the present disclosure, the pulse amplitude modulation circuit 10 further comprises a first data write transistor M4 connected in series between the first data signal end DATA PAM and the first electrode of the first driving transistor M0, and the first electrode of the first driving transistor M0 is connected to the first switch transistor M1; the first data write transistor M4 is a double-gate double-channel transistor.

[0071] The present embodiment shows the scheme of introducing the first data write transistor M4 into the pulse amplitude modulation circuit 10, which is used to transmit the data signal of the first data signal end DATA PAM to the first driving transistor M0 in the data write stage of the pulse amplitude modulation circuit 10. Generally, the driving current for driving the light emitting element LD to emit light is related to the above-mentioned data signal, and whether the light emitting element LD can emit light according to the preset brightness is closely related to the accuracy of the voltage corresponding to the data signal. In the present embodiment of the present disclosure, when the first data write transistor M4 is set as a double-gate double-channel transistor, in the data write stage, the data signal can be transmitted through the two channels of the first data write transistor M4, thereby facilitating to improve the transmission rate of the data signal, reduce the voltage drop of the data signal, and facilitate to improve the accuracy of the data signal received by the pixel driving circuit.

[0072] It should be noted that, in addition to the first data write transistor M4 and the plurality of transistors in the light emitting branch 11, the pulse amplitude modulation circuit 10 can further comprise some other units, such as a threshold compensation unit, an initialization unit, etc., which will be described in subsequent embodiments.

[0073] Figure 14 Fig. 1 shows a connection diagram of the pixel driving circuit and the light emitting element LD in the present disclosure, in an optional embodiment of the present disclosure, the pixel driving circuit comprises a first pixel driving circuit 101 and a second pixel driving circuit 102, the first pixel driving circuit 101 is used to be electrically connected with a first color light emitting element LD1, the second pixel driving circuit 102 is used to be electrically connected with a second color light emitting element LD2, and the light emitting efficiency of the first color light emitting element LD1 is less than that of the second color light emitting element LD2; please combine Figure 6 and Figure 7 In the first pixel driving circuit 101, the width-length ratio of the first switch transistor M1 is A11, and the width-length ratio of the second switch transistor M2 is A21; in the second pixel driving circuit 102, the width-length ratio of the first switch transistor M1 is A12, and the width-length ratio of the second switch transistor M2 is A22; wherein, A11>A12, and / or, A21>A22.

[0074] It should be noted that, Figure 14In the illustrated embodiment, the first pixel driving circuit 101 and the second pixel driving circuit 102 can respectively adopt the structure of the pixel driving circuit in any of the foregoing embodiments, and the present disclosure does not make specific limitations thereon. Alternatively, the first pixel driving circuit 101 and the second pixel driving circuit 102 adopt the same circuit structure, for example, the number of transistors contained in the light emitting branch 11 corresponding to the first pixel driving circuit 101 and the second pixel driving circuit 102 is the same, the connection relationship is the same, the connection relationship between the light emitting branch 11 and the pulse width modulation circuit 20 is also the same, the difference lies in that the width-length ratio of some transistors in the light emitting branch 11 is different, and the light emitting color of the light emitting element LD connected to the light emitting branch 11 is different.

[0075] In the present embodiment, the first pixel driving circuit 101 is connected with the first color light emitting element LD1, the second pixel driving circuit 102 is connected with the second color light emitting element LD2, and the light emitting efficiency of the second color light emitting element LD2 is higher than that of the first color light emitting element LD1, that is, to achieve the same brightness, the driving current required by the first color light emitting element LD1 is greater than that required by the second color light emitting element LD2.

[0076] To this end, a first feasible implementation is to set the width-length ratio A11 of the first switch transistor M1 corresponding to the first pixel driving circuit 101 to be greater than the width-length ratio A12 of the first switch transistor M1 corresponding to the second pixel driving circuit 102, and at the same time, set the width-length ratio A21 of the second switch transistor M2 corresponding to the first driving circuit to be equal to the width-length ratio A22 of the second switch transistor M2 corresponding to the second pixel driving circuit; in this way, the ability of the light emitting branch 11 corresponding to the first driving circuit to output driving current is equivalent to being improved, which is conducive to improving the driving current output by the first driving circuit, so as to improve the light emitting brightness of the first color light emitting element LD1 with lower light emitting efficiency, and is conducive to balancing the light emitting brightness difference between the first color light emitting element LD1 and the second color light emitting element LD2, and improving the display brightness uniformity. Alternatively, A11=K1×A12, K1≥1.5, the inventors have found through research that when K1<1.5, the driving current output by the light emitting branch 11 does not have obvious improvement effect, and when K1≥1.5, the driving current output by the first pixel driving circuit can be effectively improved.

[0077] The second feasible implementation manner is that the width-length ratio A21 of the second switch transistor M2 corresponding to the first pixel driving circuit 101 is greater than the width-length ratio A22 of the second switch transistor M2 corresponding to the second pixel driving circuit 102, and the width-length ratio A11 of the first switch transistor M1 corresponding to the first driving circuit is equal to the width-length ratio A12 of the first switch transistor M1 corresponding to the second pixel driving circuit. Compared with the first switch transistor M1, the second switch transistor M2 is closer to the light emitting element LD. When the width-length ratio of the second switch transistor M2 of the first pixel driving circuit 101 is set to be relatively large, it is more conducive to improving the output driving tube current of the first pixel driving circuit 101 and increasing the size of the output driving current, and thus it is more conducive to reducing the difference in luminous brightness of the first color light emitting element LD1 and the second color light emitting element LD2 and improving the display brightness uniformity. Optionally, A12=K2×A22, K2≥1.5. The inventors have found through research that when K2<1.5, the effect of improving the output driving current of the light emitting branch 11 is not obvious, and when K2≥1.5, the output driving current of the first pixel driving tube circuit can be effectively improved.

[0078] The third feasible implementation manner is that the width-length ratio A11 of the first switch transistor M1 corresponding to the first pixel driving circuit 101 is greater than the width-length ratio A12 of the first switch transistor M1 corresponding to the second pixel driving circuit 102, and the width-length ratio A21 of the second switch transistor M2 corresponding to the first pixel driving circuit 101 is greater than the width-length ratio A22 of the second switch transistor M2 corresponding to the second pixel driving circuit 102. By simultaneously increasing the width-length ratios of the first switch transistor M1 and the second switch transistor M2 in the first pixel driving circuit 101, it is conducive to further increasing the output driving current of the first pixel driving circuit 101 and reducing the difference in luminous brightness of the first color light emitting element LD1 and the second color light emitting element LD2, thereby being conducive to further improving the display brightness uniformity. Optionally, A11=K1×A12, K1≥1.5; and A12=K2×A22, K2≥1.5. In this way, the output driving current of the first pixel driving circuit 101 is obviously improved.

[0079] When the first pixel driving circuit 101 and the second pixel driving circuit 102 are structures corresponding to any one of the embodiments of the present disclosure, Figure 11 to Figure 13 In an optional embodiment of the present disclosure, when the first pixel driving circuit 101 and the second pixel driving circuit 102 are structures corresponding to any one of the embodiments of the present disclosure, the light emitting branch 11 further includes a third transistor M3, the third transistor M3 is connected in series between the first driving transistor M0 and the light emitting element LD, and the gate of the third transistor M3 is connected to the output end OUT of the pulse width modulation circuit 20. In the first pixel driving circuit 101, the width-length ratio of the third transistor M3 is A31; in the second pixel driving circuit 102, the width-length ratio of the third transistor M3 is A32; and A31>A32.

[0080] When the first pixel driving circuit 101 and the second pixel driving circuit 102 both include the third transistor M3, due to the fact that the light emitting efficiency of the first color light emitting element LD1 connected to the first pixel driving circuit 101 is lower than the light emitting efficiency of the second color light emitting element LD2 connected to the second pixel driving circuit 102, at this time, under the premise that the width-length ratios of the first switch transistor M1 and the second switch transistor M2 in the first pixel driving circuit 101 and the second pixel driving circuit 102 satisfy A11>A12 and / or A21>A22, further setting the width-length ratio A31 of the third transistor M3 in the first pixel driving circuit 101 to be greater than the width-length ratio A32 of the third transistor M3 in the second pixel driving circuit 102 is beneficial to further improving the ability of the first pixel driving circuit 101 to output a driving current, so as to further reduce the difference in light emitting brightness between the first light emitting element LD and the second light emitting element LD, thereby being beneficial to improving the display brightness uniformity.

[0081] Optionally, the first color light emitting element LD1 mentioned in the present disclosure is a red light emitting element LD, and the second color light emitting element LD2 is a green light emitting element LD or a blue light emitting element LD.

[0082] Figure 15 Fig. 1 shows a structural schematic diagram of a pulse width modulation circuit 20 in a pixel driving circuit provided by an embodiment of the present disclosure, please refer to Figure 15 In an optional embodiment of the present disclosure, the pulse width modulation circuit 20 includes an output branch 21, the output branch 21 includes a second driving transistor M00 and at least one switch transistor, and at least one transistor in the output branch 21 is a double-gate double-channel transistor. It should be noted that, Figure 15 The embodiment shown only illustrates the structure of the output branch 21 in the pulse width modulation circuit 20, and does not represent the entire circuit structure of the pulse width modulation circuit 20. The pulse width modulation circuit 20 can also include a reset unit, a threshold compensation unit, a data writing unit and the like, which will be described in subsequent embodiments. It should be noted that, Figure 15 The output end of the pulse width modulation circuit 20 shown can be connected to the pulse amplitude modulation circuit 10 in any of the foregoing embodiments.

[0083] In the foregoing embodiments, the first color light emitting element LD1 is a red light emitting element LD, and the second color light emitting element LD2 is a green light emitting element LD or a blue light emitting element LD. Figure 15The output branch 21 of the pulse width modulation circuit 20 in the embodiment shown can be regarded as a branch that is turned on by the output stage of the pulse width modulation circuit 20. When the output branch 21 is turned on, the pulse width modulation circuit 20 outputs a control signal to the pulse amplitude modulation circuit 10 to control the conduction state of the light-emitting branch 11 of the pulse amplitude modulation circuit 10, thereby achieving adjustment of the pulse width of the driving current provided to the light-emitting element LD. In the embodiment, the output branch 21 includes the second drive transistor M00 and at least one switching transistor, and at least one of the second drive transistor M00 and the switching transistor is a double-gate double-channel transistor. The double-gate double-channel transistor increases the transmission channel of the output signal, thereby facilitating the ability of the pulse width modulation circuit 20 to output a control signal to the pulse amplitude modulation circuit 10, and thereby facilitating the ability of the pulse width modulation circuit 20 to turn off the light-emitting branch 11 of the pulse amplitude modulation circuit 10.

[0084] It should be noted that, Figure 15 The embodiment shown only shows a scheme in which the output branch 21 of the pulse width modulation circuit 20 includes the second drive transistor M00 and two switching transistors, and the second drive transistor M00 and one of the switching transistors are double-gate double-channel transistors, but is not limited thereto. Please refer to Figure 16 , Figure 16 Another structure of the pulse width modulation circuit 20 in the pixel driving circuit provided by the embodiment of the present disclosure is shown. Optionally, the switching transistor in the pulse width modulation circuit 20 includes a third switching transistor M03 and a fourth switching transistor M04, the second drive transistor M00 is connected in series between the third switching transistor M03 and the fourth switching transistor M04, the gate of the third switching transistor M03 and the gate of the fourth switching transistor M04 are connected to the third switching control terminal EM3, and the fourth switching transistor M04 is connected in series between the second drive transistor M00 and the output terminal OUT of the pulse width modulation circuit 20. The second drive transistor M00, the third switching transistor M03, and the fourth switching transistor M04 are double-gate double-channel transistors. It should be noted that, Figure 16 The pulse width modulation circuit 20 in the embodiment shown can be combined with any of the pulse amplitude modulation circuits in the foregoing embodiments to form the pixel driving circuit in the present disclosure.

[0085] In the embodiment, the output branch 21 in the pulse width modulation circuit 20 includes the third switch transistor M03, the second drive transistor M00 and the fourth switch transistor M04 connected in series, and the third switch transistor M03, the second drive transistor M00 and the fourth switch transistor M04 are all double-gate double-channel transistors. In the output stage of the pulse width modulation circuit 20, the third switch transistor M03, the second drive transistor M00 and the fourth switch transistor M04 are all turned on, and the control signal is transmitted through the two channels of each transistor in the output branch 21, thereby effectively improving the ability of the pulse width modulation circuit 20 to output the control signal to the pulse amplitude modulation circuit 10, and thus facilitating the improvement of the ability of the pulse width modulation circuit 20 to turn off the light-emitting branch 11 of the pulse amplitude modulation circuit 10, and at the same time, facilitating the reduction of the overall power consumption of the pixel driving circuit.

[0086] Please continue to refer to Figure 16 In an optional embodiment of the present disclosure, the width-length ratio of the third switch transistor M03 is A3, the width-length ratio of the fourth switch transistor M04 is A4, A4=K4*A3, and K4≥2. In the transmission direction of the control signal of the output branch 21, the third switch transistor M03 is farther away from the output end of the pulse width modulation circuit 20, and the fourth switch transistor M04 is closer to the output end of the pulse width modulation circuit 20. The fourth switch transistor M04 is the transistor directly connected to the output end of the pulse width modulation circuit 20. The greater the width-length ratio of the transistor, the stronger the driving ability, and the more conducive to improving the ability to output the control signal. In the embodiment, the width-length ratio of the fourth switch transistor M04 directly connected to the pulse width modulation circuit 20 is set to be larger, which is more conducive to improving the ability to output the control signal to the pulse amplitude modulation circuit 10, improving the transmission rate of the control signal, and thus more conducive to improving the turn-off ability of the pulse width modulation circuit 20 to the pulse amplitude modulation circuit 10.

[0087] Please combine Figure 14 to Figure 16 In an optional embodiment of the present disclosure, the pixel driving circuit includes a first pixel driving circuit 101 and a second pixel driving circuit 102, the first pixel driving circuit 101 is configured to be electrically connected to a first color light-emitting element LD1, the second pixel driving circuit 102 is configured to be electrically connected to a second color light-emitting element LD2, and the light-emitting efficiency of the first color light-emitting element LD1 is less than that of the second color light-emitting element LD2. In the first pixel driving circuit 101, the width-length ratio of the third switch transistor M03 is A31, and the width-length ratio of the fourth switch transistor M04 is A41. In the second pixel driving circuit 102, the width-length ratio of the third switch transistor M03 is A32, and the width-length ratio of the fourth switch transistor M04 is A42. Wherein, A31>A32, and / or A41>A42.

[0088] In this embodiment, the first pixel driving circuit 101 is connected with the first color light emitting element LD1, the second pixel driving circuit 102 is connected with the second color light emitting element LD2, and the light emitting efficiency of the second color light emitting element LD2 is higher than that of the first color light emitting element LD1, that is, to achieve the same brightness, the driving current required by the first color light emitting element LD1 is greater than that required by the second color light emitting element LD2. At this time, in addition to differentiating the width-length ratio of the switching transistor in the pulse amplitude modulation circuit 10 corresponding to the first pixel driving circuit 101 and the second pixel driving circuit 102, the width-length ratio of the switching transistor in the pulse width modulation circuit 20 can also be differentiated, for example, the width-length ratio A31 of the third switching transistor M03 in the first pixel driving circuit 101 is greater than that A32 of the third switching transistor M03 in the second pixel driving circuit 102, and at this time A41=A42 can be set; or, the width-length ratio A41 of the fourth switching transistor M04 in the first pixel driving circuit 101 is greater than that A42 of the fourth switching transistor M04 in the second pixel driving circuit 102, and at this time A31=A32 can be set; or, the width-length ratio A31 of the third switching transistor M03 in the first pixel driving circuit 101 is greater than that A32 of the third switching transistor M03 in the second pixel driving circuit 102, and the width-length ratio A41 of the fourth switching transistor M04 in the first pixel driving circuit 101 is greater than that A42 of the fourth switching transistor M04 in the second pixel driving circuit 102, so as to improve the transmission efficiency of the data signal corresponding to the pulse width modulation circuit in the first pixel driving circuit 101, thereby improving the off ability of the pulse width modulation circuit 20 to the pulse amplitude modulation circuit 10 in the first pixel driving circuit 101, so as to ensure the light emitting brightness accuracy of the first color light emitting element LD1 corresponding to the first pixel driving circuit 101.

[0089] Figure 17 Another structure of the pulse width modulation circuit 20 in the pixel driving circuit provided by the embodiment of the present disclosure is shown in the figure, please refer to Figure 17 In an optional embodiment of the present disclosure, the pulse width modulation circuit 20 includes a second data writing transistor M05, which is connected in series between the second data signal end DATA_PWM and the first electrode of the second driving transistor M00, and the first electrode of the second driving transistor M00 is connected with the third switching transistor M03; the second data writing transistor M05 is a double-gate double-channel transistor.

[0090] In the embodiment, when the second data write transistor M05 in the pulse width modulation circuit 20 is turned on, the data signal of the second data signal end DATA_PWM can be transmitted to the second drive transistor M00. In the output stage of the pulse width modulation circuit 20, the size of the control signal generated by the output branch 21 is related to the data signal of the second data signal end DATA_PWM, that is, the off ability of the pulse width modulation circuit 20 to the pulse amplitude modulation circuit 10 is related to the data signal. In the embodiment, the second data write transistor M05 is set as a double-gate double-channel transistor, which is beneficial to improve the transmission rate of the second data write transistor M05 to the data signal and the accuracy of the data signal, and is beneficial to improve the accuracy of the control signal transmitted by the pulse width modulation circuit 20 to the pulse amplitude modulation circuit 10, and is further beneficial to ensure the off ability of the pulse width modulation circuit 20 to the pulse amplitude modulation circuit 10.

[0091] The present disclosure will be further described below in combination with the specific structure of the pixel driving circuit, Figure 18 Fig. 1 shows a schematic diagram of a pixel driving circuit provided by an embodiment of the present disclosure, Figure 19 Fig. 2 shows a corresponding timing diagram, please refer to Figure 18 Fig. 3 shows a corresponding timing diagram, please refer to Figure 18 and Figure 19 In an optional embodiment of the present disclosure, the pixel driving circuit is configured to provide a driving current to the light emitting element; the pixel driving circuit comprises a pulse amplitude modulation circuit 10 and a pulse width modulation circuit 20, the pulse amplitude modulation circuit 10 is configured to control the amplitude of the driving current based on the applied pulse amplitude modulation data, and the pulse width modulation circuit 20 is configured to control the pulse width of the driving current.

[0092] It should be noted that, Figure 18 The pixel driving circuit shown is only a schematic, and the present disclosure does not limit the actual structure of the pixel driving circuit. In some other embodiments of the present disclosure, any other feasible pixel driving circuit structure can also be used. In the pixel driving circuit, the pulse width modulation circuit 20 is electrically connected with the pulse amplitude modulation circuit 10, and the pulse amplitude modulation circuit 10 is used to be electrically connected with the light emitting element.

[0093] Please continue to refer to Figure 18 and Figure 19Optionally, the pulse amplitude modulation circuit 10 and the pulse width modulation circuit 20 each comprise an initialization unit 111 / 121, a data writing unit 112 / 122, a threshold compensation unit 113 / 123, a light emitting control unit 114 / 124, a storage capacitor C1 / C2 and a driving transistor M0 / M00. Among them, the pulse amplitude modulation circuit 10 comprises the initialization unit 111, the data writing unit 112 (including a first data writing transistor M4), the threshold compensation unit 113, the light emitting control unit 114 (including a first switch transistor M1 and a second switch transistor M2), the storage capacitor C1 and the driving transistor M0; the pulse width modulation circuit 20 comprises the initialization unit 121, the data writing unit 122 (including a second data writing transistor M05), the threshold compensation unit 123, the light emitting control unit 124 (including a third switch transistor M03 and a fourth switch transistor M04), the storage capacitor C2 and the driving transistor M00. This embodiment takes the first switch transistor M1, the second switch transistor M2, the first driving transistor M0, the third switch transistor M03, the fourth switch transistor M04 and the second driving transistor M00 as examples, which are all double-gate double-channel transistors. The initialization unit 111 / 121 is electrically connected between the initialization signal end VREF and the first node N11 / N12, and is used to provide the initialization signal of the initialization signal end VREF to the first node N11 / N12 in the initialization stage t1 (the value of the initialization signal provided by the initialization signal end of the pulse amplitude modulation circuit 10 can be the same as or different from the initialization signal provided by the initialization signal end of the pulse width modulation circuit 20). The data writing unit 112 / 122 is electrically connected between the data signal end DATA_PAM / DATA_PWM and the first electrode of the driving transistor M0 / M00, and the gate electrode of the driving transistor M0 / M00 and the first electrode plate of the storage capacitor C1 / C2 are electrically connected to the first node N11 / N12; the data writing unit 112 / 122 is used to provide the data voltage signal of the data signal end DATA_PAM / DATA_PWM to the first node N11 / N12 through the driving transistor M0 / M00 in the data writing stage t2. The threshold compensation unit 113 / 123 is electrically connected between the second electrode of the driving transistor M0 / M00 and the first node N11 / N12, and is used to compensate the threshold voltage of the driving transistor M0 / M00 to the first node N11 / N12.

[0094] In the pulse width modulation circuit 20, the second plate of the storage capacitor C2 is electrically connected with the sweep signal terminal SWEEP, and the sweep signal terminal SWEEP receives a sweep signal. The light emitting control unit 124 is electrically connected between the first power supply terminal VDD_PWM and the first node N11 in the pulse amplitude modulation circuit 10; the light emitting control unit 124 is configured to control the drive transistor M00 to generate a drive pulse in the light emitting stage t3; the first power supply terminal VDD_PWM receives a first power supply voltage signal VDD_PWM (herein the same character is used to represent the signal terminal and the signal provided by the signal terminal); and the data signal terminal DATA_PWM receives a pulse width modulation data voltage DATA_PWM (herein the same character is used to represent the signal terminal and the signal provided by the signal terminal).

[0095] In the pulse amplitude modulation circuit 10, the second plate of the storage capacitor C1 is electrically connected with the power supply signal terminal VDD_PAM, and the power supply signal terminal VDD_PAM receives a second power supply voltage signal VDD_PAM (herein the same character is used to represent the signal terminal and the signal provided by the signal terminal). The light emitting control unit 114 is electrically connected between the power supply signal terminal VDD_PAM and the light emitting element LD; the light emitting control unit 114 is configured to control the drive transistor M0 to generate a drive current flowing into the light emitting element LD in the light emitting stage, so as to drive the light emitting element LD to emit light; and the data signal terminal DATA_PAM receives a pulse amplitude modulation data voltage DATA_PAM (herein the same character is used to represent the signal terminal and the signal provided by the signal terminal).

[0096] The output terminal of the pulse width modulation circuit 20 is electrically connected with the first node N11 of the pulse amplitude modulation circuit 10, for providing a control signal to the first node N11. Since the first node N11 is electrically connected with the gate of the driving transistor M0, it is equivalent to providing a control signal to the gate of the driving transistor M0. In the pulse width modulation circuit 20, when the voltage difference between the gate and the source of the driving transistor M00 is greater than the threshold voltage of the driving transistor M00, the driving transistor M00 is in the off state. At this time, the pulse width modulation circuit 20 does not provide a control signal to the first node N11 of the pulse amplitude modulation circuit 10, and the driving transistor M0 in the pulse amplitude modulation circuit 10 provides a driving current to the light emitting element according to the pulse amplitude modulation data voltage DATA_PAM. With the change of the voltage of the sweep signal SWEEP, the gate potential of the driving transistor M00 changes synchronously, until the voltage difference between the gate and the source of the driving transistor M00 is less than or equal to the threshold voltage of the driving transistor M00, the driving transistor M00 is turned on, and the driving transistor M00 transmits the first power voltage signal VDD_PWM of the first power supply terminal VDD_PWM to the first node N11 of the pulse amplitude modulation circuit 10 as the off voltage, so that the driving transistor M0 in the pulse amplitude modulation circuit 10 is turned off, thereby stopping providing the driving current to the light emitting element LD.

[0097] It should be noted that, Figure 18 The driving circuit structure shown is an optional example of the present disclosure, and is not a limitation on the display panel driving circuit. For example, Figure 18 The pulse amplitude modulation circuit and the pulse width modulation circuit shown each include a threshold compensation unit, for compensating the data signal by the threshold voltage of the driving transistor when writing the data signal into the circuit, so as to ensure that the driving transistor provides accurate driving current and avoids being affected by the threshold voltage of the driving transistor when writing the data. The embodiments of the present disclosure are also applicable to driving circuit structures without the threshold compensation unit, for example, the pulse amplitude modulation circuit and the pulse width modulation circuit shown are adjusted as follows: the threshold compensation units 113 / 123 are removed, and the connection mode of the data writing units 112 / 122 is adjusted to be connected between the data signal end DATA_PAM / DATA_PWM and the gate of the driving transistor M0 / M00, for providing the data voltage signal of the data signal end DATA_PAM / DATA_PWM to the first node N11 / N12 through the data writing unit in the data writing stage. The present disclosure does not limit the specific structure of the pixel driving circuit. Figure 18

[0098] In addition, in order to reduce the leakage current of other transistors in the pixel driving circuit to the first node, the threshold compensation units 113 / 123 can also be removed, and the connection mode of the data writing units 112 / 122 is adjusted to be connected between the data signal end DATA_PAM / DATA_PWM and the gate of the driving transistor M0 / M00, for providing the data voltage signal of the data signal end DATA_PAM / DATA_PWM to the first node N11 / N12 through the data writing unit in the data writing stage. Figure 18 ​The pulse amplitude modulation circuit and the pulse width modulation circuit are adjusted as follows: the initialization units 111 / 121 and the threshold compensation units 113 / 123 connected to the driving transistors M0 / M00 in the pulse amplitude modulation circuit and the pulse width modulation circuit are adjusted to transistors in a double-gate structure or oxide transistors, etc.

[0099] Figure 20 Another schematic diagram of the pixel driving circuit provided by the embodiment of the present disclosure is shown, wherein the pulse amplitude modulation circuit 10 and the pulse width modulation circuit 20 each include an initialization unit 111 / 121, a data writing unit 112 / 122, a threshold compensation unit 113 / 123, a light-emitting control unit 114 / 124, a storage capacitor C1 / C2, and a driving transistor M0 / M00, and are connected to Figure 18 the same as the embodiment shown, and the working principle can be referred to Figure 18 the related descriptions of the embodiment shown, which will not be repeated here. Figure 20 the embodiment shown and Figure 18 One of the differences between the embodiment shown and Figure 20 The pulse amplitude modulation circuit 110 in the pulse amplitude modulation circuit 110 further includes a first voltage stabilizing module 115 and a second voltage stabilizing module 116. The first voltage stabilizing module 115 includes two transistors, the gates of the two transistors are respectively connected to control signals PAM_S1 and PAM_S2, the first pole is connected to a power voltage terminal VDD_PWM, and the second pole is connected to the first plate of a capacitor C3. The second pole of the capacitor C3 is connected to a first node N11 of the pulse amplitude modulation circuit 10. The first voltage stabilizing module 115 is configured to write a reference voltage VDD_PWM to the first plate of the capacitor C3 in a first time period in which the pulse amplitude modulation circuit 110 works, and write a power voltage signal VDD_PWM to the first plate of the capacitor C3 in a second time period in which the pulse amplitude modulation circuit 110 works. For example, the first time period is Figure 19 the initialization time period t1 corresponding to the timing sequence, and the second time period is Figure 19 the data writing time period t2 corresponding to the timing sequence. In this way, in the first time period and the second time period, due to the coupling effect of the capacitor C3, a stabilizing effect on the potential of the first node N11 is achieved, that is, a stabilizing effect on the gate potential of the first driving transistor M0 is achieved. The second voltage stabilizing module 116 includes a transistor connected between a power voltage terminal VDD_PAM and the first plate of the capacitor C3, and the gate of the transistor is connected to a control signal PWM_EM. In this way, when the pulse width modulation circuit transmits a control signal to the pulse amplitude modulation circuit, the second voltage stabilizing module 116 can stabilize the potential of the first node N11 to avoid changes in the gate potential of the first driving transistor M0, thereby preventing changes in the driving current, and thus facilitating improvement in the accuracy of the output driving current of the pulse amplitude modulation circuit.

[0100] It should be noted that, in practical applications, the power supply voltage signal VDD_PAM corresponding to the pulse amplitude modulation circuit and the power supply voltage signal VDD_PWM corresponding to the pulse width modulation circuit can be set to the same value, or they can be set to different values ​​as required. This disclosure does not impose specific limitations on this. The embodiments of this disclosure only use P-type transistors in the pixel driving circuit as an example for illustration, but this disclosure is not limited thereto. In some other embodiments of this disclosure, all transistors in the pixel driving circuit can be set to N-type transistors, or some transistors can be set to P-type transistors and others to N-type transistors.

[0101] It should also be noted that the structure of any one of the pulse amplitude modulation circuits 10 in the above embodiments can be combined with the structure of any one of the pulse width modulation circuits 20 in other embodiments. Furthermore, it is possible to use... Figure 6 , Figure 9 or Figure 10 The pulse amplitude modulation circuit 10 and the pulse width modulation circuit 20 can be connected using any of the following connection methods. It should also be noted that other structures of the pulse amplitude modulation circuit 10, other structures of the pulse width modulation circuit 20, and other connection methods between the pulse amplitude modulation circuit 10 and the pulse width modulation circuit 20 are all applicable to the embodiments described in this disclosure.

[0102] Based on the same inventive concept, this disclosure also provides a display device. Figure 21 The diagram shown is a structural schematic of a display device 200 provided in an embodiment of this disclosure. Please refer to it. Figure 21 The display device 200 includes the pixel driving circuit in any of the above embodiments. The display device 200 provided in this disclosure can be any electronic device with display function, such as a touch screen, mobile phone, tablet computer, laptop computer, e-reader, or television. The display device 200 provided in this disclosure has the beneficial effects of the pixel driving circuit provided in this disclosure. For details, please refer to the specific descriptions of the pixel driving circuit in the above embodiments; these descriptions will not be repeated here.

[0103] Understandable, Figure 21 The rectangular structure is used as an example to illustrate one shape of the display device 200. In some other embodiments of this disclosure, the display device 200 may also be circular, elliptical or any other feasible shape, and this disclosure does not specifically limit it.

[0104] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0105] The above description is merely a specific embodiment of this disclosure, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A pixel driving circuit, characterized by comprising: The device includes an electrically connected pulse amplitude modulation circuit and a pulse width modulation circuit, wherein the pulse amplitude modulation circuit is electrically connected to a light-emitting element and is used to provide a driving current to the light-emitting element; the pulse amplitude modulation circuit is configured to control the amplitude of the driving current, and the pulse width modulation circuit is configured to control the pulse width of the driving current. The pulse amplitude modulation circuit includes a light-emitting branch connected to the light-emitting element. The light-emitting branch includes a first driving transistor and at least one switching transistor. At least one transistor in the light-emitting branch is a dual-gate dual-channel transistor. In the light-emitting branch, the switching transistor includes a first switching transistor and a second switching transistor. The first driving transistor is connected in series between the first switching transistor and the second switching transistor. The gate of the first switching transistor is connected to a first switching control terminal, and the gate of the second switching transistor is connected to a second switching control terminal. The second switching transistor is connected in series between the first driving transistor and the light-emitting element. The first driving transistor and the first switching transistor are dual-gate dual-channel transistors, and the second switching transistor is a dual-gate dual-channel transistor or a quad-gate quad-channel transistor; the aspect ratio of the second switching transistor is greater than that of the first switching transistor.

2. The pixel driving circuit according to claim 1, characterized in that, The width-to-length ratio of the first switching transistor is A1, and the width-to-length ratio of the second switching transistor is A2, where A2 = K × A1 and K ≥ 2.

3. The pixel driving circuit of claim 1, wherein, The first switch control terminal and the second switch control terminal are the same switch control terminal.

4. The pixel driving circuit of claim 1, wherein, The output terminal of the pulse width modulation circuit is connected to the gate of the first driving transistor, or the output terminal of the pulse width modulation circuit is connected to the gate of the first driving transistor through a capacitor.

5. The pixel driving circuit of claim 1, wherein, The light-emitting branch also includes a third transistor, which is connected in series between the first driving transistor and the light-emitting element, and the gate of the third transistor is connected to the output terminal of the pulse width modulation circuit.

6. The pixel driving circuit according to claim 5, characterized in that, The third transistor is connected in series between the first driving transistor and the second switching transistor; the width-to-length ratio of the third transistor is A3, the width-to-length ratio of the first switching transistor is A1, and the width-to-length ratio of the second switching transistor is A2, wherein A1 < A3 < A2.

7. The pixel driving circuit according to claim 6, characterized in that, The third transistor is a dual-gate dual-channel transistor.

8. The pixel driving circuit according to claim 5, characterized in that, The third transistor is connected in series between the second switching transistor and the light-emitting element; the width-to-length ratio of the third transistor is A3, the width-to-length ratio of the first switching transistor is A1, and the width-to-length ratio of the second switching transistor is A2, wherein A1 < A2 < A3.

9. The pixel driving circuit according to claim 8, characterized in that, The third transistor is a four-gate four-channel transistor.

10. The pixel driving circuit according to claim 1, characterized in that, The pulse amplitude modulation circuit further includes a first data writing transistor, which is connected in series between the first data signal terminal and the first terminal of the first driving transistor, and the first terminal of the first driving transistor is connected to the first switching transistor. The first data writing transistor is a dual-gate dual-channel transistor.

11. The pixel driving circuit according to claim 1, characterized in that, The dual-gate dual-channel transistor includes a substrate and an active layer, a bottom gate, and a top gate located on the same side of the substrate. Along a first direction, the bottom gate and the top gate are located on opposite sides of the active layer, and the bottom gate is located between the active layer and the substrate. The first direction is perpendicular to the plane of the substrate. The outer edge of the orthographic projection of the bottom gate onto the plane where the active layer is located is the first edge, and the outer edge of the orthographic projection of the top gate onto the plane where the active layer is located is the second edge, with the first edge located outside the second edge.

12. The pixel driving circuit according to claim 11, characterized in that, The distance between the first edge and the second edge is D0, where D0 ≥ 1 μm.

13. The pixel driving circuit according to claim 1, characterized in that, The pixel driving circuit includes a first pixel driving circuit and a second pixel driving circuit. The first pixel driving circuit is used to be electrically connected to a first color light-emitting element, and the second pixel driving circuit is used to be electrically connected to a second color light-emitting element. The luminous efficiency of the first color light-emitting element is less than that of the second color light-emitting element. In the first pixel driving circuit, the width-to-length ratio of the first switching transistor is A11, and the width-to-length ratio of the second switching transistor is A21; in the second pixel driving circuit, the width-to-length ratio of the first switching transistor is A12, and the width-to-length ratio of the second switching transistor is A22; wherein, A11 > A12, and / or, A21 > A22.

14. The pixel driving circuit according to claim 13, characterized in that, A11 = K1 × A12, K1 ≥ 1.5; and / or, A12 = K2 × A22, K2 ≥ 1.

5.

15. The pixel driving circuit according to claim 13, characterized in that, The light-emitting branch further includes a third transistor, which is connected in series between the first driving transistor and the light-emitting element. The gate of the third transistor is connected to the output terminal of the pulse width modulation circuit. In the first pixel driving circuit, the aspect ratio of the third transistor is A31. In the second pixel driving circuit, the aspect ratio of the third transistor is A32. Wherein, A31 > A32.

16. The pixel driving circuit according to claim 1, characterized in that, The pulse width modulation circuit includes an output branch, which includes a second driving transistor and at least one switching transistor. The at least one transistor in the output branch is a dual-gate dual-channel transistor.

17. The pixel driving circuit according to claim 16, characterized in that, The switching transistors in the pulse width modulation circuit include a third switching transistor and a fourth switching transistor. The second driving transistor is connected in series between the third switching transistor and the fourth switching transistor. The gates of the third switching transistor and the fourth switching transistor are both connected to the third switching control terminal. The fourth switching transistor is connected in series between the second driving transistor and the output terminal of the pulse width modulation circuit. The second driving transistor, the third switching transistor, and the fourth switching transistor are dual-gate dual-channel transistors.

18. The pixel driving circuit according to claim 17, characterized in that, The width-to-length ratio of the third switching transistor is A3, and the width-to-length ratio of the fourth switching transistor is A4, where A4 = K4 × A3 and K4 ≥ 2.

19. The pixel driving circuit according to claim 17, characterized in that, The pulse width modulation circuit includes a second data writing transistor, which is connected in series between the second data signal terminal and the first terminal of the second driving transistor. The first terminal of the second driving transistor is connected to the third switching transistor. The second data writing transistor is a dual-gate dual-channel transistor.

20. The pixel driving circuit according to claim 17, characterized in that, The pixel driving circuit includes a first pixel driving circuit and a second pixel driving circuit. The first pixel driving circuit is used to be electrically connected to a first color light-emitting element, and the second pixel driving circuit is used to be electrically connected to a second color light-emitting element. The luminous efficiency of the first color light-emitting element is less than that of the second color light-emitting element. In the first pixel driving circuit, the aspect ratio of the third switching transistor is A31, and the aspect ratio of the fourth switching transistor is A41; in the second pixel driving circuit, the aspect ratio of the third switching transistor is A32, and the aspect ratio of the fourth switching transistor is A42; wherein, A31 > A32, and / or, A41 > A42.

21. A display device, characterized in that, Includes the pixel driving circuit described in any one of claims 1 to 20.

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