Semiconductor structure and method for manufacturing the same

Abstract

The present application provides a semiconductor structure and a manufacturing method thereof, wherein the semiconductor structure includes a substrate, an expansion portion, and a node contact portion; the substrate includes an active area and an isolation structure, the isolation structure is located between adjacent active areas, a first notch is formed in the isolation structure at the end of the active area, a second notch is formed at the end of the active area, and the first notch is connected to the second notch; the expansion portion is located in the first notch and is in contact with the active area; the node contact portion is located in the second notch and is in contact with both the active area and the expansion portion.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] The transistors and capacitors in dynamic random access memory (DRAM) are connected via node contacts. As the process shrinks, the contact area between the node contacts and the transistor's active area decreases, significantly increasing the resistance of the connection between the transistor and the capacitor, thus affecting device performance. Summary of the Invention

[0003] In view of this, the main purpose of this application is to provide a semiconductor structure and a manufacturing method thereof.

[0004] To achieve the above objectives, the technical solution of this application is implemented as follows:

[0005] An embodiment of the present application provides a semiconductor structure, including a substrate, an expansion portion, and a node contact portion; the substrate includes an active area and an isolation structure, the isolation structure is located between adjacent active areas, the isolation structure at the end of the active area forms a first notch, the end of the active area forms a second notch, and the first notch is connected to the second notch; the expansion portion is located in the first notch, and the expansion portion is in contact with the active area; the node contact portion is located in the second notch, and the node contact portion is in contact with both the active area and the expansion portion.

[0006] In some embodiments, the semiconductor structure further includes a plurality of buried word lines, the buried word lines extending along a first direction, and the plurality of buried word lines are arranged at intervals along a second direction, the first direction being perpendicular to the second direction; wherein, in the second direction, the distance between the active area and the adjacent buried word line is greater than the width of the expansion portion.

[0007] In some embodiments, a material of the expansion portion includes single crystal silicon or polycrystalline silicon, and in the second direction, a width of the expansion portion is greater than or equal to 5 angstroms and less than or equal to 15 angstroms.

[0008] In some embodiments, in a direction perpendicular to the plane of the substrate, a depth of the first notch is greater than or equal to 100 angstroms and less than or equal to 300 angstroms.

[0009] In some embodiments, in a direction perpendicular to the plane of the substrate, a depth of the second notch is less than or equal to a depth of the first notch.

[0010] In some embodiments, in a cross section parallel to the plane of the substrate, the shape of the enlarged portion includes a crescent shape, and both ends of the enlarged portion are respectively in contact with the active area; in a cross section along the extension direction of the active area, the shape of the enlarged portion includes any one of a fin shape, a quarter ellipse shape, and an ellipse shape that is greater than a quarter and less than one half.

[0011] In some embodiments, in a cross section along an extension direction of the active region, the second notch is rectangular in shape.

[0012] In some embodiments, doping ions are provided in the expansion portion, and the concentration of the doping ions is distributed in a gradient in a direction perpendicular to the plane of the substrate.

[0013] In some embodiments, the semiconductor structure further includes a plurality of bit lines and a plurality of capacitors; the bit lines extend along the second direction, the bit lines are connected to the active area through a bit line contact structure, and the node contact portions are located between adjacent bit lines; the capacitors are connected to the active area through the node contact portions.

[0014] The present invention also provides a method for manufacturing a semiconductor structure, including:

[0015] Providing a substrate, forming active regions and isolation structures in the substrate, wherein the isolation structures are located between adjacent active regions;

[0016] forming a first notch on the isolation structure at an end of the active region;

[0017] forming an enlarged portion in the first notch, wherein the enlarged portion is in contact with the active area;

[0018] forming a second notch at an end of the active region, wherein the first notch is connected to the second notch;

[0019] A node contact portion is formed in the second notch, and the node contact portion is in contact with both the active region and the expanded portion.

[0020] In some embodiments, before forming the first notch, the method further includes:

[0021] A plurality of buried word lines are formed in the substrate, the buried word lines extending along a first direction, and the plurality of buried word lines are arranged at intervals along a second direction, wherein the first direction is perpendicular to the second direction.

[0022] The embodiment of the present application provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a substrate, an expansion portion, and a node contact portion; the substrate includes an active region and an isolation structure, the isolation structure is located between adjacent active regions, a first notch is formed in the isolation structure at the end of the active region, a second notch is formed at the end of the active region, and the first notch is connected to the second notch; the expansion portion is located in the first notch, and the expansion portion is in contact with the active region; the node contact portion is located in the second notch, and the node contact portion is in contact with both the active region and the expansion portion. In the embodiment of the present application, a first notch is formed on the isolation structure at the end of the active region, an expansion portion is provided in the first notch, and the expansion portion is in contact with the active region, so as to expand the end area of ​​the active region and increase the contact area between the node contact portion and the active region, thereby reducing the contact impedance between the node contact portion and the active region and avoiding affecting the performance of the semiconductor structure device. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A top view of a node contact portion and a contact window of a transistor in the related art;

[0024] Figure 2 A top view of an active area in the related art;

[0025] Figure 3a A top view of the contact surface between the node contact portion and the active area in the related art;

[0026] Figure 3b For the Figure 3a Cross-section along the A-A' direction;

[0027] Figure 4a A schematic diagram of the contact between the enlarged portion and the active area provided in an embodiment of the present application;

[0028] Figure 4b For the Figure 4a Cross-section along the B-B' direction;

[0029] Figure 5a A top view of the enlarged portion and the active area provided in an embodiment of the present application;

[0030] Figure 5b for Figure 5a Enlarged view of point C in the middle;

[0031] Figure 5c For the Figure 5a Cross-section along the D-D' direction;

[0032] Figure 6a A schematic structural diagram of another expansion portion provided in an embodiment of the present application;

[0033] Figure 6b A schematic structural diagram of another enlarged portion provided in an embodiment of the present application;

[0034] Figure 6c A schematic structural diagram of another enlarged portion provided in an embodiment of the present application;

[0035] Figure 7 A flowchart of a method for manufacturing a semiconductor structure provided in an embodiment of the present application;

[0036] Figure 8a A top view of a substrate in the manufacturing process of a semiconductor structure provided in an embodiment of the present application;

[0037] Figure 8b For the Figure 8a Cross-section along the D-D' direction;

[0038] Figure 9a and Figure 9b A schematic diagram of a first mask layer provided in an embodiment of the present application;

[0039] Figure 10a and Figure 10b A schematic diagram of a first notch provided in an embodiment of the present application;

[0040] Figure 11a and Figure 11b A schematic diagram of an enlarged portion provided in an embodiment of the present application;

[0041] Figure 12a and Figure 12b A schematic diagram of a second mask layer provided in an embodiment of the present application;

[0042] Figure 13a and Figure 13b A schematic diagram of a second notch provided in an embodiment of the present application;

[0043] Figure 14 A schematic diagram of a polysilicon layer provided in an embodiment of the present application;

[0044] Figure 15a and Figure 15b A schematic diagram of a node contact portion provided in an embodiment of the present application;

[0045] Figure 16a 、 Figure 16b and Figure 17 A schematic diagram of a manufacturing process of a bit line provided in an embodiment of the present application;

[0046] Figures 18 to 22b A schematic diagram of the manufacturing process of the node contact portion provided in an embodiment of the present application. DETAILED DESCRIPTION

[0047] The following describes exemplary embodiments of the present application in more detail with reference to the accompanying drawings. Although exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0048] In the following description, numerous specific details are provided to provide a more thorough understanding of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present application; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0049] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0050] It should be understood that spatial relational terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatial relational terms are intended to also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, then the elements or features described as "under the other elements" or "beneath" or "beneath" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0051] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0052] In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present application, the implementation of the embodiments of the present application is described in detail below with reference to the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present application.

[0053] In dynamic random access memory, transistors and capacitors are connected through node contacts, such as Figure 1 FIG. 4 shows a top view of a node contact and a contact window 40 of a transistor in the related art, wherein the semiconductor structure includes a substrate 10, a buried word line 20, and a bit line 30; the substrate 10 includes an active area 101 and an isolation structure 102; the buried word line 20 extends along a first direction X and is spaced apart along a second direction Y; the bit line 30 extends along a second direction Y and is spaced apart along the first direction X; and the first direction X is perpendicular to the second direction Y. It is understood that when the process is scaled, the size of the contact window 40 is also scaled, resulting in a decrease in the contact area between the node contact and the active area 101 of the transistor, causing a significant increase in the resistance of the connection structure between the transistor and the capacitor, thereby affecting device performance. The present application increases the contact area between the node contact and the active area 101 by enlarging the end area of ​​the active area 101, thereby reducing the contact resistance between the node contact and the active area 101 and avoiding affecting the performance of the semiconductor structure device.

[0054] like Figure 2 FIG. 1 shows a top view of an active region 101 in the related art. It is understood that increasing the area of ​​the entire active region 101 will result in a decrease in the distance CD1 between adjacent active regions 101 in a direction perpendicular to the extension direction of the active region 101, which will increase the risk of interconnection between adjacent active regions 101. Furthermore, if CD1 is too small, electrical punch-through between adjacent active regions 101 may occur. Therefore, the size of CD1 is extremely important for the process and electrical properties of the active region 101. In practice, the only connection between the active region 101 and the node contact is the end portion of the active region 101. Therefore, by increasing the area of ​​the end portion (in the CD2 direction) of the active region 101, the contact area between the node contact and the active region 101 can be increased, thereby avoiding any impact on the process and electrical properties of the active region 101.

[0055] like Figure 3a and Figure 3b As shown in the figure, they are respectively a top view of the contact surface 401 of the node contact portion and the active area 101 in the related art and a top view of the contact surface 401 along the active area 101. Figure 3a In the cross-sectional view along the A-A' direction, the dotted circle is the contact surface 401 between the node contact portion and the active area 101. As the line width decreases, the area of ​​the contact surface 401 decreases, resulting in a significant increase in the resistance of the connection structure between the transistor and the capacitor, thereby affecting the performance of the semiconductor structure device. In related technologies, such as Figure 3bAs shown, by forming an undercut groove 1011 in the active area 101, the contact area between the node contact portion (formed by the node contact material 51) and the active area 101 is increased. However, when etching toward the side, it is easy to etch through, resulting in conduction between the bit line 30 and the node contact portion. The bit line 30 is connected to the active area 101 through the bit line contact structure 301.

[0056] Next, combine Figures 4a to 5c To describe the technical solution of this application in detail, Figure 4a This is a schematic diagram of the contact between the enlarged portion 60 and the active area 101 provided in an embodiment of the present application. Figure 4b For the Figure 4a Cross-section view along the B-B' direction, Figure 5a A top view of the enlarged portion 60 and the active area 101 provided in an embodiment of the present application is shown. Figure 5b for Figure 5a The enlarged image of point C in the middle, Figure 5c For the Figure 5a Cross-sectional view along the D-D' direction.

[0057] like Figures 4a to 5c As shown, an embodiment of the present application provides a semiconductor structure, including a substrate 10, an expansion portion 60 and a node contact portion 50; the substrate 10 includes an active area 101 and an isolation structure 102, the isolation structure 102 is located between adjacent active areas 101, and the isolation structure 102 at the end of the active area 101 is formed with a first notch 1021, and the end of the active area 101 is formed with a second notch 1012, and the first notch 1021 is connected to the second notch 1012; the expansion portion 60 is located in the first notch 1021, and the expansion portion 60 is in contact with the active area 101; the node contact portion 50 is located in the second notch 1012, and the node contact portion 50 is in contact with both the active area 101 and the expansion portion 60.

[0058] It is understood that the present application forms a first notch 1021 on the isolation structure 102 at the end of the active region 101, and sets an expansion portion 60 in the first notch 1021, and the expansion portion 60 is in contact with the active region 101, as shown in FIG. Figure 4a As shown, the area of ​​the active area 101 is expanded. When forming the second notch 1012 in the active area 101, only the end of the active area 101 needs to be etched downward, without side-digging. This can significantly reduce the etching difficulty and prevent the bit line 30 from being conductive with the node contact portion 50. At the same time, the node contact portion 50 located in the second notch 1012 can contact both the active area 101 and the expanded portion 60, which is equivalent to increasing the contact area between the node contact portion 50 and the active area 101, reducing the contact resistance between the node contact portion 50 and the active area 101, and avoiding affecting the performance of the semiconductor structure device.

[0059] It should be noted that the shapes of the first notch 1021 and the second notch 1012 can be defined by a mask pattern. In addition, the contact area between the node contact 50 and the transistor can be controlled by controlling the area of ​​the first notch 1021 and the second notch 1012 in a cross section parallel to the plane of the substrate 10 and the depth in a direction perpendicular to the plane of the substrate 10.

[0060] In some embodiments, the material of the substrate 10 includes, but is not limited to, silicon, the material of the isolation structure 102 includes a semiconductor oxide, and the material of the expansion portion 60 includes single-crystal silicon or polycrystalline silicon. It will be appreciated that, because the Schottky resistance between single-crystal silicon and polycrystalline silicon is relatively low, this embodiment uses single-crystal silicon or polycrystalline silicon to form the expansion portion 60, thereby not only expanding the area of ​​the active region 101 but also not increasing the resistance of the active region 101.

[0061] In some embodiments, the semiconductor structure further comprises a plurality of buried word lines 20, the buried word lines 20 extending along a first direction X, and the plurality of buried word lines 20 are arranged at intervals along a second direction Y, wherein the first direction X is perpendicular to the second direction Y; wherein, in the second direction Y, Figure 4a As shown, the distance L between the active area 101 and the adjacent buried word line 20 is greater than the width W of the expansion portion 60 .

[0062] It can be understood that, in this embodiment, by setting the width W of the expansion portion 60 to be smaller than the distance L between the active area 101 and the adjacent buried word line 20, it is possible to avoid contact between the side of the expansion portion 60 away from the active area 101 and the buried word line 20, thereby avoiding interconnection between adjacent buried word lines 20.

[0063] In some embodiments, the width W of the expansion portion 60 is greater than or equal to 5 angstroms and less than or equal to 15 angstroms in the second direction Y. For example, the width W of the expansion portion 60 is 10 angstroms.

[0064] like Figure 5a and Figure 5bAs shown, in some embodiments, the shape of the enlarged portion 60 includes a crescent shape in a cross section parallel to the plane of the substrate 10, with both ends of the enlarged portion 60 contacting the active area 101. It will be appreciated that in this embodiment, by configuring the enlarged portion 60 to be crescent-shaped in a cross section parallel to the plane of the substrate 10, with both ends of the crescent contacting the active area 101, the enlarged portion 60 becomes part of the active area 101, thereby expanding the area of ​​the active area 101. Furthermore, this does not affect the distance CD1 between adjacent active areas 101 in a direction perpendicular to the extension direction of the active areas 101, thereby preventing adjacent active areas 101 from being interconnected.

[0065] like Figure 5c As shown, in some embodiments, in a direction perpendicular to the plane of the substrate 10, the depth d1 of the first notch 1021 is greater than or equal to 100 angstroms and less than or equal to 300 angstroms. For example, the depth d1 of the first notch 1021 is 200 angstroms.

[0066] In some embodiments, in a direction perpendicular to the plane of the substrate 10 , a depth d2 of the second notch 1012 is less than or equal to a depth d1 of the first notch 1021 .

[0067] It should be noted that the depth d1 of the first notch 1021 refers to the distance between the lowest point of the first notch 1021 and the upper surface of the substrate 10 in a direction perpendicular to the plane of the substrate 10. Figure 5c In the embodiment, the depth d2 of the second notch 1012 is equal to the depth d1 of the first notch 1021. In other embodiments, the depth d2 of the second notch 1012 may also be less than the depth d1 of the first notch 1021, so that the node contact portion 50 located in the second notch 1012 is in full contact with the enlarged portion 60.

[0068] In some embodiments, in a cross section along the extension direction (DD' direction) of the active region 101, the shape of the enlarged portion 60 includes a fin shape (eg, Figure 5c ), a quarter of an ellipse (such as Figure 6a ), an ellipse that is larger than one quarter and smaller than one half (e.g. Figure 6b ). Among them, Figure 6a This is a structural diagram of another expansion portion 60 provided in an embodiment of the present application. Figure 6b This is a schematic structural diagram of another expansion portion 60 provided in an embodiment of the present application.

[0069] It should be noted that the difference between the fin shape and the quarter ellipse and the ellipse that is larger than a quarter and smaller than one half is that the two sides of the fin shape are both straight lines; the quarter ellipse and the ellipse that is larger than a quarter and smaller than one half have one side that is a straight line and the other side that is an arc.

[0070] It is understandable that the shape of the enlarged portion 60 is determined by the shape of the first notch 1021 . The shape of the first notch 1021 is formed by an etching process and can be manufactured using conventional techniques in the art, which will not be described in detail here.

[0071] In some embodiments, in the cross section along the extension direction (DD' direction) of the active region 101, the shape of the second notch 1012 is a rectangle (eg Figure 5c Since the present application reduces the contact resistance by enlarging the area of ​​the active region 101 , there is no need to side-dig the active region 101 . A rectangular groove can be directly etched downward to avoid side-dig causing the bit line 30 to be conductive with the node contact portion 50 .

[0072] In some embodiments, as Figure 6c FIG. 1 is a schematic diagram of the structure of another enlarged portion 60 provided in an embodiment of the present application. Dopant ions 600 are disposed in the enlarged portion 60. The concentration of the dopant ions 600 is distributed in a gradient in a direction perpendicular to the plane of the substrate 10. It will be appreciated that by disposing dopant ions in the enlarged portion 60 and distributing the dopant concentration in a gradient, the resistance of the enlarged portion 60 can be further reduced in this embodiment.

[0073] In some embodiments, the semiconductor structure further includes a plurality of bit lines 30 (eg, Figure 4a and Figure 4b ) and multiple capacitors (not shown); the bit line 30 extends along the second direction Y, the bit line 30 is connected to the active area 101 through the bit line contact structure 301, and the node contact portion 50 is located between adjacent bit lines 30; the capacitor is connected to the active area 101 through the node contact portion 50.

[0074] It should be noted that the semiconductor structure provided in the embodiment of the present application is used to form a dynamic random access memory. Figures 7 to 22b A method for manufacturing a semiconductor structure is described in detail.

[0075] like Figure 7 FIG. 1 is a flow chart of a method for manufacturing a semiconductor structure provided in an embodiment of the present application, the method comprising:

[0076] S1. Providing a substrate, forming an active region and an isolation structure in the substrate, wherein the isolation structure is located between adjacent active regions;

[0077] S2. forming a first notch on the isolation structure at an end of the active region;

[0078] S3. forming an enlarged portion in the first notch, wherein the enlarged portion is in contact with the active area;

[0079] S4, forming a second notch at an end of the active area, wherein the first notch is connected to the second notch;

[0080] S5. Form a node contact portion in the second notch, wherein the node contact portion is in contact with both the active area and the expansion portion.

[0081] In step S1, Figure 8a and Figure 8b As shown in FIG, there are respectively a top view of the substrate 10 and a top view along the semiconductor structure manufacturing process provided by the embodiment of the present application. Figure 8a In the cross-sectional view taken along the D-D' direction, an isolation structure 102 and multiple active regions 101 are formed in the substrate 10. The isolation structure 102 is used to separate adjacent active regions 101 to prevent mutual interference between adjacent active regions 101. The material of the substrate 10 includes, but is not limited to, silicon; the isolation structure 102 can specifically be a shallow trench isolation. An isolation trench can be first formed on the substrate 10 through an etching process, and then an insulating material (e.g., an oxide of a semiconductor material) can be filled in the isolation trench to form the isolation structure 102. The active region 101 can be formed in the substrate 10 by ion doping.

[0082] In step S2, as Figure 9a and Figure 9b As shown, it is a schematic diagram of the first mask layer 703 provided in an embodiment of the present application; Figure 10a and Figure 10b , which is a schematic diagram of a first notch 1021 according to an embodiment of the present application. The shape of the first notch 1021 is defined by forming a mask assembly on the substrate 10. The mask assembly used in this etching process includes a first protective layer 701, a first sacrificial layer 702, and a first mask layer 703. The area where the orthographic projection of the first mask layer 703 on the substrate 10 is not covered by the active area 101 is the area of ​​the first notch 1021.

[0083] Specifically, the first mask layer 703 is a negative photoresist, that is, the area blocked by the first mask layer 703 is the target area. During downward etching, a gas with a high selectivity ratio is used to remove part of the isolation structure 102 while minimizing damage to the active area 101, thereby forming a first notch 1021. The etching depth in the direction perpendicular to the plane of the substrate 10 is greater than or equal to 100 angstroms and less than or equal to 300 angstroms, for example, the etching depth is 200 angstroms; the etching width in the second direction Y is greater than or equal to 5 angstroms and less than or equal to 15 angstroms, for example, the etching width is 10 angstroms; and in the cross section along the extension direction (D-D' direction) of the active area 101, the shape of the first notch 1021 is similar to a fin.

[0084] It should be noted that after the etching process is completed, a first notch 1021 is formed, and semiconductor material, such as single crystal silicon or polycrystalline silicon, will be backfilled in the first notch 1021 subsequently to form an expansion portion 60. Among them, if the etching depth is too deep, pores are easily formed when the semiconductor material is backfilled, resulting in an increase in the resistance of the expansion portion 60, and thus an increase in contact resistance. The backfill process can adopt an atomic layer deposition process or a chemical vapor deposition process. If the etching depth is too low, the contact area between the node contact portion 50 and the active area 101 decreases, which also causes an increase in contact resistance. In this embodiment, by setting the depth of the first notch 1021 to be greater than or equal to 100 angstroms and less than or equal to 300 angstroms, neither pores will be formed when the semiconductor material is backfilled, nor will the contact area between the node contact portion 50 and the active area 101 be reduced, thereby avoiding an increase in contact resistance between the node contact portion 50 and the active area 101.

[0085] In some embodiments, before forming the first notch 1021 , the method further includes:

[0086] A plurality of buried word lines 20 are formed in the substrate 10 . The buried word lines 20 extend along a first direction X. The buried word lines 20 are arranged at intervals along a second direction Y. The first direction X is perpendicular to the second direction Y.

[0087] It should be noted that, generally, the first notch 1021 can be formed first and the buried word line 20 later; alternatively, the buried word line 20 can be formed first and the first notch 1021 later. However, if the first notch 1021 is formed first and the buried word line 20 later, the mask pattern for the first notch 1021 can only be aligned with reference to the active area 101. In this embodiment, by forming the buried word line 20 first and the first notch 1021 later, the mask pattern for the first notch 1021 can be aligned with reference to both the active area 101 and the adjacent buried word line 20, allowing for more precise control of the etching width of the first notch 1021.

[0088] In step S3, if Figure 11a and Figure 11b FIG. 1 is a schematic diagram of an enlarged portion 60 according to an embodiment of the present application. Semiconductor material, such as single crystal silicon or polycrystalline silicon, is backfilled into the first gap 1021 using an atomic layer deposition process or a chemical vapor deposition process to form the enlarged portion 60. The enlarged portion 60 is in contact with the active area 101, making the enlarged portion 60 a part of the active area 101, thereby increasing the area of ​​the active area 101.

[0089] It should be noted that when backfilling polysilicon, a seed layer can be deposited first to achieve good step coverage. The reaction gas can be H3SiN(C3H7)2, Si2H6, or SiH[N(CH3)2]3. The reaction temperature is greater than or equal to 380 degrees Celsius and less than or equal to 500 degrees Celsius. The reaction pressure is greater than or equal to 1 Torr and less than or equal to 3 Torr.

[0090] In some embodiments, in the second direction Y, the distance between the active area 101 and the adjacent buried word line 20 is greater than the width of the expansion portion 60. It will be appreciated that, in this embodiment, by setting the width of the expansion portion 60 to be smaller than the distance between the active area 101 and the adjacent buried word line 20, the side of the expansion portion 60 away from the active area 101 can be prevented from contacting the buried word line 20, thereby preventing adjacent buried word lines 20 from being interconnected.

[0091] In some embodiments, in the second direction Y, the width of the expansion portion 60 is greater than or equal to 5 angstroms and less than or equal to 15 angstroms.

[0092] In step S4, Figure 12a and Figure 12b As shown, it is a schematic diagram of the second mask layer 803 provided in an embodiment of the present application; Figure 13a and Figure 13b FIG. 1 is a schematic diagram of a second notch 1012 according to an embodiment of the present application. The shape of the second notch 1012 is defined by forming a mask assembly on the substrate 10. The mask assembly of this etching process includes a second protective layer 801, a second sacrificial layer 802, and a second mask layer 803. The orthographic projection area of ​​the second mask layer 803 on the substrate 10 corresponds to the area of ​​the second notch 1012.

[0093] Specifically, the second mask layer 803 is a negative photoresist, that is, the area blocked by the second mask layer 803 is the target area. During etching, the area blocked by the second mask layer 803 cannot exceed the boundary of the subsequent bit line 30, that is, the second notch 1012 is located between adjacent bit lines 30. The etching depth of the second notch 1012 in the direction perpendicular to the plane of the substrate 10 is greater than or equal to 100 angstroms and less than or equal to 300 angstroms, for example, the etching depth is 200 angstroms; in the cross section along the extension direction (D-D' direction) of the active area 101, the shape of the second notch 1012 is rectangular. Since the present application reduces the contact impedance by expanding the area of ​​the active area 101, there is no need to side-dig the active area 101, and it is sufficient to directly etch downward to form a rectangular groove, thereby avoiding side-dig causing the bit line 30 to be conductive with the node contact portion 50.

[0094] In step S5, Figure 14 As shown, it is a schematic diagram of the polysilicon layer provided in an embodiment of the present application; Figure 15a and Figure 15b As shown, it is a schematic diagram of the node contact portion 50 provided in the embodiment of the present application. Figure 14 As shown, the polysilicon (ie, the node contact material 51) is backfilled in the second gap 1012, and then Figure 15b As shown, a chemical mechanical polishing process is used to remove a portion of the node contact material 51, leaving only the node contact material 51 in the region corresponding to the second notch 1012, thereby forming a node contact portion 50. The node contact portion 50 is in contact with both the active area 101 and the enlarged portion 60, thereby reducing the contact resistance between the node contact portion 50 and the active area 101 and avoiding affecting the performance of the semiconductor structure device.

[0095] Next, see Figure 16a 、 Figure 16b and Figure 17 , which is a schematic diagram of the manufacturing process of the bit line 30 provided in an embodiment of the present application, wherein the bit line 30 is formed on the substrate 10. The bit line 30 includes a stacked structure and a sidewall structure surrounding the stacked structure; the stacked structure includes, from bottom to top, a wire adhesion layer, a wire main body layer, and a top dielectric layer; the sidewall structure includes, from inside to outside, a first silicon nitride layer, a first silicon oxide layer, and a second silicon nitride layer 302; the second silicon nitride layer 302 outside the bit line 30 region is etched away.

[0096] Next, see Figures 18 to 22b , is a schematic diagram of the manufacturing process of the node contact portion 50 provided in the embodiment of the present application. It should be noted that, Figure 17 The node contact portion 50 inside is only the node contact portion 50 located in the second notch 1012 , and a node contact portion 50 located outside the second notch 1012 needs to be prepared to achieve connection with the capacitor.

[0097] Specifically, first Figure 18 As shown, a super oxide layer 90 (SOD) is backfilled on the substrate 10. Then, as shown in FIG. Figure 19 As shown, the position of the separation groove 901 is defined by the third mask layer. Figure 20 As shown, silicon nitride 52 is backfilled in the separation groove 901. Figure 21 As shown, a wet etching process is used to clean and remove the SOD, and after the cleaning is completed, a filling hole of the node contact portion 50 is formed. Figure 22a and Figure 22b As shown, polysilicon is deposited in the filling hole to form a node contact portion 50 outside the second gap 1012. After the polysilicon is deposited, subsequent fabrication processes can be performed according to device performance requirements. The subsequent fabrication processes are well known in the art and will not be described in detail here.

[0098] In summary, an embodiment of the present application provides a semiconductor structure, including a substrate, an expansion portion and a node contact portion; the substrate includes an active area and an isolation structure, the isolation structure is located between adjacent active areas, the isolation structure at the end of the active area forms a first notch, the end of the active area forms a second notch, and the first notch is connected to the second notch; the expansion portion is located in the first notch, and the expansion portion is in contact with the active area; the node contact portion is located in the second notch, and the node contact portion is in contact with both the active area and the expansion portion; the present application forms a first notch on the isolation structure at the end of the active area, and sets an expansion portion in the first notch, and the expansion portion is in contact with the active area, so as to expand the end area of ​​the active area and increase the contact area between the node contact portion and the active area, thereby reducing the contact impedance between the node contact portion and the active area, avoiding affecting the performance of the semiconductor structure device, and solving the technical problem that when the process is miniaturized, the contact area between the node contact portion and the active area of ​​the transistor decreases, resulting in a significant increase in the resistance of the transistor-capacitor connection structure, thereby affecting the performance of the semiconductor structure device.

[0099] The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0100] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A semiconductor structure, characterized in that include: A substrate comprising an active region and an isolation structure, wherein the isolation structure is located between adjacent active regions, a first notch is formed in the isolation structure at an end of the active region, a second notch is formed at an end of the active region, and the first notch is connected to the second notch; an enlarged portion, located in the first notch, the enlarged portion being in contact with the active area; a node contact portion, located in the second notch, wherein the node contact portion contacts both the active area and the enlarged portion; a plurality of buried word lines, the buried word lines extending along a first direction, the plurality of buried word lines being arranged at intervals along a second direction, the first direction being perpendicular to the second direction; Wherein, in the second direction, the distance between the active area and the adjacent buried word line is greater than the width of the expansion portion.

2. The semiconductor structure according to claim 1, wherein: The material of the expansion portion includes single crystal silicon or polycrystalline silicon, and in the second direction, the width of the expansion portion is greater than or equal to 5 angstroms and less than or equal to 15 angstroms.

3. The semiconductor structure according to claim 1, wherein: In a direction perpendicular to the plane of the substrate, a depth of the first notch is greater than or equal to 100 angstroms and less than or equal to 300 angstroms.

4. The semiconductor structure according to claim 3, wherein: In a direction perpendicular to the plane of the substrate, the depth of the second notch is less than or equal to the depth of the first notch.

5. The semiconductor structure according to claim 1, wherein: In a cross section parallel to the plane where the substrate is located, the shape of the enlarged portion includes a crescent shape, and both ends of the enlarged portion are in contact with the active area respectively; In a cross section along an extension direction of the active region, the shape of the enlarged portion includes any one of a fin shape, a quarter ellipse shape, and an ellipse shape that is larger than a quarter and smaller than a half. The semiconductor structure according to claim 1 , wherein: In a cross section along an extending direction of the active area, the second notch is in a rectangular shape.

7. The semiconductor structure according to claim 1, wherein: Doping ions are arranged in the expansion portion, and the concentration of the doping ions is distributed in a gradient in a direction perpendicular to the plane where the substrate is located.

8. The semiconductor structure according to claim 1, wherein: The semiconductor structure further comprises: a plurality of bit lines, the bit lines extending along a second direction, the bit lines connected to the active region via a bit line contact structure, the node contact portions being located between adjacent bit lines; and A plurality of capacitors are connected to the active region through the node contacts.

9. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate, forming active regions and isolation structures in the substrate, wherein the isolation structures are located between adjacent active regions; forming a plurality of buried word lines in the substrate, wherein the buried word lines extend along a first direction and are arranged at intervals along a second direction, wherein the first direction is perpendicular to the second direction; forming a first notch on the isolation structure at an end of the active region; forming an expansion portion in the first notch, the expansion portion being in contact with the active area, and wherein a distance between the active area and the adjacent buried word line in the second direction is greater than a width of the expansion portion; forming a second notch at an end of the active region, wherein the first notch is connected to the second notch; A node contact portion is formed in the second notch, and the node contact portion is in contact with both the active region and the expanded portion.

10. The method for manufacturing a semiconductor structure according to claim 9, wherein: The expansion portion is formed by backfilling the semiconductor material in the first gap through an atomic layer deposition process or a chemical vapor deposition process.

11. The method for manufacturing a semiconductor structure according to claim 10, wherein: The semiconductor material is single crystal silicon or polycrystalline silicon.

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