Semiconductor device and manufacturing method thereof

Abstract

The present invention discloses a semiconductor device and a method for manufacturing the same. The semiconductor device includes a semiconductor substrate, at least one metal layer, a first passivation layer, and a protective layer. At least one metal layer is disposed on a portion of the semiconductor substrate to form an electrical connection with the semiconductor substrate; a step structure is formed at the junction of the boundary of the metal layer and the semiconductor substrate; and the first passivation layer covers the metal layer and the semiconductor substrate. At least one first opening is formed on the first passivation layer, and each first opening exposes a portion of the metal layer corresponding to it. The protective layer covers the first passivation layer, and a second opening is formed on the protective layer, and the second opening of the protective layer exposes all the step structures so that the boundary of the second opening is away from the step structure. Therefore, the design of the present invention avoids the step structure of the metal layer and the first opening of the first passivation layer, and can effectively reduce the warping, cracking and peeling of the edge of the protective layer.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] In semiconductor manufacturing, during the IC (integrated circuit) packaging stage, a layer of polyimide film is applied to the chip substrate to protect it. The polyimide film is then exposed, developed, and cured using photolithography techniques. Finally, grooves are formed in the polyimide film, exposing the conductive layer of the substrate that needs to be electrically connected to the outside world.

[0003] Polyimide (PIM) is the final layer in the silicon wafer process, providing physical and chemical protection on the top of the silicon wafer. This protective layer enhances the durability and stability of the chip, especially under high temperature, high pressure, high humidity, and chemical corrosion conditions. It is also an essential process in automotive chip design, providing reliability protection for the entire device.

[0004] In the IC chip design and manufacturing process, the PIM window mask is designed after the window is opened in the lower passivation layer. If the PIM mask window design is unreasonable or the substrate pattern is relatively complex, it is easy for the PIM to warp or peel off during the subsequent chip dicing and packaging process, thus losing its chip protection function and posing a serious reliability risk to the product. Summary of the Invention

[0005] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device, which can prevent the protective layer on the surface of the semiconductor device from warping or peeling off, thereby improving the reliability of the chip.

[0006] In order to achieve the above-mentioned and other related objectives, the present invention provides a semiconductor device, comprising:

[0007] semiconductor substrates;

[0008] At least one metal layer is disposed on a portion of the semiconductor substrate and is electrically connected to the semiconductor substrate; the metal layer is higher than the surface of the semiconductor substrate, and a step structure is formed at the intersection of the boundary of the metal layer and the semiconductor substrate;

[0009] a first passivation layer covering the metal layer and the semiconductor substrate; at least one first opening is formed in the first passivation layer, the number of the first openings corresponding to the number of the metal layers, and each first opening exposes a portion of the metal layer corresponding thereto;

[0010] A protective layer covers the first passivation layer, and a second opening is formed on the protective layer, the second opening exposes at least one first opening and a metal layer corresponding to the first opening, and the second opening of the protective layer exposes all step structures at corresponding positions, so that the boundary of the second opening is away from the boundary of the first opening of the first passivation layer and away from the step structure.

[0011] Optionally, a distance between a boundary of the second opening and a boundary of the adjacent metal layer is between 10 μm and 200 μm.

[0012] Optionally, a plurality of second openings are provided on the protection layer, and each second opening exposes one or more first openings and a metal layer corresponding to the first opening.

[0013] Optionally, the second opening exposes two first openings, each first opening corresponds to a metal layer, and a distance between boundaries of the two metal layers is between 10 μm and 200 μm.

[0014] Optionally, the semiconductor substrate is a substrate including an IC circuit, and the IC circuit is electrically connected to the metal layer.

[0015] Optionally, a second passivation layer is provided on the surface of the semiconductor substrate, and at least part of the metal layer is formed on the second passivation layer; the first passivation layer extends above the metal layer to cover the step structure, and extends from the step structure to the second passivation layer of the semiconductor substrate.

[0016] According to one aspect of the present invention, there is also provided a method for manufacturing a semiconductor device, the method comprising:

[0017] Providing a semiconductor substrate, forming at least one metal layer on a portion of the surface of the semiconductor substrate, wherein a boundary between the metal layer and the surface of the semiconductor substrate forms a step structure;

[0018] forming a first passivation layer on the surfaces of the metal layer and the semiconductor substrate;

[0019] Etching a first opening in the first passivation layer at a position corresponding to the metal layer, so that the first passivation layer covers an edge of the metal layer and the first opening exposes an inner area of ​​the metal layer enclosed by the edge;

[0020] forming a protective layer on the surface of the first passivation layer;

[0021] The protective layer is etched to form a second opening on the protective layer, wherein the second opening exposes at least one first opening and a metal layer corresponding to the first opening, and the second opening of the protective layer exposes a step structure at a corresponding position, so that a boundary of the second opening of the protective layer is away from a boundary of the first opening of the first passivation layer and away from the step structure.

[0022] Optionally, the step of etching the protective layer to form a second opening on the protective layer includes:

[0023] Providing a protective layer mask plate, wherein the window on the protective layer mask plate is larger than the first opening of the first passivation layer and larger than the metal layer corresponding to the first opening of the first passivation layer;

[0024] Placing a protective layer mask plate on the first passivation layer, wherein a window of the protective layer mask plate exposes a first opening of the first passivation layer and a metal layer corresponding to the first opening of the first passivation layer, and the window exposes the step structure;

[0025] The protective layer is exposed and developed based on the window on the protective layer mask plate, so as to form a second opening at a position of the protective layer corresponding to the window of the protective layer mask plate.

[0026] Optionally, a distance between a boundary of the second opening and a boundary of the adjacent metal layer is between 10 μm and 200 μm.

[0027] Optionally, the semiconductor substrate is a substrate including an IC circuit, and the IC circuit is electrically connected to the metal layer.

[0028] Compared with the prior art, the semiconductor device and the method for manufacturing the semiconductor device according to the present invention have at least the following beneficial effects:

[0029] The semiconductor device of the present invention includes a semiconductor substrate, at least one metal layer, a first passivation layer, and a protective layer. The at least one metal layer is disposed on a portion of the semiconductor substrate and electrically connected to the semiconductor substrate. The metal layer protrudes above the surface of the semiconductor substrate, and a step structure is formed at the junction of the metal layer and the semiconductor substrate. The first passivation layer covers the metal layer and the semiconductor substrate. The first passivation layer has at least one first opening formed in the first passivation layer, the number of first openings corresponding to the number of metal layers. Each first opening is located in its corresponding metal layer and exposes a portion of the corresponding metal layer. The protective layer covers the first passivation layer and has a second opening formed in the protective layer. The second opening exposes the at least one first opening and the metal layer corresponding to the first opening. The second opening of the protective layer exposes all of the step structures at the corresponding locations, such that the boundaries of the second openings are located away from the boundaries of the first openings of the first passivation layer and away from the step structures. Thus, the protective layer is disposed away from the boundaries of the first openings of the first passivation layer and away from the step structures. This design avoids the metal steps and the window design of the passivation layer, effectively reducing warping, cracking, and delamination at the protective layer window locations, thereby ensuring product reliability.

[0030] The method for manufacturing a semiconductor device in the present invention is used to form the above-mentioned semiconductor device and also has the above-mentioned technical effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 Schematic diagram of the top view of the metal layer, passivation layer opening and protection layer opening on the surface of the IC circuit in the prior art;

[0032] Figure 2 This is a cross-sectional scan photo of the metal layer, passivation layer opening, and protective layer opening on the surface of the IC circuit in the prior art;

[0033] Figure 3 Schematic diagram of a top view of a metal layer, a first opening, and a second opening on a portion of a surface of a semiconductor substrate according to an embodiment of the present invention;

[0034] Figure 4 Schematic diagram of the cross-sectional structure of the metal layer, the first opening, and the second opening on a portion of the surface of the semiconductor substrate according to an embodiment of the present invention;

[0035] Figure 5 1 is a schematic top view of the structure in which two metal layers are exposed in the second opening of the protective layer on the surface of the semiconductor substrate according to an embodiment of the present invention.

[0036] List of reference numerals:

[0037] 1 Top Metal

[0038] 2 Passivation layer

[0039] 02 Passivation layer opening

[0040] 3 Polyimide layer

[0041] 03 Polyimide layer opening

[0042] 4 steps

[0043] 5. Polyimide layer warping

[0044] 10 Metal Layer

[0045] 20 First passivation layer

[0046] 21 First Opening

[0047] 30 protective layers

[0048] 31 Second Opening

[0049] 40 Second passivation layer

[0050] 50 step structure DETAILED DESCRIPTION

[0051] The following specific embodiments illustrate the embodiments of the present invention. Those skilled in the art will readily appreciate the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different perspectives and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features of the embodiments may be combined with each other unless they conflict.

[0052] It should be noted that the diagrams provided in the embodiments of the present invention are only schematic illustrations of the basic concept of the present invention. Although the diagrams only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation, the form, quantity, and proportion of each component in actual implementation can be changed at will, and the component layout form may also be more complex. The structures, proportions, sizes, etc. illustrated in the drawings of the specification are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the conditions for the implementation of this application. Therefore, they have no technical significance. Any structural modification, change in proportional relationship, or adjustment of size should still fall within the scope of the technical content disclosed in this application without affecting the efficacy and purpose of the present invention.

[0053] Polyimide (PIM) is the last layer of silicon wafer process, which plays a physical and chemical protection role on the top layer of silicon wafer. Figure 1 Conventional IC circuit products use the same mask plate to form openings on the passivation layer 2 and the polyimide layer 3 on the surface of the product, exposing the top metal layer 1 in the underlying semiconductor structure. If the mask plate for the polyimide layer 3 and the mask plate for the passivation layer 2 are not designed properly, the polyimide layer opening 03 is located between the top metal layer 1 and the passivation layer opening 02, as shown in FIG. Figure 1 As shown. That is, Figure 2 As shown, after the silicon wafer process is complete, the polyimide layer opening 03 falls on the step 4 of the underlying top metal layer 1. Due to the shrinkage of the polyimide layer 3, the polyimide layer is prone to warping 5 or cracking and peeling after the silicon wafer is diced and rinsed. This ultimately affects product reliability, posing a significant safety risk to automotive chips.

[0054] In order to solve the background technology and the above-mentioned technical problems, the present embodiment provides a semiconductor device and a method for preparing a semiconductor device. The mask plate design of the protective layer in the semiconductor device is not limited to the window design structure of the passivation layer, which can avoid the protective layer window falling on the step of the top metal boundary, thereby reducing the risk of the protective layer warping, cracking and peeling in the subsequent chip dicing and packaging process, reducing the reliability problem of the product, and especially bringing safety protection to the automotive production chip.

[0055] The semiconductor device and the method for manufacturing the semiconductor device in this embodiment are described in detail below.

[0056] This embodiment provides a semiconductor device, referring to Figure 3 The semiconductor device includes a semiconductor substrate (not shown), at least one metal layer 10, a first passivation layer 20, and a protective layer 30. The at least one metal layer 10 is disposed on a portion of the semiconductor substrate and is electrically connected to the semiconductor substrate. The first passivation layer 20 covers the metal layer 10 and the semiconductor substrate. At least one first opening 21 is formed on the first passivation layer 20. The number of the first openings 21 corresponds to the number of the metal layers 10. Each first opening 21 is opened on the corresponding metal layer 10 and exposes a portion of the corresponding metal layer 10. The protective layer 30 covers the first passivation layer 20 and has a second opening 31 formed on the protective layer 30. The second opening 31 exposes the at least one first opening 21 and the metal layer 10 corresponding to the first opening 21. The second opening 31 of the protective layer 30 exposes all of the step structures 50, so that the boundary of the second opening 31 of the protective layer 30 is away from the boundary of the first opening 21 of the first passivation layer 20 and is arranged away from the step structure 50. The present invention sets the protective layer 30 at a position avoiding the first opening 21 of the first passivation layer 20, away from the boundary of the first opening 21 of the first passivation layer 20 and away from the step structure 50. This design avoids the metal step and the window design of the passivation layer, which can effectively reduce the warping, cracking and peeling of the window position of the protective layer 30, thereby ensuring the reliability of the product.

[0057] Specifically, refer to Figure 4The semiconductor substrate (not shown in the figure) can be a substrate containing an IC circuit, which can include a substrate, electronic devices formed on the substrate, and a metal interconnection layer covering the electronic devices and the substrate. The substrate can be or include, for example, a single crystal silicon substrate, some other suitable semiconductor substrates, a silicon-on-insulator (SOI) substrate, a gallium nitride substrate, etc. In some embodiments, the substrate also includes a semiconductor substrate and an epitaxial layer covering the semiconductor substrate. The epitaxial layer can include gallium nitride or other suitable semiconductor materials. Electronic devices include components such as transistors, resistors, capacitors, and inductors. The metal interconnection layer includes metal lines and an interlayer dielectric layer, and the interlayer dielectric layer can include materials such as silicon dioxide, silicon nitride, and low-K dielectrics. A passivation layer is also covered on top of the metal interconnection layer. In this embodiment, the passivation layer is a second passivation layer 40, and the electrical connection points of the metal interconnection layer are exposed on the second passivation layer 40.

[0058] Reference Figure 3 and 4 , at least one metal layer 10 is arranged on a portion of the semiconductor substrate and forms an electrical connection with the semiconductor substrate. In this embodiment, the metal layer 10 is electrically connected to the electrical connection point of the metal interconnection layer exposed on the second passivation layer 40, and also covers a portion of the surface of the second passivation layer 40. In addition, the metal interconnection layer may include multiple electrical connection points. In this case, multiple metal layers 10 are required to correspond to the electrical connection points one by one. The portion of the metal layer 10 on the second passivation layer 40 is higher than the surface of the second passivation layer 40, so that a step structure 50 is formed at the intersection of the edge of the metal layer 10 and the surface of the second passivation layer 40. The metal layer 10 is the top metal layer in the semiconductor substrate and is the last layer of the multi-layer metal structure of the complex IC circuit. The metal layer 10 also undergoes an etching process to form the final structural morphology. The metal layer 10 can be used as a conductive pad.

[0059] Reference Figure 4 The first passivation layer 20 covers the metal layer 10 and the second passivation layer 40 of the semiconductor substrate. Specifically, the first passivation layer 20 extends above the metal layer 10 to cover the step structure 50, and extends from the step structure 50 to the second passivation layer 40 of the semiconductor substrate. Figure 3 and 4 At least one first opening 21 is formed in the first passivation layer 20. The number of first openings 21 corresponds to the number of metal layers 10. Each first opening 21 exposes a portion of the corresponding metal layer 10. In this embodiment, the materials of the first passivation layer 20 and the second passivation layer 40 can be the same or different, and can specifically be inorganic insulating materials such as silicon dioxide or silicon nitride. The first passivation layer 20 can be formed using deposition methods such as CVD and PVD.

[0060] Reference Figure 3 and4 , the protective layer 30 covers the first passivation layer 20. A second opening 31 is formed on the protective layer 30, and the second opening 31 exposes at least one first opening 21 and the metal layer 10 corresponding to the first opening 21. The second opening 31 of the protective layer 30 exposes all the step structures 50 at the corresponding position, so that the boundary of the second opening 31 of the protective layer 30 is far away from the boundary of the first opening 21 of the first passivation layer 20 and is far away from the step structure 50. That is, referring to Figure 4 ,exist Figure 1 On the basis of the above, the polyimide layer opening 03 is expanded outward in the direction away from the step structure 50, so that the boundary of the second opening 31 after expansion is X from the metal layer 10. Optionally, the distance X between the boundary of the second opening 31 and the boundary of the adjacent metal layer 10 is between 10μm and 200μm. In this way, the mask plate window of the protective layer 30 is no longer limited to the unreasonable design of being consistent with the mask plate of the passivation layer or having a small deviation. The boundary of the second opening 31 of the protective layer 30 formed subsequently can avoid the step structure 50 at the metal layer 10 and the first opening 21 of the first passivation layer 20, reducing the probability of warping and cracking and peeling at the boundary position of the second opening 31 of the protective layer 30. Optionally, the protective layer 30 is an organic insulating material, such as polyimide (PI).

[0061] Optionally, refer to Figure 3 , and 4, a plurality of second openings 31 may be provided on the protective layer 30, each second opening 31 covering one or more first openings 21 and the metal layer 10 corresponding to the first opening 21. Figure 5 If there are multiple first openings 21 of the first passivation layer 20 that are relatively close to each other, the second openings 31 on the protective layer 30 can be designed by merging the second openings 31, that is, the mask plate of the protective layer 30 is enlarged so that it can accommodate and expose multiple adjacent first openings 21. At this time, the distance X between the boundaries of the metal layers 10 corresponding to adjacent first openings 21 is between 10μm and 200μm. For example, in a specific example, one second opening 31 exposes two first openings 21, each first opening 21 corresponds to a metal layer 10, and the distance X between the boundaries of the two metal layers 10 is between 10μm and 200μm.

[0062] Therefore, the semiconductor device in this embodiment avoids the step structure 50 of the metal layer 10 and the first opening 21 of the first passivation layer 20 through the design concept of the opening of the open protective layer, which can effectively reduce the warping, cracking and peeling of the polyimide window position. This design has been mass-produced and reliability certified for automotive products, and successfully provides more reliable and safe performance for automotive products.

[0063] In addition, this embodiment also provides a method for manufacturing a semiconductor device, the method comprising:

[0064] S1: providing a semiconductor substrate, and forming at least one metal layer on a portion of the surface of the semiconductor substrate;

[0065] Specifically, a semiconductor substrate is provided, which is a substrate containing an IC circuit. Electrical connection points are exposed on the surface of the semiconductor substrate. Specifically, the substrate includes a substrate, electronic devices formed on the substrate, and a metal interconnection layer covering the electronic devices and the substrate. The substrate can be or include, for example, a single crystal silicon substrate, some other suitable semiconductor substrates, a silicon-on-insulator (SOI) substrate, a gallium nitride substrate, etc. In some embodiments, the substrate also includes a semiconductor substrate and an epitaxial layer covering the semiconductor substrate. The epitaxial layer can be gallium nitride or other suitable semiconductor materials. Electronic devices include components such as transistors, resistors, capacitors, and inductors. The metal interconnection layer includes metal lines and interlayer dielectric layers, and the interlayer dielectric layer can include materials such as silicon dioxide, silicon nitride, and low-K dielectrics. In addition, a passivation layer is also covered on top of the metal interconnection layer, see Figure 4 In this embodiment, the passivation layer is a second passivation layer 40 , and electrical connection points of the metal interconnection layer are exposed on the second passivation layer 40 .

[0066] Reference Figure 4 A metal layer 10 is formed at the locations of the exposed electrical connection points on the semiconductor substrate. The number of metal layers 10 corresponds to the number of exposed electrical connection points. This metal layer 10 can be formed by evaporation, sputtering, or other methods. This metal layer 10 is the top metal layer and the final layer of the multi-layer metal structure of a complex IC circuit. This metal layer 10 also undergoes an etching process to form its final structure. This metal layer 10 can be used as a conductive pad.

[0067] S2: forming a first passivation layer on the surface of the metal layer and the semiconductor substrate;

[0068] Specifically, refer to Figure 4 A first passivation layer 20 is formed on the surface of the metal layer 10 and the remaining semiconductor substrate. The first passivation layer 20 can be formed by CVD, PVD, sputtering, or some other suitable deposition process. The material of the first passivation layer 20 can be silicon dioxide, silicon nitride, or aluminum nitride.

[0069] S3: etching the first passivation layer at a position corresponding to the metal layer to form a first opening, so that the first passivation layer covers an edge of the metal layer, and the first opening exposes an inner area of ​​the metal layer enclosed by the edge;

[0070] Specifically, refer to Figure 3, a first opening 21 is formed by etching at a position of the first passivation layer 20 corresponding to the metal layer 10, so that the first passivation layer 20 covers the edge of the metal layer 10, and the first opening 21 of the first passivation layer 20 exposes the inner area of ​​the metal layer 10 surrounded by the edge. When forming the first opening 21 on the first passivation layer 20, the first opening 21 can be formed by wet etching, dry etching or photolithography. In this embodiment, the formation of the first opening 21 on the first passivation layer 20 is achieved by photolithography and etching processes. Specifically, a passivation layer mask plate is first provided, and the window of the passivation layer mask plate is aligned with the position of the metal layer 10, the window exposes the middle inner area of ​​the metal layer 10 corresponding to the first passivation layer 20, and the peripheral area of ​​the passivation layer mask plate covers the edge of the metal layer 10 corresponding to the first passivation layer 20. Then, the first passivation layer 20 exposed in the window area is exposed, and the exposed area is developed with a developer to remove the first passivation layer 20 in the exposed area, thereby forming the first opening 21.

[0071] S4: forming a protective layer on the surface of the first passivation layer;

[0072] Specifically, refer to Figure 3 Alternatively, a protective layer 30 is formed on the surface of the first passivation layer 20. Alternatively, the protective layer 30 may be formed by deposition, evaporation, or spin coating. In this embodiment, the protective layer 30 is made of an organic insulating material and is formed on the surface of the first passivation layer 20 by spin coating. Alternatively, the protective layer 30 is made of polyimide.

[0073] S5: Etching the protective layer to form a second opening on the protective layer, wherein the second opening exposes at least one first opening and a metal layer corresponding to the first opening, and the second opening of the protective layer exposes the step structure so that the boundary of the second opening of the protective layer is away from the boundary of the first opening of the first passivation layer and away from the step structure.

[0074] Reference Figure 3Or 4, a second opening 31 is formed on the protective layer 30 by etching. In this embodiment, a photolithography and development process is used to form the second opening 31 on the protective layer 30. Specifically, a protective layer mask plate is provided, and the window on the protective layer mask plate is larger than the first opening 21 of the first passivation layer 20, and larger than the metal layer 10 corresponding to the first opening 21 of the first passivation layer 20. The protective layer mask plate is placed on the first passivation layer 20 of the semiconductor substrate, and the window of the protective layer mask plate exposes the first opening 21 of the first passivation layer 20 and the metal layer 10 corresponding to the first opening 21 of the first passivation layer 20, and the boundary of the window is away from the step structure 50. The protective layer 30 exposed by the window of the protective layer mask plate is exposed and developed to form a second opening 31 at the position of the protective layer 30 corresponding to the window of the protective layer mask plate. After development, the protective layer 30 needs to be baked and cured. Then, the entire semiconductor structure is subsequently diced to form a single semiconductor device.

[0075] The manufacturing method of this embodiment uses an open protective layer mask plate. The second opening 31 formed in the protective layer 30 of the protective layer mask plate avoids the stepped structure 50 of the metal layer 10 and the first opening 21 of the first passivation layer 20. This can also effectively reduce warping, cracking and delamination at the boundary of the protective layer 30. In particular, it can reduce warping and cracking at the boundary of the protective layer 30 after dicing, thereby improving product reliability.

[0076] In summary, the semiconductor device of the present invention includes a semiconductor substrate, at least one metal layer, a first passivation layer, and a protective layer. The at least one metal layer is disposed on a portion of the semiconductor substrate and electrically connected to the semiconductor substrate. The metal layer protrudes above the surface of the semiconductor substrate, and a step structure is formed at the intersection of the metal layer and the semiconductor substrate. The first passivation layer covers the metal layer and the semiconductor substrate. The first passivation layer has at least one first opening formed in it, the number of first openings corresponding to the number of metal layers. Each first opening is located in its corresponding metal layer and exposes a portion of its corresponding metal layer. The protective layer covers the first passivation layer and has a second opening formed in it. The second opening exposes the at least one first opening and the metal layer corresponding to the first opening. The second opening of the protective layer exposes all of the step structure, so that the boundary of the second opening is away from the boundary of the first opening of the first passivation layer and away from the step structure. Therefore, the present invention positions the protective layer away from the boundary of the first opening of the first passivation layer and away from the step structure. This design avoids the metal step and the window design of the passivation layer, effectively reducing warping, cracking, and delamination at the window position of the protective layer, thereby ensuring product reliability.

[0077] The method for manufacturing a semiconductor device in the present invention is used to form the above-mentioned semiconductor device and also has the above-mentioned technical effects.

[0078] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A semiconductor device, characterized in that: include: semiconductor substrates; at least one metal layer disposed on a portion of the semiconductor substrate and electrically connected to the semiconductor substrate; The metal layer is higher than the surface of the semiconductor substrate, so that a step structure is formed at the intersection of the boundary of the metal layer and the semiconductor substrate; a first passivation layer covering the metal layer and the semiconductor substrate; At least one first opening is formed on the first passivation layer, the number of the first openings corresponds to the number of the metal layers, and each first opening is opened on the corresponding metal layer and exposes a portion of the metal layer; A protective layer is covered on the first passivation layer, and a second opening is formed on the protective layer, the second opening exposes at least one of the first openings and the metal layer corresponding to the first opening, and the second opening of the protective layer exposes all step structures at corresponding positions, so that the boundary of the second opening is away from the boundary of the first opening of the first passivation layer and away from the step structure.

2. The semiconductor device according to claim 1, wherein The distance between the boundary of the second opening and the boundary of the adjacent metal layer is between 10 μm and 200 μm.

3. The semiconductor device according to claim 1, wherein A plurality of second openings are provided on the protection layer, and each of the second openings exposes one or more first openings and the metal layer corresponding to the first opening.

4. The semiconductor device according to claim 1, wherein The second opening exposes two first openings, each of the first openings corresponds to one of the metal layers, and a distance between boundaries of the two metal layers ranges from 10 μm to 200 μm.

5. The semiconductor device according to claim 3, wherein The semiconductor substrate is a substrate including an IC circuit, and the IC circuit is electrically connected to the metal layer.

6. The semiconductor device according to claim 3, wherein A second passivation layer is provided on the surface of the semiconductor substrate, and at least a portion of the metal layer is formed on the second passivation layer; the first passivation layer extends above the metal layer to cover the step structure, and extends from the step structure to the second passivation layer of the semiconductor substrate.

7. A method for manufacturing a semiconductor device, characterized in that: The manufacturing method comprises: Providing a semiconductor substrate, forming at least one metal layer on a portion of the surface of the semiconductor substrate, wherein a boundary between the metal layer and the surface of the semiconductor substrate forms a step structure; forming a first passivation layer on the surfaces of the metal layer and the semiconductor substrate; Etching a first opening in the first passivation layer at a position corresponding to the metal layer, so that the first passivation layer covers an edge of the metal layer and the first opening exposes an inner area of ​​the metal layer enclosed by the edge; forming a protective layer on the surface of the first passivation layer; The protective layer is etched to form a second opening on the protective layer, wherein the second opening exposes at least one of the first openings and a metal layer corresponding to the first opening, and the second opening of the protective layer exposes the step structure at the corresponding position, so that the boundary of the second opening of the protective layer is away from the boundary of the first opening of the first passivation layer and away from the step structure.

8. The manufacturing method according to claim 7, characterized in that The step of etching the protective layer to form a second opening on the protective layer includes: Providing a protective layer mask plate, wherein the window on the protective layer mask plate is larger than the first opening of the first passivation layer and larger than the metal layer corresponding to the first opening of the first passivation layer; placing the protective layer mask plate on the first passivation layer, wherein a window of the protective layer mask plate exposes a first opening of the first passivation layer and a metal layer corresponding to the first opening of the first passivation layer, and the window exposes the step structure; The protective layer is exposed and developed based on the window on the protective layer mask plate, so as to form a second opening at a position of the protective layer corresponding to the window on the protective layer mask plate.

9. The manufacturing method according to claim 8, characterized in that The distance between the boundary of the second opening and the boundary of the adjacent metal layer is between 10 μm and 200 μm.

10. The manufacturing method according to claim 8, characterized in that: The semiconductor substrate is a substrate including an IC circuit, and the IC circuit is electrically connected to the metal layer.

Images