A multi-channel data acquisition method and system

Abstract

The embodiment of the application provides a kind of multi-channel data acquisition method and system, comprising: receiving the multi-channel digital signal after analog-digital conversion unit conversion;Wherein, multi-channel digital signal is to the analog signal input according to the preset strobe mode Channel selection, after the analog signal selected is converted into corresponding digital signal by analog-digital conversion unit, it is obtained;Interpolation filter is used to carry out interpolation filter processing to multi-channel digital signal, and the digital signal after multi-channel synchronization is obtained;Wherein, the interpolation filter is constructed according to the number of input channel and the number of channel sampling data points, and the number of channel sampling data points is the number of data points collected by analog-digital conversion unit for each switching of channel.The application can solve the problem of different synchronization of multi-channel data acquisition based on multiplexing structure.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of data acquisition system, and particularly relate to a multi-channel data acquisition method and system. BACKGROUND

[0002] In the field of seismic observation, the performance of the data acquisition system is directly related to the observation quality of the seismic data. For a three-component geophone, a multi-channel data acquisition system is needed to achieve three-component seismic data acquisition. Due to the fact that the geophone is generally deployed in remote areas, and considering factors such as cost, power consumption, weight and the like, a multiplexing multi-channel data acquisition system based on multiple input channels and an analog-to-digital converter structure is adopted. The multi-channel data acquisition system of this structure needs to realize data acquisition of different input channels through channel switching. Due to the time difference of channel switching, the data acquired by the multi-channel exists the problem of asynchronization. SUMMARY

[0003] Therefore, the purpose of embodiments of the present application is to provide a multi-channel data acquisition method and system to solve the problem of asynchronization of multi-channel acquired data.

[0004] To achieve the above purpose, the embodiments of the present application provide a multi-channel data acquisition method, which comprises:

[0005] receiving a plurality of digital signals converted by an analog-to-digital conversion unit; wherein the plurality of digital signals are obtained by channel gating the analog signals input through a plurality of input channels according to a preset gating mode, and then converting the gated analog signals into corresponding digital signals by the analog-to-digital conversion unit;

[0006] performing interpolation filtering processing on the plurality of digital signals by using a pre-constructed interpolation filter to obtain multi-channel synchronized digital signals; wherein the interpolation filter is constructed according to the number of input channels and the number of channel sampling data points, and the number of channel sampling data points is the number of data points collected by the analog-to-digital conversion unit for each channel switching.

[0007] Optionally, performing interpolation filtering processing on the plurality of digital signals by using a pre-constructed interpolation filter to obtain multi-channel synchronized digital signals comprises:

[0008] extracting digital signals corresponding to each input channel from the plurality of digital signals;

[0009] for the digital signals of the same input channel, inserting zeros with an interpolation number between the data points collected adjacent to each other before and after channel switching; wherein the interpolation number is determined according to the number of input channels and the number of channel sampling data points.

[0010] For the two input channels before and after the channel switching, zeros with the number of channel sampling data points are inserted before the data points of the input channel after the switching, so that the data points of the input channel after the switching are moved by the number of data points compared with the data points of the input channel before the switching;

[0011] The low-pass filtering processing is performed on the digital signals of the interpolated input channels to obtain the multi-channel synchronized digital signals.

[0012] Optionally, the interpolation number is the number of input channels minus one multiplied by the number of channel sampling data points.

[0013] Optionally, after the multi-channel synchronized digital signals are obtained, the method further comprises:

[0014] The decimation processing is performed on the multi-channel synchronized digital signals to obtain the decimated digital signals.

[0015] Optionally, the three signal output ends of the three-component seismometer input corresponding analog signals through three input channels, the preset gating mode is cyclic sampling, and the number of channel sampling data points is 1; the digital signals of the three interpolated input channels are represented as:

[0016] x1[n]={x1[0],0,0,0,x1[1],0,0,0,x1[2],0,0,0,…} (27)

[0017] x2[n]={0,x2[0],0,0,0,x2[1],0,0,0,x2[2],0,0…} (28)

[0018] x3[n]={0,0,x3[0],0,0,0,x3[1],0,0,0,x3[2],0…} (29)

[0019] Wherein, x1[n] is the interpolated digital signal of the first input channel, x2[n] is the interpolated digital signal of the second input channel, and x3[n] is the interpolated digital signal of the third input channel.

[0020] The embodiment of the application further provides a multi-channel data acquisition system, comprising:

[0021] The host computer is configured to receive a plurality of digital signals converted by an analog-to-digital conversion unit, wherein the plurality of digital signals are obtained by channel gating analog signals input through a plurality of input channels according to a preset gating mode, converting the gated analog signals into corresponding digital signals by the analog-to-digital conversion unit, and performing interpolation filtering on the plurality of digital signals by using a pre-constructed interpolation filter to obtain a plurality of channel-synchronized digital signals, wherein the interpolation filter is constructed according to the number of input channels and the number of channel sampling data points, and the number of channel sampling data points is the number of data points collected by the analog-to-digital conversion unit each time the channel is switched.

[0022] Optionally, the host computer is configured to extract digital signals corresponding to each input channel from the plurality of digital signals, insert a number of zeros between data points collected adjacent to each other before and after channel switching for the digital signals of the same input channel, wherein the number of zeros is determined according to the number of input channels and the number of channel sampling data points, insert a number of zeros equal to the number of channel sampling data points before the data points of the input channel after switching for the two input channels before and after channel switching, so that the data points of the input channel after switching are moved by a number of data points equal to the number of channel sampling data points compared to the data points of the input channel before switching, and perform low-pass filtering on the digital signals of each input channel after interpolation to obtain a plurality of channel-synchronized signals.

[0023] Optionally, the number of zeros is equal to the number of input channels minus one multiplied by the number of channel sampling data points.

[0024] Optionally, the host computer is further configured to perform decimation processing on the plurality of channel-synchronized digital signals to obtain decimated digital signals.

[0025] Optionally, the system further comprises:

[0026] The host computer is configured to receive a plurality of digital signals converted by an analog-to-digital conversion unit, wherein the plurality of digital signals are obtained by channel gating analog signals input through a plurality of input channels according to a preset gating mode, converting the gated analog signals into corresponding digital signals by the analog-to-digital conversion unit, and performing interpolation filtering on the plurality of digital signals by using a pre-constructed interpolation filter to obtain a plurality of channel-synchronized digital signals, wherein the interpolation filter is constructed according to the number of input channels and the number of channel sampling data points, and the number of channel sampling data points is the number of data points collected by the analog-to-digital conversion unit each time the channel is switched.

[0027] The programmable gain amplifier is configured to connect each input channel according to the channel connection and amplification control signal, amplify the analog signals in each input channel to a corresponding predetermined multiple, and transmit the amplified analog signals to the channel switching unit.

[0028] The channel switching unit is configured to connect each input channel according to the channel switching control signal, transmit the amplified analog signals to the analog-to-digital conversion unit.

[0029] an analog-digital conversion unit, configured to perform analog-digital conversion on the received analog signal and transmit the converted digital signal to the host computer.

[0030] As can be seen from the above, the multi-channel data acquisition method and system provided by the embodiments of the present application can receive the multi-channel digital signal converted by the analog-digital conversion unit by the host computer, perform interpolation filtering on the multi-channel digital signal by using the pre-constructed interpolation filter, and obtain the multi-channel synchronized digital signal, thereby solving the data synchronization problem of multi-channel data acquisition. BRIEF DESCRIPTION OF DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only the embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0032] Figure 1 The method flowchart of the embodiments of the present application is shown in the figure;

[0033] Figure 2 The system block diagram of the embodiments of the present application is shown in the figure;

[0034] Figure 3 The host computer structure block diagram of the embodiments of the present application is shown in the figure;

[0035] Figure 4 The principle block diagram of the signal processing system of the embodiments of the present application is shown in the figure;

[0036] Figure 5 The two-channel signal schematic diagram before synchronization processing of the embodiments of the present application is shown in the figure;

[0037] Figure 6 The two-channel signal schematic diagram after synchronization processing of the embodiments of the present application is shown in the figure. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solutions and advantages of the present disclosure more clear, the present disclosure will be further described in detail below with reference to specific embodiments and drawings.

[0039] It should be noted that the technical terms or scientific terms used in the embodiments of the present application should be understood as the general meaning understood by the person skilled in the art to which the present disclosure belongs, unless otherwise defined. The terms "first", "second", and similar terms used in the embodiments of the present application do not represent any order, quantity or importance, but are only used to distinguish different components. The terms "include" or "contain" and similar terms mean that the elements or objects before the terms cover the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms "connect" or "connected" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms "up", "down", "left", "right" and the like are only used to represent relative positional relationships, and when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0040] As shown in Figure 1 The embodiments of the present application provide a multi-channel data acquisition method, comprising:

[0041] S101: receiving a plurality of digital signals converted by an analog-digital conversion unit; wherein the plurality of digital signals are obtained by converting analog signals input through a plurality of input channels according to a preset gating mode, channel gating, and converting the gated analog signals into corresponding digital signals by the analog-digital conversion unit;

[0042] In combination with Figure 2 In the present embodiment, a multi-channel data acquisition system is used to acquire a plurality of signals. The multi-channel data acquisition system includes a master control unit, a plurality of input channels, a programmable gain amplifier, a channel switching unit, an analog-digital conversion unit, and a host computer. The plurality of input channels simultaneously acquire analog signals, each input channel is connected with a programmable gain amplifier, and the master control unit controls the programmable gain amplifier to adjust the amplitude of the acquired analog signals to the amplitude requirement of the analog-digital conversion unit, so that the amplitude of the acquired analog signals is amplified or reduced. The signals of each channel after amplitude adjustment are transmitted to the channel switching unit. The master control unit sends a signal to control the channel switching unit to control each channel to be turned on or turned off according to the preset gating mode, so that each input channel is sampled by the analog-digital conversion unit according to the set gating mode. The master control unit controls the analog-digital conversion unit to perform analog-digital conversion on the sampled data and receives the converted digital signals, and then transmits them to the host computer.

[0043] The main control unit can determine the required gating mode according to the observation instruments connected to the input channels and the actual observation requirements, control the programmable gain amplifier to gate the input channels according to the gating mode to determine the gain of the gated input channels, control the channel switching unit to switch the input channels according to the gating mode, and transmit the analog signals of the channels gated according to the gating mode to the upper computer after the analog signals are converted into corresponding digital signals by the analog-to-digital conversion unit.

[0044] In some modes, in the field of seismic observation, the three signal output ends of a three-component seismometer are input into a multi-channel data acquisition system through three input channels, and the main control unit sequentially gates the three input channels according to a cyclic sampling gating mode, that is, cyclically acquires analog signals input by each channel in the order of the first input channel, the second input channel, and the third input channel. The analog signals input by each input channel are converted into corresponding digital signals by the analog-to-digital conversion unit and then transmitted to the upper computer, and the upper computer receives the multi-channel digital signals obtained by cyclic sampling of each channel and performs synchronous processing based on the multi-channel digital signals.

[0045] S102: performing interpolation filtering processing on the multi-channel digital signals by using a pre-constructed interpolation filter to obtain multi-channel synchronized digital signals; wherein the interpolation filter is constructed according to the number of input channels and the number of channel sampling data points.

[0046] In this embodiment, for a multi-channel data acquisition system with multiple input channels and one analog-to-digital conversion unit, channel switching will cause a certain time difference, resulting in asynchronous data acquisition by each channel, which is difficult to meet the data synchronization requirements in some application scenarios. Therefore, after the upper computer receives the multi-channel digital signals, it needs to perform synchronous processing on the multi-channel digital signals to synchronize the data of each channel.

[0047] In some embodiments, the interpolation filtering processing on the multi-channel digital signals by using a pre-constructed interpolation filter to obtain multi-channel synchronized digital signals includes:

[0048] Extracting digital signals corresponding to each input channel from the multi-channel digital signals;

[0049] For the digital signals of the same input channel, zeros with an interpolation number are inserted between the data points collected adjacent to the channel switching; wherein the interpolation number is determined according to the number of input channels and the number of channel sampling data points;

[0050] For the two input channels before and after the channel switching, zeros with the number of channel sampling data points are inserted before the data points of the input channel after the switching, so that the data points of the input channel after the switching are moved by the number of channel sampling data points compared with the data points of the input channel before the switching.

[0051] The digital signals of the input channels after interpolation are low-pass filtered to obtain the multi-channel synchronized digital signals.

[0052] In this embodiment, the desynchronization of the multi-channel multi-path digital signals is related to the number of input channels and the number of channel sampling data points. Therefore, the multi-path digital signals are synchronized and corrected according to the number of input channels and the number of channel sampling data points. The number of channel sampling data points refers to the number of data points collected by the analog-to-digital conversion unit when the channel switches once. The number of channel sampling data points can be determined according to the application scenario and engineering design. For example, when any input channel is selected, the number of data points obtained by sampling the analog signal input by the input channel through the analog-to-digital conversion unit can also be understood as the number of data points that can be collected within the time difference caused by channel switching. The number of channel sampling data points is determined by the hardware circuit of the channel switching unit and the related timing design.

[0053] Specifically, based on the known selection mode, the digital signals corresponding to each input channel are extracted from the total data stream of the multi-path digital signals, that is, the multi-path digital signals are separated into a digital signal corresponding to each input channel. For the digital signal of the same input channel, zeros with an interpolation number are inserted between the data points collected adjacent to the channel switching, for example, zeros with an interpolation number are inserted between the data points collected when the first input channel is selected for the first time and the data points collected when the first input channel is selected for the second time. For the two input channels before and after the channel switching, zeros with the number of channel sampling data points are inserted before the digital points of the input channel after the channel switching, that is, for the adjacent two input channels (the two input channels before and after the channel switching), the data points are moved in the same direction by inserting a certain number of zeros, and the moving distance is the number of data points of the channel sampling data points. In this way, by interpolating the digital signals of the same channel, a certain number of zeros are inserted before the digital signals of the channel after the channel switching, which can compensate for the time difference caused by the channel switching and realize the timing alignment of the multi-path digital signals.

[0054] Since interpolation in the time domain is equivalent to increasing the sampling rate, in the frequency domain, it is equivalent to periodically extending the frequency spectrum to distribute the quantization noise to a wider interval, and the redundant frequency spectrum is caused by zero insertion. Therefore, the digital signals of the input channels after interpolation are low-pass filtered to obtain the multi-channel synchronized digital signals, that is, the low-pass filter is used to filter out the false frequency signal and restore the signal of the zero insertion point. The signal after low-pass filtering is the multi-channel approximately synchronized signal.

[0055] As Figure 3 , 4As shown, in some embodiments, the host computer receives the multi-channel digital signal, decimates the multi-channel digital signal by a decimation filter set to separate a digital signal corresponding to each input channel; each digital signal is processed by an interpolation low-pass filter to perform interpolation first and low-pass filtering later, to obtain the synchronized digital signals. Since interpolation processing increases the sampling rate of the data, to reduce the cost of data transmission and the complexity of data processing, and to reduce data redundancy, the synchronized digital signals are decimated by a decimation low-pass filter under the condition of satisfying the sampling theorem, to reduce the data amount.

[0056] In some embodiments, the number of interpolations is the number of input channels minus one, multiplied by the number of channel sampling data points. For example, if the number of input channels is M and the number of channel sampling data points is N, then the number of interpolations is N×(M-1).

[0057] In combination Figure 4 As shown, if the number of input channels is M and the number of channel sampling data points is N, i.e., each gated input channel collects N data points each time, the analog signals of the M input channels are collected in a cyclic sampling manner. After being amplified, the analog signals of each input channel are converted into corresponding digital signals by an analog-to-digital conversion unit, and the host computer transmits the digital signals corresponding to each input channel to the host computer. The multi-channel digital signal x[n] received by the host computer can be represented as: x[n] = {x1[0], x1[1], …, x1[N-1], x2[0], x2[1], …, x2[N-1], x3[0], x3[1], …, x3[N-1], x4[0], x4[1], …, x4[N-1], x1[N], x1[N+2], …, x1[2N-1], x2[N], x2[N+2], …, x2[2N-1], x3[N], x3[N+2], …, x3[2N-1], x4[N], x4[N+2], …, x4[2N-1]…}(1)

[0058] Wherein x1[0], x1[1], …, x1[N-1] are N data points collected by the first input channel in the first round of cyclic sampling, x2[0], x2[1], …, x2[N-1] are N data points collected by the second input channel in the first round of cyclic sampling, x3[0], x3[1], …, x3[N-1] are N data points collected by the third input channel in the first round of cyclic sampling, and x4[0], x4[1], …, x4[N-1] are N data points collected by the fourth input channel in the first round of cyclic sampling.

[0059] The multi-channel digital signal is decimated by a decimation filter to obtain a digital signal corresponding to each input channel, represented as:

[0060] x 11 [n] = {x1[0], x1[1], …, x1[N-1], x1[N], x1[N+2], …, x1[2N-1], x1[2N], …} (2)

[0061] x 12 [n] = {x2[0], x2[1], …, x2[N-1], x2[N], x2[N+2], …, x2[2N-1], x2[2N], …} (3)

[0062] x 13 [n] = {x3[0], x3[1], …, x3[N-1], x3[N], x3[N+2], …, x3[2N-1], x3[2N], …} (4)

[0063] …

[0064] x 1M [n] = {x M [0], x M [1], …, x M [N-1], x M [N], x M [N+2], …, x M [2N-1], x M [2N], …} (5)

[0065] wherein x 1M [n] is a digital signal corresponding to the Mth input channel.

[0066] In order to compensate for the time difference caused by channel switching, integer multiple interpolation is performed on the digital signal of each input channel, and N x (M-1) zeros are inserted between the data points collected in adjacent two times, and meanwhile, N zeros are inserted before the data points of the channel after channel switching, for the two channels before and after channel switching, which is expressed as:

[0067] x 21 [n] = {x1[0], x1[1], …, x1[N-1], 0, …, 0, x1[N], x1[N+2], …, x1[2N-1], 0, …, 0, x1[2N], …} (6)

[0068] x 22 [n] = {0, …, 0, x2[0], x2[1], …, x2[N-1], 0, …, 0, x2[N], x2[N+2], …, x2[2N-1], 0, …, 0, x2[2N], …} (7)

[0069] x 23[n]={0,…,0…,0,x3[0],x3[1],…,x3[N-1],0,…,0,x3[N],x3[N+2],…,x3[2N-1],0,…,0,x3[2N],…}(8)

[0070] …

[0071] x 2M [n]={0,…,0,…,0…,0,x4[0],x M [1],…,x M [N-1],0,…,0,x M [N],x M [N+2],…,x M [2N-1],0,…,0,x M [2N],…} (9)

[0072] Specifically, for the first and second input channels before and after the switch, N zeros are inserted before the data point x2[0] of the second input channel; for the second and third input channels before and after the switch, 2N zeros are inserted before the data point x3[0] of the third input channel; for the (M-1)th and Mth input channels before and after the switch, N zeros are inserted before the data point x3[0] of the Mth input channel. M [0] Insert (M-1) before

[0073] ×N zeros, that is, the data points of the input channel after switching are shifted to the right by N data points compared with the data points of the input channel before switching. By interpolation processing to compensate for the time difference of data acquisition of each channel, the data structure of each input channel is restored to that of multi-channel synchronous acquisition, and the original signal acquired by each input channel is restored, realizing multi-channel synchronous data acquisition based on multiplexing hardware structure.

[0074] In some implementations, taking into account the characteristics of the digital signal after interpolation and low-pass filtering, the system function for extracting the low-pass filter can be designed as follows:

[0075] h1[n]={h(0),h(K),h(2K),…} (10)

[0076] h2[n]={h(1),h(K+1),h(2K+1),…} (11)

[0077] h3[n]={h(2),h(K+2),h(2K+2),…} (12)

[0078] …

[0079] h M[n]={h(K-1),h(2K-1),h(3K-1),…} (13)

[0080] Where K is the extraction multiple.

[0081] Taking four input channels as an example, the analog signals of the four input channels are collected cyclically using a cyclic sampling method, with each channel sampling data point being 1, meaning each input channel collects one data point at a time. The multi-channel digital signal x[n] received by the host computer can be represented as:

[0082] x[n]={x1[0],x2[0],x3[0],x4[0],x1[1],x2[1],x3[1],x4[1],x1[2],…} (14)

[0083] Where x1[0], x2[0], x3[0], x4[0] are the data points collected by the first input channel, the second input channel, the third input channel, and the fourth input channel during the first round of cyclic sampling, respectively, and x1[1], x2[1], x3[1], x4[1] are the data points collected by the first input channel, the second input channel, the third input channel, and the fourth input channel during the second round of cyclic sampling, respectively.

[0084] The multiple digital signals are decimated using a decimation filter bank to obtain one digital signal for each input channel, represented as:

[0085] x 11 [n]={x1[0],x1[1],x1[2],…} (15)

[0086] x 12 [n]={x2[0],x2[1],x2[2],…} (16)

[0087] x 13 [n]={x3[0],x3[1],x3[2],…} (17)

[0088] x 14 [n]={x4[0],x4[1],x4[2],…} (18)

[0089] like Figure 5 As shown, due to the time difference during channel switching, the signals acquired by different input channels exhibit significant asynchrony. To achieve signal synchronization between different input channels, three zeros are inserted between two adjacent data points within the same channel. Furthermore, for both channels before and after the channel switch, one zero is inserted before the data point of the switched channel. The digital signals of each input channel after interpolation are represented as follows:

[0090] x21 [n] = {x1[0], 0, 0, 0, x1[1], 0, 0, 0, x1[2], 0, 0, 0, …} (19)

[0091] x 22 [n] = {0, x2[0], 0, 0, 0, x2[1], 0, 0, 0, x2[2], 0, 0, …} (20)

[0092] x 23 [n] = {0, 0, x3[0], 0, 0, 0, x3[1], 0, 0, 0, x3[2], 0, …} (21)

[0093] x 24 [n] = {0, 0, 0, x4[0], 0, 0, 0, x4[1], 0, 0, 0, x4[2], …} (22)

[0094] The digital signals of each channel after interpolation processing have realized time alignment in the time domain. The interpolated signals are further subjected to low-pass filtering to obtain the signals after multi-channel synchronous processing. As shown in FIG. 6, according to the method of the present application, the signals collected by multiple channels are approximately synchronized, which can meet the application requirements of, for example, a seismic data collection scenario. Figure 6

[0095] The signals after interpolation processing and low-pass filtering are input into decimation low-pass filters for decimation, which can reduce the data volume under the condition of ensuring signal fidelity. The system functions of four decimation low-pass filters designed for four input channels can be expressed as:

[0096] h1[n] = {h(0), h(4), h(8), …} (23)

[0097] h2[n] = {h(1), h(5), h(9), …} (24)

[0098] h3[n] = {h(2), h(6), h(10), …} (25)

[0099] h4[n] = {h(3), h(7), h(11), …} (26)

[0100] In this embodiment, by decomposing a system with linear phase characteristics into a multi-phase filter structure of multiple sub-systems with lower order, compared with the traditional combination of low-pass filters and decimation filters, the calculation amount can be greatly reduced, and the calculation resources can be saved.

[0101] ​In the application scenario of seismic observation, three signal output ends of a three-component seismometer are connected to a multi-channel data acquisition system, three signal input ends input corresponding analog signals through three input channels of the system, the strobe mode is set as cyclic sampling, and the number of channel sampling data points is 1. According to the method of the application, the interpolated digital signals of the three input channels are represented as:

[0102] x1[n] = {x1[0], 0, 0, 0, x1[1], 0, 0, 0, x1[2], 0, 0, 0, …} (27)

[0103] x2[n] = {0, x2[0], 0, 0, 0, x2[1], 0, 0, 0, x2[2], 0, 0, …} (28)

[0104] x3[n] = {0, 0, x3[0], 0, 0, 0, x3[1], 0, 0, 0, x3[2], 0, …} (29)

[0105] Wherein, x1[n] is the interpolated digital signal of the first input channel, x2[n] is the interpolated digital signal of the second input channel, and x3[n] is the interpolated digital signal of the third input channel. Then, the interpolated signals are subjected to low-pass filtering processing to obtain three synchronous seismic signals, and then subjected to decimation low-pass filtering to obtain the required seismic signals.

[0106] The multi-channel data acquisition method provided by the embodiment of the application is used for interpolating and filtering the multiple digital signals of multiple input channels collected by the multi-channel data acquisition system, the digital signals of the channels are separated, interpolation is performed between the data points collected at adjacent two times for the digital signals of the same channel, interpolation is performed before the digital signals of the channels after switching, the time difference caused by channel switching is compensated in the time domain, low-pass filtering is performed, and the multiple channels are synchronized, thereby solving the problem of asynchronous data of multi-channel data acquisition.

[0107] As shown in Figure 2 , the embodiment of the application provides a multi-channel data acquisition system, which comprises:

[0108] The host computer is configured to receive a plurality of digital signals converted by an analog-to-digital conversion unit, wherein the plurality of digital signals are obtained by channel gating analog signals input through a plurality of input channels according to a preset gating mode, converting the gated analog signals into corresponding digital signals by the analog-to-digital conversion unit, and performing interpolation filtering on the plurality of digital signals by using a pre-constructed interpolation filter to obtain a plurality of channel-synchronized digital signals, wherein the interpolation filter is constructed according to the number of input channels and the number of channel sampling data points, and the number of channel sampling data points is the number of data points collected by the analog-to-digital conversion unit each time the channel is switched.

[0109] In some embodiments, the host computer is configured to extract digital signals corresponding to each input channel from the plurality of digital signals, insert a number of zeros between data points collected adjacent to each other before and after channel switching for the digital signals of the same input channel, wherein the number of zeros is determined according to the number of input channels and the number of channel sampling data points, insert a number of zeros equal to the number of channel sampling data points before the data points of the input channel after switching for the two input channels before and after channel switching, so that the data points of the input channel after switching are moved by a number of data points equal to the number of channel sampling data points compared to the data points of the input channel before switching, and perform low-pass filtering on the digital signals of each input channel after interpolation to obtain a plurality of channel-synchronized digital signals.

[0110] In some embodiments, the host computer is further configured to perform decimation processing on the plurality of channel-synchronized digital signals to obtain decimated digital signals.

[0111] In some embodiments, the multi-channel data acquisition system further comprises:

[0112] The host computer is configured to receive a plurality of digital signals converted by an analog-to-digital conversion unit, wherein the plurality of digital signals are obtained by channel gating analog signals input through a plurality of input channels according to a preset gating mode, converting the gated analog signals into corresponding digital signals by the analog-to-digital conversion unit, and performing interpolation filtering on the plurality of digital signals by using a pre-constructed interpolation filter to obtain a plurality of channel-synchronized digital signals, wherein the interpolation filter is constructed according to the number of input channels and the number of channel sampling data points, and the number of channel sampling data points is the number of data points collected by the analog-to-digital conversion unit each time the channel is switched.

[0113] The programmable gain amplifier is configured to connect each input channel according to the channel connection and amplification control signal, and amplify the analog signals in each input channel to a corresponding predetermined multiple, and then transmit them to the channel switching unit.

[0114] The channel switching unit is configured to connect each input channel according to the channel switching control signal, and transmit the amplified analog signals to the analog-to-digital conversion unit.

[0115] The analog-to-digital conversion unit is configured to perform analog-to-digital conversion processing on the received analog signals and transmit the converted digital signals to the host computer.

[0116] The multi-channel data acquisition system is described below in combination with a specific embodiment.

[0117] Each input channel corresponds to a programmable logic amplifier, the signal output end of the programmable gain amplifier is connected with the signal input end of the channel switching unit, the signal output end of the channel switching unit is connected with the signal input end of the analog-digital conversion unit, the signal output end of the analog-digital conversion unit is connected with the signal input end of the host control unit, and the signal output end of the host control unit is connected with the signal input end of the host computer.

[0118] The first control signal end of the host control unit is connected with the control end of the programmable gain amplifier, the host control unit controls the programmable gain amplifier corresponding to each input channel, amplifies the analog signal input by each input channel according to a predetermined amplification multiple, so that the amplified analog signal is within the input range of the analog-digital conversion unit. The second control signal end of the host control unit is connected with the control end of the channel switching unit, and the host control unit controls the channel switching unit to connect an input channel, and outputs the amplified analog signal corresponding to the connected input channel to the analog-digital conversion unit.

[0119] In some modes, the programmable gain amplifier includes a gain control circuit, a low-pass filter, a switch circuit, etc., the channel connection and amplification control signal output by the host control unit is processed by the gain control circuit into a control signal for controlling the control timing of multiple programmable gain amplifiers, that is, only a limited number of input and output ports and clock signal ports of the host control unit are needed, and the gain control circuit can be used to generate multiple control signals for controlling multiple programmable gain amplifiers. The control signal generated by the gain control circuit is used to control the amplification multiple of the programmable gain amplifier, and the input analog signal is first filtered by the low-pass filter to reduce noise, and the filtered analog signal passes through different resistors in the resistor circuit and the switch circuit, and different amplification multiples are realized by connecting different resistors, so that the input analog signal is amplified according to the amplification multiple.

[0120] In some embodiments, the channel switching unit includes a channel control circuit, a switch circuit and a sample-and-hold circuit, the number of sample-and-hold circuits corresponds to the number of input channels, and the channel switching control signal output by the host control unit is processed by the channel control circuit into a control signal for switching different signal holding circuits and for controlling the switch circuit, that is, only a limited number of output ports of the host control unit are needed, and the channel control circuit can be used to generate multiple control signals for switching different signal holding circuits and controlling the switch. The amplified analog signal is output to the analog-digital conversion unit after passing through the sample-and-hold circuit and the corresponding switch path.

[0121] In some embodiments, the analog-digital conversion unit is implemented based on a 24-bit ADC chip, the analog-digital conversion unit is connected to the master control unit through an SPI interface, and the master control unit is configured as a slave device for reading data of the analog-digital conversion unit. To ensure correct and stable reading of data from the analog-digital conversion unit, a timing constraint signal is provided by the master control unit. Specifically, a reference clock signal output by the master control unit is used as a reference clock of a timing constraint circuit, a first timing control signal and a second timing control signal in the form of a PWM wave are generated by the master control unit, a conversion signal (CNV signal) of the analog-digital conversion unit is controlled by the first timing control signal and has the same frequency as the first timing control signal, and the waveform of the conversion signal lags behind the first timing control signal by one system clock cycle; the data transmission and reception signal of the analog-digital conversion unit (in the SPI communication process, one bit of data is read or transmitted when the rising edge or falling edge of each data transmission and reception signal ADC_SPI_SCK arrives) is generated by the reference clock (output by the clock signal MCO of the master control unit), the first timing control signal and the second timing control signal; the first timing control signal and the second timing control signal have a phase difference of one fourth, and there are 24 data transmission and reception signals within a specified time range after the rising edge of each conversion signal (CNV signal) arrives, for the analog-digital conversion unit to transmit one bit of data to the master control unit at the rising edge or falling edge of the 24 data transmission and reception signals; and the clock signal of the master control unit as a slave device is obtained by the reference clock and the first timing control signal through an AND operation. In this way, by using an external hardware timing constraint circuit, the master control unit only needs to provide a reference clock and open a timer to control the analog-digital conversion unit, which can simplify the complexity of software design, improve the stability of the system, and reduce the power consumption of the system.

[0122] In some embodiments, the master control unit is connected to the analog-digital conversion unit, the programmable gain amplifier, and the channel switching unit through a digital isolator. The digital isolator is used to prevent crosstalk of digital signals to analog signals due to common ground, to ensure stable operation of the circuit, and to exchange, transmit, and control data between different circuit units, so that the circuit units can quickly, efficiently, and accurately communicate with each other.

[0123] It should be understood by those of ordinary skill in the art that the above discussion of any embodiment is only exemplary and is not intended to limit the scope of the disclosure (including the claims) to these examples; under the idea of the disclosure, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other changes of different aspects of the embodiments of the present application as described above. In order to be brief, they are not provided in detail.

[0124] Additionally, to simplify the description and discussion, and so as not to obscure the embodiments of the application being presented, the well-known functions or constructions of integrated circuit (IC) chips and other components can or can not be shown in the figures and will be omitted as not to unnecessarily obscure the embodiments of the application being presented. Moreover, the devices can be shown in block diagram form in order to avoid obscuring the embodiments of the application being presented, and this also acknowledges the fact that the details in regard to the implementation of the block diagram devices are highly dependent on the platform within which the embodiments of the application are to be implemented (i.e., these details should be well within the purview of one of ordinary skill in the art). Where specific details are set forth in order to describe an illustrative embodiment of the disclosure, it will be apparent to one of ordinary skill in the art that the embodiments of the application can be practiced without, or with variation of, these specific details. Thus, the description is to be considered as illustrative and not restrictive, and the scope of the application should be determined not with reference to the description, but rather with reference to the appended claims.

[0125] While the present disclosure has been described with respect to a limited number of embodiments, it will be apparent to those skilled in the art that many alternate, modifications, and variations will be suggested by the foregoing description and that the embodiments of the present disclosure are thereby not to be restricted.

[0126] It is therefore intended that the present disclosure cover all such alternatives, modifications and variations as fall within the broad scope of the appended claims. Accordingly, any and all such modifications, variations or equivalents that fall within the scope of the present disclosure should be intended to be embraced by the claims.

Claims

1. A method of multichannel data acquisition, characterized by, The method comprises the following steps: receiving a plurality of digital signals converted by an analog-to-digital conversion unit; wherein the plurality of digital signals are obtained by converting analog signals input through a plurality of input channels simultaneously according to a preset gating mode through a channel switching unit, and the analog signals are converted into corresponding digital signals by the analog-to-digital conversion unit; the plurality of digital signals are non-synchronous acquisition signals due to the time difference caused by channel switching; interpolation filtering the plurality of digital signals by using a pre-constructed interpolation filter to obtain a plurality of channel-synchronized digital signals, comprising the following steps: extracting digital signals corresponding to each input channel from the plurality of digital signals; for the digital signals of the same input channel, inserting zeros with an interpolation number between the data points collected before and after channel switching; wherein the interpolation number is determined according to the number of input channels and the number of channel sampling data points; for the two input channels before and after channel switching, inserting zeros with the number of channel sampling data points before the data points of the input channel after switching, so that the data points of the input channel after switching are moved by the number of channel sampling data points compared with the data points of the input channel before switching; performing low-pass filtering on the interpolated digital signals of each input channel to obtain a plurality of channel-synchronized digital signals; the interpolated digital signals of each input channel are signals that have been compensated for the time difference and restored to signals collected simultaneously by a plurality of input channels; wherein the interpolation filter is constructed according to the number of input channels and the number of channel sampling data points; the number of channel sampling data points is the number of data points collected by the analog-to-digital conversion unit for each channel switching; and the interpolation number is the number of input channels minus one multiplied by the number of channel sampling data points; the analog-to-digital conversion unit and the master control unit are connected through an SPI interface; the master control unit is configured as a slave device for the analog-to-digital conversion unit to read data; the analog-to-digital conversion unit is provided with a timing constraint signal by the master control unit; the reference clock signal output by the master control unit is the reference clock of the timing constraint circuit; the master control unit generates a first timing control signal and a second timing control signal in the form of a PWM wave; the conversion signal of the analog-to-digital conversion unit is controlled by the first timing control signal and has the same frequency as the first timing control signal; the waveform of the conversion signal lags behind the first timing control signal by one system clock cycle; the transmit and receive data signal of the analog-to-digital conversion unit is generated by the reference clock, the first timing control signal and the second timing control signal; the first timing control signal and the second timing control signal have a phase difference of one-quarter; after each conversion signal rising edge arrives, there are 24 transmit and receive data signals within a specified time range, which are used by the analog-to-digital conversion unit to transmit one bit of data to the master control unit at the rising or falling edge of the 24 transmit and receive data signals.

2. The method of claim 1, wherein, After obtaining the plurality of channel-synchronized digital signals, the method further comprises the following steps: performing decimation processing on the plurality of channel-synchronized digital signals to obtain decimated digital signals. ​ 3. The method of claim 1, wherein, Three signal output ends of the three-component seismometer input corresponding analog signals through three input channels, the preset gating mode is cyclic sampling, the number of channel sampling data points is 1; the interpolated three input channel digital signals are represented as: x1[n]={x1[0],0,0,0,x1[1],0,0,0,x1[2],0,0,0,…}(27) x2[n]={0,x2[0],0,0,0,x2[1],0,0,0,x2[2],0,0,…}(28) x3[n]={0,0,x3[0],0,0,0,x3[1],0,0,0,x3[2],0,…}(29) Wherein, x1[n] is the interpolated digital signal of the first input channel, x2[n] is the interpolated digital signal of the second input channel, x3[n] is the interpolated digital signal of the third input channel.

4. A multi-channel data acquisition system, characterized by Comprise: The host computer is used for receiving the multi-channel digital signal converted by an analog-digital conversion unit;Wherein, the multi-channel digital signal is obtained by converting the analog signal input through multiple input channels simultaneously into corresponding digital signals according to the preset gating mode through the channel switching unit, the multi-channel digital signal is the multi-channel digital signal collected asynchronously due to the time difference caused by channel switching; And the interpolation filter is constructed in advance to interpolate and filter the multi-channel digital signal to obtain the multi-channel synchronized digital signal, comprising: extracting the digital signal corresponding to each input channel from the multi-channel digital signal;For the digital signal of the same input channel, zero with interpolation quantity is inserted between the data points collected adjacent to the channel switching;Wherein, the interpolation quantity is determined according to the number of input channels and the number of channel sampling data points;For the two input channels before and after the channel switching, zero with the number of channel sampling data points is inserted before the data points of the input channel after the switching, so that the data points of the input channel after the switching are moved by the number of channel sampling data points compared with the data points of the input channel before the switching;The interpolated digital signal of each input channel is low-pass filtered to obtain the multi-channel synchronized digital signal;The interpolated digital signal of each input channel is compensated for the time difference and restored to the signal collected simultaneously by multiple input channels; Wherein, the interpolation filter is constructed according to the number of input channels and the number of channel sampling data points, the number of channel sampling data points is the number of data points collected by the analog-digital conversion unit for each channel switching;The interpolation quantity is the number of input channels minus one multiplied by the number of channel sampling data points; The analog-digital conversion unit is connected with the master control unit through an SPI interface, the master control unit is configured as a slave device for the analog-digital conversion unit to read data, the analog-digital conversion unit is provided with a timing constraint signal by the master control unit, a reference clock signal output by the master control unit is a reference clock of the timing constraint circuit, the master control unit generates a first timing control signal and a second timing control signal in the form of a PWM wave, the conversion signal of the analog-digital conversion unit is controlled by the first timing control signal and has the same frequency as the first timing control signal, and the waveform of the conversion signal lags behind the first timing control signal by one system clock cycle; the transceiving data signal of the analog-digital conversion unit is generated by the reference clock, the first timing control signal and the second timing control signal; the first timing control signal and the second timing control signal have a phase difference of one fourth, and after each conversion signal rising edge arrives, there are 24 transceiving data signals in a specified time range for the analog-digital conversion unit to transmit one bit of data to the master control unit at the rising edge or the falling edge of the 24 transceiving data signals.

5. The system of claim 4, wherein, The host computer is further configured to perform decimation processing on the multi-channel synchronized digital signal to obtain a decimated digital signal.

6. The system of claim 4, wherein, Further comprising: a master control unit configured to generate a channel on and amplification control signal for turning on each input channel and amplifying the analog signal in each input channel by a corresponding predetermined multiple according to the preset gating mode, generate a channel switching control signal for turning on each input channel according to the preset gating mode, and receive a digital signal output by the analog-digital conversion unit and transmit the digital signal to the host computer; a programmable gain amplifier configured to turn on each input channel and amplify the analog signal in each input channel to a corresponding predetermined multiple according to the channel on and amplification control signal, and then transmit the amplified analog signal to the channel switching unit; a channel switching unit configured to turn on each input channel according to the channel switching control signal and transmit the amplified analog signal to the analog-digital conversion unit; an analog-digital conversion unit configured to perform analog-digital conversion processing on the received analog signal and transmit the converted digital signal to the master control unit.

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