A frame rate switching device, method, electronic device, and readable storage medium

Abstract

This application discloses a frame rate switching device, method, electronic device, and readable storage medium, relating to the field of electronic devices. It solves the problem of black screens occurring during frame rate switching in dynamic frame rate systems, leading to poor display smoothness and a poor user experience. Specifically, it provides a frame rate switching device including a processor, a load switch, a power management integrated circuit, and a timing controller. The load switch controls the output power supply voltage when the frame rate switches from a first frame rate to a second frame rate. The power management integrated circuit receives the power supply voltage and provides a power supply voltage to the timing controller based on the power supply voltage. The processor sends a first control signal when the frame rate switches from the first frame rate to the second frame rate. Under the control of the first control signal, the timing controller continuously sends data signals corresponding to a first image frame at the first frame rate. The first image frame is any one of the multiple image frames last received by the timing controller before the frame rate switching.

Description

Technical Field

[0001] This application relates to the field of electronic devices, and more particularly to a frame rate switching device, method, electronic device, and readable storage medium. Background Technology

[0002] Frame rate switching is a fundamental scenario in dynamic frame rate systems, and can be divided into specified frame rate switching (also known as manual frame rate switching) and automatic frame rate switching. When the dynamic frame rate system is in a specified frame rate switching scenario, the user can specify a new frame rate through software, and the dynamic frame rate system will switch to the new frame rate after N frames. When the dynamic frame rate system is in an automatic frame rate switching scenario, the dynamic frame rate system will automatically adjust the frame rate based on the execution of the upper-layer software and switch to the new frame rate after N frames.

[0003] However, dynamic frame rate systems may experience black screens during frame rate switching, resulting in poor display smoothness and a poor user experience. Summary of the Invention

[0004] This application provides a frame rate switching device, method, electronic device, and readable storage medium, which solves the problem that black screens occur during frame rate switching in dynamic frame rate systems, resulting in poor display smoothness and a poor user experience.

[0005] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0006] In a first aspect, this application provides a frame rate switching device, comprising a processor, a load switch, a power management integrated circuit, and a timing controller. One end of the load switch is coupled to the processor, and the other end of the load switch is coupled to the power management integrated circuit. One end of the timing controller is coupled to the processor, and the other end of the timing controller is coupled to the power management integrated circuit. The load switch controls the output power supply voltage when the frame rate switches from a first frame rate to a second frame rate. The power management integrated circuit receives the power supply voltage and provides a power supply voltage to the timing controller based on the power supply voltage. The processor sends a first control signal when the frame rate switches from the first frame rate to the second frame rate. Under the control of the first control signal, the timing controller continuously sends a data signal corresponding to a first image frame at the first frame rate. The first image frame is any one of a plurality of image frames last received by the timing controller before the frame rate switching.

[0007] Based on this solution, when the frame rate switches from the first frame rate to the second frame rate, a power supply voltage is provided to the power management integrated circuit (IC) via a load switch. The IC then supplies power to the timing controller based on this voltage, meeting the controller's power requirements. Simultaneously, the processor sends a first control signal. Under the control of this signal, the timing controller continuously sends the data signal corresponding to the first image frame at the first frame rate. This first image frame is any one of the multiple image frames last received by the timing controller before the frame rate switch. Therefore, the display driver chip in the screen can continuously drive the screen to display images based on this data signal, preventing the screen from going black and thus improving display smoothness and user experience.

[0008] In conjunction with the first aspect, in one possible implementation, the timing controller includes a memory. Specifically, the timing controller is used to, under the control of the first control signal, store and maintain the first image frame in the memory, continuously read the first image frame from the memory, and send the data signal corresponding to the first image frame at a first frame rate.

[0009] Based on this solution, the timing controller stores and holds the first image frame in the memory, continuously reads the first image frame from the memory, and sends the data signal corresponding to the first image frame at the first frame rate, thereby ensuring that the display screen can continuously display images without going black, thus improving display smoothness and user experience.

[0010] In conjunction with the first aspect, in one possible implementation, the timing controller is also coupled to a load switch. The processor is further configured to send a second control signal when the frame rate switches from a first frame rate to a second frame rate. The timing controller is also configured to receive the second control signal and send a third control signal. Specifically, the load switch is configured to receive the third control signal and, under the control of the third control signal, control the output power supply voltage.

[0011] Based on this scheme, when the frame rate switches from the first frame rate to the second frame rate, the processor sends a second control signal. The timing controller generates and sends a third control signal based on this second control signal. The load switch outputs a power supply voltage under the control of the third control signal. Thus, the power management integrated circuit can provide a power supply voltage to the timing controller based on this power supply voltage to meet the power supply requirements of the timing controller. The timing controller can continuously send the data signal corresponding to the first image frame at the first frame rate, thereby ensuring that the display screen can continuously display images without going black, thus improving display smoothness and enhancing the user experience.

[0012] In conjunction with the first aspect, in one possible implementation, the device further includes an embedded controller, one end of which is coupled to the processor, and the other end of which is coupled to a load switch. The processor is also configured to send a fourth control signal when the frame rate switches from a first frame rate to a second frame rate. The embedded controller is configured to receive the fourth control signal and send a fifth control signal. The load switch is specifically configured to receive the fifth control signal and, under the control of the fifth control signal, control the output power supply voltage.

[0013] Based on this scheme, when the frame rate switches from the first frame rate to the second frame rate, the processor sends a fourth control signal. The embedded controller generates and sends a fifth control signal based on this fourth control signal. The load switch outputs a power supply voltage under the control of the fifth control signal. Thus, the power management integrated circuit can provide a power supply voltage to the timing controller based on this power supply voltage, meeting the power supply requirements of the timing controller. The timing controller can continuously send the data signal corresponding to the first image frame at the first frame rate, thereby ensuring that the display screen can continuously display images without going black, thus improving display smoothness and enhancing the user experience.

[0014] In conjunction with the first aspect, in one possible implementation, when the frame rate switching is complete: the processor is further configured to send a sixth control signal and transmit a second image frame at the second frame rate. The load switch is further configured to receive the sixth control signal and control the output power supply voltage under the control of the sixth control signal. The timing controller is further configured to receive the second image frame and transmit the data signal corresponding to the second image frame at the second frame rate.

[0015] Based on this scheme, when the frame rate switching is complete, the processor sends a sixth control signal. Under the control of this sixth control signal, the load switch continues to output power voltage. The power management integrated circuit can provide power supply voltage to the timing controller according to this power supply voltage to meet the power supply requirements of the timing controller. At the same time, the processor sends a second image frame at the second frame rate. The timing controller sends the corresponding data signal of the second image frame at the second frame rate according to the second image frame, thereby ensuring that the display screen can continuously display images without going black, thus improving display smoothness and enhancing the user experience.

[0016] In conjunction with the first aspect, in one possible implementation, the processor and the timing controller are coupled through at least one of the following: integrated circuit bus I2C, serial peripheral interface SPI, auxiliary AUX interface, and mobile industry processor interface MIPI.

[0017] In conjunction with the first aspect, in one possible implementation, the processor is further configured to send a seventh control signal when the frame rate switches from a first frame rate to a second frame rate. The timing controller is further configured to receive the seventh control signal and, under the control of the seventh control signal, disable the screen self-refresh (PSR) function.

[0018] Based on this scheme, when the processor switches the frame rate from the first frame rate to the second frame rate, it sends a seventh control signal. Under the control of the seventh control signal, the timing controller disables the screen self-refresh (PSR) function. This ensures that, under the control of the first control signal, the timing controller stores the first image frame in memory. The timing controller can continuously read the first image frame from memory and send the corresponding data signal at the first frame rate. Therefore, the display driver chip in the display can continuously drive the screen to display images according to this data signal, preventing the screen from going black and thus improving display smoothness and user experience.

[0019] A second aspect of this application provides a frame rate switching method applied to a frame rate switching device including a processor, a load switch, a power management integrated circuit, and a timing controller. One end of the load switch is coupled to the processor, and the other end of the load switch is coupled to the power management integrated circuit. One end of the timing controller is coupled to the processor, and the other end of the timing controller is coupled to the power management integrated circuit. The method includes: when the frame rate switches from a first frame rate to a second frame rate, the load switch controls the output power supply voltage. The power management integrated circuit receives the power supply voltage and provides a power supply voltage to the timing controller according to the power supply voltage. When the frame rate switches from the first frame rate to the second frame rate, the processor sends a first control signal. Under the control of the first control signal, the timing controller continuously sends a data signal corresponding to a first image frame at the first frame rate. The first image frame is any one of a plurality of image frames last received by the timing controller before the frame rate switching.

[0020] In conjunction with the second aspect, in one possible implementation, the timing controller includes a memory. Under the control of the first control signal, the timing controller continuously transmits the data signal corresponding to the first image frame at a first frame rate, including: under the control of the first control signal, the timing controller stores and holds the first image frame in the memory, continuously reads the first image frame from the memory, and transmits the data signal corresponding to the first image frame at the first frame rate.

[0021] In conjunction with the second aspect, in one possible implementation, the method further includes: when the frame rate switches from a first frame rate to a second frame rate, the processor sends a second control signal. The timing controller receives the second control signal and sends a third control signal. The load switch receives the third control signal and controls the output power supply voltage under the control of the third control signal.

[0022] In conjunction with the second aspect, in one possible implementation, the frame rate switching device further includes an embedded controller, one end of which is coupled to the processor, and the other end of which is coupled to a load switch. The method further includes: when the frame rate switches from a first frame rate to a second frame rate, the processor sends a fourth control signal. The embedded controller receives the fourth control signal and sends a fifth control signal. The load switch receives the fifth control signal and controls the output power supply voltage under the control of the fifth control signal.

[0023] In conjunction with the second aspect, in one possible implementation, the method further includes: when the frame rate switching is complete, the processor sends a sixth control signal and transmits a second image frame at the second frame rate. The load switch receives the sixth control signal and controls the output power supply voltage under the control of the sixth control signal. The timing controller receives the second image frame and transmits the data signal corresponding to the second image frame at the second frame rate.

[0024] In conjunction with the second aspect, in one possible implementation, the method further includes: when the frame rate switches from a first frame rate to a second frame rate, the processor sends a seventh control signal. The timing controller receives the seventh control signal and, under the control of the seventh control signal, disables the screen self-refresh (PSR) function.

[0025] A third aspect of this application provides an electronic device, which includes a frame rate switching device and a motherboard, a display driver board, and a display screen connected by a flexible circuit board. The frame rate switching device is as described in the first aspect or any possible implementation thereof. The processor, embedded controller, and load switch in the frame rate switching device are mounted on the motherboard, while the power management integrated circuit and timing controller in the frame rate switching device are mounted on the display driver board. The display screen includes a display driver chip and a screen that are coupled to each other.

[0026] In conjunction with the third aspect, in one possible implementation, the electronic device is a laptop computer.

[0027] A fourth aspect of this application provides a computer-readable storage medium storing a computer program that, when run on an electronic device, causes the electronic device to perform steps in the frame rate switching method as described in the second aspect or any possible implementation thereof.

[0028] A fifth aspect of this application provides a computer program product that, when run on a processor, causes the processor to perform steps in the frame rate switching method as described in the second aspect or any possible implementation thereof.

[0029] The descriptions of the second to fifth aspects in this application can be referenced to the detailed description of the first aspect; and the beneficial effects described in the second to fifth aspects can be referenced to the analysis of the beneficial effects of the first aspect, which will not be repeated here. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of the structure of a laptop computer;

[0031] Figure 2 This is a schematic diagram of the structure of a frame rate switching device provided in an embodiment of this application;

[0032] Figure 3 This is a schematic diagram of another frame rate switching device provided in an embodiment of this application;

[0033] Figure 4 A schematic diagram of another frame rate switching device provided in the embodiments of this application;

[0034] Figure 5 A schematic diagram illustrating a frame rate switching process provided in an embodiment of this application;

[0035] Figure 6 A flowchart illustrating a frame rate switching method provided in an embodiment of this application;

[0036] Figure 7 A flowchart illustrating another frame rate switching method provided in an embodiment of this application;

[0037] Figure 8 A flowchart illustrating yet another frame rate switching method provided in an embodiment of this application;

[0038] Figure 9 A flowchart illustrating another frame rate switching method provided in an embodiment of this application;

[0039] Figure 10 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0040] The following sections will discuss the fabrication and use of various embodiments in detail. However, it should be understood that many applicable inventive concepts provided in this application can be implemented in a variety of specific environments. The specific embodiments discussed are merely illustrative of specific ways of implementing and using this description and technology, and do not limit the scope of this application.

[0041] Unless otherwise defined, all technical terms used herein have the same meaning as commonly known to one of ordinary skill in the art.

[0042] Each circuit or other component may be described or referred to as "for" performing one or more tasks. In this context, "for" is used to imply a structure by indicating that the circuit / component includes a structure (e.g., a circuit system) that performs one or more tasks during operation. Therefore, even when the specified circuit / component is currently inoperable (e.g., not turned on), it can still be referred to as "for performing that task." Circuits / components used with the term "for" include hardware, such as circuits that perform operations.

[0043] The technical solutions in the embodiments of this application will be described below with reference to the accompanying drawings. In this application, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, or B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the related objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, a and b, a and c, b and c, or a, b, and c, where a, b, and c can be single or multiple. In addition, in the embodiments of this application, the words "first," "second," etc., do not limit the quantity or order.

[0044] It should be noted that, in this application, the terms "exemplary" or "for example" are used to indicate that something is being described as an example, illustration, or illustration. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0045] Before introducing the embodiments of this application, the technical terms and background technology involved in this application will be introduced first.

[0046] Frame rate: refers to the number of times a graphics processor can update per second, usually expressed as frames per second (FPS).

[0047] Load switch (LS): Used to turn the power supply on and off, and can also be used to control the on and off of pins, thereby realizing the opening and closing of the power supply.

[0048] Power management integrated circuits (PMICs) are used for automatic identification and adjustment of output voltage, voltage regulation, overcurrent protection, overheat protection, power saving, soft start, ramp-up, and detection. They can improve equipment efficiency and reliability, reduce energy consumption, extend equipment life, and protect equipment from damage.

[0049] Timing controller (TCON): A timing control chip mainly used to control the timing of pixels in a display screen.

[0050] Display Port Configuration Data (DPCD): This is a special data format used to describe the transmission path and configuration information of data in a network. It is mainly used to realize high-speed digital signal processing, such as high-definition video and radar signal processing.

[0051] Link training: The main purpose of link training is to ensure that the signal transmission quality and electrical characteristics between various devices meet the requirements in order to achieve stable data transmission.

[0052] Panel self-refresh (PSR) refers to a display that, when it detects no change in the screen content, stores the content in memory instead of continuously refreshing the screen. When the screen content changes, the display clears the previously stored content, regenerates the new content, and stores it in memory. This allows the display to maintain its display quality without requiring continuous screen refresh.

[0053] Soft screen self-refresh (soft PSR): In this embodiment of the application, soft PSR refers to the timing controller storing an image frame in memory under the control of the processor and continuously sending the data signal corresponding to the image frame.

[0054] Express data path (XDP): It can process network packets and accelerate data transmission, thereby improving system performance and response speed.

[0055] Frame rate switching is a fundamental scenario in dynamic frame rate systems. These systems can be terminal devices, including Windows laptops (hereinafter referred to as laptops), tablets, and mobile phones. The following explanation uses a laptop as an example to illustrate the frame rate switching process in a dynamic frame rate system.

[0056] like Figure 1The diagram shows a schematic of a laptop computer 100, which includes a motherboard 110, a display driver board 120, and a display screen 130 connected by a flexible printed circuit (FPC).

[0057] The motherboard 110 is equipped with a processor 111 and a load switch 112, the display driver board 120 is equipped with a power management integrated circuit 121 and a timing controller 122, and the display screen 130 includes a source driver integrated circuit (SDI) 131 and a screen 132.

[0058] Specifically, the first output terminal of the processor 111 is coupled to the controlled terminal of the load switch 112, the output terminal of the load switch 112 is coupled to the input terminal of the power management integrated circuit 121, and the output terminal of the power management integrated circuit 121 is coupled to the power input terminal of the timing controller 122. The second output terminal of the processor 111 is coupled to the input terminal of the timing controller 122, the output terminal of the timing controller 122 is coupled to the input terminal of the source driver chip 131, and the output terminal of the source driver chip 131 is coupled to the input terminal of the screen 132.

[0059] When the frame rate of the laptop 100 remains constant, the processor 111 sends a control signal to the load switch 112, which outputs a power supply voltage under the control of the control signal. This power supply voltage can be provided by the battery in the laptop 100. The power management integrated circuit 121 receives the power supply voltage and provides a power supply voltage to the timing controller 122 based on the power supply voltage. The processor 111 also sends image frames to the timing controller 122, which generates and sends a data signal to the source driver chip 131 based on the image frames sent by the processor 111. The source driver chip 131 drives the screen 132 to display images based on the data signal.

[0060] When the laptop 100 switches frame rates, the processor 111 stops sending control signals to the load switch 112, causing the load switch 112 to stop outputting power voltage. The power management integrated circuit 121 then cannot continue to supply power voltage to the timing controller 122. Simultaneously, the processor 111 stops sending image frames to the timing controller 122. Because the timing controller 122 cannot receive power voltage and image frames, it cannot generate and send data signals to the source driver chip 131 based on the image frames. This results in a black screen on the display 130 for 1-2 seconds, leading to poor display smoothness and a poor user experience.

[0061] To address the issue of black screens occurring during frame rate switching in the aforementioned dynamic frame rate system, resulting in poor display smoothness and a poor user experience, this application provides a frame rate switching device that prevents black screens during frame rate switching, thereby improving display smoothness and user experience.

[0062] like Figure 2 The diagram shown is a structural schematic of a frame rate switching device 200 provided in an embodiment of this application. The frame rate switching device 200 includes a processor 210, a load switch 220, a power management integrated circuit 230, and a timing controller 240. One end of the load switch 220 is coupled to the processor 210, and the other end of the load switch 220 is coupled to the power management integrated circuit 230. One end of the timing controller 240 is coupled to the processor 210, and the other end of the timing controller 240 is coupled to the power management integrated circuit 230.

[0063] In one possible embodiment, the first output terminal of the processor 210 is coupled to the first controlled terminal of the load switch 220, the output terminal of the load switch 220 is coupled to the input terminal of the power management integrated circuit 230, and the output terminal of the power management integrated circuit 230 is coupled to the power input terminal of the timing controller 240. The second output terminal of the processor 210 is coupled to the input terminal of the timing controller 240, and the first output terminal of the timing controller 240 is coupled to the output terminal of the frame rate switching device 200.

[0064] The load switch 220 controls the output power supply voltage when the frame rate switches from the first frame rate to the second frame rate. The power management integrated circuit 230 receives the power supply voltage and provides a power supply voltage to the timing controller 240 according to the power supply voltage. This embodiment does not limit the specific values ​​of the first and second frame rates.

[0065] Optionally, the first frame rate may be greater than the second frame rate, or the first frame rate may be less than the second frame rate; however, this embodiment does not limit this.

[0066] The processor 210 is used to send a first control signal when the frame rate switches from a first frame rate to a second frame rate.

[0067] In one possible embodiment, the processor 210 is also configured to send an image frame to the timing controller 240 at the first frame rate before the frame rate is switched from the first frame rate to the second frame rate.

[0068] The frame rate can be switched from the first frame rate to the second frame rate by the user specifying the frame rate through software, or by preset the frame rate corresponding to each application software. When the user opens different applications software, the processor 210 can switch the frame rate to the preset frame rate corresponding to the application software.

[0069] The timing controller 240 is used to continuously send the data signal corresponding to the first image frame at the first frame rate under the control of the first control signal.

[0070] Optionally, the first image frame mentioned above is any one of the multiple image frames last received by the timing controller 240 before the frame rate switching, and this embodiment of the application does not limit this.

[0071] For example, the first image frame mentioned above can be any one of the three image frames last received by the timing controller 240 before the frame rate switch.

[0072] In one possible embodiment, the first image frame is the last image frame received by the timing controller 240 before the frame rate switch. Therefore, when the frame rate switch is complete, the second image frame received by the timing controller 240 has good continuity with the first image frame, which can further improve the smoothness of the display and enhance the user experience.

[0073] In one possible embodiment, the processor 210 described above may be a central processing unit (CPU).

[0074] In one possible embodiment, the processor 210 described above may be an x86 processor.

[0075] In one possible embodiment, the first control signal can be an instruction, and the timing controller 240 is used to continuously send the data signal corresponding to the first image frame according to the instruction.

[0076] Optionally, the second output terminal of the processor 210 and the input terminal of the timing controller 240 can be coupled through at least one of the following: inter-integrated circuit (I2C), serial peripheral interface (SPI), auxiliary (AUX) interface, mobile industry processor interface (MIPI), etc. This application embodiment is not limited to this.

[0077] like Figure 2As shown, in one possible embodiment, the output of the frame rate switching device 200 can be coupled to the input of the display screen 300. The display screen 300 may include a display driver chip 310 and a screen 320 coupled to each other, with the input of the display driver chip 310 coupled to the input of the display screen 300. The display driver chip 310 receives data signals output by the timing controller 240 and drives the screen 320 to display images according to these data signals. It is understood that, in the frame rate switching device 200 provided in this application embodiment, during frame rate switching, the timing controller 240 continuously sends data signals corresponding to the first image frame at a first frame rate. The display driver chip 310 continuously drives the screen 320 to display images according to these data signals, thus preventing the screen 320 from going black, thereby improving display smoothness and enhancing the user experience.

[0078] In one possible embodiment, the frame rate switching device 200 and the display screen 300 may communicate using a point-to-point (P2P) protocol to transmit the data signal corresponding to the first image frame.

[0079] In one possible embodiment, the display driver chip 310 described above may include a source driver chip and a gate driver integrated circuit (GTDI).

[0080] Optionally, the screen 320 may be one of the following: liquid crystal display (LCD), active matrix organic light emitting diode (AMOLED), etc. The specific type of the screen 320 is not limited in this application embodiment.

[0081] The frame rate switching device 200 provided in this application embodiment provides power voltage to the power management integrated circuit 230 through the load switch 220 when the frame rate switches from a first frame rate to a second frame rate. The power management integrated circuit 230 then provides power supply voltage to the timing controller 240 according to the power supply voltage to meet the power supply requirements of the timing controller 240. Simultaneously, the processor 210 sends a first control signal, and the timing controller 240, under the control of this first control signal, continuously sends the data signal corresponding to the first image frame at the first frame rate. This first image frame is any one of the multiple image frames last received by the timing controller 240 before the frame rate switch. Therefore, the display driver chip 310 in the display screen 300 can continuously drive the screen 320 to display images according to this data signal, thus preventing the screen 320 from going black, thereby improving display smoothness and enhancing the user experience.

[0082] like Figure 3 As shown, in one possible embodiment, the timing controller 240 includes a memory 241. Specifically, the timing controller 240 is configured to, under the control of a first control signal, store and maintain a first image frame in the memory 241, continuously read the first image frame from the memory 241, and send the data signal corresponding to the first image frame at a first frame rate.

[0083] In one possible implementation, the memory 241 described above can be random access memory (RAM). The specific type of memory 241 is not limited in the embodiments of this application.

[0084] In one possible embodiment, the timing controller 240 may also include more devices, as can be found in the prior art, and will not be described in detail here.

[0085] The frame rate switching device 200 provided in this application embodiment, the timing controller 240 stores the first image frame in the memory 241 and keeps it there, continuously reads the first image frame from the memory 241, and sends the data signal corresponding to the first image frame at the first frame rate, thereby ensuring that the display screen 300 can continuously display images without going black, thus improving display smoothness and user experience.

[0086] When the frame rate switches from the first frame rate to the second frame rate, there are multiple ways to control the output power voltage of the load switch 220. One of these multiple methods can be used, or multiple methods can be used simultaneously. This application embodiment does not limit this. The various implementation methods are described below.

[0087] like Figure 3 As shown, in one possible embodiment, the second output terminal of the timing controller 240 is coupled to the second controlled terminal of the load switch 220. The processor 210 is further configured to send a second control signal when the frame rate switches from a first frame rate to a second frame rate. The timing controller 240 is further configured to receive the second control signal, generate and send a third control signal based on the second control signal. The load switch 220 is further configured to receive the third control signal through the second controlled terminal and control the output power supply voltage under the control of the third control signal.

[0088] In one possible embodiment, the second control signal can be an instruction, which the timing controller 240 decodes to generate a third control signal, which can be a level signal.

[0089] Optionally, the third control signal can be a high-level signal or a low-level signal; this application embodiment does not limit this.

[0090] The frame rate switching device 200 provided in this application embodiment, when switching the frame rate from a first frame rate to a second frame rate, the processor 210 sends a second control signal, and the timing controller 240 generates and sends a third control signal according to the second control signal. The load switch 220 outputs a power supply voltage under the control of the third control signal. Thus, the power management integrated circuit 230 can provide a power supply voltage to the timing controller 240 according to this power supply voltage to meet the power supply requirements of the timing controller 240. The timing controller 240 can continuously send the data signal corresponding to the first image frame at the first frame rate, thereby ensuring that the display screen 300 can continuously display images without going black, thus improving display smoothness and user experience.

[0091] like Figure 4 As shown, in one possible embodiment, the frame rate switching device 200 further includes an embedded controller (EC) 250. One end of the embedded controller 250 is coupled to the processor 210, and the other end of the embedded controller 250 is coupled to the load switch 220.

[0092] In one possible embodiment, the input of the embedded controller 250 is coupled to the third output of the processor 210, and the output of the embedded controller 250 is coupled to the third controlled terminal of the load switch 220.

[0093] The processor 210 is also configured to send a fourth control signal when the frame rate switches from a first frame rate to a second frame rate. The embedded controller 250 is configured to receive the fourth control signal, generate and send a fifth control signal based on the fourth control signal. The load switch 220 is also configured to receive the fifth control signal through a third controlled terminal, and control the output power supply voltage under the control of the fifth control signal.

[0094] In one possible embodiment, the input of the embedded controller 250 can communicate with the processor 210 via an Enhanced Serial Peripheral Interface (eSPI).

[0095] In one possible embodiment, the fourth control signal can be an instruction, which the embedded controller 250 decodes to generate a fifth control signal, which can be a level signal.

[0096] Optionally, the fifth control signal can be a high-level signal or a low-level signal; this application embodiment does not limit this.

[0097] The frame rate switching device 200 provided in this application embodiment, when switching the frame rate from a first frame rate to a second frame rate, the processor 210 sends a fourth control signal, the embedded controller 250 generates and sends a fifth control signal according to the fourth control signal, and the load switch 220 outputs a power supply voltage under the control of the fifth control signal. Thus, the power management integrated circuit 230 can provide a power supply voltage to the timing controller 240 according to this power supply voltage to meet the power supply requirements of the timing controller 240. The timing controller 240 can continuously send the data signal corresponding to the first image frame at the first frame rate, thereby ensuring that the display screen 300 can continuously display images without going black, thus improving display smoothness and user experience.

[0098] In one possible embodiment, when the frame rate switching is complete, the processor 210 is further configured to send a sixth control signal and send a second image frame at the second frame rate. The load switch 220 is further configured to receive the sixth control signal through a first controlled terminal and control the output power supply voltage under the control of the sixth control signal. The timing controller 240 is further configured to receive the second image frame and send the data signal corresponding to the second image frame at the second frame rate.

[0099] Optionally, the second image frame may include one image frame, or it may include multiple image frames; this application embodiment does not limit this.

[0100] Specifically, when the processor 210 detects that the link training between the processor 210 and the timing controller 240 is completed, it can determine that the frame rate switching is complete, send a sixth control signal, and send a second image frame at the second frame rate.

[0101] In one possible embodiment, the sixth control signal described above can be a level signal.

[0102] Optionally, the sixth control signal can be a high-level signal or a low-level signal; this application embodiment does not limit this.

[0103] In one possible embodiment, when the timing controller 240 receives the second image frame, the timing controller 240 may stop reading the first image frame from the memory 241 and stop sending the data signal corresponding to the first image frame. The timing controller 240 and / or the embedded controller 250 may stop sending the above-mentioned control signals (the third control signal and the fifth control signal), and stop controlling the load switch 220 to output the power supply voltage. Instead, the processor 210 sends the sixth control signal to control the load switch 220 to output the power supply voltage.

[0104] The frame rate switching device 200 provided in this application embodiment, when the frame rate switching is completed, the processor 210 sends a sixth control signal. Under the control of the sixth control signal, the load switch 220 continues to output power voltage. The power management integrated circuit 230 can provide power supply voltage to the timing controller 240 according to the power supply voltage to meet the power supply requirements of the timing controller 240. At the same time, the processor 210 sends a second image frame at a second frame rate, and the timing controller 240 sends the data signal corresponding to the second image frame at a second frame rate according to the second image frame, thereby ensuring that the display screen 300 can continuously display images without going black, thus improving display smoothness and user experience.

[0105] In one possible embodiment, processor 210 is further configured to send a seventh control signal when the frame rate switches from a first frame rate to a second frame rate. Timing controller 240 is further configured to receive the seventh control signal and, under the control of the seventh control signal, disable the screen self-refresh (PSR) function.

[0106] Specifically, when the frame rate switches from the first frame rate to the second frame rate, before sending the aforementioned first control signal to the timing controller 240, the processor 210 can first send a seventh control signal to the timing controller 240. The timing controller 240 then disables the screen self-refresh function according to this seventh control signal. Thus, the timing controller 240 gains control over storing image frames in the memory 241, ensuring that under the control of the first control signal, it stores the first image frame in the memory 241. The timing controller 240 can continuously read the first image frame from the memory 241 and send the data signal corresponding to the first image frame at the first frame rate.

[0107] The frame rate switching device 200 provided in this application embodiment includes a processor 210 that sends a seventh control signal when the frame rate switches from a first frame rate to a second frame rate. Under the control of the seventh control signal, the timing controller 240 disables the screen self-refresh (PSR) function. This ensures that, under the control of the first control signal, the timing controller 240 stores the first image frame in the memory 241. The timing controller 240 can continuously read the first image frame from the memory 241 and send the data signal corresponding to the first image frame at the first frame rate. Therefore, the display driver chip 310 in the display screen 300 can continuously drive the screen 320 to display images according to this data signal, preventing the screen 320 from going black, thus improving display smoothness and user experience.

[0108] The above Figures 2-4 The structure of the frame rate switching device 200 provided in the embodiments of this application has been introduced along with related descriptions. For ease of understanding, the specific process of the frame rate switching device 200 provided in the embodiments of this application during the frame rate switching process will be illustrated below.

[0109] like Figure 5 The diagram shown is a flowchart illustrating a frame rate switching process provided in an embodiment of this application. When the frame rate switches from a first frame rate to a second frame rate, for example, when the user switches the frame rate from the first frame rate to the second frame rate by pressing the "Fn+R" key:

[0110] The processor 210 sends a first instruction to the timing controller 240 via I2C, and simultaneously sends a second instruction, causing the load switch 220 to continuously output power voltage. Specifically, the first instruction can be the seventh control signal sent by the processor 210 to the timing controller 240, and the second instruction can be the second control signal sent by the processor 210 to the timing controller 240, or the second instruction can be the fourth control signal sent by the processor 210 to the embedded controller 250.

[0111] The timing controller 240 receives the first instruction and first turns off the PSR via the DPCD according to the first instruction.

[0112] When the processor 210 detects that the PSR is off and the load switch 220 is continuously outputting power supply voltage, it sends a third instruction to the timing controller via I2C; otherwise, it continues detection. Specifically, this third instruction can be the first control signal sent by the processor 210 to the timing controller 240.

[0113] The timing controller 240 receives a third instruction, stores the first image frame in the memory 241 according to the third instruction, and enables soft PSR through XDP, thereby continuously sending the data signal corresponding to the first image frame at the first frame rate.

[0114] The processor 210 calls the application programming interface (API) in the processor 210 to switch the frame rate and stop outputting image frames by pressing the key "Fn+R".

[0115] When the processor 210 detects that the link training between the processor 210 and the timing controller 240 is complete, it outputs the second image frame at the second frame rate.

[0116] When the timing controller 240 receives the second image frame, it first stops sending the data signal corresponding to the first image frame at the first frame rate and automatically exits the soft PSR. Then, it synchronizes the processor 210 and the timing controller 240 to the second frame rate through XDP re-sync (resynchronizing to the new frame rate). Specifically, XDP re-sync causes the processor 210 to send the image frame at the second frame rate, and causes the timing controller 240 to send the data signal corresponding to the image frame at the second frame rate.

[0117] Finally, the processor 210 sends a fourth instruction, which the timing controller 240 receives and, according to the fourth instruction, enables PSR via DPCD to complete the frame rate switching.

[0118] like Figure 6 As shown, this application embodiment also provides a frame rate switching method, which can be applied to the frame rate switching device 200 described above. The frame rate switching method includes steps S601-S604.

[0119] S601. When the frame rate switches from the first frame rate to the second frame rate, the load switch 220 controls the output power supply voltage.

[0120] S602, the power management integrated circuit 230 receives the power supply voltage and provides the power supply voltage to the timing controller 240 according to the power supply voltage.

[0121] S603. When the frame rate switches from the first frame rate to the second frame rate, the processor 210 sends a first control signal.

[0122] S604, under the control of the first control signal, the timing controller 240 continuously sends the data signal corresponding to the first image frame at the first frame rate. The first image frame is any one of the multiple image frames last received by the timing controller before the frame rate switch.

[0123] Optionally, the first image frame mentioned above is any one of the multiple image frames last received by the timing controller 240 before the frame rate switching, and this embodiment of the application does not limit this.

[0124] In one possible implementation, the timing controller 240 includes a memory 241, and the above step S604 includes: under the control of the first control signal, the timing controller 240 stores and holds the first image frame in the memory 241, continuously reads the first image frame from the memory 241, and sends the data signal corresponding to the first image frame at the first frame rate.

[0125] The frame rate switching method provided in this application embodiment, when switching the frame rate from a first frame rate to a second frame rate, provides power voltage to the power management integrated circuit 230 through the load switch 220. The power management integrated circuit 230 then provides power supply voltage to the timing controller 240 according to this power supply voltage to meet the power supply requirements of the timing controller 240. Simultaneously, the processor 210 sends a first control signal, and the timing controller 240, under the control of this first control signal, continuously sends the data signal corresponding to the first image frame at the first frame rate. This first image frame is any one of the multiple image frames last received by the timing controller before the frame rate switch. Therefore, the display driver chip 310 in the display screen 300 can continuously drive the screen 320 to display images according to this data signal, thus preventing the screen 320 from going black, thereby improving display smoothness and enhancing the user experience.

[0126] like Figure 7 As shown, in one possible implementation, the frame rate switching method further includes steps S605-S607. The order of steps S605-S607 and the above steps S601-S604 is not important; for example, they can be executed simultaneously.

[0127] S605. When the frame rate switches from the first frame rate to the second frame rate, the processor 210 sends a second control signal.

[0128] S606, the timing controller 240 receives the second control signal and sends the third control signal.

[0129] S607 and load switch 220 receive a third control signal and control the output power supply voltage under the control of the third control signal.

[0130] The frame rate switching method provided in this application embodiment involves the processor 210 sending a second control signal when the frame rate switches from a first frame rate to a second frame rate. The timing controller 240 generates and sends a third control signal based on this second control signal. The load switch 220 outputs a power supply voltage under the control of the third control signal. Thus, the power management integrated circuit 230 can provide a power supply voltage to the timing controller 240 based on this power supply voltage, meeting the power supply requirements of the timing controller 240. The timing controller 240 can then continuously send the data signal corresponding to the first image frame at the first frame rate, ensuring that the display screen 300 can continuously display images without going black, thereby improving display smoothness and enhancing the user experience.

[0131] like Figure 8As shown, in one possible implementation, the frame rate switching device 200 further includes an embedded controller 250, one end of which is coupled to the processor 210 and the other end of which is coupled to the load switch 220. The frame rate switching method further includes steps S608-S610, which can be performed in any order with the steps S601-S604, for example, they can be executed simultaneously.

[0132] S608. When the frame rate switches from the first frame rate to the second frame rate, the processor 210 sends a fourth control signal.

[0133] S609, the embedded controller 250 receives the fourth control signal and sends the fifth control signal.

[0134] S610 and load switch 220 receive the fifth control signal and control the output power supply voltage under the control of the fifth control signal.

[0135] The frame rate switching method provided in this application embodiment involves the processor 210 sending a fourth control signal when the frame rate switches from a first frame rate to a second frame rate. The embedded controller 250 generates and sends a fifth control signal based on this fourth control signal. The load switch 220 outputs a power supply voltage under the control of the fifth control signal. Thus, the power management integrated circuit 230 can provide a power supply voltage to the timing controller 240 based on this power supply voltage, meeting the power supply requirements of the timing controller 240. The timing controller 240 can then continuously send the data signal corresponding to the first image frame at the first frame rate, ensuring that the display screen 300 can continuously display images without going black, thereby improving display smoothness and enhancing the user experience.

[0136] like Figure 9 As shown, in one possible implementation, when the frame rate switching is completed, steps S611-S613 are included after step S604 above.

[0137] S611, processor 210 sends a sixth control signal and sends a second image frame at a second frame rate.

[0138] S612, the load switch 220 receives the sixth control signal and controls the output power supply voltage under the control of the sixth control signal.

[0139] S613, the timing controller 240 receives the second image frame and sends the data signal corresponding to the second image frame at the second frame rate.

[0140] The frame rate switching method provided in this application embodiment involves the processor 210 sending a sixth control signal upon completion of the frame rate switching. Under the control of this sixth control signal, the load switch 220 continues to output power voltage. The power management integrated circuit 230 can provide power supply voltage to the timing controller 240 according to this power supply voltage to meet the power supply requirements of the timing controller 240. Simultaneously, the processor 210 sends a second image frame at a second frame rate, and the timing controller 240 sends the data signal corresponding to the second image frame at the second frame rate, thereby ensuring that the display screen 300 can continuously display images without going black, thus improving display smoothness and enhancing the user experience.

[0141] like Figure 9 As shown, in one possible implementation, the frame rate switching method further includes steps S614-S615. The order of steps S614-S615 and the above steps S601-S602 is not important; for example, they can be executed simultaneously.

[0142] S614. When the frame rate switches from the first frame rate to the second frame rate, the processor 210 sends a seventh control signal.

[0143] S615, the timing controller 240 receives the seventh control signal and disables the screen self-refresh (PSR) function under the control of the seventh control signal.

[0144] The frame rate switching device 200 provided in this application embodiment includes a processor 210 that sends a seventh control signal when the frame rate switches from a first frame rate to a second frame rate. Under the control of the seventh control signal, the timing controller 240 disables the screen self-refresh (PSR) function. This ensures that, under the control of the first control signal, the timing controller 240 stores the first image frame in the memory 241. The timing controller 240 can continuously read the first image frame from the memory 241 and send the data signal corresponding to the first image frame at the first frame rate. Therefore, the display driver chip 310 in the display screen 300 can continuously drive the screen 320 to display images according to this data signal, preventing the screen 320 from going black, thus improving display smoothness and user experience.

[0145] Based on this, such as Figure 10 As shown in the figure, this application embodiment also provides an electronic device 1000, which includes a frame rate switching device 200 and a motherboard 1100, a display driver board 1200, and a display screen 300 connected by a flexible circuit board. The frame rate switching device 200 has the following structure: Figures 2-4 The structure of the frame rate switching device 200 shown in any of the attached figures.

[0146] The processor 210, embedded controller 250, and load switch 220 in the frame rate switching device 200 are mounted on the motherboard 1100. The power management integrated circuit 230 and timing controller 240 in the frame rate switching device 200 are mounted on the display driver board 1200. The display screen 300 includes a display driver chip 310 and a screen 320 that are coupled to each other.

[0147] In one possible embodiment, the processor 210 described above may be a central processing unit.

[0148] In one possible embodiment, the processor 210 described above may be an x86 processor.

[0149] Optionally, the screen 320 may be of one type, such as a liquid crystal display screen or an active matrix organic light-emitting diode panel. The specific type of the screen 320 is not limited in this embodiment.

[0150] In one possible embodiment, the electronic device 1000 is a laptop computer.

[0151] In one possible embodiment, the frame rate switching device 200 provided in this application embodiment can preset a corresponding frame rate for each upper-layer software or for different application scenarios of the electronic device 1000. The frame rate switching device 200 can automatically switch the frame rate according to the preset frame rate, and there will be no black screen during the frame rate switching process, which can improve the display smoothness and improve the user experience.

[0152] For example, taking a game application with a preset frame rate of 60 frames per second (60FPS) as an example, when a user opens the game application, the electronic device 1000 can switch the frame rate from 30 frames per second (30FPS) to 60FPS, continuously displaying 30FPS image frames during the game application's operation without blacking out the screen. At the same time, since the difference between image frames is small when the game application is open, using the electronic device 1000 provided in this application embodiment, the user perceives a higher level of display smoothness and a better user experience during frame rate switching.

[0153] This application also provides a computer-readable storage medium storing computer-executable instructions. When at least one processor of an electronic device executes the computer-executable instructions, the electronic device performs... Figures 6-9 The steps in the frame rate switching method shown in any of the attached figures.

[0154] This application also provides a computer program product, which, when at least one processor of a device runs the computer program product, enables the device to execute... Figures 6-9 The steps in the frame rate switching method shown in any of the attached figures.

[0155] The descriptions of the frame rate switching device 200 and the display screen 300 provided above can be referenced in the frame rate switching method, electronic device 1000, computer-readable storage medium and computer program product, and will not be repeated here in the embodiments of this application.

[0156] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A frame rate switching device, characterized in that, The device includes a processor, a load switch, a power management integrated circuit, and a timing controller. One end of the load switch is coupled to the processor, and the other end of the load switch is coupled to the power management integrated circuit. One end of the timing controller is coupled to the processor, and the other end of the timing controller is coupled to the power management integrated circuit. The load switch is used to control the output power supply voltage when the frame rate switches from the first frame rate to the second frame rate. The power management integrated circuit is used to receive the power supply voltage and provide a power supply voltage to the timing controller according to the power supply voltage; The processor is configured to send a first control signal when the frame rate switches from the first frame rate to the second frame rate; The timing controller is configured to continuously send data signals corresponding to the first image frame at the first frame rate under the control of the first control signal. The first image frame is any one of the multiple image frames last received by the timing controller before the frame rate switching.

2. The apparatus according to claim 1, characterized in that, The timing controller includes a memory; The timing controller is specifically configured to store and maintain the first image frame in the memory under the control of the first control signal, continuously read the first image frame from the memory, and send the data signal corresponding to the first image frame at the first frame rate.

3. The apparatus according to claim 1 or 2, characterized in that, The timing controller is also coupled to the load switch; The processor is further configured to send a second control signal when the frame rate switches from the first frame rate to the second frame rate; The timing controller is further configured to receive the second control signal and send the third control signal; The load switch is specifically used to receive the third control signal and control the output of the power supply voltage under the control of the third control signal.

4. The apparatus according to any one of claims 1-3, characterized in that, The device further includes an embedded controller, one end of which is coupled to the processor, and the other end of which is coupled to the load switch; The processor is further configured to send a fourth control signal when the frame rate switches from the first frame rate to the second frame rate; The embedded controller is used to receive the fourth control signal and send the fifth control signal; The load switch is specifically used to receive the fifth control signal and control the output of the power supply voltage under the control of the fifth control signal.

5. The apparatus according to any one of claims 1-4, characterized in that, When the frame rate switch is complete: The processor is also configured to send a sixth control signal and send a second image frame at the second frame rate; The load switch is also used to receive the sixth control signal and control the output power voltage under the control of the sixth control signal; The timing controller is further configured to receive the second image frame and send the data signal corresponding to the second image frame at a second frame rate.

6. The apparatus according to any one of claims 1-5, characterized in that, The processor and the timing controller are coupled through at least one of the following: integrated circuit bus I2C, serial peripheral interface SPI, auxiliary AUX interface, and mobile industry processor interface MIPI.

7. The apparatus according to any one of claims 1-6, characterized in that, The processor is further configured to send a seventh control signal when the frame rate switches from the first frame rate to the second frame rate; The timing controller is also used to receive the seventh control signal and disable the screen self-refresh (PSR) function under the control of the seventh control signal.

8. A frame rate switching method, characterized in that, A frame rate switching device comprising a processor, a load switch, a power management integrated circuit, and a timing controller, wherein one end of the load switch is coupled to the processor, the other end of the load switch is coupled to the power management integrated circuit, one end of the timing controller is coupled to the processor, and the other end of the timing controller is coupled to the power management integrated circuit, the method comprising: When the frame rate switches from the first frame rate to the second frame rate, the load switch controls the output power supply voltage; The power management integrated circuit receives the power supply voltage and provides a power supply voltage to the timing controller according to the power supply voltage; When the frame rate switches from the first frame rate to the second frame rate, the processor sends a first control signal; Under the control of the first control signal, the timing controller continuously sends the data signal corresponding to the first image frame at the first frame rate. The first image frame is any one of the multiple image frames last received by the timing controller before the frame rate switch.

9. The method according to claim 8, characterized in that, The timing controller includes a memory, and under the control of the first control signal, the timing controller continuously transmits the data signal corresponding to the first image frame at the first frame rate, including: Under the control of the first control signal, the timing controller stores and holds the first image frame in the memory, continuously reads the first image frame from the memory, and sends the data signal corresponding to the first image frame at the first frame rate.

10. The method according to claim 8 or 9, characterized in that, The method further includes: When the frame rate switches from the first frame rate to the second frame rate, the processor sends a second control signal; The timing controller receives the second control signal and sends the third control signal; The load switch receives the third control signal and controls the output of the power supply voltage under the control of the third control signal.

11. The method according to any one of claims 8-10, characterized in that, The frame rate switching device further includes an embedded controller, one end of which is coupled to the processor, and the other end of which is coupled to the load switch. The method further includes: When the frame rate switches from the first frame rate to the second frame rate, the processor sends a fourth control signal; The embedded controller receives the fourth control signal and sends the fifth control signal; The load switch receives the fifth control signal and controls the output of the power supply voltage under the control of the fifth control signal.

12. The method according to any one of claims 8-11, characterized in that, The method further includes: When the frame rate switching is complete, the processor sends a sixth control signal and sends a second image frame at the second frame rate; The load switch receives the sixth control signal and controls the output power voltage under the control of the sixth control signal; The timing controller receives the second image frame and sends the data signal corresponding to the second image frame at the second frame rate.

13. The method according to any one of claims 8-12, characterized in that, The method further includes: When the frame rate switches from the first frame rate to the second frame rate, the processor sends a seventh control signal; The timing controller receives the seventh control signal and disables the screen self-refresh (PSR) function under the control of the seventh control signal.

14. An electronic device, characterized in that, The electronic device includes a frame rate switching device and a motherboard, a display driver board, and a display screen connected by a flexible circuit board. The frame rate switching device is the frame rate switching device as described in any one of claims 1-7. The processor, embedded controller, and load switch in the frame rate switching device are mounted on the motherboard. The power management integrated circuit and timing controller in the frame rate switching device are mounted on the display screen driver board; The display screen includes a display driver chip and a screen that are coupled to each other.

15. The electronic device according to claim 14, characterized in that, The electronic device is a laptop computer.

16. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when run on an electronic device, causes the electronic device to perform the frame rate switching method as described in any one of claims 8-13.

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