A dual-channel WiFi communication system and method based on FPGA

Abstract

The present invention discloses a dual-channel WiFi communication system and method based on FPGA. The dual-channel WiFi communication system based on FPGA includes a Zynq chip and a dual-channel WiFi chip. The Zynq chip includes a PL end and a PS end. The PS end detects and analyzes the dual-channel WiFi chip, arbitrates the communication signal-to-noise ratio of the dual-channel WiFi chip, selects a link with a high communication noise ratio as a communication link, and then communicates with a host computer system through the PL end. The present invention adopts a dual-channel MIMO-SO WiFi communication mode, that is, one WiFi module is used as a master WiFi, which uses a transceiver mode for communication, and the other WiFi module is used as a slave WiFi, which only receives and shares a configuration signal with the master WiFi, thereby improving the communication quality of the WiFi link and using a dual arbitration master-slave mode to parse and splice WiFi data, thereby improving the WiFi data communication effect. Compared with the FPGA-based WiFi communication system on the market, the present invention has higher communication quality and communication effect.

Description

Technical Field

[0001] The present invention relates to the field of wireless communication technology, and in particular to a two-way WiFi communication system and method based on FPGA. Background Art

[0002] With the development of digital economy, progress in wireless communication technology, popularization of smart devices, rise of Internet of Things, popularity of mobile office, insufficient network coverage, demand for public WiFi and improved security performance, WiFi communication has become an important technology to meet people's access to the Internet anytime and anywhere. In people's daily lives, WiFi provides higher speed, better performance and more secure connection, becoming an indispensable wireless network technology in the digital economy era.

[0003] Although WiFi technology is constantly improving, it is still susceptible to noise interference in practical applications. Interference factors such as signal interference, physical obstacles, and wireless frequency congestion may cause WiFi communication performance to degrade. Summary of the invention

[0004] The purpose of this section is to summarize some aspects of the embodiments of the present invention and briefly introduce some preferred embodiments. Some simplifications or omissions may be made in this section and the specification abstract and the invention title of this application to avoid blurring the purpose of this section, the specification abstract and the invention title, and such simplifications or omissions cannot be used to limit the scope of the present invention.

[0005] Therefore, the object of the present invention is to provide a two-way WiFi communication system and method based on FPGA, which improves the data transmission quality.

[0006] To solve the above technical problems, according to one aspect of the present invention, the present invention provides the following technical solutions:

[0007] A dual-channel WiFi communication system based on FPGA, comprising: a Zynq chip and a dual-channel WiFi chip;

[0008] The Zynq chip includes a PS terminal and a PL terminal, wherein the PS terminal detects and analyzes the dual-channel WiFi chip, arbitrates the communication signal-to-noise ratio of the dual-channel WiFi chip, selects the link with a high signal-to-noise ratio as the communication link, and then communicates with the host computer system through the PL terminal through LVDS;

[0009] The dual-channel WiFi chip includes a WiFi communication arbitration module and a WiFi data analysis and splicing module;

[0010] The WiFi communication arbitration module is used to arbitrate the signal-to-noise ratio of the dual-path WiFi communication signals, and the path with the higher signal-to-noise ratio is used as the main path, and the other path is used as the slave path;

[0011] The WiFi data parsing and splicing module is used to parse the error detection code, checksum, and status field information of the data stored in the dual channels, splice the master and slave channel data, and use WiFi to return a retransmission data frame instruction when the bit error rate is too high.

[0012] As a preferred solution of the FPGA-based dual-channel WiFi communication system described in the present invention, the PS end includes a network transmission module, a WiFi arbitration module, and a DDR cache module;

[0013] The network transmission module is used to cache the data received through the TCP / UDP transmission protocol into the data buffer area;

[0014] The DDR cache module is used to store data transmitted by the network transmission module.

[0015] As a preferred solution of the FPGA-based dual-channel WiFi communication system described in the present invention, the PL end includes an LVDS transmission module and an AXI transmission module;

[0016] The LVDS transmission module is used to store the DDR buffer module data in the FIFO first and then send it to the host computer system via LVDS;

[0017] The AXI transmission module is used to transmit the data in the DDR to the PL end.

[0018] As a preferred solution of the FPGA-based dual-channel WiFi communication system described in the present invention, in the DDR cache module, the data cache area adopts a queue storage structure in a linear table and is implemented through sequential storage logic, and the number of data cache areas is limited by the memory capacity and the size of a single frame of data.

[0019] A method for a two-way WiFi communication system based on FPGA, the specific steps are as follows:

[0020] S1, use dual-channel 2.4GHz WiFi;

[0021] S2. The WiFi communication arbitration module arbitrates the quality of dual-channel WiFi signals and selects the WiFi link with a high signal-to-noise ratio as the main data link. The WiFi data parsing and splicing module parses the main WiFi receiving data. When a bit error is detected, the slave WiFi data is immediately retrieved and spliced ​​into the main data.

[0022] S3, using MIMO-SO WiFi communication mode, that is, one WiFi module is used as the main WiFi, which uses the transceiver mode to communicate, and the other WiFi module is used as the slave WiFi, which only receives the configuration signal shared with the main WiFi.

[0023] S4. The PS detects and analyzes the dual-channel WiFi chip, arbitrates the communication signal-to-noise ratio of the dual-channel WiFi through the WiFi arbitration module, and selects the link with the high signal-to-noise ratio as the communication link;

[0024] S5. During the initialization process, the PS side loads the configuration file content into the cache area. After that, all configuration refresh and read operations rely on the cache area. The cache area adopts a chain storage structure. The PS side changes the content in the chain buffer area according to the configuration instructions, and finally updates the content of the chain buffer area to the configuration file. The PS side restarts the system and then completes the reconfiguration of the WiFi.

[0025] Compared with the prior art, the present invention has the following beneficial effects:

[0026] 1. The present invention adopts a dual-channel MIMO-SO WiFi communication mode, that is, one WiFi module is used as the master WiFi, which uses the transceiver mode to communicate, and the other WiFi module is used as the slave WiFi, which only receives and shares the configuration signal with the master WiFi, thereby improving the communication quality of the WiFi link and using the dual arbitration master-slave mode to parse and splice the WiFi data, thereby improving the WiFi data communication effect. Compared with the FPGA-based WiFi communication system on the market, it has higher communication quality and communication effect.

[0027] 2. In the design of the DDR cache module, the data cache area adopts a queue storage structure in a linear list. This structure is implemented through sequential storage logic. The number of data cache areas is limited by the memory capacity and the size of a single frame of data. This design ensures the best balance between cache efficiency and storage resources. This design choice ensures that the DDR cache module can process data efficiently between different cache areas, while also taking into account the rational use of storage resources and cost-effectiveness. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the present invention will be described in detail below in combination with the accompanying drawings and detailed embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative labor. Among them:

[0029] Figure 1 This is a structural schematic diagram of a dual-channel WiFi communication system based on FPGA of the present invention;

[0030] Figure 2 A two-way WiFi configuration flow chart of a two-way WiFi communication system based on FPGA of the present invention;

[0031] Figure 3 The present invention is a two-way WiFi arbitration flow chart of a two-way WiFi communication system based on FPGA. DETAILED DESCRIPTION

[0032] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0033] Secondly, the present invention is described in detail with reference to schematic diagrams. When describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional diagrams showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0034] In order to make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0035] The present invention provides a two-way WiFi communication system and method based on FPGA, which improves the data transmission quality.

[0036] Example 1

[0037] like Figure 1 As shown, the FPGA-based dual-channel WiFi communication system includes a Zynq chip and a WiFi chip, wherein the Zynq chip includes a PL terminal and a PS terminal, wherein the PL terminal includes an LVDS transmission module and an AXI transmission module, and wherein the PS terminal includes a network transmission module, a WiFi arbitration module, and a DDR cache module. The WiFi arbitration module includes a WiFi communication arbitration module and a WiFi data parsing and splicing module.

[0038] The AXI transmission module is used to transmit the data in the DDR to the PL end.

[0039] The LVDS transmission module stores the DDR buffer module data in the FIFO first and then sends it to the host computer system via LVDS.

[0040] The DDR cache module is used to store data transmitted by the network transmission module. In the design of the DDR cache module, the data cache area adopts a queue storage structure in a linear list. This structure is implemented through sequential storage logic. The number of data cache areas is limited by the memory capacity and the size of a single frame of data. This design ensures the best balance between cache efficiency and storage resources. This design choice ensures that the DDR cache module can efficiently process data between different cache areas, while also taking into account the rational use of storage resources and cost-effectiveness.

[0041] The network transmission module is used to send the data cached in the data cache area to the terminal device via the TCP / UDP (customized by the user through the configuration module) transmission protocol, and to cache the data received via the TCP / UDP (customized by the user through the configuration module) transmission protocol into the data cache area.

[0042] The WiFi communication arbitration module is used to arbitrate the signal-to-noise ratio of dual-path WiFi communication signals, and uses the path with a higher signal-to-noise ratio as the main path and the other path as the slave path.

[0043] The WiFi data parsing and splicing module is used to parse the error detection code, checksum, status field and other information of the data stored in the dual channels, and splice the data of the master and slave channels. When the bit error rate is too high, the WiFi is used to send back the retransmission data frame instruction.

[0044] Example 2

[0045] like Figure 2 and Figure 3 As shown, the present invention also provides a two-way WiFi communication method based on FPGA, which specifically performs the following steps:

[0046] S1, use dual-channel 2.4GHz WiFi;

[0047] S2, the WiFi communication arbitration module arbitrates the quality of dual-channel WiFi signals and selects the WiFi link with a high signal-to-noise ratio as the main data link. The WiFi data parsing and splicing module parses the main WiFi receiving data and immediately retrieves the slave WiFi data when a bit error is detected and splices it into the main data.

[0048] S3, using MIMO-SO WiFi communication mode, that is, one WiFi module is used as the master WiFi, which uses the transceiver mode to communicate, and the other WiFi module is used as the slave WiFi, which only receives the configuration signal shared with the master WiFi;

[0049] S4. The PS detects and analyzes the dual-channel WiFi chip, arbitrates the communication signal-to-noise ratio of the dual-channel WiFi through the WiFi arbitration module, and selects the link with the high signal-to-noise ratio as the communication link;

[0050] S5. During the initialization process, the PS side loads the configuration file content into the cache area. After that, all configuration refresh and read operations rely on the cache area. The cache area adopts a chain storage structure. The PS side changes the content in the chain buffer area according to the configuration instructions, and finally updates the content of the chain buffer area to the configuration file. The PS side restarts the system and then completes the reconfiguration of the WiFi.

[0051] Although the present invention has been described above with reference to the embodiments, various modifications may be made thereto and parts thereof may be replaced by equivalents without departing from the scope of the present invention. In particular, as long as there is no structural conflict, the various features in the embodiments disclosed in the present invention may be used in combination with each other in any manner, and the fact that these combinations are not exhaustively described in this specification is only for the sake of omitting space and saving resources. Therefore, the present invention is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. A two-way WiFi communication system based on FPGA, characterized in that: include: Zynq chip and dual-channel WiFi chip; The Zynq chip includes a PL terminal and a PS terminal, wherein the PS terminal detects and analyzes the dual-channel WiFi chip, arbitrates the communication signal-to-noise ratio of the dual-channel WiFi chip signal, selects the link with a high communication signal-to-noise ratio as the communication link, and then communicates with the host computer system through the PL terminal; The WiFi arbitration module includes a WiFi communication arbitration module and a WiFi data analysis and splicing module; The WiFi communication arbitration module is used to arbitrate the signal-to-noise ratio of the dual-channel WiFi communication signal, and the channel with the higher signal-to-noise ratio is used as the main channel, using the transceiver mode for communication, and the other channel is the slave channel, which only receives the configuration signal shared with the main WiFi; The WiFi data parsing and splicing module is used to parse the error detection code, checksum, and status field information of the data stored in the two channels. When a certain bit error is detected, the slave WiFi data is immediately retrieved to splice the master and slave channel data. When the bit error rate is too high, the WiFi is used to send back the retransmission data frame instruction.

2. The FPGA-based two-way WiFi communication system according to claim 1, characterized in that: The PS end includes a network transmission module, a WiFi arbitration module, and a DDR cache module; The network transmission module is used to cache the data received through the TCP / UDP transmission protocol into the data buffer area; The DDR cache module is used to store data transmitted by the network transmission module.

3. The FPGA-based two-way WiFi communication system according to claim 1, characterized in that: The PL end includes an LVDS transmission module and an AXI transmission module; The LVDS transmission module is used to store the DDR buffer module data in the FIFO first and then send it to the host computer system via LVDS; The AXI transmission module is used to transmit the data in the DDR to the PL end.

4. The FPGA-based two-way WiFi communication system according to claim 2, characterized in that: In the DDR cache module, the data cache area adopts a queue storage structure in a linear table and is implemented through sequential storage logic. The number of data cache areas is limited by the memory capacity and the size of a single frame of data.

5. A method for a two-way WiFi communication system based on FPGA as claimed in any one of claims 1 to 4, characterized in that: The specific steps are as follows: S1, use dual-channel 2.4GHz WiFi; S2, the WiFi communication arbitration module arbitrates the quality of dual-channel WiFi signals and selects the WiFi link with a high signal-to-noise ratio as the main data link. The WiFi data parsing and splicing module parses the WiFi receiving data on the main channel. When a bit error is detected, the slave WiFi data is immediately retrieved and the data of the main and slave channels are spliced. When the bit error rate is too high, the WiFi is used to send back the retransmission data frame instruction. S3, using MIMO-SO WiFi communication mode, that is, one WiFi module acts as the master WiFi, which uses the transceiver mode to communicate, and the other WiFi module acts as the slave WiFi, which only receives and shares the configuration signal with the master WiFi; S4. The PS detects and analyzes the dual-channel WiFi chip, arbitrates the communication signal-to-noise ratio of the dual-channel WiFi through the WiFi arbitration module, and selects the link with the high signal-to-noise ratio as the communication link; S5. During the initialization process, the PS side loads the configuration file content into the cache area. After that, all configuration refresh and read operations rely on the cache area. The cache area adopts a chain storage structure. The PS side changes the content in the chain buffer area according to the configuration instructions, and finally updates the content of the chain buffer area to the configuration file. The PS side restarts the system and then completes the reconfiguration of the WiFi.

Images