Semiconductor structure manufacturing method and structure, memory

Abstract

The disclosed embodiments relate to the field of semiconductors and provide a method for fabricating a semiconductor structure, a structure thereof, and a memory device. The method comprises: providing a substrate; forming an N-layer stacked structure on the substrate, wherein each stacked structure in the N-layer stacked structures includes an insulating layer and a conductive layer; forming a mask layer including N openings; performing M etching processes to form grooves, each groove exposing a different conductive layer of the stacked structure, wherein the first M-1 etching processes etch the stacked structure along at least two openings, and wherein two adjacent etching processes etch the stacked structure along openings that are partially identical or completely different. The etching process comprises: forming a photoresist layer located on a top surface of the mask layer, the photoresist layer covering a portion of the openings, etching the stacked structure along the openings exposed by the photoresist layer to expose the top surface of the conductive layer, where M is a positive integer less than N; and forming a conductive plug, wherein the conductive plug completely fills the groove. This can reduce the number of etching processes.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductors, and in particular to a method for manufacturing a semiconductor structure, a structure thereof, and a memory. Background Art

[0002] Memory is a storage component used to store programs and various data. Random Access Memory (RAM) used in general computer systems can be divided into two types: Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM). DRAM is a commonly used semiconductor memory device in computers and is composed of many repeated storage cells.

[0003] A memory cell typically includes a capacitor and a transistor. The drain of the transistor is connected to a bit line structure, and the source is connected to a capacitor. The capacitor includes a capacitor contact structure and a capacitor. The word line structure of the memory cell can control the opening or closing of the channel region of the transistor, thereby reading the data information stored in the capacitor through the bit line structure, or writing the data information into the capacitor for storage through the bit line structure.

[0004] Currently, there is a problem of complex process when forming a conductive plug for transmitting a signal to a bit line structure. Summary of the Invention

[0005] The embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, which can at least reduce the process steps for forming a conductive plug.

[0006] According to some embodiments of the present disclosure, on one hand, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, comprising: providing a substrate; forming an N-layer stacked structure on the substrate, wherein each stacked structure in the N-layer stacked structures includes an insulating layer and a conductive layer located on a top surface of the insulating layer, and N is a positive integer greater than or equal to 8; forming a mask layer, wherein the mask layer is located on the stacked structure at the top layer, and the mask layer includes N openings spaced apart along a first direction; performing M etching processes to form a plurality of grooves, each of the grooves exposing a different conductive layer of the stacked structure, the first M-1 etching processes etches the stacked structure along at least two of the openings, and two adjacent etching processes etch the stacked structure along partially identical or completely different openings, the etching process comprising: forming a photoresist layer, wherein the photoresist layer is located on a top surface of the mask layer, the photoresist layer covers a portion of the openings, and the stacked structure is etched along the openings exposed by the photoresist layer to expose the top surface of the conductive layer, and M is a positive integer less than N; forming a conductive plug, wherein the conductive plug fills the groove.

[0007] In some embodiments, N layers of the stacked structure are formed on the substrate, and the N layers of the stacked structure are divided into: a first stacked structure, a second stacked structure, and an Nth stacked structure along a direction away from the substrate toward a direction close to the substrate; the N openings of the mask layer are divided into a first opening, a second opening, and an Nth opening along the first direction; and before performing the etching process, the mask layer is further divided into n partitions, each of which includes 8 openings; the n partitions are divided into a first sub-partition, a second sub-partition, and an nth sub-partition along the first direction; the first sub-partition includes a first opening, a second opening, and an eighth opening; the nth sub-partition includes an Nth opening, a second opening, and an eighth opening; 7 openings, N-6 openings, and up to the N opening, wherein N is greater than or equal to 8, and N is an integer multiple of 8, and performing M etching processes to form a plurality of grooves includes: performing m etching processes simultaneously in the first sub-division to the n-th sub-division to respectively expose the conductive layers of the first stacking structure to the eighth stacking structure in the first sub-division to the n-th sub-division; repeating the covering etching process until the conductive layers of the first stacking structure to the N stacking structure are respectively exposed, and the covering etching process includes: covering at least one sub-division from the first sub-division to the n-th sub-division, and etching downward the uncovered sub-division.

[0008] In some embodiments, performing m etching processes in the first sub-division includes: performing a first etching process, wherein the first etching process etches the stack structure along the first opening to the fourth opening to expose the top surface of the conductive layer of the fourth stack structure; performing a second etching process, wherein the second etching process etches the stack structure along the first opening, the second opening, the fifth opening and the sixth opening to expose the top surfaces of the conductive layers of the sixth stack structure and the second stack structure; performing a third etching process, wherein the third etching process etches the stack structure along the first opening, the third opening, the fifth opening and the seventh opening to expose the top surfaces of the conductive layers of the seventh stack structure, the fifth stack structure, the third stack structure and the first stack structure; performing a fourth etching process, wherein the fourth etching process etches the stack structure using the mask layer as a mask to expose the top surfaces of the conductive layers of the first stack structure to the eighth stack structure.

[0009] In some embodiments, the first etching process includes: forming a first photoresist layer, the first photoresist layer divides the mask layer into a first covering area and a first exposed area, the first exposed area includes the first opening to the fourth opening, the first covering area includes the fifth opening to the eighth opening, and the stacked structure is etched using the first photoresist layer and the mask layer as a mask to expose the top surface of the conductive layer of the fourth stacked structure; the second etching process includes: forming a second photoresist layer, the second photoresist layer divides the mask layer into a second covering area and a second exposed area, the second covering area includes the third opening, the fourth opening, the seventh opening and the eighth opening, the second exposed area includes the first opening, the second opening, the fifth opening and the The sixth opening, using the second photoresist layer and the mask layer as a mask to etch the stack structure to expose the top surface of the conductive layer of the sixth stack structure and the second stack structure; the third etching process includes: forming a third photoresist layer, the third photoresist layer divides the mask layer into a third covering area and a third exposed area, the third covering area includes the second opening, the fourth opening, the sixth opening and the eighth opening, the third exposed area includes the first opening, the third opening, the fifth opening and the seventh opening, using the third photoresist layer and the mask layer as a mask to etch the stack structure to expose the top surface of the conductive layer of the seventh stack structure, the fifth stack structure, the third stack structure and the first stack structure.

[0010] In some embodiments, the repeated masking and etching process includes: masking multiple sub-partitions from the first sub-partition to the nth sub-partition, exposing any sub-partition, and etching the stacking structure along the opening of the exposed sub-partition, and the number of layers of the etched stacking structure is an integer multiple of 8.

[0011] In some embodiments, the repeated capping etching process includes: the subsequent capping etching process covers one more sub-region than the previous capping etching process, and the number of layers of the stacked structure etched by each capping etching process is 8.

[0012] In some embodiments, N is greater than 8, and N is not an integer multiple of 8. Before performing the etching process, the method further includes: dividing the mask layer into n partitions, the partitions are divided into n-1 first partitions and 1 second partition, the first partition includes 8 openings, and the second partition includes openings with a remainder of N / 8. The difference in the number of layers etched by the etching process between different first partitions as a whole is an integer multiple of 8, where n is N / 8 rounded up.

[0013] In some embodiments, after each etching process and before the next etching process, the method further includes: forming a filling layer, wherein the filling layer fills the recess formed after the etching process.

[0014] In some embodiments, before forming the mask layer, the method further includes: forming an isolation layer, wherein the isolation layer is located on the top surface of the stacked structure, and the material of the isolation layer is the same as that of the insulating layer.

[0015] According to some embodiments of the present disclosure, on the other hand, the embodiments of the present disclosure further provide a semiconductor structure, including: a substrate; an N-layer stacking structure, wherein the N-layer stacking structure is located on the top surface of the substrate, and each stacking structure in the N-layer stacking structure includes an insulating layer and a conductive layer located on the top surface of the insulating layer, and N is a positive integer greater than or equal to 8; a plurality of conductive plugs arranged at intervals along a first direction, each of the plurality of conductive plugs is in contact with and connected to the conductive layer in different stacking structures, the top surface of the conductive plug is higher than the top surface of the stacking structure, and along the first direction, the height of the conductive plug shows a non-increasing or non-decreasing trend.

[0016] In some embodiments, N is an integer multiple of 8, and along the first direction, the semiconductor structure is divided into n partitions, the height of the conductive plug in each partition varies irregularly, and the change trend of the conductive plug in each partition is the same, where n=N / 8.

[0017] In some embodiments, N is not an integer multiple of 8. Along the first direction, the semiconductor structure is divided into n-1 first partitions and 1 second partition. The heights of the conductive plugs in the first partitions and the second partitions vary irregularly, and the change trend of the conductive plugs in each first partition is the same, where n is N divided by 8 rounded up.

[0018] In some embodiments, N is an integer multiple of 8, and along the first direction, the semiconductor structure is divided into n partitions, the height of the conductive plugs in each partition varies irregularly, and the change trends of the conductive plugs in each partition are partially the same or completely different, where n=N / 8.

[0019] In some embodiments, N is not an integer multiple of 8. Along the first direction, the semiconductor structure is divided into n-1 first partitions and 1 second partition. The height of the conductive plug in each first partition varies irregularly, and the change trend of the conductive plug in each first partition is partially the same or completely different, where n is N divided by 8 rounded up.

[0020] According to some embodiments of the present disclosure, another aspect of the present disclosure further provides a memory, comprising the semiconductor structure as described above.

[0021] The technical solution provided by the embodiments of the present disclosure has at least the following advantages: by forming a stacked structure, and the number of stacked structures is equal to the number of conductive plugs that need to be formed subsequently, by forming a mask layer, and the openings on the mask layer locate the positions of the conductive plugs that are subsequently formed, and the mask layer also serves as a mask for subsequent etching of the stacked structure, by performing M etching processes to form grooves that expose different conductive layers, each conductive layer is exposed, thereby providing a process basis for subsequently forming conductive plugs connected to different conductive layers, thereby enabling signal transmission to each conductive layer or signal reception from each conductive layer. By etching the stacked structure along at least two openings in the first M-1 etching processes, the etching process can be shared during the process of etching and exposing different conductive layers, thereby reducing the number of etching processes. Reducing the number of etching processes can simultaneously reduce the number of mask layers, thereby reducing the process difficulty of the semiconductor structure manufacturing method. By etching the stacked structure along partially identical or completely different openings in two adjacent etching processes, the etching process can be controlled to expose different conductive layers, thereby achieving the purpose of exposing each conductive layer, facilitating the subsequent formation of a conductive plug and a corresponding conductive layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0023] Figures 1 to 7 A schematic structural diagram corresponding to each step of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0024] Figure 8 A schematic structural diagram of a semiconductor structure provided in one embodiment of the present disclosure;

[0025] Figure 9 A schematic structural diagram of another semiconductor structure provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0026] As can be seen from the background technology, when forming a stacked conductive plug, for example, when forming 8 conductive plugs with different thicknesses, 8 masks need to be formed and 8 etchings are performed to form 8 grooves with different depths, and then the conductive plugs that fill the grooves are formed.

[0027] The present disclosure provides a method for fabricating a semiconductor structure. A stacked structure is formed, and the number of stacked structures is equal to the number of conductive plugs that need to be formed subsequently. A mask layer is formed, and the openings on the mask layer locate the positions of the conductive plugs to be formed subsequently. The mask layer also serves as a mask for subsequent etching of the stacked structure. M etching processes are performed to form grooves that expose different conductive layers, thereby exposing each conductive layer. This provides a process foundation for subsequently forming conductive plugs connected to different conductive layers, thereby enabling signal transmission to or reception from each conductive layer. The stacked structure is etched along at least two openings in the first M-1 etching processes, allowing a shared etching process to be used in the process of etching and exposing different conductive layers, thereby reducing the number of etching processes. Reducing the number of etching processes can simultaneously reduce the number of mask layers, thereby reducing the process difficulty of the semiconductor structure fabrication method. Etching the stacked structure along partially identical or completely different openings in two adjacent etching processes can control the etching process to expose different conductive layers, thereby achieving the purpose of exposing each conductive layer and facilitating the connection between a subsequently formed conductive plug and a corresponding conductive layer.

[0028] The following describes various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to facilitate a better understanding of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can still be implemented.

[0029] refer to Figures 1 to 7 , Figures 1 to 7 A schematic structural diagram corresponding to each step of a method for manufacturing a semiconductor structure provided in an embodiment of the present disclosure.

[0030] In some embodiments, a method for manufacturing a semiconductor structure may include: providing a substrate 100 .

[0031] In some embodiments, a method for manufacturing a semiconductor structure may include: forming N-layer stacked structures 110 on a substrate 100, wherein each stacked structure 110 in the N-layer stacked structures 110 includes an insulating layer 111 and a conductive layer 112 located on the top surface of the insulating layer 111, and N is a positive integer greater than 1.

[0032] In some embodiments, the method for manufacturing a semiconductor structure may include: forming a mask layer 120 , where the mask layer 120 is located on the top stack structure 110 , and the mask layer 120 includes N openings 121 arranged at intervals along a first direction X.

[0033] In some embodiments, a method for manufacturing a semiconductor structure may include: performing M etching processes to form a plurality of grooves 130, each groove 130 exposing a different conductive layer 112 of the stacked structure 110, the first M-1 etching processes all etches the stacked structure 110 along at least two openings 121, and the two adjacent etching processes etches the stacked structure 110 along partially identical or completely different openings 121, the etching process includes: forming a photoresist layer 140, the photoresist layer 140 is located on the top surface of the mask layer 120, the photoresist layer 140 covers part of the openings 121, and the stacked structure 110 is etched along the openings 121 exposed by the photoresist layer 140 to expose the top surface of the conductive layer 112, and M is a positive integer less than N.

[0034] In some embodiments, the method for manufacturing a semiconductor structure may further include: forming a conductive plug 150 , wherein the conductive plug 150 completely fills the groove 130 .

[0035] By forming a stacked structure 110, and the number of stacked structures 110 is also the number of conductive plugs 150 that need to be formed subsequently, by forming a mask layer 120, and the opening 121 on the mask layer 120 locates the position of the conductive plug 150 to be formed subsequently, and the mask layer 120 also serves as a mask for subsequent etching of the stacked structure 110, by performing M etching processes to form grooves 130 that expose different conductive layers 112, thereby exposing each conductive layer 112, thereby providing a process basis for the subsequent formation of conductive plugs 150 connected to different conductive layers 112, thereby realizing the transmission of signals to each conductive layer 112 or the reception of signals from each conductive layer 112. By etching the stacked structure 110 along at least two openings 121 through the first M-1 etching treatments, the etching process can be shared in the process of etching to expose different conductive layers 112, thereby reducing the number of etching treatments. Reducing the number of etching treatments can simultaneously reduce the number of mask layers 120, thereby reducing the process difficulty of the semiconductor structure manufacturing method. By etching the stacked structure 110 along partially identical or completely different openings 121 through two adjacent etching treatments, the etching treatment can be controlled to expose different conductive layers 112, thereby achieving the purpose of exposing each conductive layer 112, which is convenient for the subsequent formation of a conductive plug 150 corresponding to a conductive layer 112 for connection.

[0036] It should be noted that, the partially identical here means that the next etching process and the previous etching process are performed along partially identical openings and partially different openings, and the completely different here means that the next etching process and the previous etching process are performed along completely different openings. For example, the opening 121 is defined as being divided into the first opening and the second opening to the eighth opening along the first direction X. The partially identical here means that the previous etching process etches the stacked structure 110 along the first opening to the fourth opening, and the next etching process etches the stacked structure along the third opening to the sixth opening. The completely different here means that the previous etching process etches the stacked structure 110 along the first opening to the fourth opening, and the next etching process etches the stacked structure along the fifth opening to the eighth opening.

[0037] In some embodiments, the material of substrate 100 may include a semiconductor material, such as, but not limited to, silicon. In some embodiments, substrate 100 may include a base semiconductor, a compound semiconductor, or an alloy semiconductor. For example, base semiconductors include germanium; compound semiconductors include silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or Group III-V semiconductor materials; and alloy semiconductors include silicon germanium, silicon germanium carbide, germanium-tin, silicon-germanium-tin, gallium arsenic phosphide, gallium indium phosphide, gallium indium arsenide, indium gallium arsenide, aluminum indium arsenide, and / or aluminum gallium arsenide. In some embodiments, substrate 100 may also be a silicon-on-insulator (SOI) structure, a silicon-germanium-on-insulator (SGI) structure, a germanium-on-insulator (GOI) structure, or a combination thereof.

[0038] In addition, the substrate 100 can be doped according to design requirements (e.g., a P-type substrate or an N-type substrate). In some embodiments, the substrate 100 can be doped with P-type dopant ions (e.g., boron ions, aluminum ions) or N-type dopant ions (e.g., phosphorus ions, arsenic ions).

[0039] In some embodiments, the insulating layer 111 of the stacked structure 110 can isolate the conductive layer 112 and can also support the conductive layer 112, thereby preventing the conductive layer 112 from being deformed during the etching process and improving the reliability of the formed semiconductor structure. The insulating layer 111 can also reduce the etching rate to avoid etching too fast in each etching process, resulting in excessive etching of the conductive layer 112, thereby avoiding the inability to expose each conductive layer 112.

[0040] In some embodiments, the insulating layer 111 may be made of silicon nitride or silicon oxide.

[0041] In some embodiments, the conductive layer 112 may serve as a bit line structure, or other structures that need to receive signals or transmit signals.

[0042] In some embodiments, the conductive layer 112 may be made of silicon or other conductive materials.

[0043] In some embodiments, the material of the mask layer 120 can be an insulating material, such as silicon nitride or silicon oxide, etc. It only needs to satisfy the requirement that the material of the mask layer 120 is different from the material of the insulating layer 111, thereby avoiding damage to the mask layer 120 during the etching process of the stacked structure 110, thereby avoiding deformation of the opening on the mask layer, and thus improving the reliability of the semiconductor structure manufacturing method.

[0044] In some embodiments, the method of forming the mask layer 120 may be: forming an initial mask layer, the initial mask layer being located on the top stacking structure, etching the initial mask layer according to a pre-set opening position to form N openings spaced apart along a first direction, and the remaining initial mask layer serving as the mask layer 120.

[0045] In some embodiments, N is greater than or equal to 8, and N is an integer multiple of 8. Before the etching process, the mask layer 120 is further divided into n partitions, each partition includes 8 openings 121, and the difference between the number of layers etched by the etching process between each partition as a whole is an integer multiple of 8, where n = N / 8.

[0046] Taking N as 24 as an example, that is to say, before the etching process, the mask layer 120 is divided into 3 areas. By partitioning the mask layer, the entire etching process can be regarded as being performed in zones. For example, the conductive layer 112 to be exposed in the first sub-zone is the conductive layer 112 of the first to eighth layers in the direction away from the substrate 100 toward the substrate 100, the conductive layer 112 to be exposed in the second sub-zone is the conductive layer 112 of the ninth to sixteenth layers in the direction away from the substrate 100 toward the substrate 100, and the conductive layer 112 to be exposed in the third sub-zone is the conductive layer 112 of the seventeenth to twenty-fourth layers in the direction away from the substrate 100 toward the substrate 100. The partitioning here may include: the first partitioning, which is to complete the etching of the first sub-zone first, and then perform the etching of the second sub-zone, and then perform the etching of the third sub-zone; the second partitioning The second partitioning is to simultaneously etch the first sub-partition, the second sub-partition and the third sub-partition, firstly, according to the process of the first sub-partition, the three sub-partitions are etched synchronously, then the first sub-partition is covered, the second sub-partition and the third sub-partition are etched downward as a whole to form an eight-layer stacked structure 110, then the second sub-partition is also covered, and the third sub-partition is etched downward as a whole to form an eight-layer stacked structure 110, so that the first to twenty-fourth conductive layers can be exposed respectively; the third partitioning is carried out, and the third partitioning is to simultaneously etch the first sub-partition, the second sub-partition and the third sub-partition, first, according to the process of the first sub-partition, the three sub-partitions are etched synchronously, then the first sub-partition and the third sub-partition are covered, the second sub-partition is etched downward as a whole to form an eight-layer stacked structure 110, then the first sub-partition and the second sub-partition are covered, and the third sub-partition is etched downward as a whole to form a sixteen-layer stacked structure 110.

[0047] It can be understood that in the above-mentioned first partitioning scheme, the more layers of the stacked structure 110, the more etching times are performed. However, in the first partitioning scheme, one partition is processed at a time, and the number of grooves formed each time is the least; in the second and third partitioning schemes, different partitions share the etching process for etching and exposing the first to eighth conductive layers, thereby reducing the number of etching times, and in the second partitioning scheme, only eight layers of the stacked structure are etched at most each time. The fewer the number of etched layers, the better the stability of the etching process. In the third partitioning scheme, etching is performed on different partitions after completing the common etching process.

[0048] It should be noted that the above-mentioned etching solution can be divided into zones according to the first direction X, or can be randomly arranged, so as to expose the first to Nth conductive layers 112 .

[0049] In some embodiments, an N-layer stacked structure 110 is formed on a substrate 100, where N is an integer multiple of 8, and the N-layer stacked structure 110 is divided into: a first stacked structure, a second stacked structure, and an N-th stacked structure along a direction away from the substrate 100 toward a direction close to the substrate 100; the N openings 121 of the mask layer 120 are divided into a first opening, a second opening, and an N-th opening along a first direction X; the n partitions are divided into a first sub-partition, and an n-th sub-partition along the first direction X; the first sub-partition includes a first opening, a second opening, and an eighth opening; the n-th sub-partition includes an N-7 opening, an N-6 opening, and an N-th opening; performing M etching processes to form a plurality of grooves 130 includes: performing m etching processes in the first sub-partition to the n-th sub-partition, respectively, to expose the conductive layers 112 of the first stacked structure, the second stacked structure, and the N-th stacked structure in the first sub-partition, where M=n multiplied by m.

[0050] It can be understood that the method of M=n multiplied by m is the number of etching times required for the first partitioning scheme mentioned above. Compared with the related technology of exposing one groove each time by etching, the first partitioning scheme also reduces the number of etching times and reduces the process steps of the entire semiconductor structure manufacturing method.

[0051] refer to Figures 2 to 6 In some embodiments, performing m etching processes in the first sub-division includes: performing a first etching process, etching the stack structure 110 along the first opening to the fourth opening to expose the top surface of the conductive layer 112 of the fourth stack structure; performing a second etching process, etching the stack structure 110 along the first opening, the second opening, the fifth opening and the sixth opening to expose the top surfaces of the conductive layer 112 of the sixth stack structure and the second stack structure; performing a third etching process, etching the stack structure 110 along the first opening, the third opening, the fifth opening and the seventh opening to expose the top surfaces of the conductive layer 112 of the seventh stack structure, the fifth stack structure, the third stack structure and the first stack structure; performing a fourth etching process, etching the stack structure 110 using the mask layer 120 as a mask to expose the top surfaces of the conductive layer 112 of the first stack structure to the eighth stack structure.

[0052] In other words, in the first etching process, the conductive layer 112 of the fourth stacking structure is exposed at the positions of the first opening to the fourth opening. In the second etching process, the two-layer stacking structure is etched along the first opening, the second opening, the fifth opening and the sixth opening in a direction close to the substrate 100. At this time, the conductive layer 112 of the sixth stacking structure is exposed at the positions of the first opening and the second opening, the conductive layer 112 of the fourth stacking structure is exposed at the positions of the third opening and the fourth opening, the conductive layer 112 of the second stacking structure is exposed at the positions of the fifth opening and the sixth opening, and the conductive layer 112 of the seventh opening and the eighth opening is not exposed. In the third etching process, a layer is etched along the first opening, the third opening, the fifth opening and the seventh opening in a direction close to the substrate 100. The stacking structure 110 is etched. At this time, the position of the first opening exposes the conductive layer 112 of the seventh stacking structure, the position of the second opening exposes the conductive layer 112 of the sixth stacking structure, the position of the third opening exposes the conductive layer 112 of the fifth stacking structure, the position of the fourth opening exposes the conductive layer 112 of the fourth stacking structure, the position of the fifth opening exposes the conductive layer 112 of the third stacking structure, the position of the sixth opening exposes the conductive layer 112 of the second stacking structure, the position of the seventh opening exposes the conductive layer 112 of the first stacking structure, and the position of the eighth opening does not expose the conductive layer 112. In the fourth etching process, the stacking structure 110 is etched using the mask layer 120 as a mask, so as to expose the conductive layers 112 of the first to eighth stacking structures respectively.

[0053] It is understood that, by performing the above-described process, eight different conductive layers 112 can be exposed through four etching processes, thereby reducing the number of process steps in the entire semiconductor structure manufacturing method and reducing the number of mask layers 120 compared to related art.

[0054] It should be noted that in the above description, grooves 130 with decreasing depths along the first direction X are formed in the first sub-division. By adjusting the positions of the openings corresponding to the etching process, grooves with irregular depths in the first direction X can be achieved. For example, the treatment of the first opening and the second opening in the above embodiment can be swapped with the treatment of the fifth opening and the sixth opening, so that grooves with irregular depths in the first direction X can be obtained. The formation process will not be repeated here.

[0055] In some embodiments, the above description describes the etching process of the first sub-partition, and the second sub-partition to the nth sub-partition can also perform the process described above, and then continue to etch downward the stacked structure 110 according to the conductive layer 112 of the stacked structure that needs to be exposed, that is, different conductive layers 112 can be exposed.

[0056] In some embodiments, the first etching process includes: forming a first photoresist layer 160, the first photoresist layer 160 divides the mask layer 120 into a first covering area 122 and a first exposed area 123, the first covering area 122 includes the fifth opening to the eighth opening, the first exposed area 123 includes the first opening to the fourth opening, and the stacked structure 110 is etched using the first photoresist layer 160 and the mask layer 120 as a mask to expose the top surface of the conductive layer 112 of the fourth stacked structure; the second etching process includes: forming a second photoresist layer 170, the second photoresist layer 170 divides the mask layer 120 into a second covering area 124 and a second exposed area 125, the second covering area 124 includes the third opening, the fourth opening, the seventh opening and the eighth opening, and the second exposed area 125 includes the first opening, the second opening, the fourth opening, the seventh opening and the eighth opening. The stacked structure 110 is etched with the second photoresist layer 170 and the mask layer 120 as a mask to expose the top surfaces of the sixth stacked structure and the conductive layer 112 of the second stacked structure; the third etching process includes: forming a third photoresist layer 180, the third photoresist layer 180 divides the mask layer 120 into a third covering area 126 and a third exposed area 127, the third covering area 126 includes the second opening, the fourth opening, the sixth opening and the eighth opening, the third exposed area 127 includes the first opening, the third opening, the fifth opening and the seventh opening, and the stacked structure 110 is etched with the third photoresist layer 180 and the mask layer 120 as a mask to expose the top surfaces of the seventh stacked structure, the fifth stacked structure, the third stacked structure and the conductive layer 112 of the first stacked structure.

[0057] In other words, the openings 121 of the mask layer 120 are covered by forming a photoresist layer 140 on the mask layer 120, and part of the openings 121 are exposed, so that the stacked structure 110 is etched using the photoresist layer 140 and the mask layer 120 as masks, and then the stacked structure 110 is etched along which opening or openings, thereby realizing exposure of different conductive layers 112 by the grooves 130 formed by etching at different openings.

[0058] In some embodiments, the m etching processes performed in the nth sub-partition can be similar to the process described in the etching process performed on the first sub-partition in the above embodiment. The difference is that the etching performed in the nth sub-partition will continue to etch the stacked structure along different openings toward the direction close to the substrate 100, and the number of layers of the etched stacked structure 110 is an integer multiple of 8.

[0059] In some embodiments, performing m etching processes in the first sub-division may further include: performing a first etching process, etching the stack structure along the first opening and the second opening for the first etching process to expose the top surface of the conductive layer 112 of the seventh stack structure; performing a second etching process, etching the stack structure 110 along the third opening and the fourth opening for the second etching process to expose the top surface of the conductive layer of the fifth stack structure; performing a third etching process, etching the stack structure along the fifth opening and the sixth opening for the third etching process to expose the top surface of the conductive layer of the third stack structure; performing a fourth etching process, etching the stack structure along the seventh opening and the eighth opening for the fourth etching process to expose the top surface of the conductive layer of the first stack structure; performing a fifth etching process, etching the stack structure along the first opening, the third opening, the fifth opening and the seventh opening to expose the top surfaces of the conductive layers of the first to eighth stack structures, respectively.

[0060] In some embodiments, five etching processes are performed in the first partition, and the photoresist layer formed by each etching process corresponds to the opening exposed by each etching process, and the stacked structure can be etched along the opening exposed by the photoresist layer.

[0061] It is understandable that performing m etching processes in the first sub-area may also include other etching methods, that is, etching along different openings to expose the top surface of the conductive layer to be exposed. Other inferred etching methods also fall within the scope of protection of the present disclosure.

[0062] In some embodiments, an N-layer stacked structure 110 is formed on a substrate 100, where N is an integer multiple of 8, and the N-layer stacked structure 110 is divided into: a first stacked structure, a second stacked structure, and an N-th stacked structure along a direction away from the substrate 100 toward the substrate 100, the N openings 121 of the mask layer 120 are divided into a first opening, a second opening, and an N-th opening along a first direction X, and the n partitions are divided into a first sub-partition and an n-th sub-partition along the first direction X, the first sub-partition includes a first opening, a second opening, and an eighth opening, and the n-th sub-partition includes The N-7th opening, the N-6th opening, and the Nth opening are subjected to M etching processes to form a plurality of grooves 130, including: performing m etching processes simultaneously in the first sub-division to the nth sub-division to expose the conductive layers of the first stacking structure to the eighth stacking structure in the first sub-division to the nth sub-division, respectively; repeating the covering etching process until the conductive layers 112 of the first stacking structure to the Nth stacking structure are respectively exposed, and the covering etching process includes: covering at least one sub-division from the first sub-division to the nth sub-division, and etching downward the uncovered sub-division.

[0063] It can be understood that here, m etching processes are carried out simultaneously from the first sub-division to the nth sub-division, that is, the second partition or the third partition scheme in the above description. By carrying out m etching processes simultaneously from the first sub-division to the nth sub-division, the first to eighth layers of conductive layers 112 can be exposed in the first sub-division to the nth sub-division at the same time. At this time, a covering etching process is performed until the conductive layers 112 of the first stacking structure to the Nth stacking structure are respectively exposed, so that the conductive layers 112 of the first stacking structure to the Nth stacking structure can be exposed.

[0064] It should be noted that the m-times etching process performed on the first sub-region here can refer to the etching process performed on the first sub-region in the m-times etching process performed on the first sub-region to the n-th sub-region, which will not be repeated here.

[0065] In some embodiments, repeatedly performing the capping etching process includes: capping multiple sub-regions from the first sub-region to the nth sub-region, exposing any sub-region, and etching the stacked structure along the openings of the exposed sub-region, wherein the number of layers of the etched stacked structure is an integer multiple of 8. By first etching n sub-regions in the same step and then etching any sub-region separately, the conductive layers 112 of different stacked structures are exposed.

[0066] For example, take n sub-partitions including: the first sub-partition, the second sub-partition and the third sub-partition as an example, wherein the first sub-partition is set to expose the conductive layer 112 of the first stacking structure to the eighth stacking structure, the second sub-partition exposes the conductive layer 112 of the ninth stacking structure to the sixteenth stacking structure, and the third sub-partition exposes the conductive layer 112 of the seventeenth stacking structure to the twenty-fourth stacking structure, wherein m etching processes are first performed synchronously in the first sub-partition to the third sub-partition to expose the conductive layer 112 of the first stacking structure to the eighth stacking structure in the first sub-partition to the third sub-partition respectively, at this time, the first sub-partition and the third sub-partition can be covered first to expose the second sub-partition, and then the second sub-partition is etched downward as a whole by eight layers of stacking structure to expose the conductive layer 112 of the ninth stacking structure to the sixteenth stacking structure in the second sub-partition, and then the first sub-partition and the second sub-partition are covered, and the third sub-partition is etched to expose the conductive layer 112 of the seventeenth stacking structure to the twenty-fourth stacking structure.

[0067] In some embodiments, the repeated capping etching process includes: the subsequent capping etching process covers one more sub-region than the previous capping etching process, and each capping etching process etches 8 layers of the stacked structure. By etching n sub-regions in the same step, and then performing the capping etching process on different sub-regions, each etching 8 layers of the stacked structure, the conductive layers 112 of different stacked structures are exposed.

[0068] For example, take n sub-divisions including: a first sub-division, a second sub-division and a third sub-division as an example, wherein the first sub-division is set to expose the conductive layer 112 of the first stacking structure to the eighth stacking structure, the second sub-division exposes the conductive layer 112 of the seventeenth stacking structure to the twenty-fourth stacking structure, and the third sub-division exposes the conductive layer 112 of the ninth stacking structure to the sixteenth stacking structure, wherein m etching processes are first performed synchronously in the first sub-division to the third sub-division to expose the conductive layer 112 of the first stacking structure to the eighth stacking structure in the first sub-division to the third sub-division respectively, at this time, the first sub-division can be covered first, and then the second sub-division and the third sub-division are etched, and the 8-layer stacking structure is etched to expose the conductive layer 112 of the ninth stacking structure to the sixteenth stacking structure in the second sub-division and the third sub-division, and then the first sub-division and the third sub-division are covered again, and the 8-layer stacking structure of the second sub-division is etched, so that the conductive layer 112 of the seventeenth stacking structure to the twenty-fourth stacking structure can be exposed.

[0069] In some embodiments, N is greater than 8, and N is not an integer multiple of 8. Before the etching process, the mask layer 120 is further divided into n partitions, and the partitions are divided into n-1 first partitions and 1 second partition. The first partition includes 8 openings, and the second partition includes openings that are a remainder of N / 8. The difference in the number of layers etched by the etching process between different first partitions as a whole is an integer multiple of 8, where n is N / 8 rounded up.

[0070] In other words, the first partition is a partition containing 8 openings, and the second partition is a partition with less than 8 openings. Similarly, etching after partitioning can facilitate the fabrication method of the semiconductor structure and reduce the etching steps of the fabrication method of the semiconductor structure.

[0071] It should be noted that the rounding up here means that if there is a remainder when N is divided by 8, then the quotient obtained by dividing N by 8 plus 1 is the number of partitions. If there is no remainder when N is divided by 8, then the quotient obtained by dividing N by 8 is used as the number of partitions. For example, if N is 13, then the quotient obtained by dividing N by 8 is 1, and if there is a remainder, the number of partitions is 2.

[0072] In some embodiments, taking a stacking structure with 22 layers as an example, that is, the mask layer 120 is divided into 2 first partitions and 1 second partition, and each first partition includes 8 openings, and the second partition includes 6 openings. The 22-layer stacking structure is divided into: a first stacking structure, a second stacking structure, and up to a twenty-second stacking structure along the direction away from the substrate 100 toward the substrate 100. The N openings of the mask layer 120 are divided into a first opening, a second opening, and up to a twenty-second opening along the first direction X, and the two first partitions are divided into a first sub-partition and a second sub-partition along the first direction X.

[0073] In some embodiments, performing M etching processes to form multiple grooves may include: first etching the two first partitions, and then etching the second partition; in some embodiments, the first partition and the second partition may also be etched simultaneously, wherein the processing of the first partition may refer to the processing in the above embodiment where N is an integer of 8, which will not be repeated here, and the processing of the second partition may refer to the process of any consecutive 6 exposed conductive layers in the first partition. For example, the second partition includes the seventeenth opening to the twenty-second opening, and the etching process along the seventeenth opening to the twenty-second opening can be the same as the etching process along the first opening to the sixth opening in the first partition. For example, in the first partition, the first opening to the sixth opening respectively expose the conductive layer 112 of the first stacking structure to the conductive layer 112 of the sixth stacking structure, then the seventeenth opening to the twenty-second opening can also be the same as the process of the first opening to the sixth opening, first exposing the conductive layer 112 of the first stacking structure to the conductive layer 112 of the sixth stacking structure, and then etching the stacking structure along the seventeenth opening to the twenty-second opening toward the direction close to the substrate 100 as required, for example, etching the 16-layer stacking structure toward the direction close to the substrate 100 to expose the conductive layer 112 of the seventeenth stacking structure to the twenty-second stacking structure.

[0074] It should be noted that the etching process in the above-mentioned second partition only needs to ensure that it is the same as the process of exposing any consecutive 6 conductive layers in the first partition. For example, it is the same as the process of exposing the conductive layer 112 of the second stacking structure to the seventh stacking structure in the first partition. The subsequent etching of 15 layers of the stacking structure 110 in the second partition toward the direction close to the substrate 100 can be controlled to expose the conductive layer 112 of the seventeenth stacking structure to the twenty-second stacking structure. That is to say, by controlling the etching process in the second partition to be the same as the process of exposing any consecutive 6 conductive layers in the first sub-partition and controlling the number of layers of the stacking structure 110 subsequently etched toward the substrate 100, the etching process of the second partition can be completed.

[0075] It can be understood that the six openings included in the second partition in the above embodiment are only for illustration. The second partition may also include one opening, two openings, or seven openings, etc., and the etching process in the second partition can be controlled to be the same as the process of exposing any continuous conductive layer in the etching process in the first partition.

[0076] In some embodiments, the number N may also be less than 8. For example, N is equal to 5, and the 5-layer stacked structure 110 is divided into: a first stacked structure to a fifth stacked structure along a direction away from the substrate 100 toward the substrate 100, and the 5 openings 121 of the mask layer 120 are divided into a first opening to a fifth opening along the first direction X. Performing M etching processes may include: performing a first etching process, etching the stacked structure along the first opening, the second opening, and the third opening in the first etching process to expose the conductive layer 112 of the second stacked structure at positions corresponding to the first opening, the second opening, and the third opening; performing a second etching process, etching the stacked structure along the first opening, the second opening, and the fourth opening in the second ...; performing a second etching process, etching the stacked structure along the first opening, the second opening, and the fourth opening in the second etching process. a stacked structure to expose the conductive layer 112 of the fourth stacked structure at positions corresponding to the first opening and the second opening, and to expose the conductive layer 112 of the second stacked structure at the position of the fourth opening; and perform a third etching process, wherein the stacked structure is etched along the first opening, the third opening and the fifth opening to expose the conductive layer 112 of the fifth stacked structure at a position corresponding to the first opening, expose the conductive layer 112 of the fourth stacked structure at a position corresponding to the second opening, expose the conductive layer 112 of the third stacked structure at a position corresponding to the third opening, expose the conductive layer 112 of the second stacked structure at a position corresponding to the fourth opening, and expose the conductive layer 112 of the first stacked structure at a position corresponding to the fifth opening.

[0077] It should be noted that in the above embodiment, only partial etching examples are given. However, by changing the etching position and the number of film layers etched each time, the solution of finally exposing different conductive layers 112 also falls within the protection scope of the embodiments of the present disclosure.

[0078] In some embodiments, the mask layer may not be partitioned. Taking N=16 as an example, the 16-layer stacked structure 110 is divided into: a first stacked structure to a sixteenth stacked structure along a direction away from the substrate 100 toward the substrate 100, and the 16 openings 121 of the mask layer 120 are divided into a first opening to a sixteenth opening along the first direction X. Performing M etching processes to form a plurality of grooves may include: performing a first etching process, etching the stacked structure 110 along the first opening, the second opening, the third opening, the fourth opening, the ninth opening, the tenth opening, the eleventh opening, and the twelfth opening to expose the conductive layer 112 of the eighth stacked structure; performing a second ... The stacked structure 110 is etched through the fifth opening, the sixth opening, the ninth opening, the tenth opening, the thirteenth opening and the fourteenth opening to expose the conductive layer 112 of the twelfth stacked structure at positions corresponding to the first opening, the second opening, the ninth opening and the tenth opening, and the conductive layer 112 of the fourth stacked structure is exposed at positions corresponding to the fifth opening, the sixth opening, the thirteenth opening and the fourteenth opening; a third etching process is performed, and the stacked structure 110 is etched along the first opening, the third opening, the fifth opening, the seventh opening, the ninth opening, the tenth opening, the thirteenth opening and the fifteenth opening to expose the conductive layer 112 of the fourteenth stacked structure at positions corresponding to the first opening and the ninth opening, and the conductive layer 112 of the tenth stacked structure is exposed at positions corresponding to the second opening and the tenth opening. The conductive layer 112 of the second stacking structure is exposed at the positions corresponding to the third opening and the eleventh opening, the conductive layer 112 of the tenth stacking structure is exposed at the positions corresponding to the fourth opening and the twelfth opening, the conductive layer 112 of the eighth stacking structure is exposed at the positions corresponding to the fifth opening and the thirteenth opening, the conductive layer 112 of the sixth stacking structure is exposed at the positions corresponding to the sixth opening and the fourteenth opening, and the conductive layer 112 of the fourth stacking structure is exposed at the positions corresponding to the seventh opening and the fifteenth opening; a fourth etching process is performed, and the fourth etching process etches the stacking structure 110 along the first opening to the eighth opening to expose the conductive layer 112 of the fifteenth stacking structure at the position corresponding to the first opening, and exposes the conductive layer 112 of the fifteenth stacking structure at the position corresponding to the second opening. The conductive layer 112 of the thirteenth stacking structure is exposed, the conductive layer 112 of the eleventh stacking structure is exposed at the position corresponding to the third opening, the conductive layer 112 of the ninth stacking structure is exposed at the position corresponding to the fourth opening, the conductive layer 112 of the seventh stacking structure is exposed at the position corresponding to the fifth opening, the conductive layer 112 of the fifth stacking structure is exposed at the position corresponding to the sixth opening, the conductive layer 112 of the third stacking structure is exposed at the position corresponding to the seventh opening, and the conductive layer 112 of the first stacking structure is exposed at the position corresponding to the eighth opening; a fifth etching process is performed, the fifth etching process uses the mask layer as a mask, and simultaneously etches the stacking structure 110 along the first opening to the sixteenth opening to expose the conductive layers 112 of the first to sixteenth stacking structures, respectively.

[0079] It can be understood that in the above-mentioned non-partitioned example, the first etching process etches 8 layers of stacked structures 110, the second etching process etches 4 layers of stacked structures, the third etching process etches 2 layers of stacked structures 110, the fourth etching process etches 1 layer of stacked structure 110, and the fifth etching process etches 1 layer of stacked structure 110. Through 5 etchings, the conductive layers 112 of the first to sixteenth stacked structures can be exposed respectively.

[0080] It should be noted that the above-mentioned non-partitioned example only takes a 16-layer stacking structure 110 as an example. If the stacking structure is 15 layers, the process steps corresponding to exposing the conductive layer 112 of the sixteenth stacking structure in the 16-layer stacking structure can be removed, and the process of exposing the conductive layers 112 of the first stacking structure to the fifteenth stacking structure can be obtained. If the number of stacking structures 110 is higher than 16 layers, the etching method of a higher number of stacking structures 110 can still be obtained by deduction, and the etching of a higher number of stacking structures 110 obtained by deduction also falls within the protection scope of the embodiments of the present disclosure.

[0081] It can be understood that the above embodiment only describes one etching process method. Taking a stacked structure with 16 layers as an example, the opening position of each etching process or the number of film layers etched in each etching process can also be changed, which also falls within the scope of protection of this disclosure.

[0082] In some embodiments, after each etching process and before the next etching process, the process may further include: forming a filling layer 190, wherein the filling layer fills the depression formed after each etching process. By forming the filling layer 190, support can be provided for the next etching process, thereby avoiding the collapse of the film layer in the next etching process. In addition, by forming the filling layer 190, the conductive layer 112 exposed by the previous etching process can be protected, thereby avoiding damage to the conductive layer 112.

[0083] In some embodiments, the filling layer 190 may be made of insulating materials such as silicon oxide or silicon nitride.

[0084] In some embodiments, the material of the filling layer 190 can be the same as that of the insulating layer 111. By setting the material of the filling layer 190 to be the same as that of the insulating layer 111, the etching reagent does not need to be replaced during etching, and the etching selectivity ratio between the filling layer 190 and the insulating layer 111 does not need to be considered.

[0085] In some embodiments, after forming the filling layer 190, the process also includes: removing the photoresist layer. By removing the photoresist layer after forming the filling layer 190, the etching reagent used to remove the photoresist layer can be prevented from affecting the conductive layer 112. Removing the photoresist layer can also provide a process basis for the next etching process to form the photoresist layer.

[0086] In some embodiments, before forming the mask layer 120, the following may also be included: forming an isolation layer 200, where the isolation layer 200 is located on the top surface of the top stacking structure 110. By forming the isolation layer 200, it can also serve as an etching barrier layer for forming the mask layer 120. That is, when forming the opening 121 on the mask layer 120, the isolation layer 200 can be used as an etching barrier layer to avoid affecting the stacking structure 110.

[0087] In some embodiments, the isolation layer 200 may be made of insulating materials such as silicon oxide or silicon nitride.

[0088] In some embodiments, the material of the isolation layer 200 can be the same as the material of the insulating layer 111. By setting the material of the isolation layer 200 to be the same as the material of the insulating layer 111, it is not necessary to consider the etching selectivity ratio between the isolation layer 200 and the insulating layer 111 in subsequent etching processing, and it is not necessary to select additional etching reagents, thereby reducing the process difficulty of the manufacturing method of the entire semiconductor structure.

[0089] In some embodiments, before forming the conductive plug, the following step may be included: forming a dielectric layer 210, where the dielectric layer 210 covers the sidewalls of the groove. In other words, the dielectric layer 210 covers the sidewall surface of the conductive plug 150, thereby preventing the conductive plug 150 from contacting and electrically connecting with the multiple conductive layers 112, thereby improving the reliability of the semiconductor structure.

[0090] In the embodiment of the present disclosure, a stacked structure 110 is formed, and the number of the stacked structures 110 is the number of conductive plugs 150 that need to be formed subsequently. A mask layer 120 is formed, and the openings 121 on the mask layer 120 locate the positions of the conductive plugs 150 that are formed subsequently. The mask layer 120 also serves as a mask for etching the stacked structure 110. M etching processes are performed to form grooves 130 that expose different conductive layers 112, thereby exposing each conductive layer 112. This provides a process basis for subsequently forming conductive plugs 150 connected to different conductive layers 112, thereby enabling the transmission of signals to each conductive layer 112 or the reception of signals from each conductive layer 112. 2, the stacked structure 110 is etched along at least two openings 121 through the first M-1 etching processes, and the etching process can be shared in the process of etching to expose different conductive layers 112, thereby reducing the number of etching processes. Reducing the number of etching processes can simultaneously reduce the number of mask layers 120, thereby reducing the process difficulty of the semiconductor structure manufacturing method. The stacked structure 110 is etched along partially identical or completely different openings 121 through two adjacent etching processes, and the etching process can be controlled to expose different conductive layers 112, thereby achieving the purpose of exposing each conductive layer 112, which is convenient for a conductive plug 150 formed subsequently to be connected to a corresponding conductive layer 112.

[0091] Another embodiment of the present disclosure further provides a semiconductor structure, which can be manufactured by all or part of the above-mentioned embodiments. The semiconductor structure provided by another embodiment of the present disclosure will be described below with reference to the accompanying drawings. It should be noted that the parts that are the same or corresponding to the above-mentioned embodiments can refer to the corresponding description of the above-mentioned embodiments and will not be repeated below.

[0092] refer to Figure 8 and Figure 9 The semiconductor structure provided by the embodiment of the present disclosure may include: a substrate 100; an N-layer stacked structure 110, wherein the N-layer stacked structure 110 is located on the top surface of the substrate 100, and each stacked structure 110 in the N-layer stacked structure 110 includes an insulating layer 111 and a conductive layer 112 located on the top surface of the insulating layer 111, where N is a positive integer greater than 1; a plurality of conductive plugs 150 arranged at intervals along a first direction X, wherein each of the plurality of conductive plugs 150 is in contact with and connected to the conductive layer 112 in a different stacked structure 110, and the top surface of the conductive plug 150 is higher than the top surface of the stacked structure 110, and along the first direction X, the height of the conductive plug 150 shows a non-increasing or non-decreasing trend.

[0093] The semiconductor structure provided by the embodiment of the present disclosure includes: multiple conductive plugs 150 higher than the top surface of the stacked structure 110 to lead out different conductive layers 112 of different stacked structures 110, so that signals can be transmitted to different conductive layers 112 through the conductive plugs 150, or signals in different conductive layers 112 can be transmitted out, and the height of the conductive plugs 150 shows a non-increasing or non-decreasing trend, which can facilitate the manufacturing process of the semiconductor structure.

[0094] refer to Figure 8 In some embodiments, the semiconductor structure is divided into n sub-areas along a first direction, and the height of the conductive plugs 150 in each sub-area gradually decreases along the first direction. By gradually decreasing the height of the conductive plugs 150 in each sub-area along the first direction, the entire semiconductor process can be facilitated, and the process of forming the semiconductor structure can be carried out in a regular manner.

[0095] refer to Figure 9 In some embodiments, the semiconductor structure is divided into n sections along the first direction, and the height of the conductive plugs 150 in each section varies irregularly. By setting the height of the conductive plugs 150 in each section to vary irregularly, the conductive layers 112 to be connected to the conductive plugs in each section can be flexibly adjusted according to actual needs. In other words, the number of conductive layers 112 connected to each section can be flexibly selected according to needs.

[0096] In some embodiments, the number of partitions satisfies N / 8 rounded up, that is, there are at most 8 conductive plugs 150 in each partition, which can further facilitate the manufacturing method of the semiconductor structure and reduce the process difficulty of the semiconductor structure manufacturing method.

[0097] In some embodiments, N is an integer multiple of 8. Along the first direction X, the semiconductor structure is divided into n partitions. The height of the conductive plug 150 in each partition varies irregularly, and the change trend of the conductive plug 150 in each partition is the same, where n=N / 8.

[0098] For example, the semiconductor structure includes a 16-layer stacked structure, and the 16-layer stacked structure is divided into a first stacked structure, a second stacked structure to a sixteenth stacked structure from a direction away from the substrate 100 toward a direction close to the substrate 100, and the semiconductor structure is divided into two partitions, and is divided into a first sub-partition and a second sub-partition along the first direction X, wherein the eight conductive plugs 150 of the first sub-partition along the first direction X are respectively connected to the conductive layer 112 of the seventh stacked structure, the conductive layer 112 of the fifth stacked structure, the conductive layer 112 of the fourth stacked structure, the conductive layer 112 of the eighth stacked structure, and the conductive layer 112 of the third stacked structure. The conductive layer 112 of the fifteenth stack structure, the conductive layer 112 of the first stack structure, the conductive layer 112 of the sixth stack structure and the conductive layer 112 of the second stack structure, the eight conductive plugs 150 of the second sub-division along the first direction X are respectively connected to the conductive layer 112 of the fifteenth stack structure, the conductive layer 112 of the thirteenth stack structure, the conductive layer 112 of the twelfth stack structure, the conductive layer 112 of the sixteenth stack structure, the conductive layer 112 of the eleventh stack structure, the conductive layer 112 of the ninth stack structure, the conductive layer 112 of the fourteenth stack structure and the conductive layer 112 of the tenth stack structure.

[0099] That is, the number of stacked structures of the conductive layers 112 connected between the conductive plugs 150 at corresponding positions along the first direction X in different partitions is 8.

[0100] It should be noted that the corresponding positions here refer to the positions of the conductive plugs 150 arranged along the first direction X in different partitions. For example, if they are all the first conductive plugs 150 arranged along the first direction in their respective partitions, then these conductive plugs 150 are conductive plugs 150 at corresponding positions.

[0101] In some embodiments, N is not an integer multiple of 8. Along the first direction X, the semiconductor structure is divided into n-1 first partitions and 1 second partition. The heights of the conductive plugs 150 in the first partition and the second partition vary irregularly, and the change trend of the conductive plugs 150 in each first partition is the same, where n is N divided by 8 rounded up.

[0102] It can be understood that the change trend here can refer to the description of the change trend in the above embodiment where N is an integer multiple of 8, which will not be repeated here. The difference here is whether N is an integer multiple of 8.

[0103] In some embodiments, N is an integer multiple of 8, and along the first direction X, the semiconductor structure is divided into n partitions. The height of the conductive plug 150 in each partition varies irregularly, and the variation trend of the conductive plug 150 in each partition is partially the same or completely different, where n=N / 8.

[0104] It can be understood that the description of the changing trend here can also refer to the description of the changing trend in the above embodiment. The partially same here means that the changing trends of the conductive plugs 150 in some partitions are the same, and the changing trends of the conductive plugs 150 in some partitions are different. The completely different here means that the changing trends of the conductive plugs 150 in all partitions are different.

[0105] In some embodiments, N is not an integer multiple of 8. Along the first direction X, the semiconductor structure is divided into n-1 first partitions and 1 second partition. The height of the conductive plug 150 in each first partition varies irregularly, and the variation trend of the conductive plug 150 in each first partition is partially the same or completely different, where n is N divided by 8 rounded up.

[0106] It can be understood that the description of the changing trend here can also refer to the description of the changing trend in the above embodiment. The partially the same here means that the changing trends of the conductive plugs 150 in some first partitions are the same, and the changing trends of the conductive plugs 150 in some first partitions are different. The completely different here means that the changing trends of the conductive plugs 150 in all first partitions are different.

[0107] In some embodiments, another embodiment of the present disclosure further provides a memory. The memory provided by the embodiment of the present disclosure may include part or all of the contents of the above-mentioned semiconductor structure embodiment. It should be noted that the same or corresponding parts of the above-mentioned embodiments can refer to the corresponding description of the above-mentioned embodiments and will not be repeated below.

[0108] It should be noted that the memory may be a storage unit or device based on a semiconductor device or component. For example, the memory may be a volatile memory, such as dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), low power double data rate synchronous dynamic random access memory (LPDDR SDRAM), graphic double data rate synchronous dynamic random access memory (GDDR SDRAM), double data rate type dual synchronous dynamic random access memory (DDR2 SDRAM), double data rate type triple synchronous dynamic random access memory (DDR3 SDRAM), double data rate fourth generation synchronous dynamic random access memory (DDR4 SDRAM), thyristor random access memory (TRAM), etc.; or it may be a non-volatile memory, such as phase change random access memory (PRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), etc.

[0109] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present disclosure, and in actual applications, various changes may be made to them in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure. Therefore, the scope of protection of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: providing a substrate; forming an N-layer stacked structure on the substrate, wherein each stacked structure in the N-layer stacked structures includes an insulating layer and a conductive layer located on a top surface of the insulating layer, and N is a positive integer greater than or equal to 16, and N is an integer multiple of 8; forming a mask layer, the mask layer being located on the stacked structure at the top layer, and the mask layer including N openings spaced apart along a first direction, and dividing the mask layer into n partitions, each of the partitions including 8 openings, where n is N / 8; performing M etching processes to form a plurality of grooves, each of the grooves exposing a different conductive layer of the stacked structure, wherein the first M-1 etching processes all etch the stacked structure along at least two of the openings, and two adjacent etching processes etch the stacked structure along the openings that are partially the same or completely different, the etching process comprising: forming a photoresist layer, the photoresist layer being located on a top surface of the mask layer, the photoresist layer covering a portion of the openings, and etching the stacked structure along the openings exposed by the photoresist layer to expose the top surface of the conductive layer, where M is a positive integer less than N; A conductive plug is formed, and the conductive plug completely fills the groove.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein: The N-layer stacking structure is divided into: a first stacking structure, a second stacking structure, and finally an N-th stacking structure along a direction away from the substrate and toward the substrate; The N openings of the mask layer are divided into a first opening, a second opening and an Nth opening along the first direction; The n partitions are divided into a first sub-partition, a second sub-partition, and an nth sub-partition along the first direction. The first sub-partition includes a first opening, a second opening, and an eighth opening. The nth sub-partition includes an N-7th opening, an N-6th opening, and an Nth opening. The performing M etching processes to form a plurality of grooves includes: Simultaneously performing m etching processes in the first sub-region to the n-th sub-region to expose the conductive layers of the first to eighth stacked structures in the first sub-region to the n-th sub-region respectively; Repeat the covering etching process until the conductive layers of the first stacking structure to the Nth stacking structure are exposed respectively, and the covering etching process includes: covering at least one sub-division from the first sub-division to the nth sub-division, and etching downward the uncovered sub-division.

3. The method for manufacturing a semiconductor structure according to claim 2, wherein: Performing m etching processes in the first sub-region includes: Performing a first etching process, wherein the first etching process etches the stacked structure along the first opening to the fourth opening to expose the top surface of the conductive layer of the fourth stacked structure; performing a second etching process, wherein the second etching process etches the stack structure along the first opening, the second opening, the fifth opening, and the sixth opening to expose top surfaces of the conductive layers of the sixth stack structure and the second stack structure; performing a third etching process, wherein the third etching process etches the stack structure along the first opening, the third opening, the fifth opening, and the seventh opening to expose top surfaces of the conductive layers of the seventh stack structure, the fifth stack structure, the third stack structure, and the first stack structure; A fourth etching process is performed, wherein the fourth etching process etches the stack structure using the mask layer as a mask to expose top surfaces of the conductive layers from the first stack structure to the eighth stack structure.

4. The method for manufacturing a semiconductor structure according to claim 3, wherein: The first etching process includes: forming a first photoresist layer, wherein the first photoresist layer divides the mask layer into a first covered area and a first exposed area, wherein the first exposed area includes the first opening to the fourth opening, and the first covered area includes the fifth opening to the eighth opening, and etching the stacked structure using the first photoresist layer and the mask layer as masks to expose the top surface of the conductive layer of the fourth stacked structure; The second etching process includes: forming a second photoresist layer, wherein the second photoresist layer divides the mask layer into a second covering area and a second exposed area, wherein the second covering area includes the third opening, the fourth opening, the seventh opening, and the eighth opening, and the second exposed area includes the first opening, the second opening, the fifth opening, and the sixth opening; and etching the stack structure using the second photoresist layer and the mask layer as a mask to expose top surfaces of the conductive layers of the sixth stack structure and the second stack structure; The third etching process includes: forming a third photoresist layer, the third photoresist layer divides the mask layer into a third covering area and a third exposed area, the third covering area includes the second opening, the fourth opening, the sixth opening and the eighth opening, the third exposed area includes the first opening, the third opening, the fifth opening and the seventh opening, and the stack structure is etched using the third photoresist layer and the mask layer as a mask to expose the top surface of the conductive layer of the seventh stack structure, the fifth stack structure, the third stack structure and the first stack structure.

5. The method for manufacturing a semiconductor structure according to claim 2, wherein: The repeated covering etching process includes: covering multiple sub-partitions from the first sub-partition to the nth sub-partition, exposing any sub-partition, and etching the stacked structure along the opening of the exposed sub-partition, wherein the number of layers of the etched stacked structure is an integer multiple of 8.

6. The method for manufacturing a semiconductor structure according to claim 2, wherein: The repeatedly performing the capping etching process includes: the subsequent capping etching process covers one more sub-region than the previous capping etching process, and the number of layers of the stacked structure etched by each capping etching process is 8.

7. The method for manufacturing a semiconductor structure according to claim 1, wherein: After each etching process and before the next etching process, the method further includes: forming a filling layer, wherein the filling layer fills the recess formed after the etching process.

8. The method for manufacturing a semiconductor structure according to claim 1, wherein: Before forming the mask layer, the method further includes forming an isolation layer, wherein the isolation layer is located on the top surface of the stacked structure, and the material of the isolation layer is the same as that of the insulating layer.

9. A method for manufacturing a semiconductor structure, characterized in that: include: providing a substrate; forming an N-layer stacked structure on the substrate, wherein each stacked structure in the N-layer stacked structures includes an insulating layer and a conductive layer located on a top surface of the insulating layer, and N is a positive integer greater than 16, and N is not an integer multiple of 8; forming a mask layer, the mask layer being located on the stacked structure at the top layer, the mask layer including N openings spaced apart along a first direction, and dividing the mask layer into n partitions, the n partitions being divided into n-1 first partitions and one second partition, the first partition including 8 openings, the second partition including openings that are a remainder of N / 8, where n is N / 8 rounded up; performing M etching processes to form a plurality of grooves, each of the grooves exposing a different conductive layer of the stacked structure, wherein the first M-1 etching processes all etch the stacked structure along at least two of the openings, and two adjacent etching processes etch the stacked structure along the openings that are partially the same or completely different, the etching process comprising: forming a photoresist layer, the photoresist layer being located on a top surface of the mask layer, the photoresist layer covering a portion of the openings, and etching the stacked structure along the openings exposed by the photoresist layer to expose the top surface of the conductive layer, where M is a positive integer less than N; A conductive plug is formed, and the conductive plug completely fills the groove.

10. The method for manufacturing a semiconductor structure according to claim 9, wherein: The N-layer stacking structure is divided into: a first stacking structure, a second stacking structure, and finally an N-th stacking structure along a direction away from the substrate and toward the substrate; The difference in the number of layers etched by the etching process between different first subareas as a whole is an integer multiple of 8.

11. The method for manufacturing a semiconductor structure according to claim 9, wherein: After each etching process and before the next etching process, the method further includes: forming a filling layer, wherein the filling layer fills the recess formed after the etching process.

12. The method for manufacturing a semiconductor structure according to claim 9, wherein: Before forming the mask layer, the method further includes forming an isolation layer, wherein the isolation layer is located on the top surface of the stacked structure, and the material of the isolation layer is the same as that of the insulating layer.

13. A semiconductor structure, characterized in that include: substrate; N-layer stacked structures, each of which includes an insulating layer and a conductive layer located on top of the insulating layer, wherein N is a positive integer greater than or equal to 16 and is an integer multiple of 8; a plurality of conductive plugs spaced apart along a first direction, each of the plurality of conductive plugs being in contact with the conductive layer in a different stacked structure, and having heights that are non-increasing or non-decreasing along the first direction; Wherein, along the first direction, the semiconductor structure is divided into n partitions, each partition includes 8 conductive plugs, and n is N / 8.

14. The semiconductor structure according to claim 13, wherein: Along the first direction, in the n partitions, the height of the conductive plug in each partition varies irregularly, and the height of the conductive plug in each partition has the same variation trend.

15. The semiconductor structure according to claim 13, wherein: Along the first direction, in the n partitions, the heights of the conductive plugs in each partition vary irregularly, and the variation trends of the conductive plugs in each partition are partially the same or completely different.

16. A semiconductor structure, characterized in that include: substrate; N-layer stacked structures, the N-layer stacked structures being located on a top surface of the substrate, and each stacked structure in the N-layer stacked structures including an insulating layer and a conductive layer located on a top surface of the insulating layer, wherein N is a positive integer greater than 16 and is not an integer multiple of 8; a plurality of conductive plugs spaced apart along a first direction, each of the plurality of conductive plugs being in contact with the conductive layer in a different stacked structure, and having heights that are non-increasing or non-decreasing along the first direction; In which, along the first direction, the semiconductor structure is divided into n partitions, the n partitions are divided into n-1 first partitions and 1 second partition, the first partition includes 8 conductive plugs, and the second partition includes the conductive plugs with a remainder of N / 8, where n is N / 8 rounded up.

17. The semiconductor structure according to claim 16, wherein: The heights of the conductive plugs in the first partition and the second partition vary irregularly, and the heights of the conductive plugs in each first partition have the same variation trend.

18. The semiconductor structure according to claim 16, wherein: The heights of the conductive plugs in each of the first partitions vary irregularly, and the changing trends of the conductive plugs in each of the first partitions are partially the same or completely different.

19. A memory, characterized in that: Comprising the semiconductor structure according to any one of claims 13 to 18.

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