Method, computer program product, and computing device for verifying a storage circuit

Abstract

The present invention provides a method, a computer program product and a computing device for verifying a memory circuit. The method includes: dividing the address space of a chip memory circuit into multiple address blocks, including: generating the start address and block length for the address blocks in a random manner; randomly allocating at least one of the multiple address blocks; performing a functional verification simulation on the chip memory circuit using the allocated at least one address block; collecting the coverage rate of the start address and block length of the address blocks according to the results of multiple randomizations, and completing the functional verification simulation when the coverage rate reaches 100%. According to the technical solution of the present invention, it is possible to better verify the boundary and special addresses, increase the completeness of chip verification, combine the verification of the address space and functional verification, realize automatic address allocation, and increase the verification efficiency.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a method, a computer program product, and a computing device for verifying a storage circuit. Background Art

[0002] The storage circuit is an important part of the chip. The instructions and data for the chip to operate need to be stored in the storage circuit. And as the requirement for the chip computing speed is getting higher and higher, the position of the storage circuit is getting closer and closer to the computing circuit. Nowadays, directly placing the storage circuit inside the computing core and using on-chip storage have become an important architecture solution to solve the data transfer problem. During the use of the chip, in addition to using register configuration, some data or configurations may also be stored in the corresponding storage circuit random access memory space (RAM space). When the actual chip is used, the software performs dynamic memory allocation to allocate and recycle the storage space.

[0003] Most of the existing memory dynamic allocation algorithms are for software use, focusing on the allocation and recycling of the storage space. Each allocation should be sufficient, and after use, the recycling should not be invalidly occupied. However, for chip verification, usually the commands executed and the data used are less, and the space is sufficient. The focus should be on finding out the scenarios that may have problems according to the chip structure, and constructing the allocation and use of the storage space based on these scenarios. For example, specifically constructing a space that spans two actual RAMs, or constructing multiple misaligned address spaces, etc.

[0004] Therefore, a technical solution is needed that can better verify the boundaries and special addresses, increase the completeness of chip verification, combine the verification of the address space and the function verification, achieve automated address allocation, and increase the verification efficiency. Summary of the Invention

[0005] The present invention aims to provide a method, a computer program product, and a computing device for verifying a storage circuit, which can better verify the boundaries and special addresses, increase the completeness of chip verification, combine the verification of the address space and the function verification, achieve automated address allocation, and increase the verification efficiency.

[0006] According to one aspect of the present invention, there is provided a method for verifying a storage circuit, the method comprising:

[0007] Dividing the address space of the chip storage circuit into multiple address blocks, including: generating the start address and block length for the address blocks by a random method;

[0008] Randomly allocating at least one of the multiple address blocks;

[0009] Perform a functional verification simulation on the chip storage circuit using the at least one allocated address block;

[0010] Collect the coverage of the start address and block length of the address block according to the results of multiple randomizations. When the coverage reaches 100%, the functional verification simulation is completed.

[0011] According to some embodiments, the address space of the chip storage circuit is divided into multiple address blocks, and further includes:

[0012] Using the random constraint, increase the weight of the boundary and / or special addresses, and the weight includes empirical values.

[0013] According to some embodiments, the random constraint is set according to the boundary and white-box test points of the chip storage circuit.

[0014] According to some embodiments, randomly allocate at least one address block among the multiple address blocks, including:

[0015] Perform a disordered arrangement on the multiple address blocks;

[0016] Sequentially select the at least one address block from the disordered multiple address blocks.

[0017] According to some embodiments, perform dynamic address allocation on the at least one allocated address block using the memory allocation management component of the universal verification methodology, and automatically control the allocation and recycling of addresses.

[0018] According to some embodiments, performing a functional verification simulation on the chip storage circuit using the at least one allocated address block includes:

[0019] Set the actual chip storage space used according to the start address and block length of the at least one address block;

[0020] Perform use case testing on the actual chip storage space.

[0021] According to some embodiments, the actual chip storage space includes a combination of multiple storage units or is directly built by registers, and the boundaries and chip select controls between the multiple storage units are different.

[0022] According to some embodiments, each storage unit includes a storage row, a predetermined number of storage unit groups, and a predetermined number of storage groups constitute a storage block. The boundary of the chip storage circuit includes the boundary between the storage rows, the boundary between the storage groups, and / or the boundary between the storage blocks.

[0023] According to another aspect of the present invention, there is provided a computer program product including a computer program which, when executed by a processor, implements the method described in any one of the above.

[0024] According to another aspect of the present invention, there is provided a computing device including:

[0025] a processor; and

[0026] a memory storing a computer program which, when executed by the processor, implements the method described in any one of the above.

[0027] According to an embodiment of the present invention, by dividing the address space into multiple blocks, using the multiple blocks of address space for verification simulation, collecting the coverage of the start address and the space size of each allocated address space, and completing the verification of relevant functions after the coverage reaches 100%, automatic address allocation is achieved. The present invention can better verify the boundary and special addresses, increase the completeness of chip verification, combine the verification of address space and function verification, and improve the verification efficiency.

[0028] According to some embodiments, the present invention realizes dynamic memory allocation. When an application requests memory, the operating system kernel or runtime library automatically allocates a memory block of an appropriate size, automatically detects objects that are no longer in use, and releases the memory occupied by them.

[0029] According to some embodiments, automatic memory management reduces the workload required for manual management, and at the same time improves the performance of the system by avoiding problems such as memory leaks. Manual memory management is prone to errors, such as forgetting to release memory, wild pointers, double free, etc. Automatic allocation can significantly reduce such errors.

[0030] According to some embodiments, automatic memory management simplifies the code writing work, enables developers to focus more on business logic, and perform resource management more flexibly. The present invention enables the system to dynamically adjust memory resources according to actual needs, and better supports concurrent or multitasking processing.

[0031] According to some embodiments, the present invention can counteract behaviors that attempt to use a fixed memory layout for attacks, increase the difficulty for attackers, and enhance security.

[0032] It should be understood that the above general description and the following detailed description are only exemplary and do not limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments.

[0034] Figure 1A flowchart of a method for verifying a storage circuit according to an exemplary embodiment is shown.

[0035] Figure 2 A flowchart of a method for verifying dynamically allocated space according to an exemplary embodiment is shown.

[0036] Figure 3 A flowchart of a method for selecting an address block according to an exemplary embodiment is shown.

[0037] Figure 4 A block diagram of a computing device according to an exemplary embodiment is shown. Detailed Description

[0038] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be implemented in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. Like reference numerals in the figures denote like or similar parts, and thus their repetitive description will be omitted.

[0039] In addition, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of the embodiments of the present invention. However, those skilled in the art will realize that the technical solutions of the present invention can be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. may be used. In other instances, well-known methods, devices, implementations, or operations are not shown or described in detail to avoid obscuring aspects of the present invention.

[0040] The block diagrams shown in the drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities may be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0041] The flowcharts shown in the drawings are merely illustrative and not necessarily include all of the content and operations / steps, nor are they necessarily executed in the order described. For example, some operations / steps may be decomposed, while some operations / steps may be combined or partially combined, so the actual execution order may change according to the actual situation.

[0042] It should be understood that although terms such as first, second, and third may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another. Thus, the first component discussed below may be referred to as the second component without departing from the teachings of the inventive concept. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0043] The user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in the present invention are all information and data that have been authorized by the user or fully authorized by all parties. Moreover, the collection, use, and processing of relevant data need to comply with the relevant laws, regulations, and standards of the relevant countries and regions, and corresponding operation entrances are provided for users to select authorization or rejection.

[0044] Those skilled in the art can understand that the drawings are only schematic diagrams of exemplary embodiments, and the modules or processes in the drawings are not necessarily essential for implementing the present invention. Therefore, they cannot be used to limit the protection scope of the present invention.

[0045] Most of the memory dynamic allocation algorithms in the prior art are for software use, focusing on the allocation and recycling of storage space. Each allocation should be sufficient, and after use, the recycling should not be occupied invalidly. However, for chip verification, usually fewer commands are executed and less data is used, and the space is sufficient. The focus should be on finding possible problem scenarios according to the chip structure and constructing the allocation and use of storage space based on these scenarios. For example, specifically constructing a space that spans two actual random access registers (RAMs), or constructing multiple misaligned address spaces, etc.

[0046] Currently, the more commonly used verification method is to sequentially allocate several spaces according to the space size requirements, or directly evenly divide the storage space. This can only complete very simple scenario verifications. Or it is necessary to manually write the address space allocation for each scenario and manually check the coverage, which is inefficient and prone to omission. And if a method similar to the memory management unit (MMU) is used, it is too complex. Usually, it is neither necessary nor possible to have enough time to construct. In addition, for storage module verification, a scan of the storage space boundary may be separately constructed, but on the one hand, it takes time to separately construct test cases, and on the other hand, it is not combined with the actual function, and there may be omissions in the verification of coupled functions.

[0047] A seemingly continuous storage space in software is actually composed of splicing many small storage circuits, and also includes various control circuits, which is itself part of the chip design and needs to be verified. Therefore, usually, separate read / write verification and scanning of the storage module are performed.

[0048] To this end, the present invention proposes a method for chip verification space allocation, which can better verify the boundaries and special addresses, increase the completeness of chip verification, combine the verification of the address space and functional verification, realize automatic address allocation, and improve the verification efficiency.

[0049] The exemplary embodiments of the present invention will be described below with reference to the accompanying drawings.

[0050] Figure 1 The flowchart of the method for chip verification space allocation according to the exemplary embodiment is shown.

[0051] Refer to Figure 1 , in the process of chip verification, the method of the present invention obtains the starting address and address segment length of the configured address through random constraints to set the actual chip storage space used for calculation.

[0052] In S101, the address space of the chip storage circuit is divided into multiple address blocks, including: generating the starting address and block length for the address block in a random manner.

[0053] According to some embodiments, the address space boundary and white-box test points are extracted; according to the white-box test points, random constraints and functional coverage models are written. The white-box test points are the test points extracted according to the current actual circuit specifications and are actual and non-abstract.

[0054] According to some embodiments, using the random constraints, the weights of the boundaries and / or special addresses are increased, and the weights include empirical values. The random constraints are set according to the boundaries and white-box test points of the chip storage circuit. The starting address and address range of the configured address space are obtained through the random constraints; according to the starting address and the address segment length, the actual chip storage space used for calculation is set.

[0055] According to the verification scenario, the address space is divided into a predetermined number of blocks; the starting address and the address range of each address space block are randomly generated; using the random constraints, the weights of the boundaries and special addresses are increased. Different random constraints and weights are written according to the boundaries of the address space and the different chip select controls; the problem values are determined and the problem values are assigned specific weights, that is, higher weights.

[0056] For example, a storage space of 1K = 1024 bytes is not directly composed of a 1024-byte SRAM, but may be composed of multiple smaller SRAMs combined, such as 16 pieces of 64 bytes, or directly built by registers. In each case, the boundaries and chip select controls between multiple SRAMs are different, and different random constraints and weights can be written accordingly.

[0057] The weights are set by the verification personnel based on experience. The values most likely to have problems are determined and given higher weights. Generally, the boundaries of SRAM block splicing are special addresses. There may be other special addresses according to the actual circuit design, which need to be specifically identified.

[0058] In S103, at least one of the multiple address blocks is randomly allocated.

[0059] According to some embodiments, the multiple address blocks are shuffled, and the at least one address block is sequentially selected from the shuffled multiple address blocks. Refer to Figure 3 the flowchart of the method for selecting address blocks according to an example embodiment shown, and the address space scrambling process is performed in a simulation tool.

[0060] The storage circuit and the computing circuit need to cooperate. In high-level verification, the storage module is also included, but the storage circuit is abstracted and divided into relatively large granularities, only requiring it to cooperate with other modules to achieve functional verification. Dividing the address space into relatively large granularities means splitting the address space into relatively large blocks instead of fine-grained small blocks. For example, only looking at the capacity, an 8K byte storage circuit is abstracted as an array of 1024 * 8 bits and directly divided into two equal parts, with one half for input data and the other half for output data.

[0061] Accessing the same static random access memory (SRAM) with different starting addresses may trigger different row or bank conflicts of the simultaneously accessed SRAM, resulting in different timings for writing / reading data. Although it does not affect the reading and writing of SRAM simply, it may be incorrect when combined with the actual circuit function. For example, the actual circuit requires reading data in one clock cycle, but if the address is in an unaligned state, SRAM needs two clock cycles to read, which will cause a functional error. If the address is allocated in a simple aligned manner, this functional point may not be verified, resulting in the problem being overlooked. Another example is that the subsequent operation is to add the read data a and the read data b every clock cycle. If new data is read every cycle, the added data will constantly change; if a does not conflict and b conflicts and changes, the calculation result will not meet the expectation.

[0062] The address information for accessing the RAM is generated by other functional circuits, but the transfer process causes a mismatch in the bit width of some addresses and aligned access. For example, the data bit widths are different. For a 32-bit address, only 16 bits are left when transferred to the RAM. If accessing starts from 0, there is no difference, but if accessing starts from the position where the 17-bit address is valid, there is a difference. If the space is only allocated according to simple aligned addresses, the transfer problem of different addresses may not be discovered.

[0063] Therefore, it is necessary to disorder multiple address spaces and set the address spaces in combination with the functions to more completely verify the chip. The disordering process can be carried out in the simulation tool. After disordering, different address segments can be used. If stored in sequence, only the frontmost address segment may be used.

[0064] In S105, perform a functional verification simulation on the chip storage circuit using the at least one allocated address block.

[0065] According to some embodiments, perform dynamic address allocation on the at least one allocated address block using the memory allocation management component of the general verification methodology to automatically control the allocation and recycling of addresses. Set the actual chip storage space used according to the start address and block length of the at least one address block; perform use case testing on the actual chip storage space. The actual chip storage space includes a combination of multiple storage units or is directly built by registers, and the boundaries and chip select controls between the multiple storage units are different.

[0066] According to some embodiments, each storage unit includes a storage row, a predetermined number of storage unit storage groups, and a predetermined number of storage groups form a storage block. The boundaries of the chip storage circuit include the boundaries between the storage rows, the boundaries between the storage groups, and / or the boundaries between the storage blocks.

[0067] During the chip verification process, an address space with a determined capacity is usually allocated to the RAM, but the specific storage location of the data can be controlled by the environment itself. However, the same allocation process as the software is usually not used, but an allocation method is designed independently. Currently, the most commonly used verification method is to sequentially allocate several spaces according to the space size requirements or directly evenly divide the storage space.

[0068] According to some embodiments, after the address space is disordered, randomly verify any of the address spaces in various functional verification use cases to avoid that some address ranges cannot be verified due to the sequence. Perform dynamic address allocation on any of the address spaces to automatically control the allocation and recycling of addresses.

[0069] Use one or more disordered addresses for verification simulation, and in various functional verification use cases, random address spaces can be verified.

[0070] For example, assume that the on-chip storage RAM space used by the chip is 1024 bytes, which is composed of SRAM. The SRAM unit is 128-bit memory. Every 4 SRAM units form a group, with a total of 512 bits. There are 16 groups in total, divided into two blocks, with 8 groups in each block. Each time 4 groups of address subspaces are needed, then 4 groups are selected from the randomly generated 8 groups of subspaces each time. This can cover multiple blocks of addresses in the same group, across different groups, across SRAM blocks, etc. scenarios, and the address space generated at this time will not overlap, and there will be no error problems caused by data overwriting.

[0071] Assume that the chip has a requirement that all 4 groups of address spaces must be accessed within at most 2 clock cycles. The used SRAM has a limitation that within each group and each clock cycle, at most 1 access source is supported. When the 4 subspaces are randomly distributed to different groups, the simulation can pass. However, when more than 2 subspaces are randomly distributed to the same group, for example, 3 different access sources accessing the same group, it will take 3 clock cycles to complete, which does not meet the chip requirements and the simulation will fail, thus discovering register transfer level (RTL) problems.

[0072] In S107, collect the coverage rates of the starting addresses and block lengths of the address blocks according to the results of multiple randomizations. When the coverage rate reaches 100%, the functional verification simulation is completed.

[0073] According to some embodiments, the coverage rate is collected through simulation by writing a functional coverage model.

[0074] Preferably, on a randomly selected block of addresses, further use the UVM (Universal Verification Methodology) functional component UVM_MEM_MAM for dynamic address allocation, which can automatically control the allocation and recycling of addresses.

[0075] UVM_MEM_MAM is a component for memory management. It is mainly used to create and manage a block of address space in the Universal Verification Methodology (UVM) environment. This component can help users avoid some common errors when initializing the address space and provides a unified way to manage the life cycle of the address space. UVM_MEM_MAM is a component in UVM for address space management. It simplifies the initialization process of the address space and provides a unified interface to manage the address space. When using UVM for verification, reasonable use of these components can help verification engineers build and maintain the verification environment more efficiently.

[0076] The UVM_MEM_MAM tool can be used to manage the storage space. This tool can quickly convert the constraint information of the randomly obtained starting address and size of the space into array control information, so as to adapt to the UVM methodology and quickly complete the management of the address space.

[0077] By setting the start address (start_offset) and length of the address space (n_bytes) attributes of UVM_MEM_MAM, the randomly obtained constraint results can be realized. Then, by using the reserved address space region function (request_region), an address block that meets the constraints can be obtained. For example, for the above 8 sub-spaces, the following can be used:

[0078] uvm_mem_mam mam; uvm_mem_region regrion;

[0079] mam.n_bytes = 128; mam.start_offset = 16; mam.end_offset = 1024;

[0080] region = mam.request_region(8);

[0081] The following describes an exemplary embodiment according to the technical solution of the present invention.

[0082] Assume that the on-chip storage RAM space used by the chip is 1024 bytes and is composed of SRAM. The SRAM unit is 128-bit memory, and every 4 SRAM units form a group, with a total of 512 bits. There are 16 groups in total, divided into two blocks, with 8 groups in each block. Then, the main boundaries that can be recognized are the 128-bit line boundary (every integer multiple of 128 bits can be regarded as a boundary point), the 16 512-bit group boundaries, and the 2 block boundaries of the 8 groups.

[0083] Assume that the current access granularity is 8 bit = 1 byte, then set the starting address constraint for address allocation: address_start dist {0:=1, 15:=1, 16:=1, 31:=1, 32:=1, 47:=1, 48:=1, 63:=1, 64:=1, 8*64:=1, [1:1023]: / 1}, that is, the weight of each boundary point = 1, and the overall weight of the [1:1023] range = 1, so that the probability of the boundary point appearing is higher. Set the starting address to 11 different random values, and the appearance probability of each is 1 / 11, then the random weight of each boundary point is larger, and the random weight of the middle address in the [1:1023] range is smaller, making it easier to randomly reach the key boundary points.

[0084] Set the length constraint of the allocated address space: mem_size dist {[1:15]: / 1, 16: / 1, 32: / 1, 33: / 1, 48: / 1, 49: / 1, 64: / 1, 65: / 1, 128: / 1, 129: / 1, 192: / 1, 193: / 1, 256: / 1, 257: / 1, 512: / 1, 513: / 1, 1024: / 1, [1:1023]: / 1}. For example, if each line is 128 bit, then the 128-bit length just fills one line, while 129 bit just overflows 1 bit and needs to occupy 2 lines. These values are set according to the boundaries judged by the verifier himself, and the random appearance probability of a specific length is relatively large, making it easier to cover the boundary conditions.

[0085] The above combinations can cover different starting positions and cover the situation of occupying 1 block or multiple blocks of SRAM space each time, so that the functions under different SRAM combinations can be verified. For example, in a random case, if address_start = 16 (byte) and mem_size = 128 (byte) are obtained, then the ram space is divided into 8 sub-spaces. And each sub-control starts from address 16 + i * 128, where i is the number of the sub-space. At this time, each sub-space will span 3 groups. When simulating, shuffle the order of the 8 sub-spaces and randomly select one of them. For example, it is the address space from 16 to 144, that is, the boundary of the group can be covered. When using 400 - 528, the boundary of the SRAM block can also be covered.

[0086] At the same time, functional coverage modeling is performed on the starting address and the address space length. Through multiple random test cases, all boundary points and access combinations of the actual SRAM structure can be covered, thus realizing the simultaneous verification of the actual function and the SRAM structure characteristics. For example, there is a defect (bug) in the RTL. When the size is 128 bytes, it is considered to occupy the space of two groups, so only 2 chip selects are generated. Therefore, if the first two sequentially aligned spaces are always used, the error cannot be found; while in this embodiment, since it spans 3 address spaces, the error can be found. Another example is the read / write conflict control of multiple SRAMs. If there are no multiple allocation accesses, it may also be missed in testing.

[0087] Figure 2 A flowchart of a method for verifying dynamically allocated space according to an exemplary embodiment is shown.

[0088] In S201, extract the address space boundary and white-box test points.

[0089] The address space boundary refers to the starting address and the ending address of the storage space area in the storage space management system. In white-box testing, identifying these boundaries is to ensure the correct allocation, access, and release of the storage space area.

[0090] When extracting white-box test points, ensure that all code paths are tested, including loop, branch, and exception handling paths. For each function, test boundary conditions such as the maximum value, minimum value, zero value, etc. of the parameters. Test the storage space operation functions to ensure that they correctly handle boundary cases and test whether the storage space access is out of bounds.

[0091] In S203, according to the white-box test points, write random constraints and a functional coverage model.

[0092] Random constraints are used to guide the process of generating test data randomly, ensuring that the generated test data can cover specific test scenarios.

[0093] Writing random constraints and a functional coverage model according to the white-box test points is an important step to ensure the sufficiency and effectiveness of testing. Write random constraints and a functional coverage model for the storage space management module to ensure that functions such as storage space allocation, access, and release are comprehensively tested.

[0094] In S205, obtain the starting address point and address range of the configured address space through the random constraints.

[0095] By obtaining the starting address and address range of the configured address space through random constraints, it can be ensured that during the testing process, the generated test data can cover different address ranges and conform to the expected address space configuration. To work properly, some constants also need to be defined to specify the boundaries and size ranges of the address space.

[0096] In S207, according to the starting address and the length of the address segment, set the actual chip storage space used for calculation.

[0097] Setting the actual chip storage space used for calculation according to the starting address and the length of the address segment can be achieved by defining corresponding data structures and configuration parameters. First, define a data structure to represent the information of the storage space block, including the starting address and the length. Next, define a storage space management module for managing multiple storage space blocks and setting the storage space according to the given starting address and length. Create a storage space management instance according to the above definition and set the actual chip storage space. Through random constraints and coverage models, the correctness and robustness of the storage space management module under various boundary conditions can be ensured.

[0098] Figure 4 A block diagram of a computing device according to an exemplary embodiment is shown.

[0099] As Figure 4 shown, the computing device 30 includes a processor 12 and a memory 14. The computing device 30 may also include a bus 22, a network interface 16, and an I / O interface 18. The processor 12, the memory 14, the network interface 16, and the I / O interface 18 may communicate with each other through the bus 22.

[0100] The processor 12 may include one or more general-purpose CPUs (Central Processing Unit, processors), microprocessors, or application-specific integrated circuits, etc., for executing relevant program instructions. According to some embodiments, the computing device 30 may further include a high-performance display adapter (GPU) 20 for accelerating the processor 12.

[0101] The memory 14 may include machine system-readable media in the form of volatile memory, such as random access memory (RAM), read-only memory (ROM), and / or cache memory. The memory 14 is used to store one or more programs and data containing instructions. The processor 12 may read the instructions stored in the memory 14 to execute the methods according to the embodiments of the present invention above.

[0102] The computing device 30 may also communicate with one or more networks through the network interface 16. The network interface 16 may be a wireless network interface.

[0103] The bus 22 can include an address bus, a data bus, a control bus, etc. The bus 22 provides a path for exchanging information between components.

[0104] It should be noted that, in the specific implementation process, the computing device 30 may also include other components necessary for normal operation. In addition, those skilled in the art can understand that the above devices may also only include the components necessary to implement the solutions of the embodiments of this specification, and do not necessarily include all the components shown in the figure.

[0105] The present invention also provides a computer-readable storage medium, on which a computer program is stored. When the program is executed by a processor, the steps of the above method are implemented. The computer-readable storage medium may include, but is not limited to, any type of disk, including floppy disks, optical discs, DVDs, CD-ROMs, microdrives, and magneto-optical discs, ROMs, RAMs, EPROMs, EEPROMs, DRAMs, VRAMs, flash memory devices, magnetic or optical cards, nanosystems (including molecular memory ICs), network storage devices, cloud storage devices, or any type of medium or device suitable for storing instructions and / or data.

[0106] The embodiments of the present invention also provide a computer program product, which includes a computer program that can be operated to cause a computer to execute some or all of the steps of any one of the methods described in the above method embodiments.

[0107] Those skilled in the art can clearly understand that the technical solutions of the present invention can be implemented by means of software and / or hardware. The "units" and "modules" in this specification refer to software and / or hardware that can independently complete or cooperate with other components to complete specific functions, where the hardware can be, for example, a field-programmable gate array, an integrated circuit, etc.

[0108] It should be noted that, for the foregoing method embodiments, for the sake of simple description, they are all expressed as a series of action combinations. However, those skilled in the art should know that the present invention is not limited by the described action sequence, because according to the present invention, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily essential to the present invention.

[0109] In the above embodiments, the descriptions of each embodiment have their own emphases. For the parts not detailed in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0110] In several embodiments provided by the present invention, it should be understood that the disclosed device can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection between each other can be through some service interfaces. The indirect coupling or communication connection of the device or unit can be in electrical or other forms.

[0111] The units described as separate components may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0112] In addition, each functional unit in various embodiments of the present invention can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of a software functional unit.

[0113] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable memory. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a memory and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods in various embodiments of the present invention.

[0114] In the above embodiments, the descriptions of each embodiment have their own emphases. For the parts not detailed in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0115] The above specifically shows and describes the exemplary embodiments of the present invention. It should be understood that the present invention is not limited to the detailed structures, setting methods, or implementation methods described here; on the contrary, the present invention is intended to cover various modifications and equivalent settings included within the spirit and scope of the appended claims.

Claims

1. A method for verifying a storage circuit, the method comprising: The address space of the chip storage circuit is randomly divided into a plurality of address blocks, including: setting a starting address constraint of the address block, increasing the weight of the boundary and / or special address, the weight including an empirical value, and the random constraint is set according to the boundary and white box test point of the chip storage circuit; setting a block length constraint of the address block so that the random occurrence probability of a specific length is greater; generating a starting address and a block length for the address block in a random manner; randomly assigning at least one address block among the plurality of address blocks; Performing a functional verification simulation on the chip storage circuit using the at least one randomly allocated address block: setting the actual chip storage space used according to the starting address and block length of the at least one address block, and performing a use case test on the actual chip storage space; The coverage of the start address and block length of the address block is collected according to the results of multiple random operations, and the functional verification simulation is completed when the coverage reaches 100%.

2. The method according to claim 1, characterized in that Randomly allocating at least one address block among the plurality of address blocks, comprising: Arrange the multiple address blocks in random order; The at least one address block is sequentially selected from the plurality of address blocks arranged in random order.

3. The method according to claim 1, characterized in that Also includes: A memory allocation management component using a general verification methodology is used on the at least one allocated address block to perform dynamic address allocation and automatically control address allocation and recycling.

4. The method according to claim 1, characterized in that: The actual chip storage space includes a combination of multiple storage units, or is directly constructed by registers, and the boundaries and chip selection controls between the multiple storage units are different.

5. The method according to claim 4, characterized in that Each memory cell includes a memory row, a predetermined number of memory cells constitute a memory group, a predetermined number of memory groups constitute a memory block, and the boundaries of the chip memory circuit include boundaries between the memory rows, boundaries between the memory groups and / or boundaries between the memory blocks.

6. A computer program product, characterized in that The method comprises a computer program, which implements the method according to any one of claims 1 to 5 when being executed by a processor.

7. A computing device, characterized in that include: processor; as well as A memory storing a computer program, wherein when the computer program is executed by the processor, the method according to any one of claims 1 to 5 is implemented.

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