Automated ESD protection device layout design and layout-driven simulation method

Abstract

The present invention discloses an automated ESD protection device layout design and layout-driven simulation method. A parameterized ESD protection device unit layout is compiled using the Skill Script language based on device characteristics. The device layout is used as a photolithography mask to define the device geometry. The three-dimensional device is simulated in combination with process parameters prepared using a semiconductor process to complete device extraction for the front-end process (FEoL). The metal layer wiring of the back-end of line (BEoL) is extracted into a capacitance model or capacitance matrix using a wiring capacitance parameter extraction method. After the preparatory work is completed, the device layer and metal interconnect layer models are simulated using a Mix-Mode simulation method to further guide the design of an ESD protection device with excellent performance. The method of the present invention allows for automated design of ESD protection devices, and accurate extraction and simulation of models, significantly reducing the complexity of design optimization in the development of ESD protection devices and significantly shortening the development cycle.

Description

Technical Field

[0001] The present invention relates to the field of ESD protection on integrated circuit chips, and in particular to an ESD protection device design and simulation method. Background Art

[0002] Electrostatic discharge (ESD) protection design is essential for the reliability of integrated circuit chips. In actual circuit design, ESD protection devices must be placed on both the signal and power supply terminals to protect the internal functional circuits and isolate them from the outside world. ESD protection devices are the fundamental building blocks of ESD protection circuit modules. However, process flows and material parameters vary among semiconductor manufacturers, and the performance of ESD protection devices is highly dependent on process characteristics. Therefore, the design of ESD protection devices relies on manually laying out a large number of device structures for tapeout, followed by actual testing to understand the impact of process and layout structures on device protection performance. This development process is inefficient and requires extensive experience from the designer.

[0003] To address development efficiency issues and provide effective theoretical guidance for developing high-performance ESD protection devices, we have proposed a process approach: code drives the device cell layout, which serves as a geometrically defined photolithography mask and simulates the device's physical structure with process parameters. Layout capacitance extraction methods are used to extract the parasitic capacitance of metal interconnects. Finally, ESD device simulation is achieved using finite element device models and capacitor SPICE models. This approach automates the development of ESD protection devices and allows for model extraction and simulation at both the device and interconnect levels.

[0004] This method not only improves development efficiency, but also reduces the reliance on designer experience, providing a reliable technical means for the development of efficient and high-performance ESD protection devices. Summary of the Invention

[0005] In order to overcome the deficiencies of the prior art, the present invention aims to provide an automated ESD protection device layout design and layout-driven simulation method.

[0006] To achieve the above object, the technical solution adopted by the present invention is as follows:

[0007] An automated ESD protection device layout design and layout-driven simulation method, comprising the following steps:

[0008] Protection device selection and layout automation: Select the appropriate ESD protection device type based on the protection design standards and manufacturing process of the chip port; store the layout parameters of the selected device as a CDF parameter code module, and compile the device main module and geometric relationship function module; compile the Skill Script to encapsulate the device parameter unit code into a parameterized ESD device Pcell Layout, to achieve programming-driven layout automation; device layer structure simulation, using the ESD device layout as a photolithography mask to define the device geometry, combining the device geometry with process materials to generate a comprehensive device layer physical structure model, which includes device geometry information and material information of the preparation process to ensure the accuracy of the simulation model; metal interconnect SPICE capacitance model extraction, using the capacitance field solver, importing the physical information of the back-end preparation process and the metal layer wiring layout; according to the dielectric layer thickness, dielectric constant, metal line shape and height information of different metal layers, extract the parasitic capacitance model and capacitance value of the metal interconnect structure to the pad; the model's netlist synthesis connects the topological structure of the device layer model and the metal interconnect layer model, uses the Mix-Mode simulation method, builds a TLP pulse excitation source TestBench test platform, obtains the physical working state and static IV curve of the ESD protection device, and thus realizes the simulation of the ESD protection device.

[0009] The compiled Skill Script encapsulates the device parameter unit code into a parameterized ESD device Pcell layout: the parameter unit devices are the protection device from the I / O port to the gnd port, the protection device from the I / O port to the VDD port, and the power clamp protection device unit layout, and the device structure shape and structural features are encapsulated in the CDF parameter code module encapsulated in the Pcell.

[0010] In the Mix-Mode simulation method, the physical working state and static and dynamic IV curves of the ESD protection device are divided into four indicators: robustness, effectiveness, agility, and transparency according to the device performance, corresponding to the current and voltage of thermoelectric breakdown, the clamping voltage, the device's forward overshoot waveform, and parasitic capacitance; and are obtained from the device working waveform, static IV curve, and capacitance matrix under forward conditions of the simulation results.

[0011] The simulation method extracts the capacitance matrix of the Pcell metal line layout to analyze the parasitic self-capacitance and parasitic mutual capacitance, and optimizes the metal interconnection lines and metal interconnection line layout with parasitic problems in the layout.

[0012] Compared with the prior art, the present invention has the following advantages:

[0013] Through the method of the present invention, ESD protection devices can be designed automatically, and accurate extraction and simulation of models can be achieved, thereby providing optimized theoretical guidance for the ESD device layer structure and metal interconnection layer layout. This method realizes the parametric design of the layout through code drive, generates an accurate structural model in combination with process parameters, and uses finite element simulation and SPICE simulation to evaluate and optimize the electrical performance. This method improves design efficiency, reduces dependence on designer experience, and provides scientific and reliable technical support for the development of high-performance ESD protection devices. Through automated design of device layout, modular model extraction and layout-driven model simulation, the design optimization complexity in the development of ESD protection devices is greatly reduced, and the development cycle is significantly shortened. This method enables designers to quickly verify and iterate design solutions, improving the design efficiency and reliability of ESD protection devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a schematic diagram of the modular simulation process of ESD device layout automation and layout drive in the present invention.

[0015] Figure 2 It is a schematic diagram of the snapback curve and ESD protection window of the ESD protection device.

[0016] Figure 3 This is a diagram of the port-based ESD protection architecture.

[0017] Figure 4 This is a schematic diagram of ggNMOS and gdPMOS devices that implement finite element simulation of devices in combination with layout according to the present invention.

[0018] Figure 5 This is the Skill Pcell pseudo code for the present invention to realize the automated ESD protection device design.

[0019] Figure 6 It is a cross-sectional structural surface and layout diagram of the metal interconnect layer.

[0020] Figure 7 It is a parasitic transistor device of a ggNMOS device according to a specific embodiment of the present invention.

[0021] Figure 8 It is a ggNMOS equivalent circuit diagram that combines the device model of a specific embodiment of the present invention with the interconnect capacitance model. DETAILED DESCRIPTION

[0022] The following is a further description of the method of the present invention with reference to the accompanying drawings and specific embodiments, but the examples are not intended to limit the present invention. The development process of ESD protection design includes the following steps, as shown in the attached figure: Figure 1As shown in the figure: First, according to the ESD protection design standard of the chip, the signal characteristics of the protected port and the manufacturing process, select the appropriate device and power supply voltage clamping circuit; organize the structural parameters and process parameters that have a significant impact on the ESD protection performance into tables and arrays, and call them during the Pcell parameter adjustment and simulation verification; then, based on the logical relationship of the selected device structure, write code to generate parameterized layout units, store the layout structure parameters that affect the device performance as a device description format module, and compile the device main module to call the module and function module, through the Skill Script implements programming-driven automated Pcell layout; modular simulation is divided into finite element modeling of ESD protection device structure and SPICE numerical model extraction of metal interconnect parasitic capacitance according to process type; the device layer structure is extracted by using the layout to define the geometric structure photolithography mask, combining the device layout with the process flow to generate a comprehensive device layer structure. The simulation structure includes the device geometry information and material information of the preparation process to ensure the accuracy of the simulation model; the metal interconnect SPICE capacitance model is extracted using a capacitance field solver, importing the process information of the interconnect layer and the metal wiring layout. Based on information such as the dielectric layer thickness, dielectric constant and the height of different metal layers, combined with the metal line layout, the parasitic capacitance model and capacitance value of the entire device metal interconnect to the pad are extracted, and the output capacitance matrix is ​​used to identify problematic metal lines in the design; finally, by connecting the model's topological structure to integrate netlist simulation, the netlist links the device layer model and the metal interconnect layer model topology, and the Mix-Mode simulation method is used to obtain the physical working state and dynamic IV curve of the ESD protection device structure, realizing the simulation of the ESD protection device. This simulation process can accurately and reliably evaluate the device's operating performance under normal conditions.

[0023] Compared with the existing technology, the present invention has the following beneficial effects: automated design of device layout, modular model extraction and layout-driven model simulation, which reduces the complexity of design optimization for ESD protection device development and shortens the development cycle. Designers can use this method to verify the iterative design of the solution more quickly, thereby improving the design efficiency and reliability of ESD protection devices.

[0024] The first step in ESD design is to establish the ESD Design Window, as shown in the attached Figure 2 As shown: According to the technical requirements such as IO signal type, circuit function, device process, chip working status, etc., the chip normal working area, chip failure area and ESD device failure area are determined, and a design margin is left according to the process deviation; ensure that the ESD protection device operates within the ESD working window.

[0025] According to the protection requirements of the pins, the design is based on the Pad Based strategy, such as Figure 3As shown in FIG, I / O to power clamp devices, I / O to ground clamp devices, and Power Clamp devices are placed according to the position of the protected ports to provide protection for the connection between the chip and the PAD. The specific implementation example uses ggNMOS and gdPMOS, as shown in FIG. Figure 4 shown.

[0026] ggNMOS and gdPMOS serve as ESD protection devices for IO ports to power and IO ports to ground. The parameters that affect device characteristics are "channel length (L), device width (W), device insertion index (M), and SAB layer (B)." These four sets of structural parameters are used to characterize the parameterized unit shape and structural characteristics.

[0027] The Pcell unit is written in Skill script language. The Pcell component is divided into: structure parameter file (Device.cdf), logic operation callback function file (Device.callback), main function module file (Device.il, Figure 5 The automated layout generation method compiles the Skill language into layout files for different device parameters. Parameters are stored as lists and classes. Device structure parameters are added to the corresponding structure parameter file (ggNMOS.cdf). Callback functions involved in calculations are placed and called from the main function block (ggNMOS.il), which is written as a parameter library. The main function block serves as the main program body, implementing device logic relationships and logically calling physical geometric parameters.

[0028] The generated device layout is used as a mask for device geometry definition. Combined with the semiconductor process flow for device preparation, a finite element model of the device is simulated. The model contains the main information such as junction depth, doping concentration, device morphology, and device size.

[0029] The cross-section and top view of the metal interconnect layer are as follows: Figure 6 As shown in the figure, the metal layer wires act on the connection between the device end electrodes and the device layer and the external connection. There are parasitic effects between the wires. In this design method, since the electrostatic event is an instantaneous large current pulse of the picosecond level, the parasitic capacitance affects the discharge voltage of the ESD device. Therefore, the metal interconnection layer at both ends of the anode and cathode is extracted as a parasitic capacitor, and the physical metal end is mapped to a capacitor model.

[0030] The method for extracting the metal interconnect capacitance model of ESD devices uses a field solver. The solver is fast and accurate in extracting small-scale metal interconnects, and can also perform calculations based on the dielectric constant of the interlayer dielectric.

[0031] The ESD protection device port consists of two ends. The ESD current flowing into the device is defined as the anode, and the ESD current flowing out of the device is defined as the cathode. The metal interconnection line is connected from the device layer to the cathode pad and the anode pad, and the port capacitance is extracted as C anode 、C cathode The typical rise time of a current pulse (ESD) passing through a short-circuited wire is 10ns on average, and is slower for higher resistive loads. Therefore, when designing interconnects, it is necessary to minimize parasitic capacitance while ensuring connection quality, thereby maximizing the ESD stress that ESD protection devices can withstand.

[0032] The finite element device model and capacitor numerical model extracted in step 6 and step 8 describe the topology through the netlist. The corresponding effects of the finite element model and the capacitor model are as follows: Figure 8 shown.

[0033] Mix-Mode simulation uses a netlist to simulate the overall structure of the ESD protection device. Taking the ggNMOS as an example, a snapback curve can be obtained. Since the electrostatic current release principle is based on the device's parasitic transistor operation, the purpose of finite element model extraction is to reproduce the device and explain its physical mechanism and device breakdown process through simulation.

[0034] The ggNMOS device curve obtained by Mix-Mode simulation method is as follows Figure 2 As shown, the three turning points on the curve and the slope of the curve include the starting voltage V t1 , starting current I t1 , maintain voltage V h , holding current I h and thermal failure voltage V t2 , thermal failure current I t2 , on-resistance R on wait.

[0035] The design of ESD devices has four dimensions: robustness, effectiveness, agility, and transparency. Robustness is defined as the ESD level at which the ESD protection alone can withstand electrostatic stress and fail; effectiveness describes the ESD protection network's ability to limit the voltage to a safe level. BD Under (such as Figure 2 ) to prevent failure of the protected circuitry connected in parallel with the ESD protection. Agility describes the voltage clamping speed of the ESD device. Transparency indicates that the ESD protection does not affect I / O parameters and specifications such as capacitance and leakage. This simulation method can quantify the device characteristics of the design and find a layout that meets the design requirements.

[0036] The device simulation curve can be combined with the process parameters to obtain the device equivalent circuit through analysis. The equivalent circuit can explain the working mechanism of the device layout. The device equivalent circuit is as follows: Figure 7 shown.

[0037] The ggNMOS equivalent circuit analysis method is as follows: When the ESD device is subjected to ESD stress, the I / O port voltage increases until it reaches the drain-gate junction avalanche breakdown voltage of the ggNMOS. At this time, the hole current I generated by the reverse PN junction avalanche ionization gen A part of it forms a recombination current I in the P well by minority carrier recombination. b , the other part of the current I sub The parasitic well resistance R through the P well well Flows to the substrate end to ground. sub The voltage drop V caused by the parasitic well resistance Rwell Once the forward bias voltage between the base and emitter of the parasitic transistor is reached, the parasitic transistor turns on and discharges the ESD current I d Due to the current amplification effect of the transistor, after the device is turned on, the drain can maintain avalanche breakdown at a low voltage, so the drain voltage decreases and the ggNMOS experiences hysteresis. When hot spots accumulate on the device, the device or metal layer partially melts, causing device damage. t2 available.

[0038] According to the simulation results of the device layer and metal wire layer, Figure 8 As shown in FIG, by analyzing the equivalent circuit of the complete structure, the influence of the entire structure on the ESD protection performance can be revealed, and the working state of the structure in the electrostatic discharge environment can be explained.

[0039] In summary, the device layout design automation and layout-driven simulation method of the process of the present invention reduce the time cost of ESD device design. The device simulation method directly explains the physical properties and working mechanism of the device; this device development method provides good guidance for designers.

[0040] The embodiments described above may be further combined with other tools or replaced with different devices. The embodiments are merely descriptions of preferred embodiments of the present invention and do not limit the concept and scope of the present invention. Various changes and improvements made by ordinary technicians in this field to the technical solutions of the present invention without departing from the design concept of the present invention are within the scope of protection of the present invention. The scope of protection of the present invention is given by the appended claims and any equivalents thereof.

Claims

1. A method for simulating and automating the layout design and layout driving of an ESD protection device, characterized in that the steps include: Protection device selection and layout automation: Select the appropriate ESD protection device type based on the chip port protection design standards and manufacturing process; Store the layout parameters of the selected device as a CDF parameter code module, and compile the device main module and geometric relationship function module; Compile the Skill Script to encapsulate the device parameter unit code into a parameterized ESD device Pcell layout, realizing programming-driven layout automation; Device layer structure simulation: Use the ESD device layout as a photolithography mask to define the device geometry, combine the device geometry with process materials, and generate a comprehensive device layer physical structure model. This model includes device geometry information and material information of the preparation process to ensure the accuracy of the simulation model; extract the metal interconnect SPICE capacitance model: Use a capacitance field solver to import the physical information of the subsequent preparation process and the metal layer wiring layout; Based on the dielectric layer thickness, dielectric constant, metal line shape and height information of different metal layers, extract the parasitic capacitance model and capacitance value of the metal interconnect structure to the pad; The model's netlist integrates the topological structure of the connection device layer model and the metal interconnect layer model, and uses the Mix-Mode simulation method to build a TLP pulse excitation source TestBench test platform to obtain the physical working state and static IV curve of the ESD protection device, thereby realizing the simulation of the ESD protection device.

2. The simulation method according to claim 1, wherein: The compiled Skill Script encapsulates the device parameter unit code into a parameterized ESD device Pcell layout: the parameter unit devices are the protection device from the I / O port to the gnd port, the protection device from the I / O port to the VDD port, and the power clamp protection device unit layout, and the device structure, shape, and structural features are encapsulated in the CDF parameter code module encapsulated in the Pcell.

3. The simulation method according to claim 1, wherein: In the Mix-Mode simulation method, the physical working state and static and dynamic IV curves of the ESD protection device are divided into four indicators: robustness, effectiveness, agility, and transparency according to the device performance, corresponding to the current and voltage of thermoelectric breakdown, the clamping voltage, the device's forward overshoot waveform, and parasitic capacitance; and are obtained from the device working waveform, static IV curve, and capacitance matrix under forward conditions of the simulation results.

4. The simulation method according to claim 3, wherein: Extract the capacitance matrix from the Pcell metal line layout to analyze the parasitic self-capacitance and parasitic mutual capacitance, and optimize the metal interconnect lines and metal interconnect line layout with parasitic problems in the layout.

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