Integrated circuit wiring method, system, electronic device and storage medium

Abstract

The present invention provides a wiring method, system, electronic device and storage medium of an integrated circuit, which relates to the technical field of integrated circuits. The method comprises: matching bumps between chip grains according to the number of first signal connections to obtain multiple first matching bump pairs; matching bumps between different chip grains and interposers according to the number of second signal connections to obtain multiple second matching bump pairs; grouping multiple first matching bump pairs to obtain bump groups, matching bumps between different chip grains in the bump groups to obtain first connection relationships between different chip grains; dividing multiple second matching bump pairs into regions to obtain second connection relationships between different chip grains and interposers; wiring between different chip grains according to the first connection relationship, and wiring between different chip grains and the interposer according to the second connection relationship. The present invention can effectively reduce the crossover and total wiring lengths, and significantly improve wiring efficiency.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a wiring method, system, electronic equipment and storage medium for an integrated circuit. Background Art

[0002] 2.5D integrated circuit technology is an important innovation in the field of modern semiconductor packaging. It significantly enhances the connection capability and flexibility between chips and packages by introducing an interposer. 2.5D integrated circuits integrate multiple bare chips on an interposer, which is covered with an array of microbumps. These microbumps are connected to the bumps on the corresponding I / O pin array on the chip through precise docking technology. The bumps on the interposer are also connected to the package I / O pins, which are usually located in areas with restricted layout. The design of these areas takes into account the layout requirements of silicon vias, which are vertical channels inside the interposer used to connect different metal layers, and are used to connect the bumps to the metal layer of the interposer.

[0003] When multiple chips can be mounted on the interposer, the connections between the chips are routed on the network rewiring layer, which is one or more layers of metal lines on the interposer for signal transmission and interconnection between chips. Bumps are important connection points between the chip and the package. They are usually arranged in a grid pattern on the network rewiring layer, and advanced algorithms and technologies are usually used to ensure the precise layout and connection of the bumps. However, current bump matching methods are all focused on bump matching between individual chips and routing of the network rewiring layer, and cannot solve the global bump matching and routing problem between the chip and the interposer in 2.5D integrated circuits. Summary of the invention

[0004] In view of the above-mentioned deficiencies in the prior art, the present invention provides a wiring method, system, electronic device and storage medium for an integrated circuit, which effectively solves the problem of global matching wiring of bumps between a chip and an interposer in a 2.5D integrated circuit.

[0005] In a first aspect, the present invention provides a wiring method for an integrated circuit, wherein the integrated circuit comprises an interposer and at least two chiplets, wherein at least two chiplets are arranged on the interposer, and the method comprises:

[0006] Matching the bumps between the chip dies according to the first signal connection quantity to obtain a plurality of first matching bump pairs between different chip dies;

[0007] Matching the bumps between different chip dies and the interposer according to the second signal connection quantity to obtain a plurality of second matching bump pairs between different chip dies and the interposer;

[0008] Grouping the plurality of first matching bump pairs to obtain a bump group, matching the bumps between different chip particles in the bump group to obtain a first connection relationship between different chip particles;

[0009] Dividing the plurality of the second matching bump pairs into regions to obtain second connection relationships between different chip dies and the interposer;

[0010] Wiring is performed between different chip dies according to the first connection relationship, and wiring is performed between different chip dies and the interposer according to the second connection relationship.

[0011] Furthermore, the first signal connection number is the total number of bump signal connections between at least two of the chip dies, and the second signal connection number is the total number of bump signal connections between different chip dies and the interposer.

[0012] Further, at least two of the chip dies are respectively a first chip dies and a second chip dies, and the bumps between the chip dies are matched according to the first signal connection quantity to obtain a plurality of first matching bump pairs between different chip dies, including:

[0013] Establishing position coordinates according to the bump arrays of the first chip die and the second chip die;

[0014] Acquire first bump position information of a first bump in the first chip, and determine a second bump in the second chip that is closest to the first bump according to the first bump position information;

[0015] Determine a third bump in the first chip that is closest to the second bump according to the second bump position information of the second bump, and if the third bump is not the same bump as the first bump, continue to search for a bump in the second chip that is closest to the third bump until the bumps in the first chip and the second chip are a bump pair that is closest to each other, and determine the bump pair as a first matching bump pair;

[0016] The same number of the first matching bump pairs is determined according to the first signal connection number.

[0017] Further, the determining, according to the first bump position information, the second bump in the second chip that is closest to the first bump includes:

[0018] If the first target bump in the second chip that is closest to the first bump is not matched, use the first target bump as the second bump;

[0019] If the first target bump has been matched, a second target bump that is closest to the first target bump and has not been matched is used as the second bump.

[0020] Furthermore, matching the bumps between different chip dies and the interposer according to the second signal connection quantity to obtain a plurality of second matching bump pairs between different chip dies and the interposer includes:

[0021] Establishing position coordinates according to the chip die and the bump array of the interposer;

[0022] Acquire fourth bump position information of a fourth bump in the chip particle, and determine a fifth bump in the interposer that is closest to the fourth bump according to the fourth bump position information;

[0023] Determine a sixth bump in the chip that is closest to the fifth bump according to the fifth bump position information of the fifth bump, and if the sixth bump is not the same bump as the fourth bump, continue to search for a bump that is closest to the sixth bump in the interposer until the chip and the bumps in the interposer are a bump pair that are closest to each other, and determine the bump pair as a second matching bump pair;

[0024] The same number of the second matching bump pairs is determined according to the second signal connection number.

[0025] Furthermore, the step of grouping the plurality of first matching bump pairs to obtain a bump group, matching the bumps between different chip particles in the bump group, and obtaining a first connection relationship between different chip particles includes:

[0026] The bumps of the first chip die in the plurality of the first matching bump pairs are taken as a first point set, and the bumps of the second chip die in the plurality of the first matching bump pairs are taken as a second point set;

[0027] Dividing the convex blocks in the first point set into a plurality of convex block groups according to coordinates, and sorting the convex blocks in the second point set according to coordinates;

[0028] Distribute the bumps in the second point set to the bump groups with the closest distances according to the order, until the number of the bumps in the first point set and the number of the bumps in the second point set in all the bump groups is equal;

[0029] According to the matching of the bumps in the first point set in each of the bump groups with the bumps closest to the second point set, until all the bump groups complete the matching of the bumps, a first connection relationship between different chip dies is obtained.

[0030] Furthermore, the step of dividing the plurality of second matching bump pairs into regions to obtain a second connection relationship between different chip dies and the interposer includes:

[0031] Using a linear scanning algorithm to divide the area where the second matching convex block pair is located into equal-size segments to obtain a plurality of sub-areas, each of which includes one convex block;

[0032] Constructing a balanced binary tree, using leaf nodes of the balanced binary tree to represent the plurality of sub-regions;

[0033] Determine a corresponding chip region and an interposer region according to the position of the bump in the sub-region in the balanced binary tree;

[0034] Traversing the balanced binary tree to establish a set mapping relationship between the chip region and the interposer region;

[0035] Connections are allocated according to the set mapping relationship to obtain a second connection relationship between the chip die and the intermediate layer.

[0036] In a second aspect, the present invention provides a wiring system for an integrated circuit, wherein the integrated circuit comprises an interposer and at least two chiplets, wherein at least two chiplets are arranged on the interposer, and the system comprises:

[0037] A first matching module, used for matching the bumps between the chip dies according to the first signal connection quantity, to obtain a plurality of first matching bump pairs between different chip dies;

[0038] A second matching module, used for matching the bumps between different chip dies and the interposer according to the second signal connection quantity, to obtain a plurality of second matching bump pairs between different chip dies and the interposer;

[0039] A first processing module, configured to group the plurality of first matching bump pairs to obtain a bump group, match the bumps between different chip particles in the bump group, and obtain a first connection relationship between different chip particles;

[0040] A second processing module, configured to divide the plurality of second matching bump pairs into regions to obtain second connection relationships between different chip dies and the interposer;

[0041] The circuit wiring module is used to perform wiring between different chip dies according to the first connection relationship, and to perform wiring between different chip dies and the intermediate layer according to the second connection relationship.

[0042] In a third aspect, the present invention provides an electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the wiring method of the integrated circuit as described in the first aspect of the present invention.

[0043] In a fourth aspect, the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the wiring method for an integrated circuit as described in the first aspect of the present invention.

[0044] The wiring method, system, electronic device and storage medium of the integrated circuit provided by the present invention convert the bump matching problem of the chip in the integrated circuit into the matching problem between the point sets, and regard the bumps on each chip as points in the two-dimensional space, each point having a specific position coordinate. Potential matching pairs are determined by calculating the distance between the points. Since the bumps are evenly distributed on the network rewiring layer, the search advantage of the two-dimensional matrix grid can be used to quickly find the nearest bump pairs. At the same time, the matching process is carried out synchronously between each chip, and an effective conflict resolution strategy is used to avoid falling into a local optimal solution. The matching bump pairs are divided into two categories according to the connection relationship. For the bump sets without overlap, they are matched in groups and rematched within the groups, which is conducive to maintaining the locality and consistency of the matching. For the bump sets with overlap, a partition matching strategy is adopted, and all connections are allocated according to the partition result set mapping relationship between the bumps to ensure the accuracy and completeness of the matching. Through reasonable matching and partitioning strategies, the crossover and total wiring lengths are effectively reduced, and the wiring efficiency of the network rewiring layer is significantly improved, which has broad application prospects and potential economic value. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0046] Figure 1 It is a first schematic diagram of the process of the wiring method of the integrated circuit provided by the embodiment of the present invention;

[0047] Figure 2 It is a schematic diagram of the distribution of interposers and chip particles of an integrated circuit in an embodiment of the present invention;

[0048] Figure 3 is a second schematic diagram of the wiring method flow of an integrated circuit provided by an embodiment of the present invention;

[0049] Figure 4is a third schematic diagram of the process of the wiring method of the integrated circuit provided by the embodiment of the present invention;

[0050] Figure 5 is a fourth schematic diagram of the process of the wiring method of the integrated circuit provided by the embodiment of the present invention;

[0051] Figure 6 is a schematic diagram of allocation of non-overlapping convex block sets in an embodiment of the present invention;

[0052] Figure 7 is a fifth schematic diagram of the process of the wiring method of the integrated circuit provided by the embodiment of the present invention;

[0053] Figure 8 is a schematic diagram of allocation of overlapping bump sets in an embodiment of the present invention;

[0054] Fig. 9 is a schematic diagram of the structure of a wiring system for an integrated circuit provided by an embodiment of the present invention;

[0055] Fig.10 It is a structural schematic diagram of an electronic device in an embodiment of the present invention.

[0056] Description of main component symbols:

[0057] 900, wiring system of integrated circuit; 910, first matching module; 920, second matching module; 930, first processing module; 940, second processing module; 950, circuit wiring module; 1000, electronic device; 1010, processor; 1020, communication interface; 1030, memory; 1040, communication bus. DETAILED DESCRIPTION

[0058] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be further clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. It should be noted that the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0059] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0060] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used in this specification are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0061] 2.5D integrated circuits integrate multiple bare chips on an interposer, and the connections between the chips are routed on a network rewiring layer, which is one or more layers of metal lines on the interposer, used to achieve signal transmission and interconnection between chips. Bumps are important connection points between the chip and the package. They are usually arranged in a grid pattern on the network rewiring layer, and advanced algorithms and technologies are usually used to ensure the precise layout and connection of the bumps. However, current bump matching methods are all focused on bump matching between individual chips and routing of the network rewiring layer, and cannot solve the global bump matching and routing problem between the chip and the interposer in 2.5D integrated circuits.

[0062] Example 1

[0063] The embodiment of the present invention provides a wiring method for an integrated circuit, which effectively solves the problem of global matching wiring of bumps between a chip and an interposer in a 2.5D integrated circuit. The integrated circuit includes an interposer and at least two chip particles, wherein the at least two chip particles are arranged on the interposer. Figure 1 FIG. 1 is a first schematic diagram of a wiring method for an integrated circuit provided by an embodiment of the present invention. Figure 1 As shown, the method comprises the following steps:

[0064] S100 , matching bumps between chip dies according to the first signal connection quantity to obtain a plurality of first matching bump pairs between different chip dies.

[0065] In an embodiment of the present invention, the integrated circuit is a 2.5D integrated circuit, and the 2.5D integrated circuit includes three chip dies and an intermediate layer that can cover the three chip dies. Figure 2 Schematic diagram of the distribution of the interposer and chip particles of an integrated circuit in an embodiment of the present invention. Figure 2 As shown, the chip A, chip B and chip C of the integrated circuit respectively cover their own chip bump arrays, and the interposer I covers the interposer bump array.

[0066] The first signal connection number is the total bump signal connection number between at least two chip dies. In the embodiment of the present invention, it is assumed that the bump signal connection number between chip die A and chip die B is n 1. The number of bump signal connections between chip A and chip C is n 2. The number of bump signal connections between chip B and chip C isn 3, then the number of first signal connections is n 1+ n 2+ n 3.

[0067] Figure 3 is a second schematic diagram of the wiring method flow of an integrated circuit provided by an embodiment of the present invention, such as Figure 3 As shown, a breadth-first algorithm is used to find a pair of bumps with the shortest distance between chip particles as a first matching bump pair. The acquisition of the first matching bump pair includes the following steps:

[0068] S110 , establishing position coordinates according to the bump arrays of the first chip die and the second chip die.

[0069] In an embodiment of the present invention, chip A and chip B are used as the first chip and the second chip respectively. Since the bump array of the chip is a regular matrix grid, coordinates with equal spacing can be set in the X and Y directions to form a two-dimensional coordinate system, and each bump has a unique index coordinate to represent the position information of the bump.

[0070] S120 , obtaining first bump position information of a first bump in the first chip die, and determining a second bump in the second chip die that is closest to the first bump according to the first bump position information.

[0071] Optionally, select any bump from chip A a 1 as the first bump, through the bump a 1 The first bump position information can determine the bump a 1 is the index of chip B, the bump corresponding to this index b 1 is the bump in chip B away from chip A a 1 The nearest bump, move the bump b 1 as the second bump. If the chip B is separated from the bump a 1 is not matched, the first target bump is used as the second bump; if the first target bump is matched, the second target bump that is closest to the first target bump and not matched is used as the second bump. In the embodiment of the present invention, the first target bump is the bump b 1.

[0072] S130, determining a third bump in the first chip that is closest to the second bump according to the second bump position information of the second bump, and if the third bump is not the same bump as the first bump, continue to search for a bump in the second chip that is closest to the third bump until the bumps in the first chip and the second chip are a bump pair that is closest to each other, and determine the bump pair as a first matching bump pair.

[0073] Determine the bumpb 1 is the second bump, and the bump b 1 The second bump position information determines the bump b 1. Remove the bump from chip A b 1The nearest bump a 2. Place the bump a 2 as the third bump. If the third bump and the first bump are not the same bump, continue to repeat the above steps to find the bump closest to the third bump in chip B until the bumps in chip A and chip B are the closest bump pair to each other, and finally determine the bump pair as a first matching bump pair.

[0074] Optionally, the steps S120-S130 can also be used to determine the closest bump pair in chip A and chip C. Assuming that the bump pair is bump a 3 and bump c3, and the closest bump pair in chip A and chip B is bump a 1 and bump b 1. If the bump a 1 and bump a 3 If there is a conflict, find a convex block a 3 and bump c 3 The closest bump pair outside: bump a 3 ， and bumps c 3 ， , and bump removal a 1 and bump b 1 The closest bump pair other than bump a 1 ， and bumps b 1 ， Then calculate the convex a 1 and bump b 1 distance to the bump a 1 ， and bumps b 1 ， The first difference d1 of the distance is calculated while the bump a 3 and bump c 3 Distance and Bump a 3 ， and bumps c 3 ， If the first difference d1 is smaller than the second difference d2, then the bump a 1 ， and bumps b 1 ， Matched as a first mating bump pair, the bump a 3 and bump c3 is matched as another first matching bump pair. If the first difference d1 is greater than the second difference d2, then the bump a 1 and bump b 1 matches as the first matching bump pair, bump a 3 ， and bumps c 3 ， Similarly, the above steps can be used to determine a plurality of first matching bump pairs of chip B and chip C.

[0075] S140 , determining a same number of a plurality of first matching bump pairs according to the number of first signal connections.

[0076] In the embodiment of the present invention, three first matching bump pairs can be obtained after each cycle, and the above steps S110-S130 are repeated until the number of first matching bump pairs between chip die A, chip die B and chip die C meets the first signal connection number.

[0077] S200 , matching bumps between different chip dies and interposers according to the second signal connection quantity to obtain a plurality of second matching bump pairs between different chip dies and interposers.

[0078] The second signal connection number is the total number of bump signal connections between different chip dies and interposers. Assume that the number of bump signal connections between chip dies A, chip dies B, and chip dies C and interposer I are n 4. n 5 and n 6, then the number of second signal connections is n 4+ n 5+ n 6. Figure 4 is a third schematic diagram of the wiring method flow of an integrated circuit provided by an embodiment of the present invention, such as Figure 4 As shown, the breadth-first algorithm is also used to find the bump pair with the shortest distance between the chip and the interposer as the second matching bump pair. The acquisition of the second matching bump pair includes the following steps:

[0079] S210 , establishing position coordinates according to the chip die and the bump array of the interposer.

[0080] Since the bump array of the interposer layer I is also a regular matrix grid, a two-dimensional coordinate system can also be constructed, and each bump has a unique index coordinate to represent the position information of the bump.

[0081] S220 , obtaining fourth bump position information of a fourth bump in the chip particle, and determining a fifth bump in the interposer that is closest to the fourth bump according to the fourth bump position information.

[0082] Optionally, select any bump from chip A a 4 as the fourth bump, through the bump a The fourth bump position information of 4 can determine the bump a 4 Index in interposer layer I, the bump corresponding to this index i 1 is the bump of chip A in the interposer a 4 The nearest bump, move the bump i 1 as the fifth bump. Wherein, if the intermediate layer 1 is separated from the bump a If the third target bump closest to the first target bump is not matched, the third target bump is used as the fifth bump; if the third target bump is matched, the fourth target bump closest to the first target bump and not matched is used as the fifth bump. In the embodiment of the present invention, the third target bump is the bump i 1.

[0083] S230, determining a sixth bump in the chip grain that is closest to the fifth bump according to the fifth bump position information of the fifth bump, and if the sixth bump is not the same bump as the fourth bump, continue to search for a bump in the interposer that is closest to the sixth bump until the chip grain and the bumps in the interposer are a bump pair that are closest to each other, and determining the bump pair as a second matching bump pair.

[0084] Determine the bump i 1 is the fifth bump, and the bump i 1 The fifth bump position information determines the bump i 1. Remove the bump from chip A i 1The nearest bump a 6. Place the bump a 6 is used as the sixth bump. If the sixth bump and the fourth bump are not the same bump, the above steps are continued to be repeated to find the bump closest to the sixth bump in the interposer I until the chip A and the bumps in the interposer I are the bump pair closest to each other, and finally the bump pair is determined as a second matching bump pair.

[0085] Optionally, steps S220-S230 can also be used to determine the closest bump pairs between chip B and interposer I, and between chip C and interposer I. Similarly, the method for handling bump conflicts between chip particles can be used to handle bump conflicts between chip particles and interposers, thereby determining multiple second matching bump pairs.

[0086] S240 , determining a plurality of second matching bump pairs of the same number according to the second signal connection number.

[0087] In the embodiment of the present invention, three second matching bump pairs can be obtained after each cycle, and the above steps S210-S230 are repeated until the number of second matching bump pairs between chip A, chip B, chip C and interposer I meets the second signal connection number.

[0088] S300, grouping a plurality of first matching bump pairs to obtain a bump group, matching bumps between different chip dies in the bump group, and obtaining a first connection relationship between different chip dies.

[0089] The first matching bump pairs are classified according to the connection relationship between different chiplets. The first matching bump pairs of chiplets A and B are classified into one category, the first matching bump pairs of chiplets A and C are classified into one category, and the first matching bump pairs of chiplets A and B are classified into one category. All connection relationships can be divided into two categories, one is the bump connection between chiplets, and the other is the bump connection between chiplets and interposers. In order to improve the routable linearity of the network rewiring layer and reduce the wiring crossover and wiring length, all bump pairs corresponding to each type of connection relationship are re-matched.

[0090] Figure 5 4 is a fourth schematic diagram of the wiring method flow of an integrated circuit provided by an embodiment of the present invention. Figure 5 As shown, the re-matching of the bump connections between the chip dies includes the following steps:

[0091] S310 , taking bumps of a first chip die among a plurality of first matching bump pairs as a first point set, and taking bumps of a second chip die among a plurality of first matching bump pairs as a second point set.

[0092] For the re-matching of bump connections between chip dies, since there is no overlap between the chip dies, the plurality of first matching bump pairs between the chip dies can be divided into non-overlapping point sets. Figure 6 is a schematic diagram of allocation of non-overlapping bump sets in an embodiment of the present invention, such as Figure 6 As shown, the bumps of chip A are taken as the first point set X, and the bumps of chip B are taken as the second point set Y.

[0093] S320, dividing the convex blocks in the first point concentration into a plurality of convex block groups according to the coordinates, and sorting the convex blocks in the second point concentration according to the coordinates.

[0094] If the second point set Y is on the upper and lower sides of the first point set X, the first point set X is divided into n groups of convex blocks according to the horizontal coordinate, and the convex blocks in the second point set Y are sorted according to the horizontal coordinate to form a convex block queue. If the second point set Y is on the left and right sides of the first point set X, the first point set X is divided into n groups of convex blocks according to the vertical coordinate, and the convex blocks in the second point set Y are sorted according to the vertical coordinate to form a convex block queue.

[0095] S330, distributing the convex blocks in the second point set to the convex block groups with the closest distances according to the order, until the number of convex blocks in the first point set and the number of convex blocks in the second point set in all convex block groups are equal.

[0096] The bumps in the second point set Y are taken out from the bump queue in order and assigned to the nearest bump group G1 in the first point set X. If the number of bumps in the first point set X in the bump group G1 is equal to the number of bumps in the second point set Y, it means that the bump group G1 can no longer accommodate other bumps in the second point set Y. At this time, it is necessary to replace the bump in the second point set Y with the largest horizontal coordinate or vertical coordinate in the current bump group from the bump group G1, and add the replaced bumps back to the queue. Repeat the above steps until all the bumps in the second point set Y are assigned to each bump group in the first point set X.

[0097] S340, matching the bumps in the first point set in each bump group with the bumps closest to the second point set until all bump groups complete bump matching, thereby obtaining a first connection relationship between different chip dies.

[0098] Each bump group is redistributed, and each bump group is divided into two parts, L and R, according to the horizontal coordinates of the bumps in the first point set X, and bumps are alternately selected from L and R and the nearest bumps in the second point set Y in the bump group for final matching, until all bump groups complete bump matching. Alternatively, each bump group is divided into two parts, L and R, according to the horizontal coordinates of the bumps in the first point set X, and bumps are alternately selected from L and R and the nearest bumps in the second point set Y in the bump group for final matching, until all bump groups complete bump matching. Through the above steps S310-S340, the first connection relationship between the three chip particles can be obtained.

[0099] S400 , dividing the plurality of second matching bump pairs into regions to obtain second connection relationships between different chip dies and the interposer.

[0100] For the re-matching of the bumps between the chip die and the interposer, since the interposer and the chip die overlap, a linear scanning algorithm is used to perform area separation for re-matching. Figure 7 5 is a fifth schematic diagram of the wiring method flow of an integrated circuit provided by an embodiment of the present invention. Figure 7 As shown, the re-matching of the bumps between the die and the interposer includes the following steps:

[0101] S410 , using a linear scanning algorithm to divide the region where the second matching convex block pair is located into equal-size segments to obtain a plurality of sub-regions, each of which includes a convex block.

[0102] Figure 8 Schematic diagram of the allocation of overlapping bump sets in an embodiment of the present invention. Figure 8As shown, a scan line (which can be horizontal or vertical) is used to scan the entire area where the second matching bump pair is located from one end to the other, and the bump boundaries that intersect with the scan line are recorded during the scanning process. A suitable segmentation point is selected according to the position of the bump, and the area where the second matching bump pair is located on the network redistribution layer is divided into two smaller areas, and the number of bumps in one smaller area is almost equal to the number of bumps in the other smaller area. By adopting an equal-size segmentation process, the area where the second matching bump pair is located can be recursively divided into several smaller sub-areas, and each sub-area contains only one bump.

[0103] S420: Construct a balanced binary tree, and use leaf nodes of the balanced binary tree to represent multiple sub-regions.

[0104] A balanced binary tree is constructed to represent the segmented sub-region results, where the root node of the balanced binary tree represents the entire network rewiring layer, each internal node represents a segmented region, and the leaf node represents a sub-region containing a single bump.

[0105] S430 , determining the corresponding chip region and interposer region according to the positions of the bumps in the sub-region in the balanced binary tree.

[0106] After obtaining the balanced binary tree, partitioning can be performed based on the tree hierarchy. Each internal node represents a split point that can divide the bump set into the die area and the interposer area.

[0107] S440, traverse the balanced binary tree to establish a set mapping relationship between the chip region and the interposer region.

[0108] By traversing the tree-balanced binary tree, set mapping relationships between chiplet regions and interposer regions can be established, and these set mapping relationships reflect the relative positions of bumps in different regions.

[0109] S450 , allocating connections according to the set mapping relationship to obtain a second connection relationship between the chip die and the interposer.

[0110] By using these set mapping relationships, the matching relationships between all bumps can be inferred, and then, based on these matching relationships, all connections can be allocated to obtain a second connection relationship between the chip die and the interposer.

[0111] S500 , wiring is performed between different chip dies according to the first connection relationship, and wiring is performed between different chip dies and the interposer according to the second connection relationship.

[0112] The wiring method of the integrated circuit provided by the embodiment of the present invention converts the bump matching problem of the chip in the integrated circuit into the matching problem between the point sets, and regards the bumps on each chip as points in the two-dimensional space, each point having a specific position coordinate. Potential matching pairs are determined by calculating the distance between the points. Since the bumps are evenly distributed on the network rewiring layer, the search advantage of the two-dimensional matrix grid can be used to quickly find the nearest bump pairs. At the same time, the matching process is carried out synchronously between each chip, and an effective conflict resolution strategy is used to avoid falling into the local optimal solution. The matching bump pairs are divided into two categories according to the connection relationship. For non-overlapping bump sets, they are matched by group and re-matched within the group, which is conducive to maintaining the locality and consistency of the matching. For overlapping bump sets, a partition matching strategy is adopted to allocate all connections according to the partition result set mapping relationship between the bumps to ensure the accuracy and completeness of the matching.

[0113] Example 2

[0114] Based on the same technical concept as the method embodiment of the above-mentioned embodiment 1, the embodiment of the present invention provides a wiring system for an integrated circuit. Fig. 9 is a schematic diagram of the structure of the wiring system of the integrated circuit provided by the embodiment of the present invention, such as Fig. 9 As shown, the integrated circuit includes an interposer and at least two chiplets, and the at least two chiplets are arranged on the interposer. The wiring system 900 of the integrated circuit includes:

[0115] The first matching module 910 is used to match the bumps between the chip dies according to the first signal connection quantity to obtain a plurality of first matching bump pairs between different chip dies.

[0116] The second matching module 920 is used to match the bumps between different chip dies and the interposer according to the second signal connection quantity to obtain a plurality of second matching bump pairs between different chip dies and the interposer.

[0117] The first processing module 930 is used to group the plurality of first matching bump pairs to obtain a bump group, match the bumps between different chip dies in the bump group, and obtain a first connection relationship between the different chip dies.

[0118] The second processing module 940 is used to divide the plurality of second matching bump pairs into regions to obtain second connection relationships between different chip dies and the interposer.

[0119] The circuit wiring module 950 is used to perform wiring between different chip dies according to the first connection relationship, and to perform wiring between different chip dies and the intermediate layer according to the second connection relationship.

[0120] The wiring system of the integrated circuit provided by the embodiment of the present invention effectively reduces the crossover and total wiring lengths through reasonable matching and partitioning strategies, significantly improves the wiring efficiency of the network rewiring layer, and has broad application prospects and potential economic value.

[0121] It can be understood that the implementation method of the wiring method of the integrated circuit described in the above-mentioned embodiment 1 is also applicable to this embodiment and can achieve the same technical effect, so it will not be repeated here.

[0122] Example 3

[0123] Based on the same concept, an embodiment of the present invention further provides an electronic device, Fig.10 is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention, such as Fig.10 As shown, the electronic device 1000 may include: a processor 1010, a communication interface 1020, a memory 1030 and a communication bus 1040, wherein the processor 1010, the communication interface 1020, and the memory 1030 communicate with each other through the communication bus 1040. The processor 1010 may call the logic instructions in the memory 1030 to execute the steps of the wiring method of the integrated circuit described in the above embodiments. For example, it includes:

[0124] S200, matching bumps between different chip dies and interposers according to the second signal connection quantity to obtain a plurality of second matching bump pairs between different chip dies and interposers;

[0125] S300, grouping a plurality of first matching bump pairs to obtain a bump group, matching bumps between different chip dies in the bump group, and obtaining a first connection relationship between the different chip dies;

[0126] S400, dividing the plurality of second matching bump pairs into regions to obtain second connection relationships between different chip dies and the interposer;

[0127] S500 , wiring is performed between different chip dies according to the first connection relationship, and wiring is performed between different chip dies and the interposer according to the second connection relationship.

[0128] The processor 1010 may be a central processing unit (CPU). The processor may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or a combination of the above chips.

[0129] In addition, the logic instructions in the above-mentioned memory 1030 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0130] The memory 1030 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created by the processor, etc. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory may optionally include a memory remotely disposed relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0131] Example 4

[0132] Based on the same concept, an embodiment of the present invention further provides a computer-readable storage medium, which stores a computer program, and the computer program includes at least one code segment, which can be executed by a main control device to control the main control device to implement the steps of the wiring method of the integrated circuit described in the above embodiments. For example, it includes:

[0133] S200, matching bumps between different chip dies and interposers according to the second signal connection quantity to obtain a plurality of second matching bump pairs between different chip dies and interposers;

[0134] S300, grouping a plurality of first matching bump pairs to obtain a bump group, matching bumps between different chip dies in the bump group, and obtaining a first connection relationship between the different chip dies;

[0135] S400, dividing the plurality of second matching bump pairs into regions to obtain second connection relationships between different chip dies and the interposer;

[0136] S500 , wiring is performed between different chip dies according to the first connection relationship, and wiring is performed between different chip dies and the interposer according to the second connection relationship.

[0137] Based on the same technical concept, an embodiment of the present invention further provides a computer program, which is used to implement the above method embodiment when executed by a main control device.

[0138] The computer program may be stored in whole or in part on a computer-readable storage medium packaged with the processor, or may be stored in whole or in part on a memory not packaged with the processor.

[0139] Based on the same technical concept, an embodiment of the present invention further provides a processor, which is used to implement the above method embodiment. The above processor can be a chip.

[0140] In summary, the wiring method, system, electronic device and storage medium of the integrated circuit provided by the present invention convert the bump matching problem of the chip in the integrated circuit into the matching problem between the point sets, and regard the bumps on each chip as points in the two-dimensional space, each point having a specific position coordinate. Potential matching pairs are determined by calculating the distance between the points. Since the bumps are evenly distributed on the network rewiring layer, the search advantage of the two-dimensional matrix grid can be used to quickly find the nearest bump pairs. At the same time, the matching process is carried out synchronously between each chip, and an effective conflict resolution strategy is used to avoid falling into the local optimal solution. The matching bump pairs are divided into two categories according to the connection relationship. For the bump sets without overlap, they are matched in groups and rematched within the groups, which is conducive to maintaining the locality and consistency of the matching. For the bump sets with overlap, a partition matching strategy is adopted, and all connections are allocated according to the partition result set mapping relationship between the bumps to ensure the accuracy and completeness of the matching. Through reasonable matching and partitioning strategies, the crossover and total wiring lengths are effectively reduced, and the wiring efficiency of the network rewiring layer is significantly improved, which has a wide range of application prospects and potential economic value.

[0141] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0142] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

[0143] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A wiring method for an integrated circuit, characterized in that: The integrated circuit comprises an interposer and at least two chiplets, wherein the at least two chiplets are arranged on the interposer, and the method comprises: Matching the bumps between the chip dies according to the first signal connection quantity to obtain a plurality of first matching bump pairs between different chip dies; Matching the bumps between different chip dies and the interposer according to the second signal connection quantity to obtain a plurality of second matching bump pairs between different chip dies and the interposer; Grouping the plurality of first matching bump pairs to obtain a bump group, matching the bumps between different chip particles in the bump group to obtain a first connection relationship between different chip particles; Dividing the plurality of the second matching bump pairs into regions to obtain second connection relationships between different chip dies and the interposer; Performing wiring between different chip dies according to the first connection relationship, and performing wiring between different chip dies and the interposer according to the second connection relationship; Wherein, the first signal connection number is the total number of bump signal connections between at least two of the chip dies, and the second signal connection number is the total number of bump signal connections between different chip dies and the interposer; At least two of the chip dies are respectively a first chip dies and a second chip dies, and matching the bumps between the chip dies according to the first signal connection quantity to obtain a plurality of first matching bump pairs between different chip dies comprises: Establishing position coordinates according to the bump arrays of the first chip die and the second chip die; Acquire first bump position information of a first bump in the first chip, and determine a second bump in the second chip that is closest to the first bump according to the first bump position information; Determine a third bump in the first chip that is closest to the second bump according to the second bump position information of the second bump, and if the third bump is not the same bump as the first bump, continue to search for a bump in the second chip that is closest to the third bump until the bumps in the first chip and the second chip are a bump pair that is closest to each other, and determine the bump pair as a first matching bump pair; The same number of the first matching bump pairs is determined according to the first signal connection number.

2. The integrated circuit wiring method according to claim 1, characterized in that: The determining, according to the first bump position information, a second bump in the second chip that is closest to the first bump comprises: If the first target bump in the second chip that is closest to the first bump is not matched, use the first target bump as the second bump; If the first target bump has been matched, a second target bump that is closest to the first target bump and has not been matched is used as the second bump.

3. The integrated circuit wiring method according to claim 1, characterized in that: The step of matching the bumps between different chip dies and the interposer according to the second signal connection quantity to obtain a plurality of second matching bump pairs between different chip dies and the interposer includes: Establishing position coordinates according to the chip die and the bump array of the interposer; Acquire fourth bump position information of a fourth bump in the chip particle, and determine a fifth bump in the interposer that is closest to the fourth bump according to the fourth bump position information; Determine a sixth bump in the chip that is closest to the fifth bump according to the fifth bump position information of the fifth bump, and if the sixth bump is not the same bump as the fourth bump, continue to search for a bump that is closest to the sixth bump in the interposer until the chip and the bumps in the interposer are a bump pair that are closest to each other, and determine the bump pair as a second matching bump pair; The same number of the second matching bump pairs is determined according to the second signal connection number.

4. The integrated circuit wiring method according to claim 1, characterized in that: The step of grouping the plurality of first matching bump pairs to obtain a bump group, matching the bumps between different chip particles in the bump group, and obtaining a first connection relationship between different chip particles includes: The bumps of the first chip die in the plurality of the first matching bump pairs are taken as a first point set, and the bumps of the second chip die in the plurality of the first matching bump pairs are taken as a second point set; Dividing the convex blocks in the first point set into a plurality of convex block groups according to coordinates, and sorting the convex blocks in the second point set according to coordinates; Distribute the bumps in the second point set to the bump groups with the closest distances according to the order, until the number of the bumps in the first point set and the number of the bumps in the second point set in all the bump groups is equal; According to the matching of the bumps in the first point set in each of the bump groups with the bumps closest to the second point set, until all the bump groups complete the matching of the bumps, a first connection relationship between different chip dies is obtained.

5. The integrated circuit wiring method according to claim 3, characterized in that: The step of dividing the plurality of second matching bump pairs into regions to obtain a second connection relationship between different chip dies and the interposer includes: Using a linear scanning algorithm to divide the area where the second matching convex block pair is located into equal-size segments to obtain a plurality of sub-areas, each of which includes one convex block; Constructing a balanced binary tree, using leaf nodes of the balanced binary tree to represent the plurality of sub-regions; Determine a corresponding chip region and an interposer region according to the position of the bump in the sub-region in the balanced binary tree; Traversing the balanced binary tree to establish a set mapping relationship between the chip region and the interposer region; Connections are allocated according to the set mapping relationship to obtain a second connection relationship between the chip die and the intermediate layer.

6. A wiring system for an integrated circuit, characterized in that: The integrated circuit includes an interposer and at least two chiplets, and the system includes: A first matching module, used for matching the bumps between the chip dies according to the first signal connection quantity, to obtain a plurality of first matching bump pairs between different chip dies; A second matching module, used for matching the bumps between different chip dies and the interposer according to the second signal connection quantity, to obtain a plurality of second matching bump pairs between different chip dies and the interposer; A first processing module, configured to group the plurality of first matching bump pairs to obtain a bump group, match the bumps between different chip particles in the bump group, and obtain a first connection relationship between different chip particles; A second processing module, configured to divide the plurality of second matching bump pairs into regions to obtain second connection relationships between different chip dies and the interposer; A circuit wiring module, used for wiring between different chip dies according to the first connection relationship, and for wiring between different chip dies and the interposer according to the second connection relationship; Wherein, the first signal connection number is the total number of bump signal connections between at least two of the chip dies, and the second signal connection number is the total number of bump signal connections between different chip dies and the interposer; At least two of the chip dies are respectively a first chip dies and a second chip dies, and matching the bumps between the chip dies according to the first signal connection quantity to obtain a plurality of first matching bump pairs between different chip dies comprises: Establishing position coordinates according to the bump arrays of the first chip die and the second chip die; Acquire first bump position information of a first bump in the first chip, and determine a second bump in the second chip that is closest to the first bump according to the first bump position information; Determine a third bump in the first chip that is closest to the second bump according to the second bump position information of the second bump, and if the third bump is not the same bump as the first bump, continue to search for a bump in the second chip that is closest to the third bump until the bumps in the first chip and the second chip are a bump pair that is closest to each other, and determine the bump pair as a first matching bump pair; The same number of the first matching bump pairs is determined according to the first signal connection number.

7. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: The processor executes the computer program to implement the wiring method of the integrated circuit according to any one of claims 1 to 5.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the wiring method of an integrated circuit according to any one of claims 1 to 5 is implemented.

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