Semiconductor structure manufacturing method and semiconductor structure

Abstract

The present application provides a method for manufacturing a semiconductor structure and a semiconductor structure. The manufacturing method includes: forming a structure to be wired including a first chip and a plastic layer; a plurality of solder pads are provided on the front side of the first chip; the plastic layer at least encapsulates the side surface of the first chip; forming a rewiring layer, the rewiring layer being located on the front side of the chip and electrically connected to the solder pads; the rewiring layer being provided with at least one step structure facing the plastic layer; forming at least one through hole penetrating the plastic layer in the plastic layer; each through hole corresponding to a step structure, the orthographic projection of the through hole on the plane where the chip front is located all falling within the orthographic projection of the rewiring layer on the plane, and at least partially overlapping with the orthographic projection of the portion of the corresponding step structure not in contact with the plastic layer on the plane; filling the through hole with a fluid conductive material, forming a conductive portion after the conductive material is solidified, disposing an electrical component on the back side of the chip, and soldering the at least one electrical component to the conductive portion.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor structure and a semiconductor structure. Background Art

[0002] In common semiconductor packaging technology, a lead frame or conductive copper pillars are usually used to achieve electrical connection between the front and back of the chip. The chip packaging technology may include the following process: first, the chip and lead frame or conductive copper pillars are mounted on a carrier board, and then hot pressing and plastic sealing are performed.

[0003] However, during the hot-pressing and plastic-sealing process of the chip and lead frame or conductive copper pillar, the lead frame and conductive copper pillar are prone to deformation and displacement, which may lead to short circuit or open circuit between the redistribution layer on the front of the chip and the lead frame or conductive copper pillar, affecting the product yield. Summary of the Invention

[0004] Embodiments of the present application provide a method for manufacturing a semiconductor structure and a semiconductor structure.

[0005] A first aspect of an embodiment of the present application provides a method for manufacturing a semiconductor structure, the method comprising:

[0006] forming a structure to be wired, the structure to be wired comprising a first chip and a plastic encapsulation layer; the first chip comprising a chip front, a chip back opposite to the chip front, and a plurality of chip side surfaces connecting the chip front and the chip back, the chip front being provided with a plurality of bonding pads; the plastic encapsulation layer at least encapsulating the chip side surfaces;

[0007] forming a redistribution layer, the redistribution layer being located on the front side of the chip and electrically connected to the pad; the redistribution layer being provided with at least one step structure facing the plastic encapsulation layer;

[0008] At least one through hole is formed on the plastic encapsulation layer, penetrating the plastic encapsulation layer; each through hole corresponds to one of the step structures, and the orthographic projections of the through holes on the plane where the chip front surface is located all fall within the orthographic projection of the redistribution layer on the plane, and the orthographic projections of the through holes on the plane at least partially overlap with the orthographic projections of the corresponding portions of the step structures not in contact with the plastic encapsulation layer on the plane;

[0009] The through hole is filled with a fluid conductive material, and the conductive material forms the conductive portion after solidification. An electrical component is arranged on the back side of the chip, and at least one of the electrical components is welded to the conductive portion.

[0010] In one embodiment, forming a redistribution layer includes:

[0011] A first trace layer and a second trace layer located on a side of the first trace layer facing away from the structure to be wired are formed on the structure to be wired, so as to obtain a rewiring layer including the first trace layer and the second trace layer; the first trace layer includes a plurality of first trace structures; the first trace structures are electrically connected to the pads; the second trace layer includes a second trace structure located on a side of each of the first trace structures facing away from the structure to be wired, and at least one side of at least one of the second trace structures exceeds the corresponding first trace structure to form a step structure.

[0012] In one embodiment, the orthographic projection of a portion of the edge of the through hole that is not in contact with the redistribution layer on the plane is located inside the edge of the orthographic projection of a portion of the corresponding step structure that is not in contact with the plastic encapsulation layer on the plane; and / or,

[0013] A distance between a surface of the step structure facing the molding layer and not in contact with the molding layer and the molding layer is in a range of 10 μm to 60 μm.

[0014] In one embodiment, after forming the redistribution layer, a semiconductor intermediate structure is obtained; the plastic encapsulation layer includes a cutting line, and the redistribution layer is in contact with an area of ​​the plastic encapsulation layer located outside the cutting line; before forming a plurality of through holes penetrating the plastic encapsulation layer on the plastic encapsulation layer, the method for manufacturing the semiconductor structure further includes:

[0015] Placing the semiconductor intermediate structure on a support member, wherein the support member includes a plate portion and a support portion formed by extending from one side of the plate portion, wherein the support portion contacts the cutting street, and the redistribution layer faces the plate portion and has a gap between the redistribution layer and the plate portion;

[0016] After arranging electrical components on the back side of the chip and welding at least one of the electrical components to the conductive portion, the method for preparing the semiconductor structure further includes:

[0017] The obtained structure is cut along the cutting streets.

[0018] In one embodiment, after the through hole is filled with a fluid conductive material and the conductive material is solidified to form the conductive portion, the method for manufacturing the semiconductor structure further includes:

[0019] Filling a filler between the surface of the step structure facing the plastic sealing layer and not in contact with the plastic sealing layer and the plastic sealing layer to form a filling portion; or,

[0020] A plastic film layer is formed, wherein the plastic film layer covers the redistribution layer and fills a gap between a surface of the step structure that faces the plastic layer and does not contact the plastic layer and the plastic layer.

[0021] In one embodiment, the electrical component includes a second chip, the electrical component is provided on the back side of the chip, and after at least one of the electrical components is soldered to the conductive portion, the method for manufacturing the semiconductor structure further includes:

[0022] A filler is filled between the second chip and the plastic packaging layer to form a filling structure.

[0023] In one embodiment, a surface of the conductive portion facing away from the redistribution layer extends beyond a surface of the molding layer facing away from the redistribution layer.

[0024] In one embodiment, the electrical component includes a heat dissipation layer, and the heat dissipation layer is formed simultaneously with the conductive portion.

[0025] In one embodiment, the electrical component includes at least one of a second chip, an inductor, a resistor, a capacitor, and a heat dissipation layer; and / or,

[0026] The conductive material includes at least one of solder and silver paste.

[0027] A second aspect of an embodiment of the present application provides a semiconductor structure, comprising:

[0028] A first chip, comprising a chip front side, a chip back side opposite to the chip front side, and a plurality of chip side sides connecting the chip front side and the chip back side, wherein the chip front side is provided with a plurality of bonding pads;

[0029] A plastic encapsulation layer, covering the side surface of the chip, wherein the plastic encapsulation layer is provided with at least one through hole;

[0030] A conductive portion, at least partially located in the through hole; the conductive portion is made of at least one of solder and silver paste;

[0031] a redistribution layer located on a side of the plastic encapsulation layer close to the front surface of the chip, the redistribution layer being electrically connected to the bonding pad and the conductive portion; the redistribution layer being provided with at least one step structure facing the plastic encapsulation layer; each of the through holes corresponding to one of the step structures, the orthographic projections of the through holes on the plane where the front surface of the chip is located all falling within the orthographic projection of the redistribution layer on the plane, and the orthographic projections of portions of the step structures not in contact with the plastic encapsulation layer on the plane at least partially overlapping with the orthographic projections of the corresponding through holes on the plane;

[0032] The electrical component is located on a side of the plastic packaging layer away from the front surface of the chip, and at least one of the electrical components is welded to the conductive part.

[0033] In one embodiment, the redistribution layer includes a first trace layer and a second trace layer located on a side of the first trace layer facing away from the first chip; the first trace layer includes a plurality of first trace structures; the first trace structures are electrically connected to the pads; the second trace layer includes a second trace structure located on a side of each first trace structure facing away from the first chip, and at least one side of at least one second trace structure extends beyond the corresponding first trace structure to form a step structure.

[0034] In one embodiment, the conductive portion contacts both the first trace structure and the second trace structure, or the conductive portion contacts only the second trace structure.

[0035] In one embodiment, the orthographic projection of a portion of the edge of the through hole that is not in contact with the redistribution layer on the plane is located inside the edge of the orthographic projection of a portion of the corresponding step structure that is not in contact with the plastic encapsulation layer on the plane; and / or,

[0036] A distance between a surface of the step structure facing the molding layer and not in contact with the molding layer and the molding layer is in a range of 10 μm to 60 μm.

[0037] In one embodiment, the semiconductor structure further includes a filling portion located between a surface of the step structure facing the molding layer and not in contact with the molding layer and the molding layer; and / or,

[0038] The electrical component includes a second chip, and the semiconductor structure further includes a filling structure located between the second chip and the plastic packaging layer.

[0039] The main technical effects achieved by the embodiments of the present application are:

[0040] The manufacturing method and semiconductor structure provided by the embodiments of the present application are as follows: a redistribution layer electrically connected to the welding pad is provided on the front side of the first chip, an electrical component is provided on the back side of the first chip, and at least one electrical component is welded to the conductive part. Then, the electrical component can be electrically connected to the redistribution layer through the conductive part in the through hole of the plastic packaging layer, that is, the electrical connection between the front side of the chip and the back side of the chip is realized; during the preparation process of the semiconductor structure, there is no need to provide a lead frame or conductive column, which can avoid deformation and displacement of the lead frame and the conductive column, which may cause problems such as short circuit or open circuit between the redistribution layer on the front side of the chip and the first chip, thereby helping to improve product yield; the conductive part is formed by filling the through hole of the plastic packaging layer with a flowing conductive material, and the conductive material can basically fill the through hole, ensuring that the conductive material The conductive part obtained after the material is solidified has good electrical connection effects with the electrical components and the rewiring layer. Compared with the solution of forming the conductive part in the through hole by the electroplating process, it can improve the problem that the hole wall of the through hole cannot be plated with conductive material in the electroplating process, and the short circuit between the electrical component and the rewiring layer caused by the alignment deviation in the electroplating process, which helps to improve the product yield; by arranging a step structure facing the plastic layer on the rewiring layer, the orthographic projection of the part of the step structure that is not in contact with the plastic layer on the plane where the front side of the chip is located is at least partially overlapped with the orthographic projection of the corresponding through hole on the plane, then in the process of welding the conductive part to the electrical component, the gas in the through hole can be discharged through the channel between the part of the step structure that is not in contact with the plastic layer and the plastic layer, which can avoid the gas in the through hole causing the conductive part to have voids and affect the quality of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 is a flow chart of a method for manufacturing a semiconductor structure provided by an exemplary embodiment of the present application;

[0042] Figure 2 is a partial cross-sectional view of a wafer provided by an exemplary embodiment of the present application;

[0043] Figure 3 is a cross-sectional view of a first chip provided by an exemplary embodiment of the present application;

[0044] Figure 4 is a partial cross-sectional view of a first intermediate structure provided by an exemplary embodiment of the present application;

[0045] Figure 5 is a partial cross-sectional view of a second intermediate structure provided by an exemplary embodiment of the present application;

[0046] Figure 6 is a partial cross-sectional view of a third intermediate structure provided by an exemplary embodiment of the present application;

[0047] Figure 7is a partial cross-sectional view of a fourth intermediate structure provided by an exemplary embodiment of the present application;

[0048] Figure 8 is a partial cross-sectional view of a fifth intermediate structure provided by an exemplary embodiment of the present application;

[0049] Figure 9 is a partial cross-sectional view of a sixth intermediate structure provided by an exemplary embodiment of the present application;

[0050] Figure 10 is a partial cross-sectional view of a seventh intermediate structure provided by an exemplary embodiment of the present application;

[0051] Figure 11 is a partial cross-sectional view of an eighth intermediate structure provided by an exemplary embodiment of the present application;

[0052] Figure 12 is a partial cross-sectional view of a ninth intermediate structure provided by an exemplary embodiment of the present application;

[0053] Figure 13 is a partial cross-sectional view of a tenth intermediate structure provided by an exemplary embodiment of the present application;

[0054] Figure 14 is a partial cross-sectional view of an eleventh intermediate structure provided by an exemplary embodiment of the present application;

[0055] Figure 15 is a partial cross-sectional view of a twelfth intermediate structure provided by an exemplary embodiment of the present application;

[0056] Figure 16 is a partial cross-sectional view of a thirteenth intermediate structure provided by an exemplary embodiment of the present application;

[0057] Figure 17 is a partial cross-sectional view of a thirteenth intermediate structure provided by another exemplary embodiment of the present application;

[0058] Figure 18 is a partial cross-sectional view of a fourteenth intermediate structure provided by an exemplary embodiment of the present application;

[0059] Figure 19 is a cross-sectional view of a semiconductor structure provided by an exemplary embodiment of the present application;

[0060] Figure 20 is a cross-sectional view of a semiconductor structure provided by another exemplary embodiment of the present application;

[0061] Figure 21 is a cross-sectional view of a semiconductor structure provided by yet another exemplary embodiment of the present application. Specific embodiments

[0062] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0063] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. As used in this application and the appended claims, the singular forms "a," "an," "the," and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0064] It should be understood that although the terms first, second, third, etc. may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0065] The following embodiments of the present application are described in detail with reference to the accompanying drawings. In the absence of conflict, the following embodiments and features therein may be combined with each other.

[0066] The present application provides a method for manufacturing a semiconductor structure. Figure 1 The method for manufacturing the semiconductor structure includes the following steps 110 to 140.

[0067] In step 110, a structure to be wired is formed, wherein the structure to be wired includes a first chip and a plastic encapsulation layer; the first chip includes a chip front side, a chip back side opposite to the chip front side, and a plurality of chip side sides connecting the chip front side and the chip back side, and a plurality of solder pads are provided on the chip front side; the plastic encapsulation layer at least encapsulates the chip side sides.

[0068] In step 120 , a redistribution layer is formed. The redistribution layer is located on the front side of the chip and is electrically connected to the bonding pad. The redistribution layer is provided with at least one step structure facing the plastic packaging layer.

[0069] In step 130, at least one through hole is formed on the plastic encapsulation layer, penetrating the plastic encapsulation layer; each through hole corresponds to one of the step structures, and the orthographic projections of the through holes on the plane where the front side of the chip is located all fall within the orthographic projection of the redistribution layer on the plane, and the orthographic projection of the through hole on the plane at least partially overlaps with the orthographic projection of the corresponding portion of the step structure that is not in contact with the plastic encapsulation layer on the plane.

[0070] In step 140, the through hole is filled with a fluid conductive material, and the conductive material is solidified to form the conductive portion. Electrical components are arranged on the back side of the chip, and at least one of the electrical components is welded to the conductive portion.

[0071] The manufacturing method of the semiconductor structure provided in the embodiment of the present application is through setting a rewiring layer electrically connected to the welding pad on the front side of the chip of the first chip, setting an electrical component on the back side of the chip of the first chip, and welding at least one electrical component to the conductive part. Then, the electrical component can be electrically connected to the rewiring layer through the conductive part located in the through hole of the plastic packaging layer, that is, realizing the electrical connection between the front side of the chip and the back side of the chip; in the preparation process of the semiconductor structure, there is no need to set a lead frame or conductive column, which can avoid deformation and displacement of the lead frame and the conductive column, which may cause problems such as short circuit or open circuit between the rewiring layer located on the front side of the chip and the first chip, thereby helping to improve product yield; the conductive part is formed by filling the through hole of the plastic packaging layer with a flowing conductive material, and the conductive material can basically fill the through hole to ensure that the conductive material is solidified The resulting conductive part has good electrical connection effects with the electrical components and the rewiring layer. Compared with the solution of forming the conductive part in the through hole by the electroplating process, it can improve the problem that the hole wall of the through hole cannot be plated with conductive material in the electroplating process, and the short circuit between the electrical component and the rewiring layer caused by the alignment deviation in the electroplating process, which helps to improve the product yield; by arranging a step structure facing the plastic layer on the rewiring layer, the orthographic projection of the part of the step structure that is not in contact with the plastic layer on the plane where the front side of the chip is located is at least partially overlapped with the orthographic projection of the corresponding through hole on the plane, then in the process of welding the conductive part to the electrical component, the gas in the through hole can be discharged through the channel between the part of the step structure that is not in contact with the plastic layer and the plastic layer, which can avoid the gas in the through hole causing the conductive part to have voids and affect the quality of the semiconductor structure.

[0072] The following is a detailed introduction to each step of the method for manufacturing a semiconductor structure provided in an embodiment of the present application.

[0073] In step 110, a structure to be wired is formed, wherein the structure to be wired includes a first chip and a plastic encapsulation layer; the first chip includes a chip front side, a chip back side opposite to the chip front side, and a plurality of chip side sides connecting the chip front side and the chip back side, and a plurality of solder pads are provided on the chip front side; the plastic encapsulation layer at least encapsulates the chip side sides.

[0074] In one embodiment, the first chip can be manufactured by the following process:

[0075] First, a wafer is provided. The wafer has a specific function. Figure 2 The wafer 14 has an active surface, and the active surface of the wafer 14 is provided with an insulating film layer 12 and a bonding pad. The insulating film layer 12 is provided with an opening 121, and the opening 121 exposes the bonding pad. The bonding pad is used to electrically connect to external components.

[0076] Then, the wafer 14 is cut. Figure 2 The wafer 14 is cut at the position of the dotted line shown in FIG. The wafer 14 can be cut by mechanical cutting or laser cutting. Optionally, before cutting the wafer 14, a grinding device can be used to grind the back side of the wafer opposite to the active surface so that the thickness of the wafer 14 is a specified thickness. This step can be used to obtain the following: Figure 3 A first chip 10 is shown.

[0077] In one embodiment, the step of forming a structure to be wired may include the following process:

[0078] First, a first chip is mounted on a carrier board, with the front side of the first chip facing the carrier board.

[0079] Through this step, we can obtain Figure 4 The first intermediate structure shown. Figure 4 As shown, the first chip 10 is mounted on the carrier 20 via the adhesive layer 21. The adhesive layer 21 can be made of an easily peelable material to facilitate subsequent peeling of the carrier. For example, the adhesive layer 21 can be made of a thermally releasable material that loses its stickiness by heating. Figure 4 Only one first chip mounted on the carrier is shown schematically; in practice, multiple first chips may be mounted on the carrier.

[0080] In one embodiment, the carrier 20 may be circular, rectangular, or other shapes. The carrier 20 may be a small wafer substrate or a larger carrier, such as a stainless steel substrate or a polymer substrate.

[0081] Subsequently, a plastic encapsulation layer is formed, and the plastic encapsulation layer covers the chip side surface of the first chip.

[0082] Through this step, we can obtain Figure 5The second intermediate structure shown. Figure 5 As shown, the plastic encapsulation layer 30 is formed on the first chip 10 and the exposed carrier 20, covering the chip side of the first chip 10 to reconstruct a flat structure, so that after the carrier 20 is peeled off, rewiring and packaging can continue on the reconstructed flat structure.

[0083] In one embodiment, before forming the plastic encapsulation layer 30, some pre-processing steps, such as chemical cleaning, plasma cleaning, etc., can be performed to remove impurities on the surface of the first chip 10 and the carrier 20, so that the plastic encapsulation layer 30 and the first chip 10 and the carrier 20 can be more closely connected without delamination or cracking.

[0084] In one embodiment, the material of the plastic encapsulation layer 30 can be a polymer resin, a resin composite material, a polymer composite material, etc. For example, the plastic encapsulation layer 30 can be a resin with a filler, wherein the filler can be inorganic particles. The plastic encapsulation layer 30 can be formed by injection molding, compression molding, or transfer molding.

[0085] Subsequently, the carrier board is peeled off.

[0086] Through this step, we can obtain Figure 6 The third intermediate structure shown is the structure to be routed. Figure 6 In the third intermediate structure, the front surface of the first chip 10 is not covered by the plastic packaging layer 30 , and the bonding pad on the front surface of the first chip 10 is exposed.

[0087] In step 120 , a redistribution layer is formed. The redistribution layer is located on the front side of the chip and is electrically connected to the bonding pad. The redistribution layer is provided with at least one step structure facing the plastic packaging layer.

[0088] In one embodiment, before step 120 , the third intermediate structure may be mounted on the carrier, with the front side of the first chip facing away from the carrier.

[0089] In one embodiment, the step of forming a rewiring layer may include the following process: forming a first trace layer and a second trace layer located on the side of the first trace layer away from the structure to be wired on the structure to be wired, so as to obtain a rewiring layer including the first trace layer and the second trace layer; the first trace layer includes a plurality of first trace structures; the first trace structure is electrically connected to the pad; the second trace layer includes a second trace structure located on the side of each first trace structure away from the structure to be wired, and at least one side of at least one second trace structure exceeds the corresponding first trace structure to form a step structure.

[0090] Through this step, we can obtain Figure 7 The fourth intermediate structure shown. Figure 7 As shown, the plastic encapsulation layer 30 and the first chip 10 are mounted on the carrier 22 through the adhesive layer 23; the redistribution layer 40 includes a first trace layer 41 and a second trace layer 43; the first trace layer 41 includes a plurality of first trace structures 42, and the first trace structures 42 are electrically connected to the bonding pads through the conductive pillars 50 located in the openings 121 of the insulating layer 12; the second trace layer 43 includes a plurality of second trace structures 44; the portion of the second trace structure 44 that exceeds the corresponding first trace structure 42 forms a step structure 401 with the first trace structure 42.

[0091] In one embodiment, Figure 7 As shown, the distance d between the surface of the step structure 401 facing the plastic layer 30 and not in contact with the plastic layer and the plastic layer 30 is in the range of 10μm to 60μm. This setting can avoid the distance d between the surface of the step structure 401 facing the plastic layer 30 and not in contact with the plastic layer 30 and the plastic layer 30 being too small, which is not conducive to the discharge of gas in the through-hole of the plastic layer in the subsequent steps. It can also avoid the distance between the surface of the step structure 401 facing the plastic layer 30 and not in contact with the plastic layer 30 and the plastic layer 30 being too large, which makes the preparation process of the redistribution layer more difficult. In some embodiments, the distance d between the surface of the step structure 401 facing the plastic layer 30 and not in contact with the plastic layer 30 and the plastic layer 30 can be 10μm, 20μm, 30μm, 40μm, 50μm, 60μm, etc.

[0092] In one embodiment, the step of forming a first trace layer on the structure to be wired and a second trace layer located on a side of the first trace layer away from the structure to be wired may include the following process:

[0093] First, a seed layer is formed on the front side of the first chip where the structure to be wired is located. The seed layer can be formed by a sputtering process.

[0094] Then, a first insulating layer is provided on the side of the seed layer facing away from the first chip, and the first insulating layer can be provided by pressing a dry film on the side of the seed layer facing away from the first chip.

[0095] Then, the first insulating layer is exposed and developed to form a plurality of first openings.

[0096] Subsequently, electroplating is performed to form sub-trace structures in each first opening.

[0097] Then, a second insulating layer is provided on the side of the sub-trace structure facing away from the plastic encapsulation layer, and the second insulating layer can be provided by pressing a dry film.

[0098] Subsequently, the second insulating layer is exposed and developed to form a plurality of second openings, wherein the second openings correspond to the first openings one by one, and the size of at least one second opening is larger than that of the first opening.

[0099] Subsequently, electroplating is performed to form a second trace structure in each second opening, thereby obtaining a second trace layer.

[0100] Subsequently, the first and second insulating layers are removed. Chemical reagents can be used to react with the first and second insulating layers to remove the first and second insulating layers. Because the first insulating layer is partially located below the second trace layer, to completely remove the first insulating layer, the chemical reagents can be reacted with the first and second insulating layers under ultrasonic conditions.

[0101] Subsequently, the portion of the seed layer not covered by the sub-trace structure is etched away, and the portion of the retained seed layer that contacts each sub-trace structure and the sub-trace structure is the first trace structure, thereby obtaining a first trace layer including multiple first trace structures.

[0102] In one embodiment, the first trace structure 42 and the conductive pillar 50 can be formed simultaneously in the same process step.

[0103] In step 130, at least one through hole is formed on the plastic encapsulation layer, penetrating the plastic encapsulation layer; each through hole corresponds to one of the step structures, and the orthographic projections of the through holes on the plane where the front side of the chip is located all fall within the orthographic projection of the redistribution layer on the plane, and the orthographic projection of the through hole on the plane at least partially overlaps with the orthographic projection of the corresponding portion of the step structure that is not in contact with the plastic encapsulation layer on the plane.

[0104] In one embodiment, the plastic encapsulation layer includes a scribe line, and the redistribution layer contacts an area of ​​the plastic encapsulation layer outside the scribe line. Prior to step 130, the method for manufacturing a semiconductor structure further includes: peeling off the carrier to obtain a semiconductor intermediate structure; placing the semiconductor intermediate structure on a support member, the support member including a plate portion and a support portion extending from one side of the plate portion, the support portion contacting the scribe line, and the redistribution layer facing the plate portion with a gap between the plate portion and the redistribution layer.

[0105] Through the above steps, we can get Figure 8 The fifth intermediate structure shown. Figure 8 As shown, the support portion 242 of the support member 24 contacts the cutting path 32 of the plastic encapsulation layer 30, and a gap exists between the plate portion 241 of the support member 24 and the redistribution layer 40. The support member 24 may include multiple support portions 242, with two adjacent support portions 242 arranged opposite each other. The cutting path 32 of the plastic encapsulation layer 30 is the location where the plastic encapsulation layer will be subsequently cut.

[0106] By providing a support member 24, the intermediate structure can be supported to facilitate the subsequent process steps; since the support portion 241 is in contact with the cutting path 32 of the plastic encapsulation layer 30, the support portion 241 can be prevented from contacting other areas, causing other areas to be deformed due to force, thereby affecting the quality of the semiconductor structure; since the redistribution layer 40 is provided with a step structure, the strength of the redistribution layer 40 is relatively small, and by providing a gap between the plate portion 242 and the redistribution layer 40, the redistribution layer 40 can be prevented from contacting the support member 24, causing the redistribution layer 40 to be deformed due to force.

[0107] Through step 130, the following can be obtained: Figure 9 The sixth intermediate structure shown. Figure 9 As shown, the plastic encapsulation layer 30 is formed with a plurality of through holes 31 that penetrate the plastic encapsulation layer 30. The orthographic projection of each through hole 31 on the plane where the chip front surface is located completely falls within the orthographic projection of the redistribution layer 40 on the plane. The through holes 31 correspond one-to-one with the step structures 401, and the orthographic projection of each through hole 31 on the plane partially overlaps with the orthographic projection of the portion of the corresponding step structure 401 on the plane that is not in contact with the plastic encapsulation layer 30. In other embodiments, the orthographic projection of the through holes 31 on the plane may completely fall within the orthographic projection of the portion of the corresponding step structure 401 on the plane that is not in contact with the plastic encapsulation layer 30.

[0108] Since the conductive part in step 140 is formed by filling the through hole 31 with a flowing conductive material, some gas will remain in the through hole 31 when the conductive material fills the through hole. By setting the orthographic projection of the part of the step structure 401 that is not in contact with the plastic packaging layer 30 on the plane to at least partially overlap with the orthographic projection of the corresponding through hole 31 on the plane, in the subsequent process of welding the conductive part in the through hole 31 and the electrical component, the gas in the through hole 31 can be discharged through the channel between the part of the step structure 401 that is not in contact with the plastic packaging layer 30 and the plastic packaging layer 30.

[0109] In one embodiment, the orthographic projection of the portion of the edge of the through hole 31 that is not in contact with the redistribution layer 40 on the plane is located inside the edge of the orthographic projection of the portion of the corresponding step structure 401 that is not in contact with the plastic layer 30 on the plane. With this arrangement, in a direction parallel to the plane on which the chip front surface resides, the step structure 401 extends beyond the portion of the edge of the corresponding through hole 31 that is not in contact with the redistribution layer 40. When the through hole 31 is subsequently filled with flowing conductive material, the flowing conductive material flows out of the portion of the through hole 31 that is not blocked by the step structure 401 and flows onto the surface of the portion of the step structure 401 that is not in contact with the plastic layer 30. This prevents the conductive material from flowing to the surface of the plastic layer 30, causing electrical connection between two adjacent first trace structures 42 and affecting the performance of the semiconductor structure.

[0110] In one embodiment, the distance between the orthographic projection of the portion of the edge of the through hole 31 not in contact with the redistribution layer 40 on the plane and the orthographic projection of the portion of the corresponding step structure 401 not in contact with the plastic layer 30 on the plane is greater than 50 μm. This configuration can effectively prevent the conductive material from flowing to the surface of the plastic layer 30.

[0111] In one embodiment, Figure 9 As shown, part of the edge of the through hole 31 contacts the corresponding first trace structure 42, and the edge of the second trace structure 44 extends beyond the portion of the edge of the corresponding through hole 31 that is not in contact with the first trace structure 42. In other embodiments, the edge of the through hole 31 may not contact the first trace structure 42.

[0112] In one embodiment, the support portion 241 of the support member 24 is provided with a vacuum channel, through which the air between the support portion 241 and the cut line 32 of the plastic layer 30 can be extracted, thereby achieving vacuum adsorption between the support portion 241 and the cut line 32. This facilitates subsequent separation of the support member 24 from the plastic layer 30. In other embodiments, the support portion 241 and the cut line 32 of the plastic layer 30 can be adhered together by an adhesive layer. The adhesive layer can be made of an easily releasable material to facilitate subsequent separation of the carrier board. For example, the adhesive layer can be made of a thermally releasable material that loses its viscosity upon heating.

[0113] In step 140, the through hole is filled with a fluid conductive material, and the conductive material is solidified to form the conductive portion. Electrical components are arranged on the back side of the chip, and at least one of the electrical components is welded to the conductive portion.

[0114] In one embodiment, the conductive material includes at least one of solder and silver paste. The solder can be, for example, tin paste. Tin paste and silver paste have good fluidity at room temperature and are easier to fill the through-holes of the plastic layer, thereby ensuring that the conductive part formed in the through-holes of the plastic layer is better electrically connected to the rewiring layer. Tin paste is a paste-like mixture formed by mixing solder powder, flux and other surfactants, thixotropic agents, etc., and silver paste is prepared from silver or its compounds, flux, adhesive and diluent. In the subsequent steps, when the conductive part is soldered to the electrical component, the flux in the solder volatilizes and is discharged through the channel between the part of the step structure 401 that is not in contact with the plastic layer 30 and the plastic layer 30.

[0115] In one embodiment, when the conductive material is solder paste or silver paste or a mixture of the two, the conductive material may be heated to melt the conductive material and then cooled to solidify the conductive material.

[0116] In one embodiment, the step of filling the through hole with a fluid conductive material comprises the following process: filling the through hole with the fluid conductive material using a screen printing process.

[0117] During the screen printing process, the silk screen is first placed on the side of the sixth intermediate structure away from the carrier, and then the conductive material is printed into the through hole 31 through the mesh of the silk screen. After the conductive material is solidified, a conductive part is formed. Since the silk screen has a certain thickness, part of the conductive material will be filled in the mesh of the silk screen during the printing of the conductive material. Then, the conductive part finally formed is away from the surface of the rewiring layer 40 and beyond the surface of the plastic layer 40 away from the rewiring layer 40, that is, the conductive part exceeds the through hole 31. This makes it easier to weld the conductive part to the electrical component in the subsequent steps. During the screen printing process, the printing pressure and printing speed can be controlled so that the conductive material basically completely fills the through hole 31. In some embodiments, the printing pressure can be in the range of 4kg to 10kg, and the printing speed can be in the range of 20mm / s to 100mm / s.

[0118] In another embodiment, the step of filling the through hole with a fluid conductive material comprises the following process: filling the through hole with a fluid conductive material using a dispensing process.

[0119] In this embodiment, a dispensing process is used to inject the fluid conductive material into the through hole 31 , and the conductive portion finally formed may or may not extend beyond the plastic packaging layer 30 .

[0120] In one embodiment, the electrical component includes at least one of a second chip and a passive component, wherein the passive component includes at least one of an inductor, a resistor, a capacitor, and a heat sink. The second chip may have the same or different functions as the first chip.

[0121] In one embodiment, when the electrical component includes a heat dissipation layer, the heat dissipation layer is formed simultaneously with the conductive portion. This helps to simplify the manufacturing method of the semiconductor structure. Figure 10 The seventh intermediate structure shown. Figure 10 As shown, a conductive portion 70 is formed in each through hole 31, and a heat dissipation layer 80 covers the back side of the first chip 10. The surface of the conductive portion 70 facing away from the redistribution layer 40 extends beyond the surface of the plastic layer 30 facing away from the redistribution layer 40. The conductive portion 70 is in contact with both the corresponding first trace structure 42 and the corresponding second trace 44. In other embodiments, the conductive portion 70 may only be in contact with the corresponding second trace structure 44. In other embodiments, the heat dissipation layer may be formed after the conductive portion is formed. By providing a heat dissipation layer covering the back side of the chip, the heat dissipation layer can conduct the heat of the first chip away from the back side of the chip, which helps to reduce the temperature of the first chip and improve the performance of the first chip.

[0122] In one embodiment, Figure 10 As shown, the heat dissipation layer 80 is in contact with the conductive portion 70. The heat dissipation layer 80 is electrically connected to the redistribution layer 40 via the conductive portion 70. In this way, heat generated by the redistribution layer 40 can be transferred to the heat dissipation layer 80 via the conductive portion 70. The heat dissipation layer 80 then conducts away the heat, further reducing the temperature of the semiconductor structure and improving its performance.

[0123] In one embodiment, when the electrical component further includes a passive component and a second chip, after obtaining the seventh intermediate structure, step 140 further includes: disposing at least one passive component and the second chip on a side of the seventh intermediate structure facing away from the support member.

[0124] Through this step, we can obtain Figure 11 The eighth intermediate structure shown. Figure 11 As shown, the second chip 81 contacts the plurality of conductive parts 70 , and the passive component 82 contacts the plurality of conductive parts 70 .

[0125] In one embodiment, after obtaining the eighth intermediate structure, the step 140 further includes: welding the second chip 81 and the passive component 82 to the conductive part 70 respectively. Figure 12 The ninth intermediate structure shown in FIG. 1 can use a reflow process to solder the second chip 81 and the passive component 82 to the conductive portion 70 .

[0126] In one embodiment, after step 140 , the method for manufacturing the semiconductor structure further includes: filling a filler between the second chip and the plastic packaging layer to form a filling structure.

[0127] Through this step, we can obtain Figure 13 The tenth intermediate structure shown. Figure 13 As shown, the surface of the filling structure 91 facing away from the redistribution layer 40 abuts against the second chip 81, and the surface of the filling structure 91 facing the redistribution layer 40 abuts against the plastic layer 30. In this way, the filler is first filled between the second chip 81 and the plastic layer 30 to form the filling structure 91, and then the encapsulation layer (see the following description) is formed to encapsulate the electrical components. This can reduce the probability of voids at the bottom of the electrical components after encapsulation. In other words, the electrical components can have smaller voids or no voids at the bottom after encapsulation. The filling effect at the bottom of the electrical components is better, further reducing the risk of short circuits between adjacent solder bumps of the electrical components.

[0128] Both the filler forming the filling structure 91 and the material of the encapsulation layer may contain filler particles. The size of the filler particles in the filling structure 91 is smaller than the size of the filler particles in the encapsulation layer. This is more conducive to reducing the probability of voids at the bottom of the electrical component, improving the filling effect at the bottom of the electrical component, and reducing the risk of short circuit between adjacent solder bumps of the electrical component.

[0129] In one embodiment, after step 140 , the semiconductor structure manufacturing method further includes: forming an encapsulation layer covering the electrical element.

[0130] After this step, the support 24 is removed and the following is obtained: Figure 14 The eleventh intermediate structure shown. Figure 14 As shown, the encapsulation layer 92 covers the second chip 81, the heat dissipation layer 80 and the passive component 82. The encapsulation layer 92 can protect the second chip 81, the heat dissipation layer 80 and the passive component 82.

[0131] In one embodiment, Figure 14 As shown, the surface of the heat dissipation layer 80 facing away from the redistribution layer 40 exposes the encapsulation layer 92. This ensures that the heat dissipation effect of the heat dissipation layer 80 is better.

[0132] In one embodiment, the thickness of the initially formed encapsulation layer 92 may be greater than the thickness of the heat dissipation layer 80. The thickness of the encapsulation layer 92 is made substantially the same as the thickness of the heat dissipation layer 80 by thinning the side of the encapsulation layer 92 facing away from the first chip 10. This exposes the encapsulation layer 92 on the surface of the heat dissipation layer 80 facing away from the redistribution layer 40. The surface of the encapsulation layer 92 facing away from the redistribution layer 40 may be thinned by a grinding process.

[0133] In one embodiment, before forming the encapsulation layer 92, some pre-processing steps, such as chemical cleaning, plasma cleaning, etc., can be performed to remove impurities on the surface of the electrical components facing away from the first chip 10 and impurities on the surface of the plastic layer 30 facing away from the first chip 10, so that the encapsulation layer 92 can be more closely connected to the electrical components and the plastic layer 30 without delamination or cracking.

[0134] In one embodiment, the material of the encapsulation layer 92 can be a polymer resin, a resin composite material, a polymer composite material, etc. For example, the encapsulation layer 92 can be a resin with a filler, wherein the filler can be inorganic particles. The encapsulation layer 92 can be formed by injection molding, compression molding, or transfer molding.

[0135] In one embodiment, after the step of filling the through-hole with a fluid conductive material and forming the conductive portion after the conductive material is solidified, the method for manufacturing the semiconductor structure further includes: filling a filler between the surface of the step structure facing the plastic layer and not in contact with the plastic layer and the plastic layer to form a filling portion. This step can be performed after the step of forming the encapsulation layer. After the step of forming the encapsulation layer and before this step, the method for manufacturing the semiconductor structure further includes: peeling off the support member and mounting the resulting structure on a carrier, with the redistribution layer located on the side of the first chip facing away from the carrier.

[0136] Through this step, we can obtain Figure 15 The twelfth intermediate structure shown. Figure 15 As shown, the encapsulation layer 92 is attached to the carrier 26 via the adhesive layer 25; the surface of the filling portion 93 facing away from the rewiring layer 40 abuts the portion of the step structure 401 not in contact with the plastic layer 30, specifically, the surface of the second trace structure 44 facing the plastic layer 30; the surface of the filling portion 93 facing the plastic layer 30 abuts the plastic layer 30. In this manner, by first filling the space between the electrical component and the plastic layer with a filler to form the filling portion 93, and then forming a dielectric layer (described below) to cover the rewiring layer, the probability of voids at the bottom of the rewiring layer can be reduced. That is, after the dielectric layer covers the rewiring layer, the bottom of the rewiring layer can have smaller voids or no voids, resulting in a better filling effect at the bottom of the rewiring layer and improving the quality of the semiconductor structure.

[0137] The filler forming the filling portion 93 and the material of the dielectric layer may both contain filler particles. The size of the filler particles in the filling portion 93 is smaller than that of the filler particles in the dielectric layer. This is more conducive to reducing the probability of voids at the bottom of the redistribution layer and improving the filling effect at the bottom of the redistribution layer.

[0138] After the step of filling a filler between the surface of the step structure facing the molding layer and not in contact with the molding layer and the molding layer to form a filling portion, the manufacturing method of the semiconductor structure may further include: forming a dielectric layer, the dielectric layer covering the second trace structure, and the second trace structure not exposing the dielectric layer.

[0139] Through this step, we can obtain Figure 16 The thirteenth intermediate structure shown. Figure 16 As shown, the dielectric layer 94 covers each second trace structure 44 , the exposed molding layer 30 and the exposed insulating film layer 12 .

[0140] In another embodiment, after the step of filling the through-hole with a fluid conductive material and forming the conductive portion after the conductive material solidifies, the method for manufacturing the semiconductor structure further includes: forming a plastic film layer, wherein the plastic film layer covers the redistribution layer and fills the gap between the surface of the step structure facing the plastic layer and not in contact with the plastic layer and the plastic layer. This step can be performed after the step of forming the encapsulation layer. After the step of forming the encapsulation layer and before this step, the method for manufacturing the semiconductor structure further includes: peeling off the support member and mounting the resulting structure on a carrier, with the redistribution layer located on the side of the first chip facing away from the carrier.

[0141] Through this step, we can obtain Figure 17 The thirteenth intermediate structure shown. Figure 17 As shown, the encapsulation layer 92 is attached to the carrier 26 via the adhesive layer 25; the plastic film layer 99 covers the rewiring layer 40 and fills the gap between the surface of the step structure 401 facing the plastic layer 30 and not in contact with the plastic layer 30. In this way, the plastic film layer 99 that covers the rewiring layer 40 and fills the gap between the second trace structure and the plastic layer 30 can be formed in a single plastic encapsulation process, which helps simplify the manufacturing process. The material of the plastic film layer 99 can contain filler particles, which can help reduce the probability of voids at the bottom of the rewiring layer and improve the filling effect at the bottom of the rewiring layer.

[0142] In one embodiment, after obtaining the thirteenth intermediate structure, the manufacturing method of the semiconductor structure further includes: forming a rewiring structure on the side of the rewiring layer away from the first chip, the rewiring structure including a third trace structure electrically connected to the rewiring layer and a conductive protrusion located on the side of the third trace structure away from the rewiring layer.

[0143] The thirteenth intermediate structure is as follows Figure 16 As shown, the above steps can be used to obtain Figure 18 The fourteenth intermediate structure shown. Figure 18 As shown, the redistribution structure 95 is located on the side of the dielectric layer 94 facing away from the first chip 10 and includes a plurality of third trace structures 951 and a plurality of conductive bumps 952. Each third trace structure 951 can be electrically connected to one or more second trace structures 44, and each trace structure 951 can be provided with one or more conductive bumps 952. The dielectric layer 94 can be provided with openings 941 corresponding one to each second trace structure 44, with each opening 941 exposing a portion of a corresponding second trace structure 44. The third trace structures 951 are electrically connected to the second trace structures 44 via conductive structures 96 located within the openings 941.

[0144] In the above embodiment, the third trace structure includes a conductive protrusion, which facilitates electrical connection between the external structure and the semiconductor structure. In other embodiments, no rewiring structure may be formed, and only the conductive protrusion may be formed in the opening of the dielectric layer.

[0145] In one embodiment, after obtaining the fourteenth intermediate structure, the method for manufacturing the semiconductor structure further includes: forming a dielectric film layer, wherein the dielectric film layer covers the redistribution structure, and the conductive protrusion faces away from the surface of the first chip to expose the dielectric film layer.

[0146] After this step, the carrier is removed to obtain Figure 19 The semiconductor structure shown in FIG. Figure 19 As shown, the dielectric film layer 97 covers the redistribution structure 95 and the exposed dielectric layer 94 .

[0147] In one embodiment, the method for manufacturing the semiconductor structure further includes forming a plurality of conductive balls on a side of the redistribution structure facing away from the first chip using a ball planting process. After removing the carrier 26, the surface of the conductive protrusions of the redistribution structure facing away from the first chip is exposed, allowing ball planting to be performed on the surface of the conductive protrusions facing away from the first chip.

[0148] Through this step, we can obtain Figure 20 The semiconductor structure shown in FIG. Figure 20 As shown, each conductive bump 952 of the rewiring structure 95 has a conductive ball 98 formed on a surface facing away from the first chip 10. The rewiring structure 95 of the semiconductor structure can be soldered to a circuit board via the conductive balls 98, facilitating connection between the semiconductor structure and the circuit board. The conductive balls 98 can be made of solder paste, metallic tin, or a tin alloy.

[0149] In one embodiment, the thirteenth intermediate structure is as follows Figure 17 As shown, a plurality of conductive balls are formed on the side of the rewiring structure away from the first chip by using a ball planting process, and the result is as shown in FIG. Figure 21 The semiconductor structure shown.

[0150] In one embodiment, when the number of first chips included in the structure to be wired in step 110 is multiple, after step 140, the method for manufacturing a semiconductor structure further includes: cutting the obtained structure along the cutting street to obtain multiple semiconductor structures. The semiconductor structure obtained after cutting can be as follows Figure 19 、 Figure 20 or Figure 21 As shown, each semiconductor structure may include at least one first chip.

[0151] The present application also provides a semiconductor structure. Figures 19 to 21As shown, the semiconductor structure includes a first chip 10, a plastic encapsulation layer 30, a conductive portion 70, a redistribution layer 40 and electrical components.

[0152] The first chip 10 includes a front surface, a back surface opposite the front surface, and multiple side surfaces connecting the front and back surfaces. The front surface is provided with multiple solder pads. The plastic encapsulation layer 30 covers the side surfaces of the chip and is provided with at least one through-hole 31. The conductive portion 70 is at least partially located within the through-hole 31. The conductive portion 70 is made of at least one material selected from solder and silver paste. The redistribution layer 40 is located on the side of the plastic encapsulation layer 30 adjacent to the chip front surface. The redistribution layer 40 is electrically connected to the solder pads and the conductive portion 30. The redistribution layer 40 is provided with at least one stepped structure 401 facing the plastic encapsulation layer 30. Each through-hole 31 corresponds to a stepped structure 401. The orthographic projections of the through-holes 31 on the plane containing the chip front all fall within the orthographic projection of the redistribution layer 40 on the plane. The orthographic projections of the portions of the stepped structures 401 not in contact with the plastic encapsulation layer 30 on the plane at least partially overlap with the orthographic projections of the corresponding through-holes 31 on the plane. The electrical components are located on a side of the plastic packaging layer 30 away from the front surface of the chip, and at least one of the electrical components is welded to the conductive portion 70 .

[0153] In the semiconductor structure provided by the embodiment of the present application, since the material of the conductive part includes at least one of solder and silver paste, the conductive part can be obtained by filling the fluid conductive material into the through hole and solidifying it. The conductive material can fill the through hole, ensuring that the conductive part obtained after the conductive material is solidified has good electrical connection with the electrical components and the redistribution layer. Compared with the solution of forming the conductive part in the through hole by the electroplating process, the problem of the hole wall of the through hole not being plated with the conductive material in the electroplating process and the problem of short circuit between the electrical component and the redistribution layer caused by the alignment deviation in the electroplating process can be improved; the semiconductor structure does not need to be provided with a lead frame or a conductive column, which can avoid the lead frame and the conductive column. The electric column is deformed and offset, which may cause a short circuit or open circuit between the redistribution layer on the front of the chip and the chip, which helps to improve the product yield; by providing a step structure facing the plastic layer on the redistribution layer, the orthographic projection of the part of the step structure that is not in contact with the plastic layer on the plane where the front of the chip is located and the orthographic projection of the corresponding through hole on the plane at least partially overlap, then in the process of welding the conductive part to the electrical component, the gas in the through hole and the flux in the solder can be discharged through the channel between the part of the step structure that is not in contact with the plastic layer and the plastic layer, which can avoid the presence of gas or flux in the through hole causing voids in the conductive part and affecting the quality of the semiconductor structure.

[0154] In one embodiment, Figures 19 to 21As shown, the redistribution layer 40 includes a first trace layer 41 and a second trace layer 43 located on the side of the first trace layer 41 away from the first chip 10; the first trace layer 41 includes a plurality of first trace structures 42; the first trace structures 42 are electrically connected to the pads; the second trace layer 43 includes a second trace structure 44 located on the side of each first trace structure 42 away from the first chip, and at least one side of at least one second trace structure 44 exceeds the corresponding first trace structure 42 to form a step structure 401.

[0155] In one embodiment, Figures 19 to 21 As shown, the orthographic projection of the portion of the edge of the through hole 31 not in contact with the redistribution layer 40 on the plane is located inside the edge of the orthographic projection of the portion of the step structure 401 not in contact with the plastic layer 30 on the plane.

[0156] In one embodiment, Figures 19 to 21 As shown, the conductive portion 70 contacts both the first trace structure 42 and the second trace structure 44 , or the conductive portion 70 contacts only the second trace structure 44 .

[0157] In one embodiment, Figures 19 to 21 As shown, the distance d between the surface of the step structure 401 facing the molding layer 30 and not in contact with the molding layer 30 and the molding layer 30 is in a range of 10 μm to 60 μm.

[0158] In one embodiment, Figures 19 to 21 As shown, the electrical component includes a heat dissipation layer 80 , and the heat dissipation layer 80 is formed simultaneously with the conductive portion 70 .

[0159] In one embodiment, the electrical component includes at least one of a second chip, an inductor, a resistor, a capacitor, and a heat dissipation layer.

[0160] In one embodiment, Figure 19 and Figure 20 As shown, the semiconductor structure further includes a filling portion 93 located between the surface of the step structure 401 facing the molding layer 30 and not in contact with the molding layer 30 and the molding layer 30 .

[0161] In one embodiment, Figures 19 to 21 As shown, when the electrical component includes a second chip, the semiconductor structure further includes a filling structure 91 located between the second chip and the plastic packaging layer.

[0162] In one embodiment, Figure 20 and Figure 21As shown, the semiconductor structure further includes a plurality of conductive balls 98 located on a side of the redistribution layer 40 facing away from the first chip 10 .

[0163] The embodiment of the method for manufacturing a semiconductor structure provided in the embodiment of the present application and the embodiment of the semiconductor structure belong to the same inventive concept, and the description of relevant details and beneficial effects can be referred to each other, and will not be repeated here.

[0164] It should be noted that in the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It will also be understood that when an element or layer is referred to as being "on" another element or layer, it may be directly on the other element, or there may be an intermediate layer. In addition, it will be understood that when an element or layer is referred to as being "under" another element or layer, it may be directly under the other element, or there may be more than one intermediate layer or element. In addition, it will also be understood that when a layer or element is referred to as being "between" two layers or elements, it may be the only layer between the two layers or elements, or there may also be more than one intermediate layer or element. Similar reference numerals throughout the text indicate similar elements.

[0165] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present application that follow the general principles of the present application and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0166] It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: The manufacturing method comprises: forming a structure to be wired, the structure to be wired comprising a first chip and a plastic encapsulation layer; the first chip comprising a chip front, a chip back opposite to the chip front, and a plurality of chip side surfaces connecting the chip front and the chip back, the chip front being provided with a plurality of bonding pads; the plastic encapsulation layer at least encapsulating the chip side surfaces; forming a redistribution layer, the redistribution layer being located on the front side of the chip and electrically connected to the pad; the redistribution layer being provided with at least one step structure facing the plastic encapsulation layer; At least one through hole is formed on the plastic encapsulation layer, penetrating the plastic encapsulation layer; each through hole corresponds to one of the step structures, and the orthographic projections of the through holes on the plane where the chip front surface is located all fall within the orthographic projection of the redistribution layer on the plane, and the orthographic projections of the through holes on the plane at least partially overlap with the orthographic projections of the corresponding portions of the step structures not in contact with the plastic encapsulation layer on the plane; The through hole is filled with a fluid conductive material, and the conductive material forms a conductive portion after solidification. An electrical component is arranged on the back side of the chip, and at least one of the electrical components is welded to the conductive portion.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein: The forming of the redistribution layer comprises: A first trace layer and a second trace layer located on a side of the first trace layer facing away from the structure to be wired are formed on the structure to be wired, so as to obtain a rewiring layer including the first trace layer and the second trace layer; the first trace layer includes a plurality of first trace structures; the first trace structures are electrically connected to the pads; the second trace layer includes a second trace structure located on a side of each of the first trace structures facing away from the structure to be wired, and at least one side of at least one of the second trace structures exceeds the corresponding first trace structure to form a step structure.

3. The method for manufacturing a semiconductor structure according to claim 1, wherein: The orthographic projection of a portion of the edge of the through hole that is not in contact with the redistribution layer on the plane is located inside the edge of the orthographic projection of a portion of the corresponding step structure that is not in contact with the plastic encapsulation layer on the plane; and / or, A distance between a surface of the step structure facing the molding layer and not in contact with the molding layer and the molding layer is in a range of 10 μm to 60 μm.

4. The method for manufacturing a semiconductor structure according to claim 1, wherein: After forming the redistribution layer, a semiconductor intermediate structure is obtained; the plastic encapsulation layer includes a cutting line, and the redistribution layer is in contact with a region of the plastic encapsulation layer outside the cutting line; Before forming a plurality of through holes penetrating the plastic encapsulation layer on the plastic encapsulation layer, the method for manufacturing the semiconductor structure further includes: Placing the semiconductor intermediate structure on a support member, wherein the support member includes a plate portion and a support portion formed by extending from one side of the plate portion, wherein the support portion contacts the cutting street, and the redistribution layer faces the plate portion and has a gap between the redistribution layer and the plate portion; After arranging electrical components on the back side of the chip and welding at least one of the electrical components to the conductive portion, the method for preparing the semiconductor structure further includes: The obtained structure is cut along the cutting streets.

5. The method for manufacturing a semiconductor structure according to claim 1, wherein: After the through hole is filled with a fluid conductive material and the conductive material is solidified to form the conductive portion, the method for manufacturing the semiconductor structure further includes: Filling a filler between the surface of the step structure facing the plastic sealing layer and not in contact with the plastic sealing layer and the plastic sealing layer to form a filling portion; or, A plastic film layer is formed, wherein the plastic film layer covers the redistribution layer and fills a gap between a surface of the step structure that faces the plastic layer and does not contact the plastic layer and the plastic layer.

6. The method for manufacturing a semiconductor structure according to claim 1, wherein: The electrical component includes a second chip, the electrical component is provided on the back side of the chip, and after at least one of the electrical components is welded to the conductive portion, the method for manufacturing the semiconductor structure further includes: A filler is filled between the second chip and the plastic packaging layer to form a filling structure.

7. The method for manufacturing a semiconductor structure according to claim 1, wherein: The surface of the conductive portion facing away from the redistribution layer extends beyond the surface of the plastic packaging layer facing away from the redistribution layer.

8. The method for manufacturing a semiconductor structure according to claim 1, wherein: The electrical component includes a heat dissipation layer, and the heat dissipation layer is formed simultaneously with the conductive portion.

9. The method for manufacturing a semiconductor structure according to claim 1, wherein: The electrical component includes at least one of a second chip, an inductor, a resistor, a capacitor, and a heat dissipation layer; and / or, The conductive material includes at least one of solder and silver paste.

10. A semiconductor structure, characterized in that The semiconductor structure comprises: A first chip, comprising a chip front side, a chip back side opposite to the chip front side, and a plurality of chip side sides connecting the chip front side and the chip back side, wherein the chip front side is provided with a plurality of bonding pads; A plastic encapsulation layer, covering the side surface of the chip, wherein the plastic encapsulation layer is provided with at least one through hole; A conductive portion, at least partially located in the through hole; the conductive portion is made of at least one of solder and silver paste; a redistribution layer located on a side of the plastic encapsulation layer close to the front surface of the chip, the redistribution layer being electrically connected to the bonding pad and the conductive portion; the redistribution layer being provided with at least one step structure facing the plastic encapsulation layer; each of the through holes corresponding to one of the step structures, the orthographic projections of the through holes on the plane where the front surface of the chip is located all falling within the orthographic projection of the redistribution layer on the plane, and the orthographic projections of portions of the step structures not in contact with the plastic encapsulation layer on the plane at least partially overlapping with the orthographic projections of the corresponding through holes on the plane; The electrical component is located on a side of the plastic packaging layer away from the front surface of the chip, and at least one of the electrical components is welded to the conductive part.

11. The semiconductor structure according to claim 10, wherein: The redistribution layer includes a first trace layer and a second trace layer located on a side of the first trace layer away from the first chip; the first trace layer includes a plurality of first trace structures; The first trace structure is electrically connected to the bonding pad; the second trace layer includes a second trace structure located on a side of each first trace structure away from the first chip, and at least one side of at least one second trace structure exceeds the corresponding first trace structure to form a step structure.

12. The semiconductor structure according to claim 11, wherein: The conductive portion contacts both the first trace structure and the second trace structure, or the conductive portion contacts only the second trace structure.

13. The semiconductor structure according to claim 11, wherein: The orthographic projection of a portion of the edge of the through hole that is not in contact with the redistribution layer on the plane is located inside the edge of the orthographic projection of a portion of the corresponding step structure that is not in contact with the plastic encapsulation layer on the plane; and / or, A distance between a surface of the step structure facing the molding layer and not in contact with the molding layer and the molding layer is in a range of 10 μm to 60 μm.

14. The semiconductor structure according to claim 11, wherein: The semiconductor structure further includes a filling portion located between a surface of the step structure facing the molding layer and not in contact with the molding layer and the molding layer; and / or, The electrical component includes a second chip, and the semiconductor structure further includes a filling structure located between the second chip and the plastic packaging layer.

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