Semiconductor structure and method for forming the same

Abstract

The present disclosure provides a semiconductor structure and a method for forming the same, the method comprising: providing a substrate, the substrate comprising an array region, a peripheral region, and an interface region between the array region and the peripheral region; sequentially forming a first mask layer and a second mask layer on the substrate, and forming a first mask pattern located directly above the array region and a second mask pattern located directly above the interface region in the second mask layer; the unit size of the second mask pattern is smaller than the unit size of the first mask pattern; forming a third mask pattern located directly above the array region in the first mask layer based on the first mask pattern, and forming a blocking pattern located directly above the interface region based on the second mask pattern.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] In order to meet the demand for high integration of memory devices, it has been proposed to form array patterns through a self-aligned double patterning (SADP) process and a self-aligned quadruple patterning (SAQP) process.

[0003] However, as the integration density of memory devices continues to increase, the cell pitch of the array pattern continues to shrink. During the process of forming the array pattern using the SADP process and the SAQP process, the loading effect becomes increasingly severe, resulting in abnormalities in the array pattern. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a semiconductor structure and a method for forming the same in order to solve at least one problem existing in the prior art.

[0005] To achieve the above objectives, the technical solution of the embodiment of the present disclosure is implemented as follows:

[0006] In a first aspect, an embodiment of the present disclosure provides a method for forming a semiconductor structure, comprising:

[0007] Providing a substrate, the substrate comprising an array region, a peripheral region, and a boundary region between the array region and the peripheral region;

[0008] forming a first mask layer and a second mask layer in sequence on the substrate, and forming a first mask pattern located directly above the array region and a second mask pattern located directly above the boundary region in the second mask layer; a unit size of the second mask pattern is smaller than a unit size of the first mask pattern;

[0009] A third mask pattern located directly above the array region is formed in the first mask layer based on the first mask pattern, and a barrier pattern located directly above the interface region is formed based on the second mask pattern.

[0010] In an optional embodiment, forming a third mask pattern located directly above the array region in the first mask layer based on the first mask pattern, and forming a barrier pattern located directly above the boundary region based on the second mask pattern, includes:

[0011] A dielectric layer is formed to cover the first mask pattern, the second mask pattern, and the first mask layer, and the material of the dielectric layer completely fills the gaps between the second mask patterns.

[0012] In an optional embodiment, the forming of a third mask pattern located directly above the array region in the first mask layer based on the first mask pattern, and the forming of a barrier pattern located directly above the boundary region based on the second mask pattern further includes:

[0013] forming a first photoresist layer covering the dielectric layer located directly above the peripheral region and the boundary region;

[0014] removing the dielectric layer covering the top of the first mask pattern and the first mask pattern to form a first spacer; and removing the first photoresist layer and a portion of the dielectric layer located directly above the interface region;

[0015] The first mask layer located directly above the array area is etched using the first spacer as a mask to form the third mask pattern; the first mask layer located directly above the boundary area, the second mask pattern and the remaining dielectric layer constitute the blocking pattern.

[0016] In an optional embodiment, a top surface of the dielectric layer in the blocking pattern is higher than a top surface of the third mask pattern.

[0017] In an optional embodiment, before forming the first mask layer on the substrate, the forming method further includes:

[0018] forming a third mask layer on the substrate; the third mask layer comprising a fourth mask pattern located directly above the array region and the interface region;

[0019] After forming a third mask pattern located directly above the array region in the first mask layer based on the first mask pattern, and forming a barrier pattern located directly above the boundary region based on the second mask pattern, the forming method further includes:

[0020] An array pattern is formed in the array region based on the third mask pattern and the fourth mask pattern, and the array pattern is not formed in the boundary region based on the barrier pattern and the fourth mask pattern.

[0021] In an optional embodiment, a unit size of the fourth mask pattern located directly above the array region is equal to a unit size of the fourth mask pattern located directly above the boundary region.

[0022] In an optional embodiment, before forming the third mask layer on the substrate, the forming method further includes:

[0023] forming an amorphous carbon layer on the substrate;

[0024] The forming of the array pattern in the array region based on the third mask pattern and the fourth mask pattern, and not forming the array pattern in the boundary region based on the blocking pattern and the fourth mask pattern, comprises:

[0025] etching the amorphous carbon layer using the third mask pattern, the barrier pattern, and the fourth mask pattern as masks, and transferring a pattern formed by overlapping the third mask pattern and the fourth mask pattern to the amorphous carbon layer directly above the array region to form a patterned amorphous carbon layer;

[0026] The substrate is etched using the patterned amorphous carbon layer as a mask, and the remaining amorphous carbon layer is removed to form an array pattern in the array region, while no array pattern is formed in the boundary region.

[0027] In an optional embodiment, forming a first mask pattern located directly above the array region and a second mask pattern located directly above the boundary region in the second mask layer includes:

[0028] forming a fourth mask layer on the second mask layer;

[0029] forming a patterned second photoresist layer on the fourth mask layer; the patterned second photoresist layer comprising a first photoresist pattern located directly above the array region and a second photoresist pattern located directly above the boundary region, wherein a unit size of the first photoresist pattern is larger than a unit size of the second photoresist pattern;

[0030] etching the fourth mask layer using the patterned second photoresist layer as a mask to form a fifth mask pattern located directly above the array region and a sixth mask pattern located directly above the boundary region in the fourth mask layer;

[0031] forming a second spacer on a sidewall of the fifth mask pattern, and forming a third spacer on a sidewall of the sixth mask pattern;

[0032] removing the fifth mask pattern and the sixth mask pattern;

[0033] The second mask layer is etched using the second spacer and the third spacer as a mask to form the first mask pattern and the second mask pattern.

[0034] In an optional embodiment, a ratio of a unit size of the first photolithographic pattern to a unit size of the second photolithographic pattern is greater than a first preset value and less than a second preset value.

[0035] In an optional implementation, the first preset value is 1.2, and the second preset value is 2.

[0036] In an optional embodiment, providing a substrate comprises:

[0037] forming a metal layer;

[0038] forming a stacked structure in which a sacrificial layer and a supporting layer are overlapped on the metal layer;

[0039] An oxide layer is formed on the stack structure.

[0040] In an optional embodiment, forming an array pattern in the array area based on the third mask pattern and the fourth mask pattern includes:

[0041] forming an array pattern in the oxide layer based on the third mask pattern and the fourth mask pattern;

[0042] A capacitor hole array is formed in the stacked structure using the array pattern as a mask.

[0043] In an optional embodiment, forming a third mask layer on the substrate includes:

[0044] forming the fourth mask pattern on the substrate;

[0045] A filling layer covering the fourth mask pattern and the peripheral area is formed, and a side of the filling layer facing away from the substrate is planarized so that the filling layer on the array area, the peripheral area and the boundary area is flush with a top surface of the fourth mask pattern.

[0046] In an optional embodiment, forming the fourth mask pattern on the substrate includes:

[0047] forming a fifth mask layer and a sixth mask layer in sequence on the third mask layer;

[0048] forming a seventh mask pattern in the sixth mask layer, the pattern being located directly above the array region and the interface region;

[0049] forming a fourth spacer on a sidewall of the seventh mask pattern, and removing the seventh mask pattern;

[0050] etching the fifth mask layer using the fourth spacer as a mask to form an eighth mask pattern located directly above the array region and the boundary region;

[0051] forming a fifth spacer on a sidewall of the eighth mask pattern, and removing the eighth mask pattern;

[0052] The third mask layer is etched using the fifth spacer as a mask to form the fourth mask pattern located directly above the array region and the boundary region.

[0053] In a second aspect, an embodiment of the present disclosure provides a semiconductor structure, which is obtained by the method for forming a semiconductor structure in any of the aforementioned embodiments.

[0054] In the technical solution provided in the present disclosure, by reducing the unit size of the mask pattern located directly above the junction area, the material of the dielectric layer can completely fill the gap between the mask patterns in the area. On the one hand, it can provide support for the photoresist layer covering the junction area, reducing the risk of the photoresist layer sliding sideways and causing the opening at the junction of the array area and the junction area to be blocked, thereby effectively reducing the possibility of abnormalities in the array pattern and improving the reliability of the ultimately formed semiconductor structure. On the other hand, a blocking pattern can be further formed to avoid the formation of redundant patterns in the junction area, so that the size of the junction area can be reduced, which is conducive to the miniaturization development of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figures 1 to 4 A schematic diagram of the structure of the array pattern forming process provided for the related art;

[0056] Figure 5 A schematic flow chart of a method for forming a semiconductor structure according to an embodiment of the present disclosure;

[0057] Figures 6 to 19 A structural schematic diagram of the semiconductor structure formation process provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0058] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0059] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0060] In the drawings, like reference numerals refer to like elements throughout.

[0061] It should be understood that spatial relationship terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" can include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial description terms used herein are interpreted accordingly.

[0062] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0063] Related technologies have proposed using SADP and SAQP processes to form capacitor hole arrays with small cell sizes and high aspect ratios (AR). However, as the integration density of memory devices continues to increase, the cell size of the array pattern continues to shrink. During the formation of the array pattern using SADP and SAQP processes, the loading effect becomes increasingly severe, resulting in anomalies at the boundaries of the array pattern.

[0064] In order to reduce the negative impact of the load effect on the array pattern, it has been proposed to set an interface area between the array area where the array pattern is formed and the peripheral area where the peripheral circuit is formed. In the process of forming the mask pattern, a mask pattern is also formed in the mask layer directly above the interface area, so that the etching environment of the mask pattern close to the peripheral area is the same as that of the mask pattern far from the peripheral area, thereby reducing the probability of abnormalities in the array pattern at the boundary of the array area.

[0065] Figures 1 to 4 Schematic diagram of the formation process of the array pattern in the related art. Figure 1 , a mask layer 2 including a mask pattern 3 is formed on the target layer 1, a mask layer 4 is formed on the mask layer 2, and a mask pattern 5 is formed on the mask layer 4, and both the mask pattern 3 and the mask pattern 5 are formed directly above the array region and the interface region. Figure 2 and Figure 3 , forming a dielectric layer 6 covering the mask pattern 5 and the mask layer 4, and forming a photoresist layer 7 covering the dielectric layer 6 directly above the interface area and the peripheral area, and then removing the dielectric layer 6 and the mask pattern 5 on top of the mask pattern 5 to form a spacer, and etching the mask layer 4 using the spacer as a mask to form a mask pattern 8 directly above the array area. Figure 4 , the mask pattern 3 and the mask pattern 8 are transferred to the target layer 1 to form an array pattern 9.

[0066] In the process of forming the array pattern 9, since the unit size of the mask pattern 5 located directly above the array region and the boundary region is the same, Figure 3 and Figure 4 , an opening penetrating the mask layer 4 along the Z direction will also be formed in the mask layer 4 just above the interface area, which will eventually lead to the generation of redundant patterns in the target layer 1 in the interface area. Figure 2 The photoresist layer 7 located directly above the interface area is formed on the uneven dielectric layer 6, and the top corner of the dielectric layer 6 at the interface between the array area and the interface area is easily rounded, which may cause the photoresist layer 7 at the interface between the array area and the interface area to slip sideways, so that the opening at the boundary is also partially filled with photoresist, which eventually leads to Figure 4 The openings of the array pattern 9 at the corresponding positions cannot penetrate the target layer 1 .

[0067] Both of the above situations will cause anomalies in the final array pattern and will further affect the formation of the capacitor hole array in subsequent steps.

[0068] Therefore, further optimizing the formation process of the array pattern has become an urgent problem to be solved. In this regard, the present disclosure proposes the following implementation methods.

[0069] The present disclosure provides a method for forming a semiconductor structure. Figure 5 Schematic diagram of the process of forming a semiconductor structure provided by an embodiment of the present disclosure. Figure 5 As shown, the method for forming a semiconductor structure includes the following steps:

[0070] Step S101: providing a substrate, wherein the substrate comprises an array region, a peripheral region, and a boundary region between the array region and the peripheral region;

[0071] Step S102: forming a first mask layer and a second mask layer in sequence on the substrate, and forming a first mask pattern located directly above the array region and a second mask pattern located directly above the boundary region in the second mask layer; a cell size of the second mask pattern is smaller than a cell size of the first mask pattern;

[0072] Step S103 : forming a third mask pattern located directly above the array region in the first mask layer based on the first mask pattern, and forming a barrier pattern located directly above the boundary region based on the second mask pattern.

[0073] Figures 6 to 19 The schematic diagram of the semiconductor structure forming process provided by the embodiment of the present disclosure is shown below. Figure 5 、 Figures 6 to 19 The method for forming the semiconductor structure provided by the embodiment of the present disclosure is described in detail.

[0074] Reference Figure 6 , performing step S101, providing a substrate 100, the substrate 100 includes an array area a, a peripheral area c and a boundary area b located between the array area a and the peripheral area c.

[0075] It should be noted that the figure only shows part of the array area a and part of the peripheral area c, and the size of the junction area b in the X direction is only an example. The present disclosure does not limit the specific sizes of the array area a, the junction area b and the peripheral area c in the X direction.

[0076] In some embodiments, providing a substrate 100 includes: forming a metal layer 101; forming a stacked structure on the metal layer 101, in which a sacrificial layer 103 and a supporting layer 102 are arranged in an overlapping manner along the Z direction; and forming a polysilicon layer 104 and an oxide layer 105 on the stacked structure. The oxide layer 105 is a target etching layer for forming an array pattern.

[0077] In some specific examples, the material of the metal layer 101 includes but is not limited to tungsten; the material of the support layer 102 includes but is not limited to silicon oxide; and the material of the sacrificial layer 103 includes but is not limited to silicon nitride.

[0078] In some specific examples, the material of the oxide layer 105 includes but is not limited to doped silicon oxide, such as phosphorus-doped silicon oxide and phosphorus-boron-doped silicon oxide.

[0079] In some embodiments, in conjunction with reference Figures 6 to 11 The method for forming a semiconductor structure includes forming a fourth mask pattern 30 on a substrate 100 through a SAQP process, and the specific process is as follows.

[0080] Combined with reference Figure 6 and Figure 7 , a third mask layer 202 , a fifth mask layer 203 and a sixth mask layer 204 are sequentially formed on the substrate 100 ; a seventh mask pattern 10 is formed in the sixth mask layer 204 and is located directly above the array region a and the boundary region b.

[0081] In the embodiment of the present disclosure, the sixth mask layer 204 includes a first sub-mask layer 2041, a second sub-mask layer 2042 and a third sub-mask layer 2043 arranged in sequence along the Z direction. A patterned third photoresist layer 205 is first formed on the third sub-mask layer 2043, and the sixth mask layer 204 is etched using the patterned third photoresist layer 205 as a mask to form a seventh mask pattern 10. In this process, the first sub-mask layer 2041 serves as an etching stop layer, so that the opening formed by etching the sixth mask layer 204 can stop on the first sub-mask layer 2041 or inside the first sub-mask layer 2041.

[0082] In some specific examples, the material of the third mask layer 202 includes but is not limited to silicon-rich silicon oxynitride; the material of the fifth mask layer 203 includes but is not limited to amorphous carbon; the material of the first sub-mask layer 2041 includes but is not limited to silicon oxide; the material of the second sub-mask layer 2042 includes but is not limited to spin-on hard mask (SOH) material (for example, silicon hard mask material, carbon hard mask material, organic hard mask material, etc.); the material of the third sub-mask layer 2043 includes but is not limited to silicon oxynitride.

[0083] In some specific examples, the third mask layer 202 , the fifth mask layer 203 and the sixth mask layer 204 are formed by a deposition process or a spin coating process, and the sixth mask layer 204 is etched by a dry etching process.

[0084] In the embodiments of the present disclosure, the deposition process includes but is not limited to chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD) and atomic layer deposition (ALD); the spin coating process includes but is not limited to spin-on dielectrics (SOD) process; the dry etching process includes but is not limited to plasma etching (PE), sputtering etching (SE), ion beam etching (IBE) and reactive ion etching (RIE).

[0085] Reference Figure 8 , forming a second dielectric layer 206 covering the seventh mask pattern 10. Here, the second dielectric layer 206 is formed by an ALD process, and the second dielectric layer 206 also covers the bottom of the opening between the seventh mask patterns 10 and the top surface of the sixth mask layer 204 located directly above the peripheral region c.

[0086] Combined with reference Figure 8 and Figure 9 , remove the second dielectric layer 206 covering the top of the seventh mask pattern 10 and the bottom of the opening to form a fourth spacer on the sidewall of the seventh mask pattern 10, and remove the seventh mask pattern 10. Use the fourth spacer as a mask to etch the fifth mask layer 203 to form an eighth mask pattern 20 located directly above the array area a and the boundary area b.

[0087] In some specific examples, an anisotropic etching process is used to etch the second dielectric layer 206. The anisotropic etching process includes but is not limited to a plasma etching process with high selectivity. When the top of the seventh mask pattern 10 and the second dielectric layer 206 located on the sixth mask layer 204 are etched away, the second dielectric layer 206 covering the sidewalls of the seventh mask pattern 10 may not be laterally etched, thereby forming a fourth spacer located on the sidewalls of the seventh mask pattern 10.

[0088] Combined with reference Figure 10 and Figure 11, forming a third dielectric layer 207 covering the eighth mask pattern 20; removing the third dielectric layer 207 covering the top of the eighth mask pattern 20 and the bottom of the opening between the eighth mask pattern 20 to form a fifth spacer on the sidewall of the eighth mask pattern 20, and removing the eighth mask pattern 20. Using the fifth spacer as a mask, the third mask layer 202 is etched to form a fourth mask pattern 30 located directly above the array area a and the boundary area b.

[0089] In some embodiments, after etching the fifth mask layer 203 using the fourth spacer as a mask to form the eighth mask pattern 80, a portion of the material of the first sub-mask layer 2041 remains on the top of the eighth mask pattern 80. The material of the first sub-mask layer 2041 remaining on the top of the eighth mask pattern 80 can be removed first, and then the third dielectric layer 207 covering the eighth mask pattern 80 is formed.

[0090] In some specific examples, the material of the second dielectric layer 206 and / or the third dielectric layer 207 includes at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon carbonitride, silicon carbon oxynitride, or boron nitride.

[0091] In the embodiment of the present disclosure, the unit size of the fourth mask pattern 30 located directly above the array region a is equal to the unit size of the fourth mask pattern 30 located directly above the boundary region b.

[0092] Reference Figure 12 After forming the fourth mask pattern 30 on the substrate 100 using the SAQP process, a filling layer 2021 covering the fourth mask pattern 30 and the peripheral area c is formed, and the side of the filling layer 2021 facing away from the substrate 100 is planarized so that the filling layer 2021 on the array area a, the boundary area b and the peripheral area c is flush with the top surface of the fourth mask pattern 30.

[0093] In some specific examples, the filling layer 2021 is formed by an ALD process, and the material of the filling layer 2021 completely fills the gaps between the fourth mask patterns 30 and covers the top surfaces of the fourth mask patterns 30. The side of the filling layer 2021 facing away from the substrate 100 is planarized by a chemical mechanical polishing (CMP) process to remove the portion of the filling layer 2021 that is higher than the top surfaces of the fourth mask patterns 30. The top surfaces of the filling layer 2021 are made flush with the top surfaces of the fourth mask patterns 30, thereby providing a flat support surface for the subsequently formed mask layer.

[0094] In some specific examples, the material of the filling layer 2021 includes, but is not limited to, a spin-on hard mask material (eg, a silicon hard mask material, a carbon hard mask material, an organic hard mask material, etc.).

[0095] Combined with reference Figures 13 to 15 , perform step S102, sequentially form a first mask layer 301 and a second mask layer 302 on the substrate 100, and form a first mask pattern 501 located directly above the array area a and a second mask pattern 502 located directly above the boundary area b in the second mask layer 302.

[0096] Reference Figure 13 The specific process of executing step S102 includes: forming a fourth mask layer 303 on the second mask layer 302; forming a patterned second photoresist layer 304 on the fourth mask layer 303, the patterned second photoresist layer 304 includes a first photoresist pattern 3041 located directly above the array area a and a second photoresist pattern 3042 located directly above the junction area b, and the unit size of the first photoresist pattern 3041 is larger than the unit size of the second photoresist pattern 3042.

[0097] It should be noted that, in the embodiments of the present disclosure, the unit size of the mask pattern or the photolithography pattern refers to the pitch of the mask pattern or the photolithography pattern, that is, the size of a periodic pattern. The smaller the unit size, the higher the density of the pattern.

[0098] In the embodiment of the present disclosure, two photolithographic patterns with different unit sizes can be formed in one photomask, and then the two photolithographic patterns are transferred to the photoresist layer located on the fourth mask layer 303 through a photolithography process to form a patterned second photoresist layer 304 .

[0099] In the embodiment of the present disclosure, a ratio of a unit size of the first photolithographic pattern 3041 to a unit size of the second photolithographic pattern 3042 is greater than a first preset value and less than a second preset value.

[0100] In some specific examples, the first preset value is 1.2, and the second preset value is 2.

[0101] In the embodiment of the present disclosure, the ratio of the unit size of the first photolithography pattern 3041 to the unit size of the second photolithography pattern 3042 should be neither too large nor too small. If the ratio is too small, it means that the unit size of the first photolithography pattern 3041 and the second photolithography pattern 3042 are not much different. When the first dielectric layer 306 is subsequently formed, the material of the first dielectric layer 306 cannot completely fill the gap between the second mask patterns 502. If the ratio is too large, it means that the unit size of the first photolithography pattern 3041 and the second photolithography pattern 3042 is too different, which will increase the difficulty of subsequent processes.

[0102] Combined with reference Figure 13 and Figure 14The fourth mask layer 303 includes a fourth sub-mask layer 3031, a fifth sub-mask layer 3032, and a sixth sub-mask layer 3033 arranged sequentially along the Z direction. The specific process of performing step S102 further includes: etching the fourth mask layer 303 using the patterned second photoresist layer 304 as a mask, transferring the first photoresist pattern 3041 and the second photoresist pattern 3042 to the fourth mask layer, thereby forming a fifth mask pattern 401 located directly above the array region a and a sixth mask pattern 402 located directly above the boundary region b. The cell size of the fifth mask pattern 401 is the same as that of the first photoresist pattern 3041, and the cell size of the sixth mask pattern 402 is the same as that of the second photoresist pattern 3042. During this process, the fourth sub-mask layer 3031 serves as an etch stop layer, ensuring that the opening formed by etching the fourth mask layer 303 stops on or within the fourth sub-mask layer 3031.

[0103] In some specific examples, the first mask layer 301 , the second mask layer 302 and the fourth mask layer 303 are formed by a deposition process or a spin coating process, and the fourth mask layer 303 is etched by a dry etching process.

[0104] In some specific examples, the material of the first mask layer 301 includes but is not limited to silicon-rich silicon oxynitride; the material of the second mask layer 302 includes but is not limited to amorphous carbon; the material of the fourth sub-mask layer 3031 includes but is not limited to silicon oxide; the material of the fifth sub-mask layer 3032 includes but is not limited to spin-on hard mask material (for example, silicon hard mask material, carbon hard mask material, organic hard mask material, etc.); the material of the sixth sub-mask layer 3033 includes but is not limited to silicon oxynitride.

[0105] Combined with reference Figure 14 and Figure 15 A self-aligned patterning process is used to form a first mask pattern 501 located directly above the array region a and a second mask pattern 502 located directly above the interface region b in the second mask layer 302. The specific process may include: forming a second spacer on the sidewall of the fifth mask pattern 401 and forming a third spacer on the sidewall of the sixth mask pattern 402; removing the fifth mask pattern 401 and the sixth mask pattern 402; and etching the second mask layer 302 using the second and third spacers as masks to form the first and second mask patterns 501 and 502. Here, the second and third spacers can be formed simultaneously, and the method for forming the second and third spacers is similar to the method for forming the fourth spacer described above, and will not be repeated here.

[0106] In the embodiment of the present disclosure, since the unit size of the fifth mask pattern 401 is larger than the unit size of the sixth mask pattern 402, after the first mask pattern 501 and the second mask pattern 502 are formed by a self-aligned patterning process, the unit size of the first mask pattern 501 and the second mask pattern 502 is further reduced relative to the unit size of the fifth mask pattern 401 and the sixth mask pattern 402, and the unit size of the first mask pattern 501 is larger than the unit size of the second mask pattern 502.

[0107] Combined with reference Figures 15 to 18 , performing step S103, forming a third mask pattern 60 located directly above the array region a in the first mask layer 301 based on the first mask pattern 501, and forming a blocking pattern 70 located directly above the boundary region b based on the second mask pattern 502.

[0108] Reference Figure 16 The specific process of executing step S103 includes: forming a first dielectric layer 306 covering the first mask pattern 501, the second mask pattern 502 and the first mask layer 301, and making the material of the first dielectric layer 306 completely fill the gap between the second mask patterns 502.

[0109] In the embodiment of the present disclosure, the first dielectric layer 306 can be formed using an ALD process. Since the unit size of the second mask pattern 502 is smaller than the unit size of the first mask pattern 501, when the thickness of the first dielectric layer 306 covering the first mask pattern 501 reaches the thickness requirement for forming a spacer, the material of the first dielectric layer 306 can completely fill the gaps between the second mask patterns 502 and form a flat top surface.

[0110] In some specific examples, the material of the first dielectric layer 306 includes at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon carbonitride, silicon carbon oxynitride, or boron nitride.

[0111] Reference Figure 17 , forming a first photoresist layer 307 covering the first dielectric layer 306 located directly above the peripheral region c and the boundary region b.

[0112] In the embodiment of the present disclosure, because the material of the first dielectric layer 306 completely fills the gaps between the second mask patterns 502 and forms a flat top surface, when forming the first photoresist layer 307 covering the first dielectric layer 306 located directly above the junction region b, the first photoresist layer 307 is formed on the flat first dielectric layer 306. All portions of the first photoresist layer 307 extending along the X-direction are evenly supported, thereby reducing the risk of the first photoresist layer 307 sliding sideways and causing the opening at the junction of the array region a and the junction region b to be blocked by the slipped photoresist.

[0113] Combined with reference Figure 17 and Figure 18 , the first dielectric layer 306 covering the top of the first mask pattern 501 and the first mask pattern 501 are removed to form a first spacer, and the first photoresist layer 307 and a portion of the first dielectric layer 306 directly above the junction area b are removed; the first mask layer 301 directly above the array area a is etched using the first spacer as a mask to form a third mask pattern 60. The first mask layer 301 directly above the junction area b, the second mask pattern 502, and the remaining first dielectric layer 306 constitute a blocking pattern 70.

[0114] like Figure 18 As shown, the top surface of the first dielectric layer 306 in the barrier pattern 70 is higher than the top surface of the third mask pattern 60 .

[0115] In the embodiment of the present disclosure, since the material of the first dielectric layer 306 completely fills the gaps between the second mask patterns 502, when the third mask pattern 60 located directly above the array area a is formed through a self-aligned patterning process, only a portion of the first dielectric layer 306 located directly above the junction area b will be etched, and the remaining first dielectric layer 306 still covers the first mask layer 301 in this area, and no opening penetrating the first mask layer 301 along the Z direction is formed in the first mask layer 301. In addition, the first mask layer 301 located directly above the junction area b, the second mask pattern 502 and the remaining first dielectric layer 306 together constitute a blocking pattern 70. The top surface of the first dielectric layer 306 in the blocking pattern 70 is higher than the top surface of the third mask pattern 60. The blocking pattern 70 can avoid the formation of redundant patterns in the junction area b during the subsequent formation of the array pattern.

[0116] Combined with reference Figure 18 and Figure 19 The method for forming a semiconductor structure further includes forming an array pattern 80 in the array region a based on the third mask pattern 60 and the fourth mask pattern 30 , and not forming an array pattern in the boundary region b based on the barrier pattern 70 and the fourth mask pattern 30 .

[0117] In some embodiments, before forming the third mask layer 202 on the substrate 100, an amorphous carbon layer 201 is first formed on the substrate 100. After forming the third mask pattern 60 and the barrier pattern 70, the amorphous carbon layer 201 is etched using the third mask pattern 60, the barrier pattern 70, and the fourth mask pattern 30 as masks. The pattern formed by the overlap of the third mask pattern 60 and the fourth mask pattern 30 is transferred to the amorphous carbon layer 201 directly above the array region a to form a patterned amorphous carbon layer. The oxide layer 105 in the substrate 100 is etched using the patterned amorphous carbon layer as a mask, and the remaining amorphous carbon layer is removed to form the array pattern 80 in the array region a.

[0118] In the embodiment of the present disclosure, during the process of transferring the pattern formed by the overlap of the third mask pattern 60 and the fourth mask pattern 30 to the amorphous carbon layer 201 directly above the array region a, because the barrier pattern 70 does not include an opening penetrating the first mask layer 301 in the Z direction, an opening penetrating the amorphous carbon layer 201 in the Z direction is further prevented from being formed in the amorphous carbon layer 201 directly above the junction region b. Furthermore, when etching the oxide layer 105 using the patterned amorphous carbon layer as a mask, the amorphous carbon layer 201 directly above the junction region b completely covers the oxide layer 105 in the junction region b, thereby preventing the oxide layer 105 in the junction region b from being etched, thereby avoiding the formation of an unnecessary pattern in the junction region b.

[0119] In some embodiments, the method for forming a semiconductor structure further includes: forming a capacitor hole array in the stacked structure using the array pattern 80 as a mask.

[0120] In the embodiment of the present disclosure, while alleviating the load effect during the array pattern formation process, the array pattern can be formed only in the array area a. When forming the capacitor hole array, the generation of etching holes in the junction area b can be further avoided. Therefore, the size of the junction area b in the X direction can be appropriately reduced, that is, the redundant space reserved for the abnormal pattern can be reduced, and the circuit structure in the peripheral area can be closer to the array area, thereby improving the integration of the semiconductor structure.

[0121] It should be noted that the method for forming a semiconductor structure provided by the present disclosure can be applied not only to the formation process of a capacitor hole array, but also to the formation process of other array patterns with small unit size and large aspect ratio.

[0122] In the embodiments of the present disclosure, the number of minimum repeating units in each mask pattern is only an example, and the present disclosure does not limit the specific number of minimum repeating units in the mask pattern set directly above the array region a and the boundary region b.

[0123] In the embodiment of the present disclosure, by reducing the unit size of the mask pattern located directly above the junction area, the material of the dielectric layer can completely fill the gap between the mask patterns in the area. On the one hand, it can provide support for the photoresist layer covering the junction area, reducing the risk of the photoresist layer sliding sideways and causing the opening at the junction of the array area and the junction area to be blocked, thereby effectively reducing the possibility of abnormalities in the array pattern and improving the reliability of the semiconductor structure finally formed; on the other hand, a blocking pattern can be further formed to avoid the formation of redundant patterns in the junction area, so that the size of the junction area can be reduced, which is conducive to the miniaturization of the semiconductor structure.

[0124] Based on the same concept as the above embodiments, the present disclosure also provides a semiconductor structure, which is manufactured by the method for forming the semiconductor structure in any of the above embodiments. The technical effects that can be achieved by the method for forming the semiconductor structure in any of the above embodiments can also be achieved by this semiconductor structure, and will not be described one by one here.

[0125] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0126] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising an array region, a peripheral region, and a boundary region between the array region and the peripheral region; forming a first mask layer and a second mask layer in sequence on the substrate, and forming a first mask pattern located directly above the array region and a second mask pattern located directly above the boundary region in the second mask layer; a unit size of the second mask pattern is smaller than a unit size of the first mask pattern; A third mask pattern is formed in the first mask layer based on the first mask pattern and is located directly above the array area. A blocking pattern is formed based on the second mask pattern and is located directly above the junction area, including: forming a dielectric layer covering the first mask pattern, the second mask pattern and the first mask layer, and making the material of the dielectric layer completely fill the gap between the second mask patterns; forming a first photoresist layer covering the dielectric layer directly above the peripheral area and the junction area; removing the dielectric layer covering the top of the first mask pattern and the first mask pattern to form a first spacer; and removing the first photoresist layer and a portion of the dielectric layer directly above the junction area; the first mask layer directly above the junction area, the second mask pattern and the remaining dielectric layer constitute the blocking pattern.

2. The method for forming a semiconductor structure according to claim 1, wherein: The method further comprises forming a third mask pattern located directly above the array region in the first mask layer based on the first mask pattern, and forming a barrier pattern located directly above the boundary region based on the second mask pattern. The first mask layer located directly above the array region is etched using the first spacer as a mask to form the third mask pattern.

3. The method for forming a semiconductor structure according to claim 2, wherein: A top surface of the dielectric layer in the blocking pattern is higher than a top surface of the third mask pattern.

4. The method for forming a semiconductor structure according to claim 1, wherein: Before forming the first mask layer on the substrate, the forming method further includes: forming a third mask layer on the substrate; the third mask layer comprising a fourth mask pattern located directly above the array region and the interface region; After forming a third mask pattern located directly above the array region in the first mask layer based on the first mask pattern, and forming a barrier pattern located directly above the boundary region based on the second mask pattern, the forming method further includes: An array pattern is formed in the array region based on the third mask pattern and the fourth mask pattern, and the array pattern is not formed in the boundary region based on the barrier pattern and the fourth mask pattern.

5. The method for forming a semiconductor structure according to claim 4, wherein: A cell size of the fourth mask pattern located directly above the array region is equal to a cell size of the fourth mask pattern located directly above the boundary region.

6. The method for forming a semiconductor structure according to claim 5, wherein: Before forming the third mask layer on the substrate, the forming method further includes: forming an amorphous carbon layer on the substrate; The forming of the array pattern in the array region based on the third mask pattern and the fourth mask pattern, and not forming the array pattern in the boundary region based on the blocking pattern and the fourth mask pattern, comprises: etching the amorphous carbon layer using the third mask pattern, the barrier pattern, and the fourth mask pattern as masks, and transferring a pattern formed by overlapping the third mask pattern and the fourth mask pattern to the amorphous carbon layer directly above the array region to form a patterned amorphous carbon layer; The substrate is etched using the patterned amorphous carbon layer as a mask, and the remaining amorphous carbon layer is removed to form an array pattern in the array region, while no array pattern is formed in the boundary region.

7. The method for forming a semiconductor structure according to claim 1, wherein: The forming of a first mask pattern located directly above the array region and a second mask pattern located directly above the boundary region in the second mask layer includes: forming a fourth mask layer on the second mask layer; forming a patterned second photoresist layer on the fourth mask layer; the patterned second photoresist layer comprising a first photoresist pattern located directly above the array region and a second photoresist pattern located directly above the boundary region, wherein a unit size of the first photoresist pattern is larger than a unit size of the second photoresist pattern; etching the fourth mask layer using the patterned second photoresist layer as a mask to form a fifth mask pattern located directly above the array region and a sixth mask pattern located directly above the boundary region in the fourth mask layer; forming a second spacer on a sidewall of the fifth mask pattern, and forming a third spacer on a sidewall of the sixth mask pattern; removing the fifth mask pattern and the sixth mask pattern; The second mask layer is etched using the second spacer and the third spacer as a mask to form the first mask pattern and the second mask pattern.

8. The method for forming a semiconductor structure according to claim 7, wherein: A ratio of a cell size of the first photolithographic pattern to a cell size of the second photolithographic pattern is greater than a first preset value and less than a second preset value.

9. The method for forming a semiconductor structure according to claim 8, wherein: The first preset value is 1.2, and the second preset value is 2.

10. The method for forming a semiconductor structure according to claim 4, wherein: The providing of a substrate comprises: forming a metal layer; forming a stacked structure in which a sacrificial layer and a supporting layer are overlapped on the metal layer; An oxide layer is formed on the stack structure.

11. The method for forming a semiconductor structure according to claim 10, wherein: The forming of an array pattern in the array area based on the third mask pattern and the fourth mask pattern comprises: forming an array pattern in the oxide layer based on the third mask pattern and the fourth mask pattern; A capacitor hole array is formed in the stacked structure using the array pattern as a mask.

12. The method for forming a semiconductor structure according to claim 4, wherein: The step of forming a third mask layer on the substrate comprises: forming the fourth mask pattern on the substrate; A filling layer covering the fourth mask pattern and the peripheral area is formed, and a side of the filling layer facing away from the substrate is planarized so that the filling layer on the array area, the peripheral area and the boundary area is flush with a top surface of the fourth mask pattern.

13. The method for forming a semiconductor structure according to claim 12, wherein: The forming of the fourth mask pattern on the substrate comprises: forming a fifth mask layer and a sixth mask layer in sequence on the third mask layer; forming a seventh mask pattern in the sixth mask layer, the pattern being located directly above the array region and the interface region; forming a fourth spacer on a sidewall of the seventh mask pattern, and removing the seventh mask pattern; etching the fifth mask layer using the fourth spacer as a mask to form an eighth mask pattern located directly above the array region and the boundary region; forming a fifth spacer on a sidewall of the eighth mask pattern, and removing the eighth mask pattern; The third mask layer is etched using the fifth spacer as a mask to form the fourth mask pattern located directly above the array region and the boundary region.

14. A semiconductor structure, characterized in that The semiconductor structure is obtained by the method for forming a semiconductor structure according to any one of claims 1 to 13.

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