Transistor and electronic device

Abstract

The application provides a transistor, which is provided with a p-type well region and an n-type drift region between a source contact doped region and a drain contact doped region, the p-type well region and a gate of the transistor are located on two sides of a metal oxide layer of the transistor respectively, and the p-type well region is in contact with a first region of a first surface of the metal oxide layer, the gate is in contact with a second region of a second surface of the metal oxide layer, a projection of the second region on a thickness direction of the metal oxide layer falls into a projection of the first region on the thickness direction of the metal oxide layer, or the two projections coincide. In the case that a voltage is applied on the gate, the carriers generated by the gate inversion can be limited in the p-type well region, so that the conduction characteristic between the source and the drain of the transistor is more controllable with the change of the voltage applied on the gate, which is beneficial to reduce the static power consumption and the heat loss of the transistor, and is beneficial to improve the thermal stability of the transistor and the electronic equipment using the transistor.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, and more specifically, to a transistor and an electronic device. Background Technology

[0002] Under constant current bias, power amplifiers using conventional transistors exhibit high quiescent power consumption and low power amplifier back-off efficiency. Furthermore, the self-heating effect of transistors can create a positive feedback loop, easily leading to thermal runaway of the device and even the entire circuit system, resulting in poor stability. Summary of the Invention

[0003] This application provides a transistor in which the charge carriers obtained by gate inversion can be confined within the p-type well region, resulting in more uniform and stable output characteristics. This transistor also features low static power consumption, good thermal stability, and high energy conversion efficiency.

[0004] In a first aspect, a transistor is provided, comprising: a source, a drain, a gate, a metal oxide layer, a first doped region, a source contact doped region, a drain contact doped region, a p-type well region, an n-type drift region, and a substrate. The first doped region is located on the substrate and is a p-type doped region. The source contact doped region is located between the first doped region and the source and is in contact with the source. The drain contact doped region is located between the first doped region and the drain and is in contact with the drain. The source contact doped region and the drain contact doped region are n-type doped regions. The p-type well region is located between the source contact doped region and the first doped region and is in contact with the source. The doped region is in contact with the n-type drift region, which is located between the drain contact doped layer and the first doped region and is in contact with the drain contact doped region. The p-type well region is in contact with the n-type drift region. The p-type well region is in contact with a first region of a first surface of the metal oxide layer. The gate is in contact with a second region of a second surface of the metal oxide layer. The first surface and the second surface are two opposite surfaces of the metal oxide layer in the thickness direction. The projection of the second region in the thickness direction is located inside the projection of the first region in the thickness direction, or the projection of the second region in the thickness direction coincides with the projection of the first region in the thickness direction.

[0005] It should be understood that in the above technical solutions, the contact between different structures can be understood as an electrical connection between different structures, or that different structures can conduct electricity to each other.

[0006] In one possible implementation, the first doped layer, the source contact doped region, the drain contact doped region, the p-type well region, and the n-type drift region can all be located on the epitaxial layer of the transistor. That is, the different regions mentioned above can be formed by the epitaxial layer of the transistor using different fabrication techniques.

[0007] In one possible implementation, the first doped layer, the source contact doped region, the drain contact doped region, the p-type well region, and the n-type drift region are multiple independent structures, and these structures can satisfy the positional or electrical connection relationships described in the above technical solutions.

[0008] In some scenarios, the aforementioned source contact doped region can also be referred to as the first n-type high-concentration doped region or the first n+ region, and the drain contact doped region can also be referred to as the second n-type high-concentration doped region or the second n+ region.

[0009] In some scenarios, the projection relationship between the first region and the second region in the thickness direction of the metal oxide layer can also be understood as follows: the size of the p-type well region in the first direction can be a first length, the size of the gate in the first direction can be a second length, the first length is greater than or equal to the second length, and the second region is not located outside the first region. Here, the first direction is the direction of the connection between the source and the drain.

[0010] In this technical solution, by setting the size and positional relationship between the contact area between the gate and the metal oxide layer and the contact area between the p-type well region and the metal oxide layer, the carriers generated by gate inversion are controlled to be confined inside the p-type well region. Thus, during the process of applying voltage to the gate, the source and drain of the transistor can be gradually turned on. Compared with the case where the source and drain of the transistor are fully turned on when the critical voltage is reached, the output characteristics of the transistor provided in this application are easier to control, which is beneficial to reducing the static power consumption and heat loss of the transistor, improving the energy conversion efficiency of the transistor, and improving the thermal stability of the transistor.

[0011] In conjunction with the first aspect, in some implementations of the first aspect, the transistor further includes a charge balancing layer located between the first doped region and the n-type drift region, the charge balancing layer being in contact with both the first doped layer and the n-type drift region.

[0012] This charge balance layer can also be called an n+ type charge balance layer, or in other words, this charge balance layer may include a high concentration of n-type impurities.

[0013] Electrons ionized in the charge balance layer can balance with holes ionized in the first doped layer, thus ensuring that the n-type drift region is unaffected by the first doped layer. The n-type drift region exhibits near-one-dimensional electrical characteristics in the lateral direction. The implementation of this technical solution is beneficial for improving the controllability of p-type well region punch-through and for enhancing the stability of transistor output characteristics.

[0014] In conjunction with the first aspect, in some implementations of the first aspect, the doping concentration of the charge balancing layer is greater than or equal to 1 × 10⁻⁶. 17 cm -3 And less than or equal to 1×10 20 cm-3 .

[0015] By setting the doping concentration of the charge balancing layer within the threshold range provided by this technical solution, the charge balancing effect between the charge balancing layer and the first doped layer is better, and the first doped layer has less impact on the n-type drift region. The implementation of this technical solution is beneficial for further improving the stability of transistor output characteristics.

[0016] In conjunction with the first aspect, in some implementations of the first aspect, the dimension of the charge balancing layer in the thickness direction is greater than or equal to 50 nm and less than or equal to 500 nm.

[0017] By setting the size of the charge balancing layer in the thickness direction within the threshold range provided by this technical solution, the charge balancing effect between the charge balancing layer and the first doped layer is better, and the first doped layer has less impact on the n-type drift region. The implementation of this technical solution is beneficial for further improving the stability of transistor output characteristics.

[0018] In conjunction with the first aspect, in some implementations of the first aspect, the source is electrically connected to the substrate; the transistor further includes one or more of a metal layer, a field plate, or a dielectric layer, the metal layer being connected to the side of the substrate away from the first doped region, the field plate being located between the gate and the drain and close to the gate, and the dielectric layer being located on the side of the metal oxide layer away from the substrate.

[0019] In this technical solution, by electrically connecting the source and substrate of the transistor, the source and substrate have the same potential. The transistor with this structure is more suitable for high-frequency power amplifier scenarios.

[0020] The metal layer facilitates grounding when the transistor is mounted on the circuit board, the field plate helps to increase the breakdown voltage of the gate, and the dielectric layer can cover the surface of the transistor, thereby protecting the aforementioned source, drain and other components in the transistor.

[0021] In conjunction with the first aspect, in some implementations of the first aspect, the transistor further includes a connection region for connecting the source to the substrate, the connection region including a highly doped lead-out region and / or a metal region.

[0022] In one possible implementation, the metal region can be a metal via.

[0023] The connectivity of highly doped lead-in regions is relatively weak, while the manufacturing process of transistors containing highly doped lead-in regions is relatively simple; conversely, the connectivity of metal regions is relatively strong, while the manufacturing process of transistors containing metal regions is relatively complex. This technical solution provides various connection region structures, and different structures can be applied to different products or scenarios, which helps to expand the application range of the transistors provided in this application.

[0024] In conjunction with the first aspect, in some implementations of the first aspect, the doping concentration of the p-type well region is less than or equal to 5 × 10⁻⁶. 16 cm -3 .

[0025] By setting the doping concentration of the p-type well region within the range provided by this technical solution, the p-type well region has a better control effect on the carriers generated by gate inversion, and the conduction characteristics of the source and drain of the transistor are more controllable, or in other words, the output characteristics of the transistor are more controllable.

[0026] In conjunction with the first aspect, in some implementations of the first aspect, the size of the first region in a first direction is less than or equal to 0.5 μm, and the first direction is the direction in which the source and the drain are connected.

[0027] It should be understood that the size of the first region in the first direction is greater than zero.

[0028] By setting the size of the first region in contact with the metal oxide layer in the first direction within the range provided by this technical solution, the p-type well region has a better control effect on the electrons generated by gate inversion, and the conduction characteristics of the source and drain of the transistor are more controllable, or in other words, the output characteristics of the transistor are more controllable.

[0029] In a second aspect, a transistor is provided, comprising: a source, a drain, a gate, a GaN layer, an AlGaN layer, and a regulating island, wherein the source and the drain are respectively contacted at both ends of the AlGaN layer; the gate is located between the source and the drain and is in contact with the AlGaN layer; the regulating island is located between the drain and the gate and is in contact with the AlGaN layer, wherein the regulating island comprises one or more of the following: p-type doped GaN, p-type doped AlGaN, or metal.

[0030] GaN layers can also be called GaN buffer layers, and AlGaN layers can also be called AlGaN barrier layers.

[0031] In one possible implementation, the transistor further includes a nucleation layer located between the substrate and the GaN layer.

[0032] In this technical solution, by setting a regulating island between the gate and drain that contacts the AlGaN layer, the carriers within the regulating island can, to a certain extent, regulate the conduction characteristics of the local 2DEG channels within the GaN layer corresponding to the location of the regulating island. Therefore, when a voltage is applied to the transistor, the aforementioned local 2DEG channels can be gradually turned on. Compared to the case where all 2DEG channels are turned on when a critical voltage is reached, the conduction characteristics of the source and drain of the transistor provided by this technical solution are more controllable, and the output characteristics of the transistor are more controllable. This is beneficial for reducing the static power consumption and heat loss of the transistor, improving the energy conversion efficiency of the transistor, and enhancing the thermal stability of the transistor.

[0033] In conjunction with the second aspect, in some implementations of the second aspect, the regulating island includes multiple sub-regulating islands, which are spaced apart from each other.

[0034] The output characteristics of a transistor can be adjusted by setting multiple spaced-apart sub-control islands within the transistor. Different numbers of sub-control islands correspond to different output characteristics of the transistor. The implementation of this technical solution facilitates the control of the transistor's output characteristics over a wider range, thereby obtaining transistors suitable for different application scenarios and expanding the application scope of transistors.

[0035] In conjunction with the second aspect, in some implementations of the second aspect, the regulating island includes a first sub-regulating island, a second sub-regulating island, and a third sub-regulating island, the second sub-regulating island being located between the first sub-regulating island and the third sub-regulating island, the first sub-regulating island forming an ohmic contact or a Schottky contact with the gate, and / or the third sub-regulating island forming an ohmic contact or a Schottky contact with the drain.

[0036] In this technical solution, three sub-regulation islands can be set in the transistor, making it more suitable for power amplifier applications. Furthermore, the specific interface structure described above is formed between the first sub-regulation island and the gate, and / or between the third sub-regulation island and the drain. The electrical characteristics of the regulation islands corresponding to this interface structure are more intuitive, facilitating more effective control over the transistor's output characteristics.

[0037] In conjunction with the second aspect, in some implementations of the second aspect, the source is electrically connected to the substrate; the transistor further includes one or more of a metal layer, a field plate, or a dielectric layer, the metal layer being in contact with the substrate on the side away from the GaN layer, the field plate being located between the gate and the drain and close to the gate, and the dielectric layer being located on the side of the AlGaN layer away from the GaN layer.

[0038] In this technical solution, by electrically connecting the source and substrate of the transistor, the source and substrate have the same potential. The transistor with this structure is more suitable for high-frequency power amplifier scenarios.

[0039] The metal layer facilitates grounding when the transistor is mounted on the circuit board, the field plate helps to increase the breakdown voltage of the gate, and the dielectric layer can cover the surface of the transistor, thereby protecting the aforementioned source, drain and other components in the transistor.

[0040] In conjunction with the second aspect, in some implementations of the second aspect, the transistor further includes a metal via for connecting the source to the substrate.

[0041] In one possible implementation, one end of the metal via is connected to the source and the other end is connected to the substrate.

[0042] Metal vias are particularly suitable for GaN HEMT transistors. This technical solution utilizes metal vias to connect the transistor's source and substrate. Metal vias offer better conductivity, which helps reduce heat loss during transistor operation and improves the transistor's energy conversion efficiency.

[0043] The explanations and descriptions of the beneficial effects in the following technical solutions can be found in the relevant descriptions in the first and second aspects. For the sake of brevity, they will not be repeated here.

[0044] Thirdly, a transistor is provided, comprising a source, a drain, a gate, a metal oxide layer, a first doped region, a source contact doped region, a drain contact doped region, an n-type well region, a p-type drift region, and a substrate. The first doped region is located on the substrate and is an n-type doped region. The source contact doped region is located between the first doped region and the source and is in contact with the source. The drain contact doped region is located between the first doped region and the drain and is in contact with the drain. The source contact doped region and the drain contact doped region are p-type doped regions. The n-type well region is located between the source contact doped region and the first doped region and is doped with the source contact doped region. The gate is in contact with the p-type drift region, which is located between the drain contact doped layer and the first doped region and is in contact with the drain contact doped region. The n-type well region is in contact with the p-type drift region. The n-type well region is in contact with a first region of a first surface of the metal oxide layer. The gate is in contact with a second region of a second surface of the metal oxide layer. The first surface and the second surface are two opposite surfaces of the metal oxide layer in the thickness direction. The projection of the second region in the thickness direction is located inside the projection of the first region in the thickness direction, or the projection of the second region in the thickness direction coincides with the projection of the first region in the thickness direction.

[0045] In conjunction with the third aspect, in some implementations of the third aspect, the transistor further includes a charge balancing layer located between the first doped region and the p-type drift region, the charge balancing layer being in contact with both the first doped layer and the p-type drift region.

[0046] In conjunction with the third aspect, in some implementations of the third aspect, the doping concentration of the charge balancing layer is greater than or equal to 1 × 10⁻⁶. 17 cm -3 And less than or equal to 1×10 20 cm -3 .

[0047] In conjunction with the third aspect, in some implementations of the third aspect, the dimension of the charge balancing layer in the thickness direction is greater than or equal to 50 nm and less than or equal to 500 nm.

[0048] In conjunction with the third aspect, in some implementations of the third aspect, the source is electrically connected to the substrate; the transistor further includes one or more of a metal layer, a field plate, or a dielectric layer, the metal layer being connected to the side of the substrate away from the first doped region, the field plate being located between the gate and the drain and close to the gate, and the dielectric layer being located on the side of the metal oxide layer away from the substrate.

[0049] In conjunction with the third aspect, in some implementations of the third aspect, the transistor further includes a connection region for connecting the source to the substrate, the connection region including a highly doped lead-out region and / or a metal region.

[0050] In conjunction with the third aspect, in some implementations of the third aspect, the doping concentration of the n-type well region is less than or equal to 5 × 10⁻⁶. 16 cm -3 .

[0051] In conjunction with the third aspect, in some implementations of the third aspect, the size of the first region in a first direction is less than or equal to 0.5 μm, and the first direction is the direction in which the source and the drain are connected.

[0052] Fourthly, an electronic device is provided, comprising transistors as described in the first aspect and any possible implementation thereof, and / or comprising transistors as described in the second aspect and any possible implementation thereof, and / or comprising transistors as described in the third aspect and any possible implementation thereof.

[0053] In one possible implementation, the electronic device can be a power amplifier. Attached Figure Description

[0054] Figure 1 This is a schematic diagram of a general LDMOS model provided in an embodiment of this application.

[0055] Figure 2 This is a schematic diagram of a general GaN HEMT model provided in an embodiment of this application.

[0056] Figure 3This is a schematic diagram of the output characteristic curve of a transistor provided in an embodiment of this application.

[0057] Figure 4 This is a schematic diagram of the transfer characteristic curve of a transistor provided in an embodiment of this application.

[0058] Figure 5 This is a schematic diagram of the structure of an LDMOS transistor provided in an embodiment of this application.

[0059] Figure 6 This is a schematic diagram of another LDMOS transistor provided in an embodiment of this application.

[0060] Figure 7 This is a schematic diagram of another LDMOS transistor provided in the embodiments of this application.

[0061] Figure 8 This is a schematic diagram of another LDMOS transistor provided in the embodiments of this application.

[0062] Figure 9 This is a schematic diagram of the structure of a GaN HEMT transistor provided in an embodiment of this application.

[0063] Figure 10 This is a schematic diagram of another GaN HEMT transistor provided in an embodiment of this application.

[0064] Figure 11 This is a schematic diagram of another GaN HEMT transistor provided in the embodiments of this application.

[0065] Figure 12 This is a schematic diagram of another GaN HEMT transistor provided in the embodiments of this application.

[0066] Figure 13 This is a schematic diagram of another GaN HEMT transistor provided in the embodiments of this application.

[0067] Figure 14 This is a graph showing the output characteristics of the LDMOS transistor provided in the embodiments of this application.

[0068] Figure 15 This is a graph showing the output characteristics of the GaN HEMT transistor provided in the embodiments of this application. Detailed Implementation

[0069] The embodiments of this application are described in detail below, and examples of these embodiments are illustrated in the accompanying drawings. In the drawings, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0070] The terminology used in the following embodiments is for the purpose of describing specific embodiments only and is not intended to limit this application. For example, "first" and "second" in this specification are for ease of description only and should not be construed as implying a necessary sequential or hierarchical relationship between them. The term "and / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0071] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. In the description of this application, it should be understood that the terms “center,” “longitudinal,” “lateral,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer,” etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are used only for the convenience of describing this application and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0072] Unless otherwise specified, in the following embodiments, the connection between components can be understood as an electrical connection, that is, the components can be electrically connected to each other. The electrical connection between two components can be a direct contact electrical connection, or it can be an electrical connection achieved through a third component.

[0073] Before introducing the embodiments of this application, some technical terms that may be used in the following embodiments will be explained.

[0074] A field-effect transistor (FET) is an electronic device that controls current through an electric field effect. It relies on an electric field region to control the shape of the conductive channel, thus controlling the conductivity of the channel for a certain type of charge carrier in the semiconductor material.

[0075] Laterally diffused metal oxide semiconductor (LDMOS) is frequently used in microwave / RF circuits and is fabricated on an epitaxial layer of a highly doped silicon substrate.

[0076] A high electron mobility transistor (HEMT), also known as a modulation-doped field-effect transistor (MODFET), is a type of field-effect transistor that uses two materials with different band gaps to form a heterojunction, providing a channel for charge carriers.

[0077] A power amplifier, also known as a power amplifier, generally refers to an amplification circuit whose primary purpose is to enhance the power of DC, continuous wave, or pulse wave signals. An audio power amplifier can amplify low-power audio signals to a level sufficient to drive speakers or headphones.

[0078] A dependent / controlled source is a voltage or current source that is controlled by the current or voltage of another part of a circuit. Based on whether the controlling quantity is voltage or current, and whether the controlled source is a voltage or current source, dependent sources are classified into four types: voltage-controlled voltage source (VCVS), voltage-controlled current source (VCCS), current-controlled voltage source (CCVS), and current-controlled current source.

[0079] Doping is a process in semiconductor manufacturing where impurities are introduced into a pure intrinsic semiconductor, altering its electrical properties. These impurities are called dopants, and the type of impurity introduced depends on the type of semiconductor being manufactured. Lightly and moderately doped semiconductors are called impure semiconductors, while heavily doped semiconductors require consideration of the effects of Fermi statistics, a condition known as degenerate semiconductors.

[0080] n-type semiconductors, also known as electronic semiconductors, are doped with "donor impurities" (or n-type impurities, such as phosphorus, arsenic, and antimony), which cause an imbalance between the electron and hole densities of their atoms. The electron density that conducts electricity exceeds the density of flowing holes, and the conductivity is determined by the fact that these majority carriers are negatively charged electrons.

[0081] p-type semiconductors, also known as hole-type semiconductors, are doped with "acceptor impurities" (or p-type impurities, such as boron, aluminum, gallium, indium, etc.) which cause an imbalance between the electron density and hole density of their atoms. The density of flowing holes exceeds the density of conductive electrons, and the conductivity is determined by the fact that these majority carriers are positively charged holes.

[0082] Epitaxy is a technique used in semiconductor device manufacturing where new crystals are grown on an existing wafer to support a new semiconductor layer. Typically, epitaxial layers are a few micrometers thick, and their presence can improve the performance, stability, and reliability of semiconductor devices.

[0083] A p-type well is formed by doping an n-type substrate with a p-type impurity, and the region containing the p-type impurity can be called a p-type well.

[0084] Drift region: A structure in a high-voltage device that withstands a high electric field, typically with low doping.

[0085] A charge balancing layer is a layer used to achieve charge balance with adjacent semiconductor layers. That is, the number of electrons ionized in this layer is close to the number of holes ionized in the adjacent p-type layer. The effect of the charge balancing layer is usually more sensitive to the total amount of charge.

[0086] The sinker region is a structure that connects directly from the epitaxial layer to the substrate.

[0087] Output characteristics refer to the output characteristics of a semiconductor transistor, where the source is grounded, the gate voltage is fixed, the drain voltage is scanned, and the drain current is monitored to obtain I. DS -V DS curve.

[0088] The transfer characteristic refers to the characteristic of a semiconductor transistor where the source is grounded, the drain voltage is fixed, the gate voltage is scanned, and the drain current is monitored to obtain I. DS -V GS curve.

[0089] A Schottky contact is a metal-semiconductor interface that has rectification characteristics (diode characteristics).

[0090] An ohmic contact refers to a region on a semiconductor device that has a linear and symmetrical current-voltage characteristic curve.

[0091] p-GaN islands are local p-type structures on the semiconductor surface.

[0092] The depletion region is the area in which holes in a p-type semiconductor are consumed or electrons in an n-type semiconductor are consumed. This depletion is usually caused by changes in the internal electric field due to an applied voltage.

[0093] The channel punch-through effect is a phenomenon in which the depletion regions of the source and drain of a field-effect transistor (FET) become connected. Specifically, as the voltage increases, the depletion region reaches the boundary of the structure, at which point the structure can no longer block the current, and the current begins to increase.

[0094] Figure 1 The figure shown is a general model of an LDMOS transistor provided in an embodiment of this application. The LDMOS transistor includes a source 101, a drain 102, a gate 103, a source contact doped region 104, a well region 105, a metal oxide layer 106, a drain contact doped region 107, and a semiconductor substrate 108.

[0095] The source 101 and the gate 103 are separated by a metal oxide layer 106, and the drain 102 and the gate are separated by a metal oxide layer 106. The gate 103 is generally made of a metal material. The gate 103, the metal oxide layer 106 and the semiconductor substrate 108 can form a metal-oxide-semiconductor (MOS) structure.

[0096] The source contact doped region 104 can be formed by doping impurities on the semiconductor substrate 108, and the source contact doped region 104 can be located close to the source 101. Similarly, the drain contact doped region 107 can be formed by doping on the semiconductor substrate 108, and the drain contact doped region 107 can be located close to the drain 102. In some examples, the source contact doped region 104 can be doped with the same type of impurity as the drain contact doped region 107, such as n-type impurities or p-type impurities.

[0097] Well region 105 can be formed by doping impurities on semiconductor substrate 108, and well region 105 is located between source contact doped region 104 and drain contact doped region 107. In some examples, well region 105 is obtained by doping p-type impurities in an n-type semiconductor, in which case well region 105 can also be called p-type well. In some examples, well region 105 is obtained by doping n-type impurities in a p-type semiconductor, in which case well region 105 can also be called n-type well.

[0098] In some examples, the semiconductor substrate 108 may also be doped with a certain concentration of impurities, for example, the semiconductor substrate 108 may be doped with a low concentration of n-type impurities.

[0099] Based on the type of charge carriers in LDMOS transistors, LDMOS can be divided into n-type LDMOS and p-type LDMOS. Specifically, an LDMOS transistor that uses electrons as charge carriers can be called an n-type LDMOS transistor, while an LDMOS transistor that uses holes as charge carriers can be called a p-type LDMOS transistor.

[0100] In some examples, the source contact doped region 104 and the drain contact doped region 107 are both highly doped with n-type impurities, the well region 105 can be p-type doped, and the semiconductor substrate 108 is lightly doped with n-type impurities. In this case, electrons inverted from the gate 103 accumulate between the source contact doped region 104 and the drain contact doped region 107. When a voltage of Vth is applied to the gate 103, the electrons inverted from the gate 103 can conduct through the source contact doped region 104 and the drain contact doped region 107, thus achieving punch-through between the source contact doped region 104 and the drain contact doped region 107.

[0101] In some examples, the source contact doped region 104 and the drain contact doped region 107 are both highly p-type doped, the well region 105 can be n-type doped, and the semiconductor 108 is lightly p-type doped. In this case, the holes generated by the inversion of the gate 103 accumulate between the source contact doped region 104 and the drain contact doped region 107. When a voltage of Vth is applied to the gate 103, the holes generated by the inversion of the gate 103 can conduct the source contact doped region 104 and the drain contact doped region 107, and the source 101 and the drain 102 are turned on.

[0102] Figure 2 The diagram shows the structure of a gallium nitride (GaN) HEMT provided in an embodiment of this application. The GaN HEMT includes a source 201, a drain 202, a gate 203, an AlGaN barrier layer 204, and a GaN layer 205.

[0103] In this structure, the AlGaN barrier layer 204 and the GaN layer 205 are arranged adjacently to form an AlGaN / GaN heterojunction. In this heterojunction, the side of the GaN layer 205 closest to the AlGaN barrier layer 204 can accumulate a large number of electrons under the influence of a built-in electric field. This region where electrons accumulate can be called a two-dimensional electron gas (2DEG) channel 206. The 2DEG channel 206 can serve as a connecting channel between the source 201 and the drain 202.

[0104] In some examples, when the voltage difference (gate-source voltage) between the gate 203 and the source 201 is zero, a two-dimensional electron gas channel 206 already exists between the source 201 and the drain 202, meaning that the source 201 and the drain 202 are conducting. Adjusting the gate-source voltage to be less than the threshold voltage Vth disconnects the two-dimensional electron gas channel 206, thus disconnecting the source 201 and the drain 202.

[0105] In some examples, when the voltage difference (gate-source voltage) between the gate 203 and the source 201 is zero, the two-dimensional electron gas channel 206 between the source 201 and the drain 202 cannot be connected. By adjusting the gate-source voltage to be greater than the threshold voltage Vth, the two-dimensional electron channel 206 between the source 201 and the drain 202 can connect the source 201 and the drain 202.

[0106] As mentioned earlier, by adjusting the gate voltage of an LDMOS transistor or a GaNHEMT transistor, the current between the source and drain of both transistors can be changed. By controlling the gate voltage and adjusting the voltage between the source and drain of the transistor, the output characteristic curve of the transistor can be obtained (e.g., Figure 3 (As shown). By controlling the source and drain voltages and adjusting the gate voltage, the transfer characteristic curve of the transistor can be obtained (e.g., Figure 4 (As shown).

[0107] Combination Figure 3 and Figure 4 When the source and drain voltages remain constant, as the gate voltage increases, when the gate voltage falls below the threshold voltage Vth, the current I between the source and drain... DS The changes are relatively small; this region can be called the cutoff region. Figure 3 In region 310), the source and drain can be considered as not conducting. When the gate voltage continues to increase to a value greater than the threshold voltage Vth, the current I between the source and drain... DS As the voltage gradually increases, the source and drain are already conducting. In this case, keeping the drain voltage constant, the voltage difference between the source and drain (drain-source voltage V) is gradually increased. DS Within a certain range, the current between the source and drain (drain-source current I) DS ) Basically with V DS The linear increase of is linearly increasing, and this region can be called the linear region or the Ohmic region. Figure 3 Region 320 in the middle). When the drain-source voltage V DS When the drain-source current I continues to increase beyond the linear region, DS The rate of increase slows down until it essentially stops changing; this region can be called the saturation region. Figure 3 (Region 330 in the middle).

[0108] When the drain-source current I of the transistor DS With V DS When the linear change of the transistor is in a region where it changes linearly, the transistor performs the function of an amplifier. For example... Figure 1 and Figure 2 The transistors shown often perform constant voltage bias, that is, operate in the saturation region 330, for example. Figure 3 Point W1 in the diagram. To enable the transistor to function as a power amplifier, a constant current bias can be applied to the aforementioned transistor, for example, to make the transistor operate at... Figure 3 Point W2 is shown. The drain-source voltage V of the transistor. DS As the voltage rises to W2, the transistor generates additional static power consumption. This static power consumption increases the overall power consumption of the circuit and reduces its efficiency. Furthermore, at the transistor's drain-source voltage V... DS During the rise, the self-heating effect of the transistor will cause the on-resistance of the transistor to increase, and the overall heat dissipation of the circuit will further increase, resulting in a decrease in the stability of the transistor and even the circuit.

[0109] In order to reduce the static power consumption of the transistor power amplifier during operation, reduce the heat dissipation of the transistor, and improve the stability of the transistor and circuit system, this application provides a transistor, which is described below.

[0110] Figure 5 The first transistor 500 provided in the embodiment of this application is shown. The first transistor 500 may also be called an LDMOS transistor. The first transistor 500 may include a source 510, a drain 520, a gate 570, a metal oxide layer 580, and a substrate 591.

[0111] The substrate 591 can be made of one or more materials such as silicon, silicon carbide, or gallium nitride. The source 510 and drain 520 are located on opposite sides of the metal oxide layer 580, and the gate 570 is located on the side of the metal oxide layer 580 away from the substrate 591. A first doped layer 592 can be disposed on the side of the substrate 591 closest to the metal oxide layer 580.

[0112] The first transistor 500 may further include a source contact doped region 530 and a drain contact doped region 540. The source contact doped region 530 may be located between the first doped layer 592 and the source 510, and the source contact doped region 530 is in contact with the source 510. The drain contact doped region 540 may be located between the first doped layer 592 and the drain 520, and the drain contact doped region 540 is in contact with the drain 520.

[0113] The first transistor 500 may further include a well region 550 and a drift region 560. The well region 550 may be located between the first doped layer 592 and the source contact doped region 530, and the well region 550 is in contact with the source contact doped region 530. The drift region 560 may be located between the first doped layer 592 and the drain contact doped region 540, and the drift region 560 may be in contact with the drain contact doped region 540. Furthermore, the well region 550 and the drift region 560 may be in contact with each other.

[0114] In some scenarios, the relationship between the first doped layer 592 and the source contact doped region 530 can also be understood as follows: the first doped layer 592, the source contact doped region 530, the drain contact doped region 540, the well region 550 and the drift region 560 together form an epitaxial layer.

[0115] Alternatively, the first doped layer 592, drain contact doped region 540, well region 550, and drift region 560 can be formed on the epitaxial layer through different doping methods and other processes. On the side of the first doped layer 592 facing the source electrode 510, the well region 550 and the source contact doped region 530 are formed, respectively. The well region 550 can contact the first doped layer 592 and the source contact doped region 530, respectively, and the source contact doped region 530 can contact the well region 550 and the source electrode, respectively. On the side of the first doped layer 592 facing the drain electrode 520, the drift region 560 and the drain contact doped region 540 are formed, respectively. The drift region 560 can contact the first doped layer 592 and the drain contact doped region 540, respectively, and the drain contact doped region 540 can contact the drift region 560 and the drain electrode 520, respectively.

[0116] In some examples, the source contact doped region 530 may also be referred to as the first high-concentration doped region 530, and the drain contact doped region 540 may also be referred to as the second high-concentration doped region 540.

[0117] The end of the well region 550 away from the first doped layer 592 may contact the metal oxide layer 580. For example, the well region 550 may contact a first region of the first surface of the metal oxide layer 580. The gate 570 may contact a second region of the second surface of the metal oxide layer 580. Here, the first surface and the second surface are two surfaces of the metal oxide layer 580 that are disposed opposite each other in the thickness direction.

[0118] In some examples, the projection of the second region onto the first plane may fall within the range of the projection of the first region onto the first plane, which is a plane perpendicular to the thickness direction of the metal oxide layer 580. Alternatively, the projection of the second region onto the thickness direction of the metal oxide layer 580 may fall within the range of the projection of the first region onto the thickness direction of the metal oxide layer 580.

[0119] In some examples, the projection of the second region onto the first plane may coincide with the projection of the first region onto the first plane, or in other words, the projections of the second region and the first region onto the thickness direction of the metal oxide layer 580 may coincide.

[0120] Figure 5 The diagram shows a cross-sectional view of the first transistor 500 on a second plane. This second plane is parallel to the thickness direction of the metal oxide layer 580. The direction in which the source 510 and drain 520 are connected on this second plane is taken as the first direction. The size of the first region of the well region 550 in contact with the metal oxide layer 580 in this first direction can be L1, and the size of the second region of the gate 570 in contact with the metal oxide layer 580 in this first direction can be L2. Here, L1 ≥ L2.

[0121] In some examples, the gate 570 is a regular cuboid, and the end of the well region 550 that contacts the metal oxide layer 580 can also be regarded as a regular cuboid. In this case, the relationship between the first region and the second region can also be described as follows: the size of the gate 570 in the first direction is less than or equal to the size of the end of the well region 550 near the metal oxide layer 580, and the gate 570 is not located outside the first region where the well region 550 contacts the metal oxide layer 580.

[0122] In other words, the boundary of the gate 570 on the second plane is not located outside the boundary of the well region 550 in contact with the metal oxide layer 580 on the second plane.

[0123] For example, the left boundary of the gate 570 on the second plane may coincide with the left boundary of the contact area between the well region 550 and the metal oxide layer 580 on the second plane, and the right boundary of the gate 570 on the second plane may be located to the left of the right boundary of the contact area between the well region 550 and the metal oxide layer 580 on the second plane. Alternatively, the right boundary of the gate 570 on the second plane may coincide with the right boundary of the contact area between the well region 550 and the metal oxide layer 580 on the second plane, and the left boundary of the gate 570 on the second plane may be located to the right of the left boundary of the contact area between the well region 550 and the metal oxide layer 580 on the second plane. Alternatively, the left and right boundaries of the gate 570 on the second plane may coincide with the left and right boundaries of the contact area between the well region 550 and the metal oxide layer 580 on the second plane, respectively.

[0124] By setting the relative positional relationship between the gate 570 and the well region 550, when a voltage is applied to the gate 570, the carriers obtained by the inversion of the gate 570 can be confined within the well region 550 and cannot directly penetrate the two sides of the well region 550 and the source contact doped region 530 and the drain contact doped region 540. This is beneficial for uniformly (e.g., linearly) controlling the output characteristics of the transistor by controlling the voltage of the gate 570, which is beneficial for improving the uniformity of the transistor's output characteristics. This, in turn, helps the transistor to operate at a lower static power consumption operating point, reduces the transistor's heat dissipation, and improves the stability of the transistor and the circuit.

[0125] In some examples, the doping concentration of well region 550 is less than or equal to 5 × 10⁻⁶. 15 cm -3 (For example, 1×10) 15 cm -3 2×10 15 cm -3 3×10 15 cm -3 Or 4×10 15 cm -3 wait).

[0126] In some examples, the end of the well region 550 that contacts the metal oxide layer 580 has a dimension of less than 0.5 μm in the first direction (e.g., 0.4 μm, 0.3 μm, 0.2 μm, or 0.1 μm, etc.).

[0127] By controlling the size of the end of the well region 550 that contacts the metal oxide layer 580 and the doping concentration in the well region 550, it is beneficial to reduce the probability of the well region 550 being punched through during the application of voltage to the gate 570, which is beneficial to improve the uniformity of the transistor output characteristics.

[0128] In some examples, the source contact doped region 530 and the drain contact doped region 540 both contain high concentrations of n-type impurities, the well region 550 contains p-type impurities, the substrate 591 is a p-type substrate, and the first doped layer 592 contains p-type impurities. In this case, the source contact doped region 530 can also be referred to as the first n+ region, the drain contact doped region 540 can also be referred to as the second n+ region, and the well region 550 can also be referred to as the p-type well region.

[0129] In some examples, the source contact doped region 530 and the drain contact doped region 540 both contain high concentrations of p-type impurities, the well region 550 contains n-type impurities, the substrate 591 is an n-type substrate, and the first doped layer 592 contains n-type impurities. In this case, the source contact doped region 530 can also be referred to as the first p+ region, the drain contact doped region 540 can also be referred to as the second p+ region, and the well region 550 can also be referred to as the n-type well region.

[0130] In some examples, such as Figure 6 As shown, the first transistor 500 may further include a charge balancing layer 593, which is located between the drift region 560 and the first doped layer 592, and the charge balancing layer 593 is in contact with the drift region 560 and the first doped layer 592 respectively.

[0131] The charge balancing layer 593 can be highly doped. For example, if the first transistor 500 is an n-type MOS transistor, the charge balancing layer 593 can be highly n-type doped. If the first transistor 500 is a p-type MOS transistor, the charge balancing layer 593 can be highly p-type doped.

[0132] In some examples, the dimension of the charge balancing layer 593 in the thickness direction of the metal oxide layer 580 is greater than or equal to 50 nm and less than or equal to 500 nm, for example, it can be 100 nm, 200 nm, 300 nm or 400 nm, etc.

[0133] In some examples, the doping concentration of the charge balance layer 593 is greater than or equal to 1 × 10⁻⁶. 17 cm -3 And less than or equal to 1×10 20 cm -3 For example, the doping concentration of the charge balance layer 593 can be 1×10⁻⁶. 18 cm -3 Or 5×10 18 cm -3 Or 1×10 19 cm -3 wait.

[0134] The electrons (or holes) ionized in the charge balance layer 593 can be balanced with the holes (or electrons) ionized in the first doped layer 592, so that the drift region 560 is not affected by the first doped layer 592. The drift region 560 has similar one-dimensional electrical characteristics in the lateral direction (or the aforementioned first direction), which is beneficial to improving the controllability of the well region 550 punch-through and improving the stability of the transistor output characteristics.

[0135] In some examples, such as Figure 7 As shown, the first transistor 500 may also be provided with a connection region 594, which is used to connect the source 510 and the substrate 591.

[0136] In some examples, the connection region 594 can be a highly doped sinker region, with one end connected to the source 510 and the other end connected to the substrate 591. If the first transistor 500 is an n-type MOS transistor, the highly doped sinker region can be a p-type highly doped sinker region. If the first transistor 500 is a p-type MOS transistor, the highly doped sinker region can be an n-type highly doped sinker region.

[0137] In some examples, the connection region 594 can be a metal region (or the connection region 594 is composed of a metallic material), one end of which is connected to the source 510 and the other end is connected to the substrate 591.

[0138] In some examples, the connection region 594 may be composed of a highly doped lead-out region and a metal region, with the highly doped lead-out region connected to the metal region. For example, the connection region 594 can be considered as a pillar, with a first portion in the axial direction representing the highly doped lead-out region and a second portion in the axial direction representing the metal region, the first and second portions being in contact with each other. One end of the connection region 594 containing the highly doped lead-out region can be connected to the source 510, and the other end of the connection region 594 containing the metal region can be connected to the substrate 591. Alternatively, one end of the connection region 594 containing the metal region can be connected to the source 510, and the other end of the connection region 594 containing the highly doped lead-out region can be connected to the substrate 591.

[0139] In some examples, the connection region 594 can also be connected to the first doped region 592, which is connected to the substrate 591, so that the connection region 594 can realize the electrical connection between the source 510 and the substrate 591.

[0140] By electrically connecting the source and substrate of the transistor through the connection region 594, the source and substrate have the same potential. This structure of transistor is more suitable for high-frequency power amplifier scenarios.

[0141] like Figure 8 As shown, the first transistor 500 may further include one or more of a metal layer 595, a field plate 596, or a dielectric layer 597. The metal layer 595 is in contact with the side of the substrate 591 away from the first doped region 592, the field plate 596 is located between the gate 570 and the drain 520 and is disposed close to the gate 570, and the dielectric layer 597 may be located on the side of the metal oxide layer 580 away from the substrate 591.

[0142] The metal layer 595 facilitates grounding when the first transistor 500 is mounted on the circuit board, the field plate 596 helps to improve the breakdown voltage of the gate 570, and the dielectric layer 597 can cover the surface of the first transistor 500, thereby protecting the aforementioned source 510, drain 520 and other components in the first transistor 500.

[0143] It should be noted that the above description of the structure of the first transistor 500 should not be construed as a limitation on the manufacturing process of the first transistor 500. For example, the first doped layer 592 disposed on the substrate 591 can be formed by epitaxial growth on the substrate 591, or it can be formed by other feasible methods. The well region 550 in contact with the first doped layer 592 can be another region belonging to the same epitaxial layer as the first doped layer 592, or it can be another separate structure connected to the first doped layer 592.

[0144] Figure 9 The image shows a second transistor 900 provided in an embodiment of this application. This second transistor 900 may also be referred to as a GaNHEMT transistor 900.

[0145] The second transistor 900 may include a source 910, a drain 920, a GaN layer 930, a substrate 940, a gate 950, an AlGaN layer 960, and a modulation island 970.

[0146] The substrate 940 can be one or more materials such as SiC, Si, GaN or AlN. The GaN layer 930 can also be called a GaN buffer layer, and the AlGaN layer 960 can also be called an AlGaN barrier layer.

[0147] A GaN layer 930 is disposed on a substrate 940, and an AlGaN layer 960 is disposed close to the GaN layer 930 and located on the side of the GaN layer 930 away from the substrate 940. The GaN layer 930 is in contact with both the substrate 940 and the AlGaN layer 960. A 2DEG (not shown in the figure) can be formed in the vicinity of the adjacent side of the GaN layer 930 and the AlGaN layer 960. This 2DEG can be used to connect the source 910 and the drain 920 of the second transistor 900.

[0148] The source 910 and drain 920 are respectively contacted at both ends of the AlGaN layer 960, and both the source 910 and drain 920 can contact the GaN layer 930. The gate 950 is in contact with the AlGaN layer 960 on the side opposite to the GaN layer 930 and is located between the source 910 and drain 920.

[0149] The regulating island 970 is located between the gate 950 and the drain 920. The regulating island 970 can contact the AlGaN layer 960 and is located on the side opposite to the GaN layer 930.

[0150] In some examples, the regulating island 970 may be composed of one or more of p-type doped GaN, p-type doped AlGaN, or metal.

[0151] By setting a regulating island between the gate and drain that contacts the AlGaN layer, the carriers within the regulating island can, to some extent, regulate the conduction characteristics of the local 2DEG channels within the GaN layer corresponding to the location of the regulating island. Therefore, when a voltage is applied to the second transistor 900, the aforementioned local 2DEGs can be gradually turned on. Compared to the case where all 2DEGs are turned on when a critical voltage is reached, the conduction characteristics of the source and drain of the second transistor 900 provided by this technical solution are more controllable, and the output characteristics of the second transistor 900 are also more controllable. This is beneficial for reducing the static power consumption and heat loss of the second transistor, improving the energy conversion efficiency of the second transistor 900, and enhancing the thermal stability of the second transistor 900.

[0152] In some examples, such as Figure 10 As shown, the modulation island 970 may include multiple sub-modulation islands, all located between the gate 950 and the drain 920. Each of the multiple sub-modulation islands can contact the AlGaN layer 960. The multiple sub-modulation islands are spaced apart from each other.

[0153] For example, the regulating island 970 may include a first sub-regulating island 971, a second sub-regulating island 972, and a third sub-regulating island 973. These three sub-regulating islands are spaced apart from each other, wherein the first sub-regulating island 971 is disposed near the gate 950, and the third sub-regulating island 972 is disposed near the drain 920.

[0154] In some examples, such as Figure 11 As shown, the first sub-regulation island 971 can form an ohmic contact or a Schottky contact with the gate 950.

[0155] In some examples, such as Figure 11 As shown, the third sub-regulation island 973 can form an ohmic contact or a Schottky contact with the drain 920.

[0156] This creates the specific interface structure described above between the first sub-regulating island 971 and the gate 950, and / or between the third sub-regulating island 973 and the drain 920. The electrical characteristics of the regulating islands corresponding to this interface structure are more intuitive, which is beneficial for more effective control of the output characteristics of the second transistor 900.

[0157] For example, the regulating island 970 may also include more sub-regulating islands, such as 4, 5, 7, etc., and multiple sub-regulating islands can jointly regulate the conduction characteristics of the second transistor 900.

[0158] Different numbers of sub-regulation islands correspond to different output characteristics of the second transistor 900. The implementation of this technical solution is conducive to realizing the regulation of the output characteristics of the second transistor 900 within a wider range, thereby obtaining transistors suitable for different application scenarios and improving the application range of the second transistor 900.

[0159] In some examples, the second transistor 900 may also include a lead-out region 980, which may be a p-type heavily doped lead-out region. The lead-out region 980 may be used to connect the source 910 and the substrate 940.

[0160] For example, such as Figure 12 As shown, the lead-out region 980 can be disposed on the side of the GaN layer 930 and the substrate 940 near the source 910. One end of the lead-out region 980 can contact the source 910, and the end of the lead-out region 980 near the substrate 940 can contact the substrate 940.

[0161] Constructing the region connecting the source 910 and the substrate 940 by doping the semiconductor simplifies the structure of the second transistor 900 and improves its production efficiency.

[0162] In one possible implementation, the second transistor 900 further includes a nucleation layer located between the substrate and the GaN layer.

[0163] like Figure 13 As shown, the second transistor 900 may further include one or more of a metal layer 990, a field plate 952, or a dielectric layer 951. The metal layer 990 is in contact with the side of the substrate 940 away from the GaN layer 930, the field plate 952 is located between the gate 950 and the drain 920 and is disposed close to the gate 950, and the dielectric layer 951 may be located on the side of the AlGaN layer 960 away from the substrate 940.

[0164] The metal layer 990 facilitates grounding when the second transistor 900 is mounted on the circuit board, the field plate 952 helps to improve the breakdown voltage of the gate 950, and the dielectric layer 951 can cover the surface of the second transistor 900, thereby protecting the aforementioned source 910, drain 920 and regulating island 970 components in the second transistor 900.

[0165] Figure 14 and Figure 15 The figures shown are schematic diagrams of the output characteristic curves of the first transistor 500 and the second transistor 900 provided in the embodiments of this application.

[0166] Figure 14 The first curve 1410, the second curve 1420, and the third curve 1430 in the figure represent the output characteristic curves of the first transistor 500 when the gate voltage is 4V, 2V, 0V, and -2V, respectively. Figure 14 As shown, for the same drain-source current I1, the drain-source voltages of the first curve 1410, the second curve 1420, the third curve 1430, and the fourth curve 1440 are V1, V2, V3, and V4, respectively, where V1 < V2 < V3 < V4. In other words, as the gate voltage of the first transistor 500 decreases from 4V to 2V, 0V, and -2V, the drain-source voltage of the first transistor 500 gradually increases from V1 to V2, V3, and V4. This achieves the amplification effect of the voltage-controlled voltage under constant current bias, and the first transistor 500 basically realizes the function of an amplifier.

[0167] It should also be noted that the output characteristic curves of the first transistor 500 measured at different gate voltages are merely illustrative examples and should not be construed as limiting the function or attributes of the first transistor 500 provided in this application.

[0168] Figure 15 Curves 1510, 1520, 1530, and 1540 in the figure represent the output characteristic curves of the second transistor 900 when its gate voltage is 4V, 3V, 2V, and 1V, respectively. Figure 15 It can be seen that for the same drain-source current I2, the drain-source voltages of the fifth curve 1510, the sixth curve 1520, the seventh curve 1530, and the eighth curve 1540 are V5, V6, V7, and V8, respectively, where V5 < V6 < V7 < V8. In other words, as the gate voltage of the second transistor 900 decreases from 4V to 3V, 2V, and 1V, the drain-source voltage of the second transistor 900 gradually increases from V5 to V6, V7, and V8. This achieves the amplification effect of the voltage-controlled voltage under constant current bias, and the second transistor 900 basically realizes the function of an amplifier.

[0169] It should also be noted that the output characteristic curves of the second transistor 900 measured at different gate voltages are merely illustrative examples and should not be construed as limiting the function or attributes of the second transistor 900 provided in this application.

[0170] In addition, this application also provides an electronic device that may include one or more first transistors 500 in the foregoing embodiments, and may also include one or more second transistors 900 in the foregoing embodiments, or may include one or more first transistors 500 and second transistors 900 simultaneously.

[0171] In some examples, the electronic device can be a power amplifier or a power amplification device.

[0172] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0173] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A transistor, characterized in that, include: Source, drain, gate, metal oxide layer, first doped layer, source contact doped region, drain contact doped region, p-type well region, n-type drift region, and substrate. The first doped layer is located on the substrate, and the first doped layer is a p-type doped region; The source contact doped region is located between the first doped layer and the source and is in contact with the source; the drain contact doped region is located between the first doped layer and the drain and is in contact with the drain. The source contact doped region and the drain contact doped region are n-type doped regions; The p-type well region is located between the source contact doped region and the first doped layer and is in contact with the source contact doped region; the n-type drift region is located between the drain contact doped layer and the first doped layer and is in contact with the drain contact doped region; the p-type well region is in contact with the n-type drift region. The p-type well region is in contact with a first region of a first surface of the metal oxide layer, and the gate is in contact with a second region of a second surface of the metal oxide layer. The first surface and the second surface are two opposite surfaces of the metal oxide layer in the thickness direction. Wherein, the projection of the second region in the thickness direction is located inside the projection of the first region in the thickness direction, or the projection of the second region in the thickness direction coincides with the projection of the first region in the thickness direction. Wherein, the doping concentration of the p-type well region is less than or equal to 5 × 10⁻⁶. 16 cm -3 The size of the first region in the first direction is less than or equal to 0.5 μm, and the first direction is the direction in which the source and the drain are connected.

2. The transistor according to claim 1, characterized in that, The transistor further includes a charge balancing layer located between the first doped layer and the n-type drift region, and the charge balancing layer is in contact with both the first doped layer and the n-type drift region.

3. The transistor according to claim 2, characterized in that, The doping concentration of the charge balance layer is greater than or equal to 1×10⁻⁶. 17 cm -3 And less than or equal to 1×10 20 cm -3 .

4. The transistor according to claim 2 or 3, characterized in that, The charge balancing layer has a dimension in the thickness direction that is greater than or equal to 50 nm and less than or equal to 500 nm.

5. The transistor according to any one of claims 1 to 3, characterized in that, The source electrode is electrically connected to the substrate; The transistor further includes one or more of a metal layer, a field plate, or a dielectric layer, wherein the metal layer is connected to the side of the substrate away from the first doped layer, the field plate is located between the gate and the drain and is disposed close to the gate, and the dielectric layer is located on the side of the metal oxide layer away from the substrate.

6. The transistor according to claim 5, characterized in that, The transistor further includes a connection region for connecting the source electrode to the substrate, the connection region including a highly doped lead-out region and / or a metal region.

7. An electronic device, characterized in that, Includes the transistor as described in any one of claims 1 to 6.

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