An FPGA speed reduction bridge, rate adaptation method, electronic device and medium

Abstract

The present application provides an FPGA speed reduction bridge, a rate adaptation method, an electronic device, and a medium. The FPGA speed reduction bridge includes: an FPGA multi-rate Ethernet interface, a rate adaptation module, a rate adaptation control module, and a protocol adaptation module; among them, the multi-rate Ethernet interface can be configured as one of multiple different configured rates, is connected to an external Ethernet device, and communicates data with the Ethernet device at the configured rate; the rate adaptation module is connected to the multi-rate Ethernet interface and includes an asynchronous FIFO for caching Ethernet packet data received by the multi-rate Ethernet interface from the Ethernet device; the protocol adaptation module is connected to the rate adaptation module and includes a MAC layer encoding / decoding module and a PCS layer encoding / decoding module; the rate adaptation control module is used to adapt the configured rate of the multi-rate Ethernet interface and output clock signals used by the MAC layer and PCS layer encoding / decoding modules based on the adapted configured rate.

Description

Technical Field

[0001] This application belongs to the field of chip technology, and particularly relates to an FPGA speed reduction bridge, a rate adaptation method, an electronic device, and a medium. Background Art

[0002] As ASIC (Application-Specific Integrated Circuit) becomes larger and more complex, it must be fully verified before tape-out. In addition to verification means such as EDA / EMU, FPGA (Field-Programmable Gate Array) prototype verification is becoming an indispensable means for accelerating verification convergence of large-scale SOC chips.

[0003] The rate of Ethernet interfaces is getting higher and higher. The standard single-link highest rate of the ETH interface based on the IEEE 802.3 protocol has reached 1.6 Tbps. At the same time, in order for ASIC chips to be competent in more scenarios, the interfaces often support multiple rates and generally downwardly compatible with multiple rates. For example, the rate of a single link of the Ethernet interface supports multiple rate modes such as 400G / 200G / 100G / 50G / 25G / 10G / 1G, making its application scenarios more diverse. However, due to the generally complex ASIC logic, it can generally only run at dozens of MHz on the FPGA platform, so it is necessary to reduce the frequency of the ASIC logic. Summary of the Invention

[0004] The purpose of this application is to provide an FPGA speed reduction bridge, a rate adaptation method, an electronic device, and a medium, aiming to solve problems such as protocol adaptation, rate adaptation, and lossless transmission.

[0005] In the first aspect of this application, an FPGA speed reduction bridge is provided, including: an FPGA multi-rate Ethernet interface, a rate adaptation module, a rate adaptation control module, and a protocol adaptation module; where

[0006] The FPGA multi-rate Ethernet interface can be configured as one of multiple different configured rates, is connected to an external Ethernet device, and communicates with the Ethernet device at the configured configured rate.

[0007] The rate adaptation module is connected to the FPGA multi-rate Ethernet interface, and includes an asynchronous FIFO for caching Ethernet packet data received by the FPGA multi-rate Ethernet interface from the Ethernet device.

[0008] The protocol adaptation module is connected to the rate adaptation module, and includes a MAC layer encoding / decoding module and a PCS layer encoding / decoding module. The MAC layer encoding / decoding module is used to perform MAC layer encoding on the Ethernet packet data stored in the asynchronous FIFO. The PCS layer encoding / decoding module is used to perform PCS layer encoding on the encoded data output by the MAC layer encoding / decoding module;

[0009] The rate adaptation control module is used to adapt the configured rate of the FPGA multi-rate Ethernet interface, and output the clock signals used by the MAC layer encoding / decoding module and the PCS layer encoding / decoding module based on the adapted configured rate.

[0010] In an alternative embodiment, the FPGA multi-rate Ethernet interface includes a first DRP dynamic configuration module, a first memory, a first QPLL frequency synthesizer, and a first register; the first memory is used to store configuration parameters corresponding to one or more configured rates. The first DRP dynamic configuration module receives a first configuration signal from an external software through a software control interface, and configures the first QPLL frequency synthesizer according to the configuration parameters corresponding to the configured rate specified by the first configuration signal. After the first QPLL frequency synthesizer is configured, the configuration parameters corresponding to the configured rate specified by the first configuration signal are written into the first register; the configured rate specified by the first configuration signal is one of the configured rates corresponding to the configuration parameters stored in the first memory or the configured rate specified by the external software.

[0011] In an alternative embodiment, the rate adaptation control module includes: a second DRP dynamic configuration module, a second memory, a second QPLL frequency synthesizer, a CPLL frequency synthesizer, and a second register; the second memory is used to store configuration parameters corresponding to one or more configured rates. The second DRP dynamic configuration module receives a second configuration signal from an external software through a software control interface, and configures the second QPLL frequency synthesizer and the CPLL frequency synthesizer according to the configuration parameters corresponding to the configured rate specified by the second configuration signal. After the second QPLL frequency synthesizer and the CPLL frequency synthesizer are configured, the configuration parameters corresponding to the configured rate specified by the second configuration signal are written into the second register; the configured rate specified by the second configuration signal is one of the configured rates corresponding to the configuration parameters stored in the second memory or the configured rate specified by the external software.

[0012] In an alternative embodiment, the rate adaptation control module further includes: a first clock buffer, a second clock buffer, and a third clock buffer;

[0013] The second register is provided with a user-configured frequency division interface. By configuring the user-configured frequency division interface to 32-division, a 32-division clock signal is obtained, and the 32-division clock signal is stored in the first clock buffer to obtain a 32-division clock signal output to the PCS layer codec module. The 32-division clock signal is turned off once every 32 cycles and then stored in the second clock buffer to obtain a 33-division clock signal output to the MAC layer codec module. The 32-division clock signal is turned off once every 1 cycle, and two are turned off every 32 cycles and then stored in the third clock buffer to obtain a 66-division clock signal output to the PCS layer codec module.

[0014] In an optional implementation, the asynchronous FIFO in the rate adaptation module is provided with: a nearly full alarm watermark threshold, a nearly empty alarm watermark threshold, and a read start watermark threshold. When the amount of data in the asynchronous FIFO is greater than or equal to the nearly full alarm watermark threshold, the external software is triggered to reconfigure the configuration value of the minimum average frame interval of the MAC layer codec module to reduce it; when the amount of data in the asynchronous FIFO is less than or equal to the nearly empty alarm watermark threshold, the external software is triggered to reconfigure the read start watermark threshold to increase it.

[0015] In an optional implementation, the asynchronous FIFO in the rate adaptation module is provided with: a nearly full alarm watermark threshold, a release nearly full alarm watermark threshold, a nearly empty alarm watermark threshold, a release nearly empty alarm watermark threshold and a read start watermark threshold;

[0016] When the amount of data in the asynchronous FIFO is greater than or equal to the almost-full alarm watermark threshold, if the rate adaptation module is configured in an adaptive inter-frame interval adjustment mode, the MAC layer codec module is triggered to periodically delete the inter-frame interval of the Ethernet message data until the amount of data in the asynchronous FIFO is less than or equal to the threshold for releasing the almost-full alarm watermark; if the cumulative number of times the almost-full alarm watermark threshold is greater than or equal to the first set threshold, the configuration value of the minimum average frame interval of the MAC layer codec module is reduced;

[0017] When the amount of data in the asynchronous FIFO is less than or equal to the empty alarm watermark threshold, if the rate adaptation module is configured as the adaptive inter-frame interval adjustment mode, the MAC layer codec module is triggered to periodically insert inter-frame intervals into the Ethernet message data until the amount of data in the asynchronous FIFO is greater than or equal to the release of the empty alarm watermark threshold; if the cumulative number of times the empty alarm watermark threshold is greater than or equal to the second set threshold, the read start watermark threshold is raised.

[0018] In an alternative embodiment, the following thresholds are sorted from largest to smallest as follows: the full-alarm waterline threshold, the deactivate full-alarm waterline threshold, the read start waterline threshold, the deactivate empty-alarm waterline threshold, and the empty-alarm waterline threshold.

[0019] The second aspect of the present application provides a rate adaptation method, which is implemented by using the FPGA downspeed bridge described in the first aspect. The method includes:

[0020] Configure the FPGA multi-rate Ethernet interface to one of multiple different configured rates;

[0021] Use the rate adaptation control module to adapt the configured rate of the FPGA multi-rate Ethernet interface and output the clock signals used by the MAC layer codec module and the PCS layer codec module; the configured rate adapted by the rate adaptation control module has a preset adaptation relationship with the configured rate of the FPGA multi-rate Ethernet interface.

[0022] In an alternative embodiment, configuring the FPGA multi-rate Ethernet interface to one of multiple different configured rates includes:

[0023] The first DRP dynamic configuration module of the rate adaptation control module receives a first configuration signal from an external software through a software control interface;

[0024] Configure the first QPLL frequency synthesizer of the rate adaptation control module according to the configuration parameters corresponding to the configured rate specified by the first configuration signal;

[0025] If the first QPLL frequency synthesizer is configured, write the configuration parameters corresponding to the configured rate specified by the first configuration signal into the first register of the rate adaptation control module; the configured rate specified by the first configuration signal is one of the configured rates corresponding to the configuration parameters stored in the first memory of the rate adaptation control module or the configured rate specified by the external software.

[0026] In an alternative embodiment, using the rate adaptation control module to adapt the configured rate of the FPGA multi-rate Ethernet interface and output the clock signals used by the MAC layer codec module and the PCS layer codec module includes:

[0027] The second DRP dynamic configuration module of the rate adaptation control module receives a second configuration signal from an external software through a software control interface;

[0028] Configure the second QPLL frequency synthesizer and the CPLL frequency synthesizer of the rate adaptation control module according to the configuration parameters corresponding to the configured rate specified by the second configuration signal;

[0029] If the second QPLL frequency synthesizer and CPLL frequency synthesizer are configured, the configuration parameters corresponding to the configuration rate specified by the second configuration signal are written into the second register of the rate adaptation control module; the configuration rate specified by the second configuration signal is one of the configuration rates corresponding to the configuration parameters stored in the second memory of the rate adaptation control module or the configuration rate specified by the external software.

[0030] In an optional embodiment, the method further comprises:

[0031] The user-configured frequency division interface of the second register is configured to be divided by 32, so as to obtain a divided-by-32 clock signal;

[0032] The 32-frequency clock signal is stored in a first clock buffer to obtain a 32-frequency clock signal output to the PCS layer encoding and decoding module;

[0033] The 32-frequency divided clock signal is turned off once every 32 cycles and then stored in a second clock buffer to obtain a 33-frequency divided clock signal output to the MAC layer encoding and decoding module;

[0034] The 32-frequency-divided clock signal is turned off by one per cycle, and by two per 32 cycles, and then stored in a third clock buffer to obtain a 66-frequency-divided clock signal output to the PCS layer encoding and decoding module.

[0035] In an optional embodiment, the method further comprises:

[0036] Setting a nearly full alarm watermark threshold, a nearly empty alarm watermark threshold and a read start watermark threshold for the asynchronous FIFO in the rate adaptation module;

[0037] If it is detected that the amount of data in the asynchronous FIFO is greater than or equal to the full alarm waterline threshold, trigger the external software to reconfigure the configuration value of the minimum average frame interval of the MAC layer codec module to reduce it;

[0038] If it is detected that the amount of data in the asynchronous FIFO is less than or equal to the empty alarm watermark threshold, external software is triggered to reconfigure the read start watermark threshold to increase it.

[0039] In an optional embodiment, the method further comprises:

[0040] Setting a nearly full alarm watermark threshold, a release nearly full alarm watermark threshold, a nearly empty alarm watermark threshold, a release nearly empty alarm watermark threshold and a read start watermark threshold for the asynchronous FIFO in the rate adaptation module;

[0041] If it is detected that the amount of data in the asynchronous FIFO is greater than or equal to the almost-full alarm watermark threshold, and the rate adaptation module is configured in an adaptive interframe interval adjustment mode, the MAC layer codec module is triggered to periodically delete the interframe interval of the Ethernet message data until the amount of data in the asynchronous FIFO is less than or equal to the release of the almost-full alarm watermark threshold;

[0042] If the accumulated number of times the alarm waterline threshold is about to be full is greater than or equal to the first set threshold, reducing the configuration value of the minimum average frame interval of the MAC layer encoding and decoding module;

[0043] If it is detected that the amount of data in the asynchronous FIFO is less than or equal to the empty alarm watermark threshold, and the rate adaptation module is configured in the adaptive interframe interval adjustment mode, the MAC layer codec module is triggered to periodically insert an interframe interval into the Ethernet message data until the amount of data in the asynchronous FIFO is greater than or equal to the release empty alarm watermark threshold;

[0044] If the accumulated number of times the empty alarm watermark threshold is reached is greater than or equal to the second set threshold, the read start watermark threshold is increased.

[0045] A third aspect of the present application provides an electronic device, including a processor and a memory, wherein the memory stores a plurality of instructions, and the processor is used to read the instructions and execute the method of the first aspect.

[0046] A fourth aspect of the present application provides a computer-readable storage medium, which stores a plurality of instructions, and the plurality of instructions can be read by a processor to execute the method of the first aspect.

[0047] Compared with the related art, the technical solution of the present application has at least the following advantages:

[0048] The present application solves the problem of lossless line rate transparent transmission of Ethernet test equipment traffic through an FPGA speed reduction bridge by combining rate adaptation and frequency deviation adaptation; it also solves the problem in related technologies that the FPGA speed reduction bridge cannot test the real PFC / PAUSE of ASIC DUT by matching the rate of the real Ethernet test equipment through flow control; it also increases the connection rate with the real Ethernet test equipment to up to 10Gbps, speeds up verification efficiency, and improves the convergence speed of prototype verification; it realizes multi-rate connection between the FPGA speed reduction bridge and the real Ethernet test equipment, and solves the problem of multi-rate switching.

[0049] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by practicing the present application. The purpose and other advantages of the present application can be realized and obtained through the structures and processes indicated in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following will briefly introduce the drawings required for use in the description of the embodiments or related technologies. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0051] Figure 1 is a block diagram of an implementation structure of an FPGA speed reduction bridge according to related technologies.

[0052] Figure 2 is a block diagram of an implementation structure of an FPGA speed reduction bridge according to an exemplary embodiment of the present application.

[0053] Figure 3 is a block diagram of the structure of an FPGA multi-rate Ethernet interface according to an exemplary embodiment of the present application.

[0054] Figure 4 is a flow chart of rate adaptation of an FPGA multi-rate Ethernet interface according to an exemplary embodiment of the present application.

[0055] Figure 5 is a block diagram of the structure of a rate adaptation control module according to an exemplary embodiment of the present application.

[0056] Figure 6 is a flow chart of rate adaptation of a rate adaptation control module according to an exemplary embodiment of the present application.

[0057] Figure 7 is an equivalent frequency division block diagram of a rate adaptation control module according to an exemplary embodiment of the present application.

[0058] Figure 8 is a block diagram of frequency offset adaptation according to an exemplary embodiment of the present application.

[0059] Figure 9 is a diagram showing the high and low effects of each waterline set for an asynchronous FIFO according to an exemplary embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0060] In order to make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present application.

[0061] The method provided by this application can be implemented in the following terminal environment. The terminal may include one or more of the following components: a processor, a memory, and a display screen. Among them, at least one instruction is stored in the memory, and the instruction is loaded and executed by the processor to implement the method described in the following embodiments.

[0062] The processor may include one or more processing cores. The processor uses various interfaces and lines to connect various parts within the entire terminal, and by running or executing instructions, programs, code sets, or instruction sets stored in the memory, as well as calling data stored in the memory, it executes various functions of the terminal and processes data.

[0063] The memory may include a Random Access Memory (RAM), and may also include a Read-Only Memory (ROM). The memory can be used to store instructions, programs, codes, code sets, or instructions.

[0064] The display screen is used to display the user interfaces of various application programs.

[0065] In addition, those skilled in the art can understand that the structure of the above terminal does not constitute a limitation on the terminal. The terminal may include more or fewer components, or combine certain components, or have different component arrangements. For example, the terminal also includes components such as a radio frequency circuit, an input unit, a sensor, an audio circuit, and a power supply, which will not be elaborated here.

[0066] Combined with the relevant technical status mentioned in the background technology, in order to be able to connect to a real test instrument, a speed reduction bridge needs to be added in front of the ASIC logic to be tested to match the speed of the real test instrument and the speed after the ASIC is speed-reduced.

[0067] The inventors of this application found the core problems that the speed reduction bridge needs to solve:

[0068] 1. Speed adaptation, which essentially needs to solve the problem of clock matching.

[0069] 2. Protocol adaptation. The lower Ethernet interface protocol for connecting to a real instrument is completely different from the actual ASIC DUT high-speed Ethernet interface protocol; the related technology is the adaptation of the 1G to 10G / 100G high-speed Ethernet protocol.

[0070] As an auxiliary verification means in ASIC verification, the inventors of this application found through retrieval that in the related technology, after MAC layer encoding, it is directly connected to the DUT. For example, Figure 1 in the FPGA speed reduction bridge structure of the related technology shown, some functions are not implemented, and only the problem of the presence or absence of traffic is solved.

[0071] Therefore, the FPGA speed reduction bridge in the related art has the following defects:

[0072] The protocol adaptation only reaches the MAC layer encoding and cannot test and cover the PCS logic of the ASIC. The possible reason is that the rate adaptation problem cannot be solved, resulting in the abandonment of the test of the PCS on the FPGA prototype;

[0073] The interface connected to the tester only supports a 1G rate and cannot cover the scenario of multi-rate switching;

[0074] During rate adaptation, packets are violently discarded through the status of the FIFO or the tester packet sending is paused by sending PAUSE flow control frames, resulting in the inability to test scenarios such as lossless transmission of ASIC DUTs such as ROCE. Many extreme situations in the line rate scenario cannot be effectively covered on the FPGA prototype, and stress tests cannot be effectively tested on the FPGA prototype either. Only functional tests can be performed.

[0075] Based on the above analysis, to solve the problems existing in the related art, this application proposes an FPGA speed reduction bridge and a rate adaptation method, which solves the problem of rate matching after the frequency reduction of a real Ethernet test device through the FPGA interface and the ASIC DUT. Through the combination of rate adaptation and frequency offset adaptation, this application solves the problem of lossless line rate transparent transmission of the Ethernet test device traffic through the FPGA speed reduction bridge; it also solves the problem that the FPGA speed reduction bridge in the related art cannot test the real PFC / PAUSE of the ASIC DUT by flow controlling the real Ethernet test device to match the rate; it also increases the connection rate with the real Ethernet test device up to 10 Gbps, speeds up the verification efficiency, and improves the convergence speed of the prototype verification; it realizes multi-rate connection between the FPGA speed reduction bridge and the real Ethernet test device and solves the problem of multi-rate switching.

[0076] See Figure 2 As shown, this application exemplarily proposes an FPGA speed reduction bridge, including: an FPGA multi-rate Ethernet interface, a rate adaptation module, a rate adaptation control module, and a protocol adaptation module; among them,

[0077] The FPGA multi-rate Ethernet interface can be configured as one of multiple different configured rates, is connected to an external Ethernet device, and communicates data with the Ethernet device at the configured configured rate;

[0078] The rate adaptation module is connected to the FPGA multi-rate Ethernet interface and includes an asynchronous FIFO for caching the Ethernet packet data received by the FPGA multi-rate Ethernet interface from the Ethernet device;

[0079] The protocol adaptation module is connected to the rate adaptation module, and includes a MAC layer encoding and decoding module and a PCS layer encoding and decoding module. The MAC layer encoding and decoding module is used to perform MAC layer encoding on the Ethernet packet data stored in the asynchronous FIFO, and the PCS layer encoding and decoding module is used to perform PCS layer encoding on the encoded data output by the MAC layer encoding and decoding module;

[0080] The rate adaptation control module is used to adapt the configured rate of the FPGA multi-rate Ethernet interface, and output the clock signals used by the MAC layer encoding and decoding module and the PCS layer encoding and decoding module based on the adapted configured rate.

[0081] In an optional embodiment of the present application, the FPGA multi-rate Ethernet interface includes a first DRP dynamic configuration module, a first memory, a first QPLL frequency synthesizer, and a first register; the first memory is used to store configuration parameters corresponding to one or more configured rates, the first DRP dynamic configuration module receives a first configuration signal from an external software through a software control interface, and configures the first QPLL frequency synthesizer according to the configuration parameters corresponding to the configured rate specified by the first configuration signal. After the first QPLL frequency synthesizer is configured, the configuration parameters corresponding to the configured rate specified by the first configuration signal are written into the first register; the configured rate specified by the first configuration signal is one of the configured rates corresponding to the configuration parameters stored in the first memory or the configured rate specified by the external software.

[0082] In some embodiments, the first register is an FPGA Serdes, such as GTY. In this embodiment, the first QPLL frequency synthesizer is located inside the GTY.

[0083] As an optional implementation manner, as shown in Figure 3 The external software configures the DRP (Dynamic Reconfiguration Port) of the FPGA multi-rate Ethernet interface through an APB (Advanced Peripheral Bus) software control interface. The first memory of the FPGA multi-rate Ethernet interface can be a ROM, which can store configuration parameters of multiple configured rates, such as Serdes configuration parameters of four configured rates of 1G / 2.5G / 5G / 10G. After the external software issues a rate switching command through the APB software control interface, the DRP dynamic configuration module follows Figure 4The exemplary process reads the Serdes configuration parameters corresponding to the configured rate from the ROM and writes them to the Serdes lane (i.e., the first register) through the Serdes DRP interface. After the configuration is completed, the Serdes lane is reset; alternatively, the external software can also drive the DRP dynamic configuration module through the APB software control interface, and dynamically configure the serdes configuration parameters corresponding to the configured rate specified by the external software to the Serdes lane through the Serdes DRP interface to complete the speed switching of the FPGA multi-rate Ethernet interface.

[0084] See Figure 4 As shown, exemplarily, first, if the CPLL clock lock signal or the QPLL clock lock signal is detected, it is determined whether a configuration signal for rate switching is received; if so, the corresponding ROM address in the FPGA multi-rate Ethernet interface is selected according to the configured rate specified in the configuration signal, and the address of the corresponding second register (GTY, i.e., the FPGA Serdes) is read; after waiting for the DRP interface to be ready, the fields to be reconfigured in the second register are masked, and the fields to be reconfigured are written to the second register; after waiting for the DRP interface to be ready again, it is determined whether the second register is configured completely. If it is completed, the GTY is reset. If not, it returns to wait for the next configuration.

[0085] In an optional embodiment of the present application, the rate adaptation control module includes: a second DRP dynamic configuration module, a second memory, a second QPLL frequency synthesizer, a CPLL frequency synthesizer, and a second register; the second memory is used to store the configuration parameters corresponding to one or more configured rates. The second DRP dynamic configuration module receives a second configuration signal from the external software through the software control interface, and configures the second QPLL frequency synthesizer and the CPLL frequency synthesizer according to the configuration parameters corresponding to the configured rate specified by the second configuration signal. After the second QPLL frequency synthesizer and the CPLL frequency synthesizer are configured, the configuration parameters corresponding to the configured rate specified by the second configuration signal are written into the second register; the configured rate specified by the second configuration signal is one of the configured rates corresponding to the configuration parameters stored in the second memory or the configured rate specified by the external software.

[0086] The configured rate specified by the second configuration signal has a preset adaptation relationship with the configured rate specified by the first configuration signal for configuring the FPGA multi-rate Ethernet interface.

[0087] In some embodiments, the second register is the FPGA Serdes, such as GTY. In this embodiment, the second QPLL frequency synthesizer and the CPLL frequency synthesizer are located inside the GTY.

[0088] In another optional embodiment of the present application, the rate adaptation control module further includes: a first clock buffer, a second clock buffer, and a third clock buffer;

[0089] The second register is provided with a user-configured frequency division interface. By configuring the user-configured frequency division interface to 32-frequency division, a 32-frequency division clock signal is obtained, and the 32-frequency division clock signal is stored in the first clock buffer to obtain a 32-frequency division clock signal output to the PCS layer encoding and decoding module. After turning off one of the 32-frequency division clock signals every 32 cycles and storing it in the second clock buffer, a 33-frequency division clock signal output to the MAC layer encoding and decoding module is obtained. After turning off one of the 32-frequency division clock signals every 1 cycle and turning off 2 of them every 32 cycles and storing it in the third clock buffer, a 66-frequency division clock signal output to the PCS layer encoding and decoding module is obtained.

[0090] In the embodiment of the present application, the adaptation between the rate of the Ethernet test device and the logic to be tested of the ASIC DUT is mainly completed through two steps: rate adaptation and frequency offset adaptation. The multi-rate Ethernet interface of the FPGA is used to complete the adaptation of multiple rate switching of the ASIC DUT.

[0091] During the rate adaptation process, in an optional embodiment of the present application, after the logic to be tested of the ASIC DUT is overall downscaled by 10 times, the service logic clock is 50 MHz, and the highest frequency of the FPGA multi-rate Ethernet interface logic is 83.0125 MHz. The timing is relatively easy to converge. Therefore, a two-step rate adaptation method is adopted in this embodiment:

[0092] The first step is the transmission rate adaptation. Solve the line rate adaptation from Base-x to Base-R (1.25 Gbps (1G) <-> 1.03125 Gbps (after 10G downscaling)), 3.125 Gbps (2.5G) <-> 2.578125 Gbps (after 25G downscaling)), and the rate adaptation from Base-R to Base-R RS-FEC (10.3125 Gbps (10G) <-> 10.625 Gpbs (after 100G RS-FEC 544 downscaling), etc.); Although the line rate of 1G / 2.5G is higher than the line rate after 10G / 25G downscaling, because 1G / 2.5G uses 8b / 10b encoding and its encoding efficiency is not as high as that of 64b / 66b encoding of 10G / 25G, the overall rate can be matched.

[0093] The second step: frequency offset adaptation. In the Ethernet protocol, it is required to be able to handle jitter of plus or minus 100 ppm. The rate adaptation module of the downscaling bridge can accurately match the rate to ensure that there is no disconnection for a positive 100 ppm frequency offset and no packet loss for a negative 100 ppm.

[0094] Through the above two steps, the FPGA speed reduction bridge can transparently transmit the traffic of all Ethernet test devices without loss, so that various stress tests can be performed on the ASIC DUT logic to be tested after equal ratio frequency reduction. At the same time, the problems that the related technical solutions cannot test the PCS layer encoding and cannot perform lossless service tests are solved. The constructed scenario can effectively simulate various extreme situations of the digital logic part of the ASIC actual scenario, especially the Ethernet interface part, and truly scales and simulates the duty cycle of the clock generated by the ASIC.

[0095] In essence, the transmission rate adaptation is to achieve the matching of the asynchronous FIFO read and write clocks in the rate adaptation module with the clocks of the MAC layer encoding and decoding module and the PCS layer encoding and decoding module. Taking the 1G <-> 10G rate adaptation as an example, the recovered clock of the 1G Ethernet interface is 125MHz. The clock signals required by the 10G MAC layer, PCS layer, and PMA layer are 312.5MHz, 156.25MHz, and 322.265625MHz respectively. After 10-fold frequency reduction, they are 31.25MHz, 15.625MHz, and 32.265625MHz respectively. Obviously, the 32.2265625MHz cannot be simply obtained by dividing the recovered 125MHz clock. At the same time, it is not recommended in the FPGA to cascade the PLL (phase-locked loop) with the recovered clock of the Serdes (deserializer) for frequency division, because the recovered clock jitter is large, and exceeding the threshold of the PLL will cause the PLL to not lock, which will introduce additional unstable factors and increase the difficulty of problem location. Therefore, in the optional embodiment of this application, the rate adaptation control module as shown in Figure 5 is adopted to obtain the line rate 32 / 33 / 66 frequency division clocks required by the protocol adaptation module and the rate adaptation module.

[0096] The rate adaptation control module supports two modes of rate adaptation: the hardware automatic configuration mode and the software and hardware combined configuration mode.

[0097] In the hardware automatic configuration mode, the ROM serving as the second memory stores multiple configured rates, such as the deceleration Serdes configuration parameters for four configured rates of 10G / 25G / 50G / 100G. The multiple configured rates held by this second memory can correspond one-to-one with the multiple configured rates stored in the FPGA multi-rate Ethernet interface, and have a set adaptation relationship. For example, the four configured rates of 10G / 25G / 50G / 100G are respectively adapted to the four configured rates stored in the FPGA multi-rate Ethernet interface. That is to say, the Serdes configuration parameters of the multiple configured rates stored in the second memory of the rate adaptation controller are the deceleration rate Serdes configuration parameters of the multiple configured rates stored in the second memory of the FPGA multi-rate Ethernet interface.

[0098] During adaptation, after the external software issues a speed change command through the APB (Advanced Peripheral Bus) software control port, the DRP dynamic configuration module reads the Serdes configuration parameters corresponding to the rate from the second memory ROM according to the exemplary process as shown in Figure 6 and writes them into the second register Serdes through the Serdes DRP interface. After the configuration is completed, the second register Serdes is reset.

[0099] See Figure 6 As shown, exemplarily, first, if the CPLL clock lock signal or the QPLL clock lock signal is detected, it is determined whether a configuration signal for rate switching is received; if so, the corresponding ROM address is selected according to the configured rate specified in the configuration signal, and the corresponding GTY (FPGA Serdes) address is read from the selected ROM address; after waiting for the DRP interface to be ready, the VCO frequency of the second QPLL frequency synthesizer, and the source clock and division ratio of the CPLL frequency synthesizer are configured; after waiting for the DRP interface to be ready again, it is determined whether the second QPLL frequency synthesizer or the CPLL frequency synthesizer is configured completely. If it is completed, the GTY is reset. If not, it returns to wait for the next configuration.

[0100] In the software and hardware combined configuration mode, since the second memory ROM only stores a limited number of various Serdes configuration parameters, for other speed reduction rates such as 40G / 200G / 400G / 800G, etc., the external software can drive the DRP dynamic configuration module through the APB software control interface to write the corresponding serdes configuration parameter process into Serdes through the DRP interface.

[0101] Due to the limitation of the structure of the second register Serdes of the FPGA, there is only 1 user-configurable frequency division interface open to users. Direct frequency division by the counter or cascading PLLs is not very friendly to the implementation of the FPGA. In order to obtain the three clocks of line rate 32 / 33 / 66 frequency division required by the protocol adaptation module through the only user-configurable frequency division interface, the user-configurable frequency division interface left by the second register Serdes of the FPGA is configured as 32 frequency division, and then through this 32-frequency division clock, the 33-frequency division and 66-frequency division clocks are obtained using the gating clock equivalent frequency division method, as shown in Figure 7 below.

[0102] 32-frequency division clock: The Serdes 32-frequency division clock is directly obtained after passing through the first clock buffer BUFGCE;

[0103] 33-frequency division clock: After every 32 cycles of the Serdes 32-frequency division clock, one cycle of the clock is turned off to obtain an equivalent line rate 33-frequency division clock;

[0104] 66 - divided clock: After every 1 cycle of the Serdes 32 - divided clock, the clock is turned off for 1 cycle, and after every 32 cycles, the clock is turned off for 2 cycles, resulting in an equivalent line rate 66 - divided clock.

[0105] Frequency offset adaptation mainly aims to match the traffic adaptation caused by the frequency offset between the RX recovered clock in the receive direction of the FPGA multi - rate Ethernet interface and the local divided clock in the transmit direction from the FPGA speed - down bridge to the ASIC DUT. Frequency offset refers to the offset of the crystal oscillator relative to the nominal center frequency. The 802.3 protocol allows a frequency offset of within ±100 ppm between connected partners. As Figure 8 shown, exemplarily, when the RX recovered clock in the receive direction has a positive frequency offset and the local divided clock has a negative frequency offset, the data traffic in the receive direction per unit time is greater than the data stream that can be transmitted in the transmit direction, which will cause the water level of the asynchronous FIFO in the rate adaptation module to rise. After accumulating for a period of time, it will lead to the problem that the asynchronous FIFO is full and Ethernet packet data is discarded.

[0106] When the recovered clock in the receive direction has a negative frequency offset and the local divided clock has a positive frequency offset, per unit time, the data traffic in the receive direction is less than the data stream that can be transmitted in the transmit direction, which will cause the water level of the asynchronous FIFO in the rate adaptation module to drop. After accumulating for a period of time, it will lead to the asynchronous FIFO being emptied. If the asynchronous FIFO is emptied exactly during the transmission of an Ethernet packet data, it will cause the packet to be interrupted, and further cause the Ethernet packet data received by the ASIC DUT to be incorrect.

[0107] To solve the above two problems, in an optional embodiment of the present application, a fine - tuned inter - packet gap (IPG) method of combining software and hardware coarse - tuning and hardware adaptive adjustment can be used to adapt to the frequency offset.

[0108] In an optional embodiment of the present application, in the software - hardware combined coarse - tuning method, the following can be set for the asynchronous FIFO in the rate adaptation module: the full - alarm water - level threshold, the empty - alarm water - level threshold, and the read - start water - level threshold. When the data volume in the asynchronous FIFO is greater than or equal to the full - alarm water - level threshold, it triggers the external software to re - configure the configuration value of the minimum average frame interval of the MAC - layer encoding and decoding module to make it smaller; when the data volume in the asynchronous FIFO is less than or equal to the empty - alarm water - level threshold, it triggers the external software to re - configure the read - start water - level threshold to make it larger. In some embodiments, when the water level of the asynchronous FIFO reaches the read - start water - level threshold, the read enable of the asynchronous FIFO is set to valid, thus starting the process of reading data out from the FIFO.

[0109] In some alternative embodiments, when the FIFO issues a nearly full waterline alarm, that is, when the amount of data in the asynchronous FIFO is greater than or equal to the nearly full alarm waterline threshold, an interrupt can be triggered to report to the external software. The external software reconfigures the minimum average IPG value of the MAC encoding and decoding module, for example, subtracts 1 from it, and clears the interrupt. If the FIFO nearly full waterline alarm trigger interrupt is triggered again, the external software can continue to reconfigure the minimum average IPG value of the MAC encoding and decoding module, such as subtracting 1. In this way, the problem that when the RX recovery clock frequency offset in the receiving direction is a positive frequency offset and the local divided clock frequency offset is a negative frequency offset, the data traffic in the receiving direction per unit time is greater than the data stream that can be sent in the sending direction, resulting in the asynchronous FIFO being full and discarding Ethernet packet data can be solved.

[0110] In some other alternative embodiments, when the FIFO issues a nearly empty waterline alarm, that is, when the amount of data in the asynchronous FIFO is less than or equal to the nearly empty alarm waterline threshold, an interrupt is triggered to report to the external software. The external software configures the read start waterline threshold of the asynchronous FIFO to be incremented by 1 and clears the interrupt. If the FIFO nearly empty waterline alarm interrupt is triggered again, the external software continues to increment the read start waterline threshold of the asynchronous FIFO by 1. In this way, the problem that when the RX recovery clock frequency offset in the receiving direction is a negative frequency offset and the local divided clock frequency offset is a positive frequency offset, the data traffic in the receiving direction per unit time is less than the data stream that can be sent in the sending direction, resulting in the Ethernet packet data received by the ASIC DUT being incorrect can be solved.

[0111] In the alternative embodiments of the present application, in the hardware adaptive fine-tuning mode, the following can be set for the asynchronous FIFO in the rate adaptation module: nearly full alarm waterline threshold, release nearly full alarm waterline threshold, nearly empty alarm waterline threshold, release nearly empty alarm waterline threshold, and read start waterline threshold;

[0112] When the amount of data in the asynchronous FIFO is greater than or equal to the nearly full alarm waterline threshold, if the rate adaptation module is configured in the adaptive inter-frame interval adjustment mode, the MAC layer encoding and decoding module is triggered to periodically delete the inter-frame interval of the Ethernet packet data until the amount of data in the asynchronous FIFO is less than or equal to the release nearly full alarm waterline threshold; if the cumulative number of times of the nearly full alarm waterline threshold is greater than or equal to the first set threshold, the configured value of the minimum average frame interval of the MAC layer encoding and decoding module is decreased;

[0113] When the amount of data in the asynchronous FIFO is less than or equal to the empty alarm watermark threshold, if the rate adaptation module is configured as the adaptive inter-frame interval adjustment mode, the MAC layer codec module is triggered to periodically insert inter-frame intervals into the Ethernet message data until the amount of data in the asynchronous FIFO is greater than or equal to the release of the empty alarm watermark threshold; if the cumulative number of times the empty alarm watermark threshold is greater than or equal to the second set threshold, the read start watermark threshold is raised.

[0114] In some embodiments, when the asynchronous FIFO of the rate adaptation module reaches or is lower than the empty alarm waterline, an empty waterline alarm should be generated. The rate adaptation module decides whether to perform adaptive IPG (inter-frame gap) adjustment according to the pre-configuration of the external software. If adaptive IPG adjustment is performed, the MAC layer codec module periodically inserts IPG into the Ethernet message data based on the DIC (Deficit IDLE Count) algorithm until the FIFO waterline is greater than or equal to the threshold value of the empty alarm waterline. The MAC layer codec module stops inserting the IPG value and continues to send the IPG according to the DIC algorithm. In addition, the number of empty alarms can also be counted. When the number of this count is greater than the first set threshold, the read start waterline of the asynchronous FIFO of the rate adaptation module should be increased. In this way, when the RX recovery clock frequency deviation in the receiving direction is positive and the local frequency division clock frequency deviation is negative, the data flow in the receiving direction per unit time is greater than the data flow that can be sent in the sending direction, which causes the asynchronous FIFO to be full and discard the Ethernet message data.

[0115] In other embodiments, when the asynchronous FIFO of the rate adaptation module reaches or exceeds the full alarm waterline, a FIFO full alarm is generated, the rate adaptation module decides whether to perform adaptive IPG adjustment according to the pre-configuration of the external software, and the MAC layer codec module periodically deletes the IPG of the Ethernet message data based on the DIC algorithm until the FIFO waterline is less than or equal to the value of releasing the full alarm waterline. In addition, the number of full waterline alarms can be counted, and when the number of this count is greater than the second set threshold, the configuration value of the minimum average frame interval is reduced. Among them, when executing periodic deletion of IPG, the average minimum average frame interval requirements of the 802.3 receiving end should be met. This method can solve the problem that when the RX recovery clock frequency deviation in the receiving direction is negative and the local frequency division clock frequency deviation is positive, the data flow in the receiving direction per unit time is less than the data flow that can be sent in the sending direction, resulting in errors in the Ethernet message data received by the ASIC DUT.

[0116] The above-mentioned software and hardware combined coarse adjustment method and hardware adaptive fine adjustment method can cooperate with each other and complement each other to jointly complete frequency deviation adaptation. Figure 9, exemplarily, the following thresholds are ordered from large to small as follows: the almost full alarm waterline threshold, the release of the almost full alarm waterline threshold, the read start waterline threshold, the release of the almost empty alarm waterline threshold, and the almost empty alarm waterline threshold.

[0117] Accordingly, exemplarily, the present application provides a rate adaptation method in a second aspect, which is implemented by using the FPGA speed reduction bridge proposed in the first aspect, and the method includes:

[0118] The FPGA multi-rate Ethernet interface is configured to one of a plurality of different configuration rates;

[0119] The rate adaptation control module is used to adapt the configuration rate configured by the FPGA multi-rate Ethernet interface, and output the clock signal used by the MAC layer codec module and the PCS layer codec module; the configuration rate adapted by the rate adaptation control module has a preset adaptation relationship with the configuration rate configured by the FPGA multi-rate Ethernet interface.

[0120] In an optional embodiment of the present application, the FPGA multi-rate Ethernet interface is configured to one of a plurality of different configuration rates, including:

[0121] The first DRP dynamic configuration module of the rate adaptation control module receives a first configuration signal received from external software through a software control interface;

[0122] Configure the first QPLL frequency synthesizer of the rate adaptation control module according to the configuration parameters corresponding to the configuration rate specified by the first configuration signal;

[0123] If the first QPLL frequency synthesizer is configured, the configuration parameters corresponding to the configuration rate specified by the first configuration signal are written into the first register of the rate adaptation control module; the configuration rate specified by the first configuration signal is one of the configuration rates corresponding to the configuration parameters stored in the first memory of the rate adaptation control module or the configuration rate specified by the external software.

[0124] In an optional embodiment of the present application, the rate adaptation control module is used to adapt the configured rate of the FPGA multi-rate Ethernet interface, and output the clock signal used by the MAC layer codec module and the PCS layer codec module, including:

[0125] The second DRP dynamic configuration module of the rate adaptation control module receives a second configuration signal from external software through a software control interface;

[0126] Configure the second QPLL frequency synthesizer and the CPLL frequency synthesizer of the rate adaptation control module according to the configuration parameters corresponding to the configuration rate specified by the second configuration signal;

[0127] If the second QPLL frequency synthesizer and the CPLL frequency synthesizer are configured and completed, write the configuration parameters corresponding to the configuration rate specified by the second configuration signal into the second register of the rate adaptation control module; the configuration rate specified by the second configuration signal is one of the configuration rates corresponding to the configuration parameters stored in the second memory of the rate adaptation control module or the configuration rate specified by the external software.

[0128] The configuration rate specified by the second configuration signal has a preset adaptation relationship with the configuration rate specified by the first configuration signal for configuring the multi-rate Ethernet interface of the FPGA.

[0129] In an alternative embodiment of the present application, the method further includes:

[0130] Configure the user configuration frequency division interface of the second register to be divided by 32 to obtain a 32-divided clock signal;

[0131] Store the 32-divided clock signal in the first clock buffer to obtain a 32-divided clock signal output to the PCS layer encoding and decoding module;

[0132] After turning off one of the 32-divided clock signals every 32 cycles and storing it in the second clock buffer, obtain a 33-divided clock signal output to the MAC layer encoding and decoding module;

[0133] After turning off one of the 32-divided clock signals every 1 cycle and turning off 2 of them every 32 cycles and storing it in the third clock buffer, obtain a 66-divided clock signal output to the PCS layer encoding and decoding module.

[0134] In an alternative embodiment of the present application, the method further includes:

[0135] Set the full-alarm waterline threshold, empty-alarm waterline threshold, and read start waterline threshold for the asynchronous FIFO in the rate adaptation module;

[0136] If it is detected that the data volume in the asynchronous FIFO is greater than or equal to the full-alarm waterline threshold, trigger the external software to reconfigure the configured value of the minimum average frame interval of the MAC layer encoding and decoding module to make it decrease;

[0137] If it is detected that the data volume in the asynchronous FIFO is less than or equal to the empty-alarm waterline threshold, trigger the external software to reconfigure the read start waterline threshold to make it increase.

[0138] In an alternative embodiment of the present application, the method further includes:

[0139] Setting a nearly full alarm watermark threshold, releasing a nearly full alarm watermark threshold, a nearly empty alarm watermark threshold, releasing a nearly empty alarm watermark threshold and a read start watermark threshold for the asynchronous FIFO in the rate adaptation module;

[0140] If it is detected that the amount of data in the asynchronous FIFO is greater than or equal to the almost-full alarm watermark threshold, and the rate adaptation module is configured in an adaptive interframe interval adjustment mode, the MAC layer codec module is triggered to periodically delete the interframe interval of the Ethernet message data until the amount of data in the asynchronous FIFO is less than or equal to the release of the almost-full alarm watermark threshold;

[0141] If the accumulated number of times the alarm waterline threshold is about to be full is greater than or equal to the first set threshold, reducing the configuration value of the minimum average frame interval of the MAC layer encoding and decoding module;

[0142] If it is detected that the amount of data in the asynchronous FIFO is less than or equal to the empty alarm watermark threshold, and the rate adaptation module is configured in the adaptive interframe interval adjustment mode, the MAC layer codec module is triggered to periodically insert an interframe interval into the Ethernet message data until the amount of data in the asynchronous FIFO is greater than or equal to the release empty alarm watermark threshold;

[0143] If the accumulated number of times the empty alarm watermark threshold is reached is greater than or equal to the second set threshold, the read start watermark threshold is increased.

[0144] The specific implementation details of the above rate adaptation method can be found in the description of the embodiment of the first aspect, and will not be repeated here.

[0145] It is understood that the circuit structures, names and parameters described in the above embodiments are only examples. Those skilled in the art can also easily combine and adjust the structural features of the above embodiments according to the use requirements, and should not limit the concept of the present application to the specific details of the above examples.

[0146] The present application also provides an electronic device, including a processor and a memory. The memory stores multiple instructions, and the processor is configured to read the instructions and execute any of the methods in the foregoing first aspect. The processor and the memory may be connected through a bus or other means. Taking the connection through a bus as an example, the processor may be a Central Processing Unit (CPU). The processor may also be other general-purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field-Programmable Gate Arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc., or a combination of the above types of chips.

[0147] As a non-transitory computer-readable storage medium, the memory can be used to store non-transitory software programs, non-transitory computer-executable programs, and modules, such as the program instructions / modules corresponding to the methods in the embodiments of the present application. By running the non-transitory software programs, instructions, and modules stored in the memory, the processor can execute various functional applications and data processing of the processor, that is, implement the methods in the foregoing method embodiments.

[0148] The memory may include a program storage area and a data storage area. Among them, the program storage area can store an operating system and application programs required for at least one function; the data storage area can store data created by the processor, etc. In addition, the memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid-state storage devices. In some embodiments, the memory may optionally include a memory remotely disposed relative to the processor, and these remote memories can be connected to the processor through a network. Examples of the above networks include, but are not limited to, the Internet, enterprise intranets, local area networks, mobile communication networks, and combinations thereof.

[0149] Although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. An FPGA speed reduction bridge, characterized in that, include: FPGA multi-rate Ethernet interface, rate adaptation module, rate adaptation control module and protocol adaptation module; wherein, The FPGA multi-rate Ethernet interface can be configured to one of a plurality of different configuration rates, and is connected to an external Ethernet device and performs data communication with the Ethernet device at the configured configuration rate; The rate adaptation module is connected to the FPGA multi-rate Ethernet interface, and includes an asynchronous FIFO for caching Ethernet message data received by the FPGA multi-rate Ethernet interface from the Ethernet device; The protocol adaptation module is connected to the rate adaptation module, and includes a MAC layer encoding and decoding module and a PCS layer encoding and decoding module, wherein the MAC layer encoding and decoding module is used to perform MAC layer encoding on the Ethernet message data stored in the asynchronous FIFO, and the PCS layer encoding and decoding module is used to perform PCS layer encoding on the encoded data output by the MAC layer encoding and decoding module; The rate adaptation control module is used to adapt the configuration rate of the FPGA multi-rate Ethernet interface, and output the clock signal used by the MAC layer codec module and the PCS layer codec module based on the adapted configuration rate; Among them, when the amount of data in the asynchronous FIFO in the rate adaptation module is greater than the almost full alarm waterline threshold, the rate adaptation module decides whether to perform adaptive inter-frame interval adjustment based on the pre-configuration of the external software. If adaptive inter-frame interval adjustment is performed, the MAC layer codec module periodically deletes the inter-frame interval of the Ethernet message data until the amount of data in the FIFO is less than or equal to the almost full alarm waterline threshold.

2. The FPGA speed reduction bridge according to claim 1, wherein The FPGA multi-rate Ethernet interface includes a first DRP dynamic configuration module, a first memory, a first QPLL frequency synthesizer and a first register; the first memory is used to store configuration parameters corresponding to one or more configuration rates, the first DRP dynamic configuration module receives a first configuration signal from external software through a software control interface, and configures the first QPLL frequency synthesizer according to the configuration parameters corresponding to the configuration rate specified by the first configuration signal. After the first QPLL frequency synthesizer is configured, the configuration parameters corresponding to the configuration rate specified by the first configuration signal are written into the first register; the configuration rate specified by the first configuration signal is one of the configuration rates corresponding to the configuration parameters stored in the first memory or the configuration rate specified by the external software.

3. The FPGA speed reduction bridge according to claim 1, characterized in that, The rate adaptation control module includes: a second DRP dynamic configuration module, a second memory, a second QPLL frequency synthesizer, a CPLL frequency synthesizer and a second register; the second memory is used to store configuration parameters corresponding to one or more configuration rates, the second DRP dynamic configuration module receives a second configuration signal from external software through a software control interface, and configures the second QPLL frequency synthesizer and the CPLL frequency synthesizer according to the configuration parameters corresponding to the configuration rate specified by the second configuration signal. After the second QPLL frequency synthesizer and the CPLL frequency synthesizer are configured, the configuration parameters corresponding to the configuration rate specified by the second configuration signal are written into the second register; the configuration rate specified by the second configuration signal is one of the configuration rates corresponding to the configuration parameters stored in the second memory or the configuration rate specified by the external software.

4. The FPGA speed reduction bridge according to claim 3, characterized in that, The rate adaptation control module further includes: a first clock buffer, a second clock buffer and a third clock buffer; The second register is provided with a user-configured frequency division interface. By configuring the user-configured frequency division interface to 32-division, a 32-division clock signal is obtained, and the 32-division clock signal is stored in the first clock buffer to obtain a 32-division clock signal output to the PCS layer codec module. The 32-division clock signal is turned off once every 32 cycles and then stored in the second clock buffer to obtain a 33-division clock signal output to the MAC layer codec module. The 32-division clock signal is turned off once every 1 cycle, and two are turned off every 32 cycles and then stored in the third clock buffer to obtain a 66-division clock signal output to the PCS layer codec module.

5. The FPGA speed reduction bridge according to claim 1, wherein The asynchronous FIFO in the rate adaptation module is provided with: a nearly full alarm watermark threshold, an almost empty alarm watermark threshold and a read start watermark threshold. When the amount of data in the asynchronous FIFO is greater than or equal to the nearly full alarm watermark threshold, the external software is triggered to reconfigure the configuration value of the minimum average frame interval of the MAC layer codec module to reduce it; When the amount of data in the asynchronous FIFO is less than or equal to the empty alarm watermark threshold, external software is triggered to reconfigure the read start watermark threshold to increase it.

6. The FPGA speed reduction bridge according to claim 1, characterized in that The asynchronous FIFO in the rate adaptation module is provided with: a threshold value for a nearly full alarm watermark, a threshold value for releasing a nearly full alarm watermark, a threshold value for an empty alarm watermark, a threshold value for releasing an nearly empty alarm watermark, and a read start watermark threshold; When the amount of data in the asynchronous FIFO is greater than or equal to the almost-full alarm watermark threshold, if the rate adaptation module is configured in an adaptive interframe interval adjustment mode, the MAC layer codec module is triggered to periodically delete the interframe interval of the Ethernet message data until the amount of data in the asynchronous FIFO is less than or equal to the release of the almost-full alarm watermark threshold; If the accumulated number of times the alarm waterline threshold is about to be full is greater than or equal to the first set threshold, reducing the configuration value of the minimum average frame interval of the MAC layer encoding and decoding module; When the amount of data in the asynchronous FIFO is less than or equal to the empty alarm watermark threshold, if the rate adaptation module is configured as an adaptive interframe interval adjustment mode, the MAC layer codec module is triggered to periodically insert an interframe interval into the Ethernet message data until the amount of data in the asynchronous FIFO is greater than or equal to the release empty alarm watermark threshold; If the accumulated number of times the empty alarm watermark threshold is reached is greater than or equal to the second set threshold, the read start watermark threshold is increased.

7. The FPGA speed reduction bridge according to claim 6, wherein The following thresholds are sorted from large to small as follows: almost full alarm watermark threshold, almost full alarm watermark threshold, read start watermark threshold, almost empty alarm watermark threshold, almost empty alarm watermark threshold.

8. A rate adaptation method, characterized in that, The method is implemented using the FPGA speed reduction bridge according to any one of claims 1 to 7, and the method comprises: The FPGA multi-rate Ethernet interface is configured to one of a plurality of different configuration rates; The rate adaptation control module is used to adapt the configuration rate configured by the FPGA multi-rate Ethernet interface, and output the clock signal used by the MAC layer codec module and the PCS layer codec module; the configuration rate adapted by the rate adaptation control module has a preset adaptation relationship with the configuration rate configured by the FPGA multi-rate Ethernet interface.

9. The rate adaptation method according to claim 8, wherein The FPGA Multi-Rate Ethernet interface is configured to one of several different configuration rates, including: The first DRP dynamic configuration module of the rate adaptation control module receives a first configuration signal received from external software through a software control interface; Configure the first QPLL frequency synthesizer of the rate adaptation control module according to the configuration parameters corresponding to the configuration rate specified by the first configuration signal; If the first QPLL frequency synthesizer is configured, the configuration parameters corresponding to the configuration rate specified by the first configuration signal are written into the first register of the rate adaptation control module; the configuration rate specified by the first configuration signal is one of the configuration rates corresponding to the configuration parameters stored in the first memory of the rate adaptation control module or the configuration rate specified by the external software.

10. The rate adaptation method according to claim 8, wherein Adapting the configured rate of the FPGA multi-rate Ethernet interface using the rate adaptation control module, and outputting the clock signal used by the MAC layer codec module and the PCS layer codec module, including: The second DRP dynamic configuration module of the rate adaptation control module receives a second configuration signal from external software through a software control interface; Configure the second QPLL frequency synthesizer and the CPLL frequency synthesizer of the rate adaptation control module according to the configuration parameters corresponding to the configuration rate specified by the second configuration signal; If the second QPLL frequency synthesizer and CPLL frequency synthesizer are configured, the configuration parameters corresponding to the configuration rate specified by the second configuration signal are written into the second register of the rate adaptation control module; the configuration rate specified by the second configuration signal is one of the configuration rates corresponding to the configuration parameters stored in the second memory of the rate adaptation control module or the configuration rate specified by the external software.

11. The rate adaptation method according to claim 10, characterized in that, The method further comprises: The user-configured frequency division interface of the second register is configured to be divided by 32, so as to obtain a divided-by-32 clock signal; The 32-frequency clock signal is stored in a first clock buffer to obtain a 32-frequency clock signal output to the PCS layer encoding and decoding module; The 32-frequency divided clock signal is turned off once every 32 cycles and then stored in a second clock buffer to obtain a 33-frequency divided clock signal output to the MAC layer encoding and decoding module; The 32-frequency-divided clock signal is turned off by one per cycle, and by two per 32 cycles, and then stored in a third clock buffer to obtain a 66-frequency-divided clock signal output to the PCS layer encoding and decoding module.

12. The rate adaptation method according to claim 8, wherein The method further comprises: Setting a nearly full alarm watermark threshold, a nearly empty alarm watermark threshold and a read start watermark threshold for the asynchronous FIFO in the rate adaptation module; If it is detected that the amount of data in the asynchronous FIFO is greater than or equal to the full alarm waterline threshold, trigger the external software to reconfigure the configuration value of the minimum average frame interval of the MAC layer codec module to reduce it; If it is detected that the amount of data in the asynchronous FIFO is less than or equal to the empty alarm watermark threshold, external software is triggered to reconfigure the read start watermark threshold to increase it.

13. The rate adaptation method according to claim 8, characterized in that The method further comprises: Setting a nearly full alarm watermark threshold, a release nearly full alarm watermark threshold, a nearly empty alarm watermark threshold, a release nearly empty alarm watermark threshold and a read start watermark threshold for the asynchronous FIFO in the rate adaptation module; If it is detected that the amount of data in the asynchronous FIFO is greater than or equal to the almost-full alarm watermark threshold, and the rate adaptation module is configured in an adaptive interframe interval adjustment mode, the MAC layer codec module is triggered to periodically delete the interframe interval of the Ethernet message data until the amount of data in the asynchronous FIFO is less than or equal to the release of the almost-full alarm watermark threshold; If the accumulated number of times the alarm waterline threshold is about to be full is greater than or equal to the first set threshold, reducing the configuration value of the minimum average frame interval of the MAC layer encoding and decoding module; If it is detected that the amount of data in the asynchronous FIFO is less than or equal to the empty alarm watermark threshold, and the rate adaptation module is configured in the adaptive interframe interval adjustment mode, the MAC layer codec module is triggered to periodically insert an interframe interval into the Ethernet message data until the amount of data in the asynchronous FIFO is greater than or equal to the release empty alarm watermark threshold; If the accumulated number of times the empty alarm watermark threshold is reached is greater than or equal to the second set threshold, the read start watermark threshold is increased.

14. An electronic device, characterized in that, It comprises a processor and a memory, wherein the memory stores a plurality of instructions, and the processor is used to read the instructions and execute the rate adaptation method as described in any one of claims 8 to 13.

15. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a plurality of instructions, and the plurality of instructions can be read by a processor and executed by the rate adaptation method as described in any one of claims 8-13.

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