Clock Alignment Methods

Abstract

The present invention relates to a clock alignment method, comprising: a first driver chip determines a count update value of the first driver chip according to a current count value of its pulse count signal and a preset fixed delay time, and transmits the count update value of the first driver chip to a second driver chip; for each of the second driver chip to the second-to-last driver chip, the driver chip receives the count update value transmitted by the previous driver chip, and updates the current count value of the pulse count signal of the driver chip to the count update value of the previous driver chip; then determines the count update value of the driver chip according to the current count value of the driver chip and the fixed delay time, and transmits the count update value of the driver chip to the next driver chip; the last driver chip receives the count update value of the previous driver chip, and updates the current count value of its own pulse count signal to the count update value of the previous driver chip.

Description

Technical Field

[0001] The present invention relates to the technical field of LED driving, and more particularly to a clock alignment method applied to an LED driving system. Background Art

[0002] LED driver chips are a type of driver chips that provide stable working conditions and protection for LED lamps, and also control the brightness of LED lamps. Figure 1 The figure shows a typical LED driver chip topology, in which VLED is the external LED power supply voltage, and the LED driver chip provides stable current to several LED light strings through several current sinks inside, and controls the switching of transistors (MOS tubes) through pulse width modulation (PWM) signals; thus, the LED lamp can be dimmed by controlling the current size of the current sink or the duty cycle of the PWM signal.

[0003] In LED light board applications, multiple driver chips are usually cascaded, and each driver chip independently controls multiple strings of LED lights. Figure 2 The figure shows a typical topological structure of an LED driving system, in which the first driver chip and the last driver chip are also connected to a microprocessor (MCU, Microprogrammed Control Unit) respectively. The MCU is located at the first level of the cascade transmission chain, and configures working parameters and LED brightness information for all driver chips in the cascade transmission chain through a communication bus (BUS). The communication bus includes a clock line and a data line. The communication bus input of the first driver chip comes from the MCU, and the communication bus input of other driver chips comes from the communication bus output of the previous driver chip.

[0004] The generation principle of the PWM signal of the driver chip for controlling the brightness of the LED lamp is as follows: the clock transmitted from the previous driver chip is used as the working clock to generate a pulse counting signal, which starts counting from 0, and is reset to zero and restarted after counting to the configured maximum value (for example, 127). The maximum value plus one is the period of the pulse counting signal; then the pulse counting signal is compared with the brightness value received by the driver chip (transmitted to each driver chip by the MCU through the BUS). When it is less than the brightness value, the PWM signal is high, and when it is greater than the brightness value, the PWM signal is low. The pulse counting signals of all driver chips start counting at the same time after the LED lamp board is powered on to ensure the synchronization of the brightness of all LED lamps on the lamp board.

[0005] Since the clock lines of all driver chips except the first one are provided by the previous driver chip, if the clock signal of any driver chip is temporarily interrupted or glitches occur due to disturbance during the communication process, it will be transmitted to all subsequent driver chips in sequence, causing the clocks of all subsequent driver chips to be misaligned with the previous driver chips that have not experienced clock signal disturbance. This clock misalignment causes the pulse counting signals of different driver chips to be misaligned, which causes the brightness control of the controlled LED lights to be misaligned, making the brightness control of LEDs in different areas of the LED light board inconsistent, affecting the display effect. Summary of the invention

[0006] The object of the present invention is to provide a clock alignment method to solve the problem of pulse counting signal misalignment caused by clock misalignment of each driver chip in an LED driver system.

[0007] Based on the above purpose, the present invention provides a clock alignment method, which is applied to an LED driving system, wherein the LED driving system includes a plurality of driver chips cascaded in sequence, each driver chip is electrically connected to one or more LED lamps, and each driver chip generates a pulse width modulation signal for controlling the brightness of the LED lamp connected to the driver chip through its own periodic pulse counting signal. The method includes:

[0008] The first driver chip determines a count update value of the first driver chip according to a current count value of a pulse count signal of the first driver chip and a preset fixed delay time, and transmits the count update value of the first driver chip to the second driver chip;

[0009] For each of the second driver chip to the second-to-last driver chip, the driver chip receives the count update value transmitted by the previous driver chip, and updates the current count value of the pulse count signal of the driver chip to the count update value of the previous driver chip; then determines the count update value of the driver chip according to the current count value of the driver chip and the fixed delay time, and transmits the count update value of the driver chip to the next driver chip;

[0010] The last driver chip receives the count update value of the previous driver chip, and updates the current count value of its own pulse count signal to the count update value of the previous driver chip.

[0011] Furthermore, the fixed delay time is the time taken for an upstream driver chip among any two adjacent driver chips to transmit its count update value to a downstream driver chip.

[0012] Furthermore, the LED driving system also includes a microprocessor, which is respectively connected to the first driver chip and the last driver chip, and the microprocessor is used to transmit a command signal to the first driver chip, and the command signal is transmitted along each driver chip in turn, wherein the command signal includes a header, a middle segment and a tail, the header is used to identify the type of the command signal, the middle segment is used to store count value data, and the tail is used to mark the end of the command signal.

[0013] Further, the first driver chip determines a count update value of the first driver chip according to a current count value of a pulse count signal of the first driver chip and a preset fixed delay time, and transmits the count update value of the first driver chip to the second driver chip, specifically including:

[0014] The microprocessor transmits the command signal to the first driver chip;

[0015] The first driving chip receives the command signal;

[0016] The first driver chip determines a count update value of the first driver chip according to a current count value of a pulse count signal of the first driver chip and the fixed delay time;

[0017] The first driver chip writes the count update value of the first driver chip into the middle section of the command signal to update the command signal;

[0018] The first driving chip transmits the updated command signal to the second driving chip.

[0019] Further, determining the count update value of the first driver chip according to the current count value of the pulse count signal of the first driver chip and the fixed delay time specifically includes:

[0020] Determine a fixed delay value according to the fixed delay time;

[0021] The count update value of the first driver chip is determined according to the current count value of the pulse count signal of the first driver chip and the fixed delay value.

[0022] Further, determining the count update value of the first driver chip according to the current count value of the pulse count signal of the first driver chip and the fixed delay value specifically includes:

[0023] Adding a current count value of a pulse count signal of the first driver chip to the fixed delay value to obtain an initial update value of the first driver chip;

[0024] Comparing the initial update value of the first driver chip with the period of the pulse counting signal;

[0025] If the initial update value of the first driver chip is smaller than the period of the pulse counting signal, the initial update value of the first driver chip is used as the count update value of the first driver chip;

[0026] If the initial update value is greater than or equal to the period of the pulse counting signal, the difference between the initial update value of the first driver chip and the period of the pulse counting signal is used as the count update value of the first driver chip.

[0027] Furthermore, the driver chip receives the count update value transmitted by the previous driver chip, specifically including:

[0028] The driver chip receives a command signal transmitted by a previous driver chip, and obtains a count update value of the previous driver chip stored in the middle segment of the command signal.

[0029] Further, determining the count update value of the driver chip according to the current count value of the driver chip and the fixed delay time specifically includes:

[0030] Adding the current count value of the pulse count signal of the driver chip to the fixed delay value to obtain an initial update value of the driver chip;

[0031] comparing the initial update value of the driver chip with the period of the pulse counting signal;

[0032] If the initial update value of the driver chip is less than the period of the pulse counting signal, the initial update value of the driver chip is used as the count update value of the driver chip;

[0033] If the initial update value of the driver chip is greater than or equal to the period of the pulse counting signal, the difference between the initial update value of the driver chip and the period of the pulse counting signal is used as the count update value of the driver chip.

[0034] Further, the count update value of the driver chip is transmitted to the next driver chip, specifically including:

[0035] Writing the count update value of the driver chip into the middle section of the command signal to update the command signal;

[0036] The updated command signal is transmitted to the next driver chip.

[0037] Furthermore, the head portion, the middle portion and the tail portion are of the same size.

[0038] The clock alignment method of the present invention is applied to an LED driving system. When the clocks of the driving chips in the transmission chain do not match each other due to a brief interruption of the clock signal or a glitch during the communication process, the pulse counting signals of the driving chips other than the first driving chip can be automatically aligned with the first driving chip, thereby ensuring the consistency of the brightness control of each LED lamp. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 This is a schematic diagram of a typical LED driver chip topology structure;

[0040] Figure 2 It is a schematic diagram of the topological structure of a typical LED driving system;

[0041] Figure 3 is a structural block diagram of an LED driving system according to an embodiment of the present invention;

[0042] Figure 4 is a flowchart of a clock alignment method according to an embodiment of the present invention;

[0043] Figure 5 4 is a structural block diagram of a command signal according to an embodiment of the present invention. DETAILED DESCRIPTION

[0044] The preferred embodiments of the present invention are given below in conjunction with the accompanying drawings and described in detail.

[0045] The embodiment of the present invention provides a clock alignment method, which is applied to an LED driving system, such as Figure 3 As shown, the LED driving system includes a microprocessor 10 and a plurality of driver chips 20 cascaded in sequence, each driver chip 20 is electrically connected to one or more LED lamps 30, each driver chip 20 controls the brightness of the LED lamp 30 connected thereto through a periodic PWM signal, and each driver chip 20 generates a PWM signal by comparing its own pulse counting signal with a preset brightness value.

[0046] like Figure 4 As shown, the clock alignment method includes the following steps:

[0047] S100: The first driver chip determines a count update value of the first driver chip according to a current count value of its pulse count signal and a preset fixed delay time, and transmits the count update value of the first driver chip to the second driver chip.

[0048] Each driver chip has its own pulse counting signal, and each driver chip compares its own pulse counting signal with the preset brightness value. When it is greater than the brightness value, the PWM signal is made low, and when it is less than the brightness value, the PWM signal is made high, thereby generating a periodic PWM signal. The PWM signal is connected to the gate of the transistor and is used to control the on and off of the transistor, thereby controlling the brightness of the LED lamp 30 connected to the driver chip.

[0049] In some embodiments, the fixed delay time is the time taken for an upstream driver chip among any two adjacent driver chips to transmit its count update value to a downstream driver chip.

[0050] In some embodiments, the microprocessor 10 is connected to the first driver chip and the last driver chip respectively, and the microprocessor 10 is used to transmit a command signal 40 to the first driver chip, such as Figure 5 As shown, the command signal 40 may include a header 41 , a middle section 42 and a tail 43 , wherein the header 41 is used to identify the type of the command signal 10 , the middle section 42 is used to store count value data, and the tail 43 is used to mark the end of the command signal 40 .

[0051] In some embodiments, step S100 specifically includes the following steps:

[0052] S110: the microprocessor 10 transmits a command signal 40 to the first driver chip;

[0053] S120: The first driver chip receives the command signal 40;

[0054] S130: The first driver chip determines a count update value of the first driver chip according to a current count value of its pulse count signal and a fixed delay time;

[0055] S140: the first driver chip writes its count update value into the middle segment 42 of the command signal 40 to update the command signal 40;

[0056] S150: The first driver chip transmits the updated command signal to the second driver chip.

[0057] In step S110, the count value data stored in the middle segment 42 of the command signal 40 issued by the microprocessor 10 is 0. After the command signal 40 is transmitted to the first driver chip, the first driver chip can modify it and write its count update value into the middle segment 42. At this time, the count update value of the first driver chip will be stored in the middle segment 42 of the command signal 40. Then, the command signal 40 will be sent by the first driver chip to the second driver chip, thereby realizing the transmission of the count update value through the command signal 40.

[0058] Since each driver chip needs to receive the complete header 41 of the command signal 40 before it can identify the command type and send the command signal 40 to the next driver chip, the command transmission between any two driver chips has a delay time, which is the time taken to transmit the complete header 41. The fixed delay time in step S100 is the time taken to transmit the complete header 41. Assuming that the size of the header 41 is the first byte, the size of the middle segment 42 is the second byte, and the size of the tail 43 is the third byte, then the delay time of the command transmission between any two driver chips is the time taken to transmit the first byte of data, and the fixed delay time is the time taken to transmit the first byte of data.

[0059] In some embodiments, step S130 specifically includes the following steps:

[0060] S131: Determine a fixed delay value according to the fixed delay time;

[0061] S132: Determine a count update value of the first driver chip according to a current count value of the pulse count signal of the first driver chip and a fixed delay value.

[0062] The fixed delay value refers to the bit size that can be transmitted with a fixed delay time. In this embodiment, it is the size of the header 41, that is, the first byte. Exemplarily, the sizes of the header 41, the middle section 42, and the tail 43 of the command signal 40 are all two bytes, and the fixed delay value is the bit size of two bytes, that is, 16.

[0063] In some embodiments, step S132 specifically includes the following steps:

[0064] S132a: Add the current count value of the pulse count signal of the first driver chip to the size of the header to obtain an initial update value of the first driver chip;

[0065] S132b: Compare the initial update value of the first driver chip with the period of the pulse counting signal;

[0066] S132c: if the initial update value of the first driver chip is less than the period of the pulse counting signal, use the initial update value of the first driver chip as the count update value of the first driver chip;

[0067] S132d: If the initial update value is greater than or equal to the period of the pulse counting signal, the difference between the initial update value of the first driver chip and the period of the pulse counting signal is used as the count update value of the first driver chip.

[0068] Taking the fixed delay value of 16 and the period of the pulse counting signal of 128 as an example, if the current count value is 120, then 16+120=136, and the initial update value is 136, which exceeds the period 128. Therefore, the count update value of the first driver chip is 136-128=8; if the current count value is 100, then the initial update value is 16+100=116, which is less than the period 128. Therefore, the count update value of the first driver chip is 116.

[0069] S200: For each of the second driver chip to the last driver chip, the driver chip receives the count update value transmitted by the previous driver chip, and updates the current count value of the pulse counting signal of the driver chip to the count update value of the previous driver chip; then the count update value of the driver chip is determined according to the current count value of the driver chip and the fixed delay time, and the count update value of the driver chip is transmitted to the next driver chip.

[0070] In some embodiments, the driver chip receives the count update value transmitted by the previous driver chip, specifically including:

[0071] The driver chip receives the command signal transmitted by the previous driver chip, and obtains the count update value of the previous driver chip stored in the middle section 42 of the command signal 40 .

[0072] For example, the second driver chip can receive the command signal 40 transmitted by the first driver chip and obtain the count update value of the first driver chip stored in its intermediate segment 42, while the third driver chip receives the command signal 40 to obtain the count update value of the second driver chip, and so on.

[0073] After a driver chip updates its current count value to the count update value of the previous driver chip, it can be made consistent with the count value of the first driver chip.

[0074] In some embodiments, the method for determining the count update value of each of the second driver chip to the penultimate driver chip is the same as that of the first driver chip, which specifically includes:

[0075] Adding a current count value of the pulse count signal of the driver chip to a fixed delay value to obtain an initial update value of the driver chip;

[0076] Comparing the initial update value of the driver chip with the period of the pulse counting signal;

[0077] If the initial update value of the driver chip is less than the period of the pulse counting signal, the initial update value of the driver chip is used as the count update value of the driver chip;

[0078] If the initial update value of the driver chip is greater than or equal to the period of the pulse counting signal, the difference between the initial update value of the driver chip and the period of the pulse counting signal is used as the count update value of the driver chip.

[0079] In some embodiments, transmitting the count update value of the driver chip to the next driver chip specifically includes:

[0080] Writing the count update value of the driver chip into the middle section 42 of the command signal 40 to update the command signal;

[0081] The updated command signal is transmitted to the next driver chip.

[0082] S300: The last driver chip receives the count update value of the previous driver chip, and updates the current count value of its own pulse count signal to the count update value of the previous driver chip.

[0083] After the last driver chip receives the count update value of the previous driver chip (i.e., the penultimate driver chip), it can update the current count value of its own pulse count signal to the count update value of the previous driver chip, so that its current count value will be synchronized to be consistent with the first driver chip. Therefore, after the command signal is transmitted from the first driver chip to the last driver chip, the pulse count signals of each driver chip will be aligned with the first driver chip, so that the brightness control of each LED lamp 30 remains consistent.

[0084] In some embodiments, the microprocessor 10 can send a command signal at regular intervals. After each command signal is transmitted in the transmission chain, the pulse counting signals of each driver chip will be aligned to repair the clock mismatch between the driver chips in the transmission chain caused by a brief interruption of the clock signal or glitches during the communication process.

[0085] In some embodiments, the LED driving system may be a driving system for an LED backlight panel of a liquid crystal display. The microprocessor of the liquid crystal display may periodically send a VSYNC (wait for vertical synchronization) command to the driver chip through a bus to achieve refresh synchronization of the display screen. The VSYNC command may be used as a command signal in the method of the present invention, that is, the count update value of each driver chip may be stored in the middle segment of the VSYNC command. In this way, each time the microprocessor refreshes the synchronous display screen, the clock misalignment fault may be synchronously repaired without the need for the microprocessor to perform additional repair processing and without causing additional communication bandwidth occupancy, thereby reducing the resource usage of the microprocessor.

[0086] The clock alignment method of the embodiment of the present invention is applied to an LED driving system. When the clocks of the driving chips in the transmission chain do not match each other due to a brief interruption of the clock signal or glitches during the communication process, the pulse counting signals of the driving chips other than the first driving chip can be automatically aligned with the first driving chip, thereby ensuring the consistency of the brightness control of each LED lamp 30.

[0087] The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. The above embodiment of the present invention can also be modified in various ways. That is, all simple, equivalent changes and modifications made according to the claims and the description of the present invention fall within the scope of protection of the claims of the present invention. The contents not described in detail in the present invention are all conventional technical contents.

Claims

1. A clock alignment method, characterized in that: Applied to an LED driving system, the LED driving system comprises a plurality of driving chips cascaded in sequence, each driving chip is electrically connected to one or more LED lamps, each driving chip generates a pulse width modulation signal for controlling the brightness of the LED lamp connected to the driving chip through its own periodic pulse counting signal, the method comprises: The first driver chip determines a count update value of the first driver chip according to a current count value of a pulse count signal of the first driver chip and a preset fixed delay time, and transmits the count update value of the first driver chip to the second driver chip; For each of the second driver chip to the second-to-last driver chip, the driver chip receives the count update value transmitted by the previous driver chip, and updates the current count value of the pulse count signal of the driver chip to the count update value of the previous driver chip; then determines the count update value of the driver chip according to the current count value of the driver chip and the fixed delay time, and transmits the count update value of the driver chip to the next driver chip; The last driver chip receives the count update value of the previous driver chip, and updates the current count value of its own pulse count signal to the count update value of the previous driver chip; The fixed delay time is the time taken by an upstream driver chip of any two adjacent driver chips to transmit its count update value to a downstream driver chip.

2. The clock alignment method according to claim 1, characterized in that: The LED driving system also includes a microprocessor, which is connected to the first driving chip and the last driving chip respectively. The microprocessor is used to transmit a command signal to the first driving chip, and the command signal is transmitted along each driving chip in sequence, wherein the command signal includes a header, a middle section and a tail, the header is used to identify the type of the command signal, the middle section is used to store count value data, and the tail is used to mark the end of the command signal.

3. The clock alignment method according to claim 2, characterized in that: The first driver chip determines a count update value of the first driver chip according to a current count value of a pulse count signal of the first driver chip and a preset fixed delay time, and transmits the count update value of the first driver chip to the second driver chip, specifically including: The microprocessor transmits the command signal to the first driver chip; The first driving chip receives the command signal; The first driver chip determines a count update value of the first driver chip according to a current count value of a pulse count signal of the first driver chip and the fixed delay time; The first driver chip writes the count update value of the first driver chip into the middle section of the command signal to update the command signal; The first driving chip transmits the updated command signal to the second driving chip.

4. The clock alignment method according to claim 3, characterized in that: Determining the count update value of the first driver chip according to the current count value of the pulse count signal of the first driver chip and the fixed delay time specifically includes: Determine a fixed delay value according to the fixed delay time; The count update value of the first driver chip is determined according to the current count value of the pulse count signal of the first driver chip and the fixed delay value.

5. The clock alignment method according to claim 4, characterized in that: Determining the count update value of the first driver chip according to the current count value of the pulse count signal of the first driver chip and the fixed delay value specifically includes: Adding a current count value of a pulse count signal of the first driver chip to the fixed delay value to obtain an initial update value of the first driver chip; Comparing the initial update value of the first driver chip with the period of the pulse counting signal; If the initial update value of the first driver chip is smaller than the period of the pulse counting signal, the initial update value of the first driver chip is used as the count update value of the first driver chip; If the initial update value is greater than or equal to the period of the pulse counting signal, the difference between the initial update value of the first driver chip and the period of the pulse counting signal is used as the count update value of the first driver chip.

6. The clock alignment method according to claim 4, characterized in that: The driver chip receives the count update value transmitted by the previous driver chip, which specifically includes: The driver chip receives a command signal transmitted by a previous driver chip, and obtains a count update value of the previous driver chip stored in the middle segment of the command signal.

7. The clock alignment method according to claim 4, characterized in that: Determining the count update value of the driver chip according to the current count value of the driver chip and the fixed delay time specifically includes: Adding the current count value of the pulse count signal of the driver chip to the fixed delay value to obtain an initial update value of the driver chip; Comparing the initial update value of the driver chip with the period of the pulse counting signal; If the initial update value of the driver chip is less than the period of the pulse counting signal, the initial update value of the driver chip is used as the count update value of the driver chip; If the initial update value of the driver chip is greater than or equal to the period of the pulse counting signal, the difference between the initial update value of the driver chip and the period of the pulse counting signal is used as the count update value of the driver chip.

8. The clock alignment method according to claim 4, characterized in that: The count update value of the driver chip is transmitted to the next driver chip, specifically including: Writing the count update value of the driver chip into the middle section of the command signal to update the command signal; The updated command signal is transmitted to the next driver chip.

9. The clock alignment method according to claim 7, characterized in that: The head, the middle section and the tail are of the same size.

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