Semiconductor structure and manufacturing method thereof, and memory

Abstract

The present disclosure provides a semiconductor structure, a manufacturing method thereof, and a memory. The manufacturing method of the semiconductor structure includes: first, forming an active pillar extending in a vertical direction; then, performing multiple ion implantations on the active pillar to form a channel doping region and a first doping region and a second doping region located on the upper and lower sides of the channel doping region; finally, forming a first gate structure covering a first side of the active pillar and a second gate structure covering a second side of the active pillar, where the second side is opposite to the first side; wherein the projection of the first gate structure on the active pillar and the projection of the second gate structure on the active pillar both cover at least a portion of the channel doping region.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a manufacturing method thereof, and a memory. Background Art

[0002] As the feature size of dynamic random access memory (DRAM) decreases, the development of existing planar transistors has reached the limits of manufacturing processes. To overcome these limitations, non-planar transistors, such as vertical transistors, have become the mainstream development trend. However, how to reduce vertical transistor leakage, improve transistor performance, and simplify the doping process for vertical transistors remain urgent challenges. Summary of the Invention

[0003] Based on this, the embodiments of the present disclosure provide a semiconductor structure, a manufacturing method thereof, and a memory to solve the technical problems existing in the background technology.

[0004] The present disclosure provides a method for manufacturing a semiconductor structure, comprising:

[0005] forming active pillars extending in a vertical direction;

[0006] Performing multiple ion implantations on the active pillar to form a channel doping region and a first doping region and a second doping region respectively located on upper and lower sides of the channel doping region;

[0007] forming a first gate structure and a second gate structure, wherein the first gate structure covers a first side of the active pillar, and the second gate structure covers a second side of the active pillar, the second side being an opposite side to the first side;

[0008] The projection of the first gate structure on the active pillar at least covers a portion of the channel doping region, and the projection of the second gate structure on the active pillar at least covers a portion of the channel doping region.

[0009] In some embodiments, multiple ion implantations are performed on the active pillars, including:

[0010] Implanting the active pillar with a first dopant ion at a first energy;

[0011] Implanting the active pillar with second doping ions at a second energy;

[0012] The active pillar is implanted with a third doping ion at a third energy; wherein,

[0013] The first energy is greater than the second energy, and the second energy is greater than the third energy.

[0014] In some embodiments, the first doping ion is a phosphorus ion, the second doping ion is a boron ion, and the third doping ion is an arsenic ion.

[0015] In some embodiments, implanting the active pillar with first dopant ions at a first energy includes:

[0016] The implantation dose of the first doping ion is 3.0E13 cm -2 -7.0E13cm -2 , the first energy is 80KeV-100KeV.

[0017] In some embodiments, the step of implanting the active pillar with a third dopant ion at a third energy further includes:

[0018] The implantation dose of the third dopant ion is 3.0E13 cm -2 -7.0E13cm -2 , the third energy is 15KeV-25KeV.

[0019] In some embodiments, the method further comprises:

[0020] Ion implantation is performed on the active pillar using the second doping ions at a fourth energy; wherein the fourth energy is different from the second energy.

[0021] In some embodiments, the second energy is 15KeV-25KeV, the fourth energy is 10KeV-20KeV, and the implantation dose of the second dopant ion when implanted with the second energy and when implanted with the fourth energy is 1.0E13cm -2 -5.0E13cm -2 .

[0022] In some embodiments, the method further comprises:

[0023] implanting the active pillar with the first doping ions at a fifth energy;

[0024] The fifth energy is not greater than the third energy.

[0025] In some embodiments, when the first doping ions are implanted into the active pillar at a fifth energy, the implantation dose of the first doping ions is 5.0E13 cm -2 -9.0E13cm -2 , the fifth energy is 10KeV-20KeV.

[0026] In some embodiments, the method further comprises:

[0027] forming a node contact plug above the active pillar;

[0028] The node contact plug is doped so that a net doping concentration of the node contact plug is higher than a net doping concentration of the first doping region and has the same doping type as the first doping region.

[0029] The present disclosure also provides a semiconductor structure, including:

[0030] An active pillar extending in a vertical direction, the active pillar comprising a channel doping region and a first doping region and a second doping region respectively located on upper and lower sides of the channel doping region;

[0031] A first gate structure covers a first side of the active pillar, and a second gate structure covers a second side of the active pillar, where the second side is opposite to the first side; wherein,

[0032] The projection of the first gate structure on the active pillar at least covers a portion of the channel doping region, and the projection of the second gate structure on the active pillar at least covers a portion of the channel doping region.

[0033] In some embodiments, the channel doping region, the first doping region and the second doping region all include first doping ions, second doping ions and third doping ions, and the ion type of the first doping ions is the same as the ion type of the third doping ions and is opposite to the ion type of the second doping ions.

[0034] In some embodiments, the first doping ion is a phosphorus ion, the second doping ion is a boron ion, and the third doping ion is an arsenic ion.

[0035] In some embodiments, an average net doping concentration of the first doping region is higher than an average net doping concentration of the second doping region, and the net doping concentration in the first doping region increases in a direction away from the channel doping region.

[0036] In some embodiments, along the extension direction of the active pillar, the net doping concentration of the channel doping region first increases and then decreases, and along the direction away from the channel doping region, the net doping concentration of the second doping region first increases and then gradually decreases.

[0037] In some embodiments, the structure further comprises:

[0038] a node contact plug, the node contact plug being located on the active pillar;

[0039] The net doping concentration of the node contact plug is greater than the net doping concentration of the first doping region.

[0040] In some embodiments, the plurality of active pillars are distributed in an array of rows and columns, each of the first gate structures covers a first side of the active pillars in a column, and each of the second gate structures covers a second side of the active pillars in a column.

[0041] An embodiment of the present disclosure further provides a memory comprising the semiconductor structure as described in any of the above embodiments.

[0042] An embodiment of the present disclosure provides a semiconductor structure, a manufacturing method thereof, and a memory, wherein the manufacturing method of the semiconductor structure includes: forming an active pillar extending in a vertical direction; performing multiple ion implantation on the active pillar to form a channel doping region and a first doping region and a second doping region respectively located on the upper and lower sides of the channel doping region; forming a first gate structure and a second gate structure, the first gate structure covering a first side of the active pillar, and the second gate structure covering a second side of the active pillar, the second side being the opposite side of the first side; wherein the projection of the first gate structure on the active pillar covers at least a portion of the channel doping region, and the projection of the second gate structure on the active pillar covers at least a portion of the channel doping region.

[0043] In the embodiment of the present disclosure, by performing multiple ion implantations on the active column, the doping ion type, ion implantation dose and ion implantation energy in each ion implantation can be controlled, so that the first doping region and the second doping region formed are respectively located on the upper and lower sides of the channel doping region, thereby ensuring that the projections of the subsequently formed first gate structure and the second gate structure on the active column at least cover a portion of the channel doping region. Here, the channel doping region can be used as the channel region of the transistor structure, and the first doping region and the second doping region can be used as the source region and the drain region of the transistor structure, respectively. The projections of the first gate structure and the second gate structure on the active column at least cover a portion of the channel doping region, which can achieve the overlap of the first gate structure and the second gate structure with the channel region of the transistor structure, improve the control of the first gate structure and the second gate structure over the channel region, reduce the gate induced drain leakage current, and thus effectively improve the electrical performance and yield of the semiconductor structure.

[0044] The details of one or more embodiments of the present disclosure are set forth in the accompanying drawings and the description below. Other features and advantages of the present disclosure will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0046] Figure 1A schematic flow chart of a method for manufacturing a semiconductor structure provided in an embodiment of the present disclosure;

[0047] Figure 2 A schematic structural diagram of a semiconductor structure during the manufacturing process provided in the disclosed embodiment;

[0048] Figure 3 Schematic diagram of multiple ion implantation of a semiconductor structure provided by an embodiment of the present disclosure, wherein Figures a, b, and c are schematic diagrams of ion implantation of the active pillar using first dopant ions, second dopant ions, and third dopant ions, respectively;

[0049] Figure 4 A schematic diagram of the structure of a semiconductor structure after multiple ion implantation provided by an embodiment of the present disclosure;

[0050] Figure 5 A trend diagram of a first doping ion concentration, a second doping ion concentration, a third doping ion concentration, and a net doping concentration as a function of depth in a semiconductor structure provided by an embodiment of the present disclosure;

[0051] Figure 6 A schematic cross-sectional view of a semiconductor structure during the manufacturing process provided in the disclosed embodiment;

[0052] Figure 7 A schematic cross-sectional view of a semiconductor structure provided by an embodiment of the present disclosure;

[0053] Figure 8 A schematic diagram of a working state of a semiconductor structure provided by an embodiment of the present disclosure is provided. Figure 9 Schematic diagram of another operating state of a semiconductor structure provided by an embodiment of the present disclosure, wherein Figure a of each figure shows the operating state of the semiconductor structure, and Figure b shows the trend of drain-source current (IDS) changing with gate voltage (Vg);

[0054] Figure 10 A schematic structural diagram of another semiconductor structure provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0055] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0056] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0057] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0058] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. However, when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part exists in the present disclosure.

[0059] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0060] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates another way. It should also be understood that the terms "comprising" and / or "comprising" when used in this specification sheets determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items. All numerical ranges herein include endpoint values.

[0061] With the development of semiconductor technology, the size of semiconductor devices is getting smaller and smaller. The current mainstream development trend is to use vertical transistors to increase the density of transistors. However, in the vertical transistor structure, since the source region, channel region and drain region are arranged side by side in the vertical direction, the doping of the source, drain and channel regions will become difficult. In addition, problems such as gate-induced drain leakage (GIDL) will have a significant adverse effect on the formation of the semiconductor structure, resulting in reduced electrical performance and yield of the semiconductor structure. In order to reduce the leakage of the vertical transistor, the gate structure should be ensured to overlap with the channel region as much as possible. Therefore, how to better control the doping of the vertical transistor structure and ensure that the gate structure overlaps with the channel region is a technical difficulty.

[0062] Based on this, the present disclosure proposes the following technical solutions:

[0063] The present disclosure provides a method for manufacturing a semiconductor structure. Figure 1 A schematic diagram of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure is shown in the attached figure. Figure 1 As shown, the method includes the following steps:

[0064] Step S101: forming an active pillar 11 extending in a vertical direction;

[0065] Step S102 : performing multiple ion implantations on the active pillar 11 to form a channel doping region 113 and a first doping region 111 and a second doping region 112 located on upper and lower sides of the channel doping region 113 in the active pillar 11 ;

[0066] Step S103: forming a first gate structure 21 and a second gate structure 22, wherein the first gate structure 21 covers a first side of the active pillar 11, and the second gate structure 22 covers a second side of the active pillar 11, the second side being opposite to the first side;

[0067] The projection of the first gate structure 21 on the active pillar 11 at least covers a portion of the channel doping region 113 , and the projection of the second gate structure 22 on the active pillar 11 at least covers a portion of the channel doping region 113 .

[0068] Here, the direction of ion implantation is perpendicular to the plane of the substrate 10, and the projections of the first gate structure 21 and the second gate structure 22 on the active pillar 11 refer to the projections of the first gate structure 21 and the second gate structure 22 on the sidewalls of the active pillar 11 along a direction perpendicular to the extension of the active pillar 11. In some other embodiments, the direction of ion implantation may also be at a certain angle to the plane of the substrate 10 (i.e., tilted implantation).

[0069] In the disclosed embodiment, by performing multiple ion implantations on the active pillar 11, the doping ion type, ion implantation dose, and ion implantation energy in each ion implantation can be controlled, so that the first doping region 111 and the second doping region 112 formed are located on the upper and lower sides of the channel doping region 113, respectively. This ensures that the projections of the subsequently formed first gate structure 21 and the second gate structure 22 on the active pillar 11 both cover at least a portion of the channel doping region 113. Here, the channel doping region 113 can serve as the channel region of the transistor structure, and the first doping region 111 and the second doping region 112 can serve as the source region and the drain region of the transistor structure, respectively. The projections of the first gate structure 21 and the second gate structure 22 on the active pillar 11 both cover at least a portion of the channel doping region 113, thereby achieving overlap between the first gate structure 21 and the second gate structure 22 and the channel region of the transistor structure, improving the control of the first gate structure 21 and the second gate structure 22 over the channel region, reducing gate-induced drain leakage current, and thereby effectively improving the electrical performance and yield of the semiconductor structure.

[0070] Attachment Figure 2 A schematic diagram of a semiconductor structure during the manufacturing process provided in the disclosed embodiment; Figure 3 Schematic diagram of multiple ion implantation of a semiconductor structure provided by an embodiment of the present disclosure, wherein FIG a, FIG b and FIG c are schematic diagrams of ion implantation of the active pillar using the first doping ion, the second doping ion and the third doping ion respectively; Figure 4 A schematic diagram of the structure of a semiconductor structure after multiple ion implantation according to an embodiment of the present disclosure; Figure 5 A trend diagram of the first doping ion concentration, the second doping ion concentration, the third doping ion concentration and the net doping concentration as a function of depth in a semiconductor structure provided in an embodiment of the present disclosure, wherein curve 1 is the concentration variation trend of the first doping ion concentration, curve 2 is the concentration variation trend of the second doping ion concentration, curve 3 is the concentration variation trend of the third doping ion concentration, and curve 4 is the concentration variation trend of the net doping concentration; Figure 6The following is a cross-sectional diagram of a semiconductor structure during the manufacturing process provided in the disclosed embodiment. Figure 2 To the attached Figure 6 The manufacturing method of the semiconductor structure provided by the embodiment of the present disclosure is further described.

[0071] First, see the attached Figure 2 , executing step S101: forming an active pillar 11 extending in a vertical direction.

[0072] The active pillars 11 can be formed by the following steps: providing a substrate (not shown); etching the substrate using a lithography-etching (LE) process to form the active pillars 11; the remaining substrate is defined as the substrate 10. The substrate material includes a single element semiconductor material (e.g., silicon, germanium), a Group III-V compound semiconductor material, a Group II-VI compound semiconductor material, an organic semiconductor material, or other semiconductor materials known in the art. Here, the active pillars 11 can be one or multiple active pillars arranged in rows and columns.

[0073] After forming the active pillar 11, see the attached Figure 3 , step S102 is performed: multiple ion implantations are performed on the active pillar 11 to form a channel doping region 113 and a first doping region 111 and a second doping region 112 located on the upper and lower sides of the channel doping region 113 (see the attached FIG. Figure 4 ).

[0074] Here, the first doping region 111 and the second doping region 112 have the same doping type, and the doping type is opposite to that of the channel doping region 113 .

[0075] The specific steps of performing multiple ion implantations on the active pillar 11 may include: performing ion implantations on the active pillar 11 while controlling the doping ion type, ion implantation dose, and ion implantation energy in each ion implantation, so as to sequentially form a second doping region 112, a channel doping region 113, and a first doping region 111 in the active pillar 11. In some other embodiments, multiple ion implantations may be performed on the substrate, and then the substrate may be etched to form the active pillar 11 including the channel doping region 113, the first doping region 111, and the second doping region 112. This is not specifically limited here.

[0076] It should be noted that the ion implantation dose determines the ion doping concentration, that is, the greater the implantation dose, the higher the ion doping concentration; the ion implantation energy determines the ion incidence depth, that is, the greater the implantation energy, the greater the ion velocity obtained and the deeper the ion implantation depth.

[0077] In some embodiments, see Appendix Figure 3 , multiple ion implantations are performed on the top of the active pillar 11, including:

[0078] Implanting the active pillar 11 with a first doping ion at a first energy E1;

[0079] Implanting the active pillar 11 with a second doping ion at a second energy E2;

[0080] The active pillar 11 is implanted with a third doping ion at a third energy E3; wherein,

[0081] The first energy E1 is greater than the second energy E2, and the second energy E2 is greater than the third energy E3.

[0082] Here, by setting the first energy E1 to be greater than the second energy E2, and the second energy E2 to be greater than the third energy E3, the depth of the ion implantation can be effectively controlled to ensure that the first doped region 111 and the second doped region 112 are respectively located on both sides of the channel doped region 113. Here, the depth refers to the distance from the top of the active pillar 11 to the doped region.

[0083] Specifically, the ion type of the first doping ions is the same as the ion type of the third doping ions, and is opposite to the ion type of the second doping ions.

[0084] It should be noted that the first doping ions are injected into the active column 11 with the first energy E1, mainly to form the second doping region 112 in the active column 11; the second doping ions are injected into the active column 11 with the second energy E2, mainly to form a partial channel doping region 113 in the active column 11; the third doping ions are injected into the active column 11 with the third energy E3, mainly to form the first doping region 111 in the active column 11.

[0085] In actual operation, when the first doping ions are implanted into the active pillar 11 with the first energy E1, the implantation dose of the first doping ions is 3.0E13 cm -2 -7.0E13cm -2 , the first energy E1 is 80KeV-100KeV.

[0086] When the third doping ion is implanted into the active pillar 11 at the third energy E3, the implantation dose of the third doping ion is 3.0E13 cm -2 -7.0E13cm -2 , the third energy E3 is 15KeV-25KeV.

[0087] Here, by limiting the injection dose and injection energy of the first doping ions and the third doping ions, it is possible to ensure that the subsequently formed first doping region 111 and the second doping region 112 are located at the top and bottom of the active column 11 respectively, while ensuring that the first doping region 111 and the second doping region 112 have a higher doping concentration.

[0088] In some specific embodiments, see the attached Figure 3 In Figure b, the multiple ion implantation process also includes:

[0089] The second doping ions are used to perform ion implantation into the active pillars 11 at a fourth energy E4; wherein the fourth energy E4 is different from the second energy E2.

[0090] Here, the second doping ion is implanted in two steps, which can effectively solve the problem that the channel region is too long to be doped in one step. In addition, the fourth energy E4 is different from the second energy E2, which can make the second doping ion concentration uniform at different depths in the channel region.

[0091] In actual operation, the second energy E2 is 15KeV-25KeV, the fourth energy E4 is 10KeV-20KeV, and the implantation dose of the second dopant ion when implanted with the second energy E2 and the fourth energy E4 is 1.0E13cm -2 -5.0E13cm -2 Specifically, the second energy E2 is greater than the fourth energy E4.

[0092] In some embodiments, see Appendix Figure 3 In FIG. a, after the active pillar 11 is implanted with the third doping ion at the third energy E3, the multiple ion implantation process further includes:

[0093] Implanting the active pillar 11 with the first doping ion at a fifth energy E5;

[0094] The fifth energy E5 is not greater than the third energy E3.

[0095] Since the peak value of the third doping ion concentration in the first doping region 111 is at a certain depth, the third doping ion concentration in the first doping region 111 near the top of the active pillar 11 is relatively low (e.g., Figure 5 As shown), this will result in a high contact resistance when the active pillar 11 is electrically connected to structures such as a capacitor formed subsequently and located on top of the active pillar 11, thereby affecting the electrical performance of the semiconductor structure. In order to reduce the contact resistance of the first doping region 111, the first doping ion can be injected into the active pillar 11 by setting a fifth energy E5 that is less than the third energy E3 to compensate, thereby increasing the net doping concentration at the top of the active pillar 11 and reducing the contact resistance. The net doping (NetActive) concentration refers to the doping concentration after the different types of doping ions in the doping region are neutralized.

[0096] In actual operation, when the first doping ions are implanted into the active pillar 11 at the fifth energy E5, the implantation dose of the first doping ions is 5.0E13 cm -2 -9.0E13cm-2 , the fifth energy E5 is 10KeV-20KeV.

[0097] In some specific embodiments, the first doping ion and the third doping ion are one of N-type ions or P-type ions, and the second doping ion is the other of N-type ions or P-type ions. N-type ions include phosphorus ions and arsenic ions, and P-type ions include boron ions.

[0098] Preferably, the first doping ion is phosphorus ion, the second doping ion is boron ion, and the third doping ion is arsenic ion. Here, using phosphorus ions to ion-implant the active pillar 11 with a relatively high energy is advantageous for forming the second doping region 112 at the bottom of the active pillar 11. This is because phosphorus ions have a high diffusion rate and the ion diffusion can extend to a greater depth. Using arsenic ions to ion-implant the active pillar 11 is advantageous for forming the first doping region 111 at the top of the active pillar 11. This is because arsenic ions have a low diffusion rate, which helps to suppress the poor depth extension during ion diffusion.

[0099] By adopting the above-mentioned ion implantation process steps and limiting the doping ion type, ion implantation dose and ion implantation energy in the ion implantation process, it is possible to ensure that the subsequently formed first gate structure 21 and second gate structure 22 cover the channel region of the transistor structure, while effectively controlling the net doping concentration of each doping region, thereby further reducing the gate-induced drain leakage current.

[0100] In some embodiments, see Appendix Figure 5 Curve 1 shows the concentration variation trend of the first doping ion concentration, Curve 2 shows the concentration variation trend of the second doping ion concentration, Curve 3 shows the concentration variation trend of the third doping ion concentration, and Curve 4 shows the net doping concentration variation trend. It can be seen that the net doping concentration in the first doping region 111 increases as it moves away from the channel doping region 113; along the extension direction of the active pillar 11, the net doping concentration in the channel doping region 113 first increases and then decreases; and along the direction away from the channel doping region 113, the net doping concentration in the second doping region 112 first increases and then gradually decreases.

[0101] In some specific embodiments, referring to curve 4, the average net doping concentration of the first doping region 111 of the active pillar 11 is higher than the average net doping concentration of the second doping region 112. Here, the higher average net doping concentration of the first doping region 111 can effectively reduce the contact resistance and improve the electrical performance of the semiconductor structure.

[0102] Finally, see Appendix Figure 6, performing step S103: forming a first gate structure 21 and a second gate structure 22, wherein the first gate structure 21 covers a first side of the active pillar 11, and the second gate structure 22 covers a second side of the active pillar 11, the second side being the opposite side to the first side; wherein,

[0103] The projection of the first gate structure 21 on the active pillar 11 at least covers a portion of the channel doping region 113 , and the projection of the second gate structure 22 on the active pillar 11 at least covers a portion of the channel doping region 113 .

[0104] In some embodiments, the specific steps of forming the first gate structure 21 and the second gate structure 22 include: forming a first gate oxide layer 211 and a second gate oxide layer 221 covering the first side and the second side of the active pillar 11 respectively; forming a first gate conductive layer 212 covering the first gate oxide layer 211 and a second gate conductive layer 222 covering the second gate oxide layer 221.

[0105] Here, the material of the first gate conductive layer 212 and the second gate conductive layer 222 may include metal and / or polysilicon (Poly), etc. The material of the first gate oxide layer 211 and the second gate oxide layer 221 may include, but is not limited to, silicon oxide. The method for forming the first gate conductive layer 212 and the second gate conductive layer 222 includes, but is not limited to, one or more of physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD) processes. The method for forming the first gate oxide layer 211 and the second gate oxide layer 221 includes, but is not limited to, in-situ oxidation.

[0106] In actual operation, the projection of the first gate structure 21 on the active pillar 11 and the projection of the second gate structure 22 on the active pillar 11 do not overlap. This can increase the area of ​​the channel region covered by the gate structure, thereby effectively improving the gate structure's control over the channel region, thereby reducing gate-induced drain leakage current and improving the electrical performance and yield of the semiconductor device. In some other embodiments, the projection of the first gate structure 21 on the active pillar 11 and the projection of the second gate structure 22 on the active pillar 11 may also overlap.

[0107] In some embodiments, see Appendix Figure 6 The method for manufacturing a semiconductor structure provided by the embodiment of the present disclosure further includes:

[0108] forming a node contact plug 31 above the active pillar 11;

[0109] The node contact plug 31 is doped so that the net doping concentration of the node contact plug 31 is higher than the net doping concentration of the first doping region 111 and has the same doping type as the first doping region 111 .

[0110] Here, the material of the node contact plug 31 includes but is not limited to polysilicon. The node contact plug 31 can be formed by epitaxial growth or by etching after depositing the node contact plug material on the top of the active pillar 11, which is not specifically limited here.

[0111] In actual operation, as shown in the attached Figure 5 As shown, the net doping concentration of the node contact plug 31 is higher than the net doping concentration of the first doping region 111. The first doping ions in the node contact plug 31 can diffuse downward to reduce the contact resistance of the first doping region 111. The node contact plug 31 contacts the metal layer subsequently formed on the node contact plug 31, which can also reduce the Schottky contact resistance.

[0112] In some embodiments, the method for manufacturing a semiconductor structure provided by the embodiments of the present disclosure may further include:

[0113] A buried bit line structure (not shown) is formed in the substrate 10 . The bit line structure is located below the active pillar 11 and is connected to the second doped region 112 .

[0114] The bit line structure can be formed by implanting cobalt (Co) or nickel-platinum alloy (NiPt) into substrate 10 through an ion implantation process. Cobalt (Co) or nickel-platinum alloy (NiPt) reacts with substrate 10 to form cobalt silicide (CoSi) or platinum nickel silicide (PtNiSi). Then, after annealing, the cobalt silicide (CoSi) or platinum nickel silicide (PtNiSi) diffuses to the bottom of active pillars 11 in substrate 10, thereby forming a bit line structure in substrate 10.

[0115] The present disclosure also provides a semiconductor structure, Figure 7 A cross-sectional schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure is shown in FIG. Figure 7 , the semiconductor structure includes:

[0116] An active pillar 11 extending in a vertical direction, the active pillar 11 including a channel doping region 113 and a first doping region 111 and a second doping region 112 located on upper and lower sides of the channel doping region 113 respectively;

[0117] The first gate structure 21 covers the first side of the active pillar 11, and the second gate structure 22 covers the second side of the active pillar 11, where the second side is opposite to the first side;

[0118] The projection of the first gate structure 21 on the active pillar 11 at least covers a portion of the channel doping region 113 , and the projection of the second gate structure 22 on the active pillar 11 at least covers a portion of the channel doping region 113 .

[0119] Here, the projections of the first gate structure 21 and the second gate structure 22 on the active pillar 11 refer to the projections of the first gate structure 21 and the second gate structure 22 on the sidewalls of the active pillar 11 along the extending direction perpendicular to the active pillar 11 .

[0120] In the embodiment of the present disclosure, the first doping region 111 and the second doping region 112 are respectively located on the upper and lower sides of the channel doping region 113, and the projections of the first gate structure 21 and the second gate structure 22 on the active pillar 11 at least cover a portion of the channel doping region 113. Here, the channel doping region 113 can serve as the channel region of the transistor structure, and the first doping region 111 and the second doping region 112 can serve as the source region and the drain region of the transistor structure, respectively. The projections of the first gate structure 21 and the second gate structure 22 on the active pillar 11 both cover at least a portion of the channel doping region 113, which can achieve the overlap of the first gate structure 21 and the second gate structure 22 with the channel region of the transistor structure, improve the control of the first gate structure 21 and the second gate structure 22 over the channel region, reduce gate-induced drain leakage current, and thus effectively improve the electrical performance and yield of the semiconductor structure.

[0121] In actual operation, when the transistor structure is in the off state, that is, when the voltage of the first gate structure 21 and the second gate structure 22 are both -0.4V, the leakage current of the transistor structure is less than 0.1fA, that is, Ioff(-0.4V)<0.1fA. This shows that the first gate structure 21 and the second gate structure 22 have a high control capability over the channel region.

[0122] Figure 8 A schematic diagram of a working state of a semiconductor structure provided by an embodiment of the present disclosure is provided. Figure 9 A schematic diagram of another working state of a semiconductor structure provided in an embodiment of the present disclosure, wherein Figure a of each figure is the working state of the semiconductor structure, and Figure b is a trend diagram of the drain-source current (IDS) changing with the gate voltage (Vg).

[0123] In some embodiments, see Appendix Figure 8 , it can be seen that when the first gate structure 21 and the second gate structure 22 of the transistor structure are turned on at the same time, that is, a scan voltage (Sweep Vg) is applied to the gate structure, and its operating voltage is 2V, the performance of the transistor structure is calculated when writing 0 (NC=1V, BL=0V) and writing 1 (NC=0V, BL=1V), respectively. It can be found that no matter writing 0 or writing 1, the on-state current of the transistor structure is greater than 2μA, that is, Ion(2V)>2μA (as shown in the attached figure). Figure 8 (as shown in Figure b).

[0124] In actual operation, the transistor structure has an on / off ratio of 11 orders, a subthreshold swing (SS) of 80, and a threshold voltage Vt (1 nA) of 0.5 V.

[0125] In other embodiments, see the attached Figure 9 It can be seen that when one gate structure is in the off state (voltage is -0.4V), the other gate structure is in the on state. In the range of gate voltage from -0.4V to 2V, the transistor leakage current is always less than 0.5fA.

[0126] In some embodiments, see Appendix Figure 7 Active pillar 11 is located on substrate 10. The distance from the top of active pillar 11 to the bottom of active pillar 11, i.e., height D1 of active pillar 11, is 160 nm. The material of substrate 10 includes a single element semiconductor material (e.g., silicon, germanium), a Group III-V compound semiconductor material, a Group II-VI compound semiconductor material, an organic semiconductor material, or other semiconductor materials known in the art. Here, active pillar 11 can be one or multiple active pillars arranged in rows and columns.

[0127] In some specific embodiments, the active pillar 11 is a quadrangular prism; in some other embodiments, the active pillar 11 may also be a polygonal prism, a cylinder, or an elliptical cylinder, etc., and the shape of the active pillar 11 is not specifically limited herein. It should be noted that when the active pillar 11 is a cylinder or an elliptical cylinder, the surface of the active pillar 11 can be smoothly rounded to avoid tip discharge or leakage in the transistor structure formed by the active pillar 11 during operation; when the active pillar 11 is a quadrangular prism or a polygonal prism, the edges and corners of the active pillar 11 can be chamfered to ensure a smooth transition of the edges and corners of the active pillar 11, thereby avoiding the formation of tips that may cause leakage or discharge.

[0128] In some embodiments, the Figure 7 The first doping region 111 can serve as one of the source region or the drain region of the transistor structure, and the second doping region 112 can serve as the other of the source region or the drain region of the transistor structure. For example, the first doping region 111 serves as the source region, and correspondingly, the second doping region 112 serves as the drain region. Here, the first doping region 111 and the second doping region 112 have the same doping type, which is opposite to the doping type of the channel doping region 113. At the same time, the first doping region 111 and the second doping region 112 are both heavily doped regions, which helps reduce resistance and improve the conductivity of the semiconductor structure.

[0129] In some specific embodiments, Figure 5The channel doping region 113, the first doping region 111 and the second doping region 112 all include first doping ions, second doping ions and third doping ions, and the ion type of the first doping ions is the same as the ion type of the third doping ions and is opposite to the ion type of the second doping ions.

[0130] In actual operation, the first doping ion and the third doping ion are either N-type ions or P-type ions, and the second doping ion is the other of the N-type ion and the P-type ion. The N-type ions include phosphorus ions and arsenic ions, and the P-type ions include boron ions. Preferably, the first doping ion is a phosphorus ion, the second doping ion is a boron ion, and the third doping ion is an arsenic ion.

[0131] In some embodiments, Figure 5 The average net doping concentration of the first doping region 111 is higher than the average net doping concentration of the second doping region 112, and the net doping concentration in the first doping region 111 increases as it moves away from the channel doping region 113. The high average net doping concentration of the first doping region 111 effectively reduces contact resistance and improves the electrical performance of the semiconductor structure.

[0132] In some specific embodiments, along the extension direction of the active pillar 11 , the net doping concentration of the channel doping region 113 first increases and then decreases, and in the direction away from the channel doping region 113 , the net doping concentration of the second doping region 112 first increases and then gradually decreases.

[0133] In actual operation, Figure 5 The net doping concentration of the first doping region 111 is in the range of 2E16 cm -3 -3E20cm -3 The net doping concentration of the second doping region 112 is in the range of 2E16 cm -3 -5E18cm -3 , the net doping concentration of the channel doping region 113 is in the range of 2E16cm -3 -2E18cm -3 It is understandable that the higher the doping concentration, the more carriers there are and the stronger the conductivity. However, the higher the doping concentration, the higher the possibility of leakage. Here, by setting the doping concentration of the second doping region 112 to 2E16cm -3 -2E18cm -3 The possibility of leakage can be reduced while the second doping region 112 has a certain conductivity. By setting the doping concentration of the first doping region 111 to 2E16cm -3 -3E20cm -3 The first doped region 111 can be made to have stronger conductivity, thereby improving the conduction rate of the semiconductor structure.

[0134] In some embodiments, the Figure 7 The first gate structure 21 includes a first gate oxide layer 211 and a first gate conductive layer 212 , and the second gate structure 22 includes a second gate oxide layer 221 and a second gate conductive layer 222 .

[0135] In some specific embodiments, the first gate oxide layer 211 and the second gate oxide layer 221 cover the sidewalls of the active pillar 11; the first gate conductive layer 212 covers the first gate oxide layer 211, and the second gate conductive layer 222 covers the second gate oxide layer 221. Here, the gate oxide layer is located between the gate conductive layer and the channel region, and is used to electrically isolate the channel region and the gate conductive layer, thereby reducing the hot carrier effect in the transistor structure. The material of the first gate conductive layer 212 and the second gate conductive layer 222 may include metal and / or polysilicon (Poly). The material of the first gate oxide layer 211 and the second gate oxide layer 221 may include, but is not limited to, silicon oxide.

[0136] Specifically, along the extension direction of the active pillar, the dimension D2 of the first gate structure 21 is 30nm, the dimension D3 of the second gate structure 22 is 30nm, and the dimension D4 from the end of the first gate structure 21 close to the top of the active pillar 11 to the end of the second gate structure 22 away from the top of the active pillar 11 is 80nm.

[0137] In actual operation, the projection of the first gate structure 21 on the active pillar 11 and the projection of the second gate structure 22 on the active pillar 11 do not overlap. This can increase the area of ​​the channel region covered by the gate structure, thereby effectively improving the gate structure's control over the channel region, thereby reducing gate-induced drain leakage current and improving the electrical performance and yield of the semiconductor device. In some other embodiments, the projection of the first gate structure 21 on the active pillar 11 and the projection of the second gate structure 22 on the active pillar 11 may also overlap.

[0138] In addition, the projection of the first gate structure 21 on the active pillar 11 and the projection of the second gate structure 22 on the active pillar 11 do not overlap, which can increase the coverage area of ​​the gate structure on the channel region, which is conducive to setting a channel region with a larger length, so as to improve the short channel effect of the transistor structure while ensuring the control of the gate structure on the channel region, thereby improving the electrical performance and yield of the semiconductor structure.

[0139] Attachment Figure 10 A schematic diagram of another semiconductor structure provided in the embodiment of the present disclosure is shown in FIG. Figure 10 , the semiconductor structure provided by the present disclosure may further include:

[0140] A plurality of active pillars 11 are distributed in an array of rows and columns on the substrate 10;

[0141] Each first gate structure 21 covers a first side of a column of active pillars 11 , and each second gate structure 22 covers a second side of a column of active pillars 11 (not shown in the figures).

[0142] In some embodiments, see Appendix Figure 7 , the semiconductor structure provided by the present disclosure further includes:

[0143] A node contact plug 31 , the node contact plug 31 is located on the active pillar 11 ;

[0144] The net doping concentration of the node contact plug 31 is greater than the net doping concentration of the first doping region 111 .

[0145] The material of the node contact plug 31 includes but is not limited to polysilicon. Along the extending direction of the active pillar 11 , the dimension D5 of the node contact plug 31 is 20 nm.

[0146] In actual operation, as shown in the attached Figure 5 As shown, the net doping concentration of the node contact plug 31 is higher than the net doping concentration of the first doping region 111. The first doping ions in the node contact plug 31 can diffuse downward to reduce the contact resistance of the first doping region 111. The node contact plug 31 contacts the metal layer subsequently formed on the node contact plug 31, which can also reduce the Schottky contact resistance.

[0147] In some embodiments, the semiconductor structure provided by the embodiments of the present disclosure further includes: a bit line structure (not shown in the figure), which is located in the substrate 10 below the active pillar 11 and connected to the second doped region 112 .

[0148] It should be noted that the bit line structure can be connected to the drain region in the transistor structure, the source region of the transistor structure is connected to the capacitor structure, and the voltage signal on the gate structure can control the opening or closing of the transistor structure, thereby reading the data information stored in the capacitor structure through the bit line structure, or writing the data information into the capacitor structure for storage through the bit line structure.

[0149] An embodiment of the present disclosure further provides a memory, comprising: a semiconductor structure as provided in any of the above embodiments.

[0150] In summary, in the disclosed embodiment, by performing multiple ion implantations on the active pillar 11, the doping ion type, ion implantation dose, and ion implantation energy in each ion implantation can be controlled, so that the first doping region 111 and the second doping region 112 formed are located on the upper and lower sides of the channel doping region 113, respectively, thereby ensuring that the projections of the subsequently formed first gate structure 21 and the second gate structure 22 on the active pillar 11 both cover at least a portion of the channel doping region 113. Here, the channel doping region 113 can serve as the channel region of the transistor structure, and the first doping region 111 and the second doping region 112 can serve as the source region and the drain region of the transistor structure, respectively. The projections of the first gate structure 21 and the second gate structure 22 on the active pillar 11 both cover at least a portion of the channel doping region 113, which can achieve overlap between the first gate structure 21 and the second gate structure 22 and the channel region of the transistor structure, thereby improving the control of the first gate structure 21 and the second gate structure 22 over the channel region, reducing gate-induced drain leakage current, and effectively improving the electrical performance and yield of the semiconductor structure.

[0151] It should be noted that the semiconductor structure manufacturing method provided in the embodiments of the present disclosure can be applied to DRAM structures or other semiconductor devices, and is not further limited herein. The embodiments of the semiconductor structure manufacturing method provided in the present disclosure and the embodiments of the semiconductor structure are based on the same concept; the technical features of the technical solutions described in the various embodiments can be arbitrarily combined unless they conflict.

[0152] The above are only preferred embodiments of the present disclosure and are not intended to limit the scope of protection of the present disclosure. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present disclosure should be included in the scope of protection of the present disclosure.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: forming active pillars extending in a vertical direction; Performing multiple ion implantations on the active pillar to form a channel doping region and a first doping region and a second doping region respectively located on upper and lower sides of the channel doping region; forming a first gate structure and a second gate structure, wherein the first gate structure covers a first side of the active pillar, and the second gate structure covers a second side of the active pillar, the second side being an opposite side to the first side; The projection of the first gate structure on the active pillar covers at least a portion of the channel doping region, and the projection of the second gate structure on the active pillar covers at least a portion of the channel doping region. There are non-overlapping portions between the projections of the first gate and the second gate on the active pillar.

2. The method according to claim 1, characterized in that Performing multiple ion implantations on the active pillars, including: Implanting the active pillar with a first dopant ion at a first energy; Implanting the active pillar with second doping ions at a second energy; The active pillar is implanted with a third doping ion at a third energy; wherein, The first energy is greater than the second energy, and the second energy is greater than the third energy.

3. The method according to claim 2, characterized in that Implanting the active pillar with first doping ions at a first energy includes: The implantation dose of the first doping ion is 3.0E13 cm-2-7.0E13 cm-2, and the first energy is 80 KeV-100 KeV.

4. The method according to claim 2, characterized in that Implanting the active pillar with third doping ions at a third energy also includes: The implantation dose of the third doping ion is 3.0E13 cm-2-7.0E13 cm-2, and the third energy is 15 KeV-25 KeV.

5. The method according to claim 2, characterized in that The method further comprises: ion implantation is performed on the active pillar using the second doping ions at a fourth energy; wherein the fourth energy is different from the second energy; The second energy is 15KeV-25KeV, the fourth energy is 10KeV-20KeV, and the implantation dosage of the second dopant ions when implanted with the second energy and when implanted with the fourth energy is both 1.0E13cm-2-5.0E13cm-2.

6. The method according to claim 2, characterized in that The method further comprises: implanting the active pillar with the first doping ions at a fifth energy; The fifth energy is not greater than the third energy; When the first doping ions are implanted into the active pillar at a fifth energy, an implantation dose of the first doping ions is 5.0E13 cm-2-9.0E13 cm-2, and the fifth energy is 10 KeV-20 KeV.

7. The method according to claim 1, characterized in that The method further comprises: forming a node contact plug above the active pillar; The node contact plug is doped so that a net doping concentration of the node contact plug is higher than a net doping concentration of the first doping region and has the same doping type as the first doping region.

8. A semiconductor structure, characterized in that include: An active pillar extending in a vertical direction, the active pillar comprising a channel doping region and a first doping region and a second doping region respectively located on upper and lower sides of the channel doping region; A first gate structure covers a first side of the active pillar, and a second gate structure covers a second side of the active pillar, where the second side is opposite to the first side; wherein, The projection of the first gate structure on the active pillar covers at least a portion of the channel doping region, and the projection of the second gate structure on the active pillar covers at least a portion of the channel doping region. There are non-overlapping portions between the projections of the first gate and the second gate on the active pillar.

9. The structure according to claim 8, characterized in that The channel doping region, the first doping region and the second doping region all include first doping ions, second doping ions and third doping ions, wherein the ion type of the first doping ions is the same as the ion type of the third doping ions and is opposite to the ion type of the second doping ions.

10. The structure according to claim 9, characterized in that The first doping ions are phosphorus ions, the second doping ions are boron ions, and the third doping ions are arsenic ions.

11. The structure according to claim 8, characterized in that An average net doping concentration of the first doping region is higher than an average net doping concentration of the second doping region, and the net doping concentration in the first doping region increases in a direction away from the channel doping region.

12. The structure according to claim 8, characterized in that Along the extension direction of the active pillar, the net doping concentration of the channel doping region first increases and then decreases, and along the direction away from the channel doping region, the net doping concentration of the second doping region first increases and then gradually decreases.

13. The structure according to claim 8, characterized in that The structure further comprises: a node contact plug, the node contact plug being located on the active pillar; The net doping concentration of the node contact plug is greater than the net doping concentration of the first doping region.

14. The structure according to claim 8, characterized in that The plurality of active pillars are distributed in an array of rows and columns. Each of the first gate structures covers a first side of the active pillars in a column, and each of the second gate structures covers a second side of the active pillars in a column.

15. A memory, characterized in that: Comprising the semiconductor structure according to any one of claims 8 to 14.

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