Semiconductor structure and method for forming the same

Abstract

The present disclosure relates to the field of semiconductor technology, specifically a semiconductor structure and a method for forming the same. The semiconductor structure includes a substrate, a bitline structure, an insulating layer, a gate dielectric layer, and a gate electrode layer. The substrate includes a plurality of first trenches and a plurality of second trenches, each of which divides a plurality of semiconductor pillars within the substrate. Each semiconductor pillar forms a plurality of semiconductor pillar groups distributed along a second direction, and the semiconductor pillar groups include a plurality of semiconductor pillars spaced apart along the first direction. In a direction parallel to the substrate, the cross-sectional dimensions of the semiconductor pillars are uniform at all locations. The bitline structure is located below the semiconductor pillars and extends along the second direction. The insulating layer is located at the bottom of the first and second trenches. The gate dielectric layer is located on the surface of the sidewalls of each semiconductor pillar in the semiconductor pillar group that are not covered by the insulating layer. The gate electrode layer covers a portion of the surface of the gate dielectric layer. The conductor structure disclosed herein can provide a stable threshold voltage, reduce leakage, and increase on-current.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] Memory devices are widely used in mobile devices such as mobile phones and tablets due to their advantages such as small size, high integration, and fast transmission speeds. As the core component of memory devices, transistors play a crucial role in the device's electrical performance. However, due to process limitations, transistors are prone to structural defects during the manufacturing process, resulting in low product yields.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the Invention

[0004] In view of this, the present disclosure provides a semiconductor structure and a method for forming the same, which can provide a stable threshold voltage, reduce leakage, and increase on-current.

[0005] According to one aspect of the present disclosure, there is provided a semiconductor structure comprising:

[0006] A substrate comprising a plurality of first trenches spaced apart along a first direction and extending along a second direction, and a plurality of second trenches spaced apart along the second direction and extending along the first direction, wherein the second direction intersects the first direction; each of the first trenches and each of the second trenches divides a plurality of semiconductor pillars within the substrate, wherein the plurality of semiconductor pillars form a plurality of semiconductor pillar groups spaced apart along the second direction, wherein the semiconductor pillar groups include a plurality of semiconductor pillars spaced apart along the first direction; and in a direction parallel to the substrate, the cross-sectional dimensions of the semiconductor pillars are uniform at all locations.

[0007] a bit line structure, located below the semiconductor pillar and extending along the second direction;

[0008] an insulating layer, located at the bottom of the first trench and the second trench;

[0009] a gate dielectric layer, located on a surface of a sidewall of each semiconductor column in the semiconductor column group that is not covered by the insulating layer;

[0010] The gate electrode layer covers a portion of the surface of the gate dielectric layer.

[0011] In an exemplary embodiment of the present disclosure, the insulating layer includes:

[0012] a first insulating material layer, located at the bottom of the first trench and the second trench;

[0013] The second insulating material layer conformally covers the bottom, sidewalls and top surface of the first insulating material layer.

[0014] In an exemplary embodiment of the present disclosure, the insulating layer includes:

[0015] a first insulating material layer, covering a portion of the bottom surface of the first trench and the second trench, and having a first preset gap with the semiconductor pillar;

[0016] The second insulating material layer covers the surface of the first insulating material layer and fills the first preset gap.

[0017] In an exemplary embodiment of the present disclosure, the first insulating material layer is made of silicon nitride, and the second insulating material layer is made of silicon oxide.

[0018] In an exemplary embodiment of the present disclosure, the insulating layer includes:

[0019] a first insulating material layer covering the entire bottom surface of the first trench and the second trench;

[0020] a second insulating material layer, located on a surface of the first insulating material layer and having a second preset gap with the semiconductor pillar;

[0021] The third insulating material layer covers the surface of the second insulating material layer and fills the second preset gap.

[0022] In an exemplary embodiment of the present disclosure, the first insulating material layer and the second insulating material layer are both made of silicon nitride, and the third insulating material layer is made of silicon oxide.

[0023] According to one aspect of the present disclosure, a method for forming a semiconductor structure is provided, comprising:

[0024] forming a substrate, the substrate comprising a plurality of first trenches spaced apart along a first direction and extending along a second direction, and a plurality of second trenches spaced apart along the second direction and extending along the first direction, wherein the second direction intersects the first direction; each of the first trenches and each of the second trenches divides a plurality of semiconductor pillars within the substrate, the plurality of semiconductor pillars forming a plurality of semiconductor pillar groups spaced apart along the second direction, the semiconductor pillar groups comprising a plurality of semiconductor pillars spaced apart along the first direction; and in a direction parallel to the substrate, the cross-sectional dimensions of the semiconductor pillars are uniform at all locations;

[0025] forming a bit line structure below the semiconductor pillar, wherein the bit line structure extends along the second direction;

[0026] forming an insulating layer at the bottom of the first trench and the second trench;

[0027] forming a second gate dielectric layer on the surface of the sidewall of each semiconductor column in the semiconductor column group that is not covered by the insulating layer by an atomic layer deposition process;

[0028] forming a first gate dielectric layer between the second gate dielectric layer and the sidewall of the semiconductor pillar by an in-situ water vapor oxidation process;

[0029] A gate electrode layer is formed to cover a portion of the surface of the second gate dielectric layer.

[0030] In an exemplary embodiment of the present disclosure, the thickness of the second gate dielectric layer is 2 nm to 3 nm.

[0031] In an exemplary embodiment of the present disclosure, forming the substrate includes:

[0032] providing a substrate;

[0033] Etching the substrate to form a plurality of first grooves spaced apart along a first direction and extending along a second direction;

[0034] filling the first trench with an insulating material;

[0035] Etching the substrate and the insulating material to form a plurality of second trenches spaced apart along the second direction and extending along the first direction;

[0036] Forming the bit line structure includes:

[0037] forming a bit line trench below the plurality of semiconductor pillars distributed along the second direction, wherein the bit line trench extends along the second direction;

[0038] forming a bit line material layer in the bit line trench;

[0039] forming a protective layer on sidewalls of the second trench;

[0040] Ions are implanted into the bit line material layer through the second trench to form a bit line structure.

[0041] In an exemplary embodiment of the present disclosure, before forming the insulating layer, the forming method further includes:

[0042] Filling the second trench having the protection layer with the insulating material so that the second trench is completely filled with the insulating material;

[0043] The insulating material and the protection layer are etched with the bottom of the second trench as a stop layer to expose sidewalls of the semiconductor pillar adjacent to the first trench and the second trench.

[0044] In an exemplary embodiment of the present disclosure, forming the insulating layer, the first gate dielectric layer, and the second gate dielectric layer includes:

[0045] forming a second insulating layer and a first insulating layer in the first trench and the second trench, wherein the second insulating layer conformally covers the bottom and sidewalls of the first trench and the second trench, the top of the second insulating layer is lower than the top surface of the semiconductor pillar, and the first insulating layer is located on the surface of the second insulating layer and is flush with the top of the second insulating layer;

[0046] removing the second insulating layer between the first insulating layer and the sidewall of the semiconductor pillar to form a first gap;

[0047] forming a second dielectric layer on the surface of the structure formed by the first insulating layer and the semiconductor pillars by using an atomic layer deposition process;

[0048] An in-situ water vapor oxidation process is used to form a first dielectric layer between the second dielectric layer and the sidewall of the semiconductor pillar. The first dielectric layer and the second dielectric layer fill the first gap. The first insulating layer, the first dielectric layer and the second dielectric layer located on the surface of the first insulating layer, the first dielectric layer and the second dielectric layer located between the first insulating layer and the semiconductor pillar, and the second insulating layer located at the bottom of the first insulating layer are used as the insulating layer. The first dielectric layer located on a side of the insulating layer away from the bit line structure is used as a first gate dielectric layer, and the second dielectric layer located on a side of the insulating layer away from the bit line structure is used as a second gate dielectric layer.

[0049] In an exemplary embodiment of the present disclosure, forming the first insulating layer and the second insulating layer includes:

[0050] forming a second insulating material conformally covering an inner wall of the first trench and an inner wall of the second trench;

[0051] forming a first insulating material in the first trench having the second insulating material and in the second trench;

[0052] The first insulating material is etched back to form the first insulating layer; and the second insulating material is etched back to form the second insulating layer.

[0053] In an exemplary embodiment of the present disclosure, forming the insulating layer, the first gate dielectric layer, and the second gate dielectric layer includes:

[0054] forming a second insulating layer on sidewalls of the first trench and the second trench;

[0055] forming a first insulating layer in the first trench having the second insulating layer and in the second trench, wherein a top portion of the second insulating layer is lower than a top surface of the semiconductor pillar, and a top portion of the first insulating layer is flush with a top portion of the second insulating layer;

[0056] removing the second insulating layer to form a second gap;

[0057] forming a second dielectric layer on the surface of the structure formed by the first insulating layer and the semiconductor pillars by using an atomic layer deposition process;

[0058] An in-situ water vapor oxidation process is used to form a first dielectric layer between the second dielectric layer and the sidewall of the semiconductor pillar. The first dielectric layer and the second dielectric layer fill the second gap. The first insulating layer, the first dielectric layer and the second dielectric layer located on the surface of the first insulating layer, and the first dielectric layer and the second dielectric layer located between the first insulating layer and the semiconductor pillar serve as the insulating layer. The first dielectric layer located on a side of the insulating layer away from the bit line structure serves as a first gate dielectric layer, and the second dielectric layer located on a side of the insulating layer away from the bit line structure serves as a second gate dielectric layer.

[0059] In an exemplary embodiment of the present disclosure, forming the insulating layer, the first gate dielectric layer, and the second gate dielectric layer includes:

[0060] forming a first insulating layer at the bottom of the first trench and the second trench, wherein the first insulating layer includes a first portion and a second portion adjacent to each other, wherein the first portion covers the entire bottom surface of the first trench and the second trench, and the second portion is located on a surface of the first portion away from the bit line structure, and a third gap is formed between the second portion and the semiconductor pillar;

[0061] forming a second dielectric layer on the surface of the structure formed by the first insulating layer and the semiconductor pillars by using an atomic layer deposition process;

[0062] An in-situ water vapor oxidation process is used to form a first dielectric layer between the second dielectric layer and the sidewall of the semiconductor pillar. The first dielectric layer and the second dielectric layer fill the third gap. The first insulating layer, the first dielectric layer and the second dielectric layer located on the surface of the first insulating layer, and the first dielectric layer and the second dielectric layer located between the first insulating layer and the semiconductor pillar serve as the insulating layers. The first dielectric layer located on a side of the insulating layer away from the bit line structure serves as a first gate dielectric layer, and the second dielectric layer located on a side of the insulating layer away from the bit line structure serves as a second gate dielectric layer.

[0063] In an exemplary embodiment of the present disclosure, the material of the first insulating layer is silicon nitride, and the materials of the first gate dielectric layer and the second gate dielectric layer are both silicon oxide.

[0064] The semiconductor structure and its formation method disclosed herein have the following advantages: because the cross-sectional dimensions of the semiconductor pillars are uniform in a direction parallel to the substrate, the sidewalls of the semiconductor pillars are flat surfaces, and the gate dielectric layer formed on the sidewalls has a flat formation base, making it easy to obtain a gate dielectric layer with a relatively uniform thickness; the semiconductor pillars, the gate dielectric layer, and the gate electrode layer can together constitute a transistor. In the transistor, because the thickness of different regions of the gate dielectric layer is relatively uniform, the threshold voltage of different regions in the transistor is relatively stable, and local leakage is less likely to occur, the on-state current is improved, the structural defects are reduced, and the product yield is high. At the same time, because the multiple semiconductor pillars are divided by the first trenches and the second trenches, the bit line structure is located below the semiconductor pillars, and the insulating layer is located at the bottom of the first trenches and the second trenches, the bit line structure below the semiconductor pillars can be insulated and isolated from the subsequently formed gate electrode layer by the insulating layer, which can reduce the risk of short circuit or coupling between the bit line structure and the gate electrode layer, and help further improve the product yield. In addition, since the bit line structure is buried under the semiconductor pillar, there is no need to design a space for accommodating the bit line structure, which helps to miniaturize the product design and improve product integration.

[0065] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0067] Figure 1Schematic diagram of a gate dielectric layer in a related technology disclosed herein.

[0068] Figure 2 Schematic diagram of a gate dielectric layer in another related technology disclosed herein.

[0069] Figure 3 FIG. 1 is a schematic diagram of a semiconductor structure in an embodiment of the present disclosure.

[0070] Figure 4 1 is a top view of the substrate in an embodiment of the present disclosure.

[0071] Figure 5 Schematic diagram of the semiconductor structure in the first embodiment of the present disclosure.

[0072] Figure 6 Schematic diagram of a semiconductor structure in the second embodiment of the present disclosure.

[0073] Figure 7 Schematic diagram of a semiconductor structure in the third embodiment of the present disclosure.

[0074] Figure 8 Flowchart of a method for forming a semiconductor structure in an embodiment of the present disclosure.

[0075] Figure 9 In the embodiment of the present disclosure Figure 4 Cross-sectional view taken along the bb' direction.

[0076] Figure 10 In the embodiment of the present disclosure Figure 4 Cross-sectional view taken along the aa' direction.

[0077] Figure 11 In the embodiment of the present disclosure, step S230 is completed. Figure 4 Cross-sectional view taken along the bb' direction.

[0078] Figure 12 In the embodiment of the present disclosure, step S330 is completed. Figure 4 Cross-sectional view taken along the aa' direction.

[0079] Figure 13 In the embodiment of the present disclosure, step S410 is completed. Figure 4 Cross-sectional view taken along the aa' direction.

[0080] Figure 14 In the embodiment of the present disclosure, step S510 is completed. Figure 4 Cross-sectional view taken along the aa' direction.

[0081] Figure 15 In the embodiment of the present disclosure, step S5102 is completed. Figure 4 Cross-sectional view taken along the aa' direction.

[0082] Figure 16 In the embodiment of the present disclosure, step S520 is completed. Figure 4 Cross-sectional view taken along the aa' direction.

[0083] Figure 17 In the embodiment of the present disclosure, step S540 is completed. Figure 4 Cross-sectional view taken along the aa' direction.

[0084] Figure 18 In the embodiment of the present disclosure, step S620 is completed. Figure 4 Cross-sectional view taken along the aa' direction.

[0085] Figure 19 In the embodiment of the present disclosure, step S630 is completed. Figure 4 Cross-sectional view taken along the aa' direction.

[0086] Figure 20 In the embodiment of the present disclosure, step S650 is completed. Figure 4 Cross-sectional view taken along the aa' direction.

[0087] Figure 21 In the embodiment of the present disclosure, step S710 is completed. Figure 4 Cross-sectional view taken along the aa' direction.

[0088] Figure 22 In the embodiment of the present disclosure, step S810 is completed. Figure 4 Cross-sectional view taken along the aa' direction.

[0089] Figure 23 In the embodiment of the present disclosure, step S830 is completed. Figure 4 Cross-sectional view taken along the aa' direction.

[0090] Figure 24 In the embodiment of the present disclosure, step S840 is completed. Figure 4 Cross-sectional view taken along the aa' direction.

[0091] Figure 25 The following example is a step S170 completed in the disclosed embodiment. Figure 4 Cross-sectional view taken along the bb' direction.

[0092] Figure 26 In another embodiment of the present disclosure, step S170 is completed. Figure 4 Cross-sectional view taken along the bb' direction.

[0093] Description of reference numerals:

[0094] 100, gate dielectric layer; 1, substrate; 11, base; 111, first trench; 112, second trench; 113, semiconductor pillar; 12, insulating material; 110, semiconductor pillar group; 2, bit line structure; 3, insulating layer; 31, first insulating material layer; 311, first insulating layer; 3111, first portion; 3112, second portion; 312, second insulating layer; 301, first gap; 302, second gap; 303, third gap; 32, second insulating material layer; 33, third insulating material layer; 310, first insulating material; 320, second insulating material; 330, third insulating material; 4, gate dielectric layer; 41, first gate dielectric layer; 42, second gate dielectric layer; 410, first dielectric layer; 420, second dielectric layer; 5, gate electrode layer; 6, protective layer; 7, passivation layer; x, first direction; y, second direction. DETAILED DESCRIPTION

[0095] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0096] Although relative terms such as "upper" and "lower" are used in this specification to describe the relationship of one illustrated component to another, these terms are used herein for convenience only, such as in accordance with the orientation of the illustrations in the accompanying drawings. It will be understood that if the illustrated device were flipped upside down, the component described as "upper" would become the component "lower." When a structure is referred to as "on" another structure, this may mean that the structure is integrally formed with the other structure, that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via the other structure.

[0097] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0098] In the process of transistor manufacturing, in order to increase the channel length without increasing the structure size, the channel is usually designed to be concave (such as Figure 1 and Figure 2However, during the process of forming the gate dielectric layer 100 on the channel surface, the thickness of the gate dielectric layer 100 at the corners of the recessed channel is often greater than that in other regions (for example, d2>d1), resulting in uneven thickness distribution in different regions of the gate dielectric layer 100, and thus uneven threshold voltage distribution in different regions of the ultimately formed transistor. Moreover, after power is applied, regions with relatively thin gate dielectric layer 100 are prone to leakage, resulting in low product yield.

[0099] Based on this, the present disclosure provides a semiconductor structure. Figure 3 A schematic diagram of the semiconductor structure of the present disclosure is shown in FIG. Figure 3 and Figure 4 As shown, the semiconductor structure includes a substrate 1, a bit line structure 2, an insulating layer 3, a gate dielectric layer 4 and a gate electrode layer 5, wherein:

[0100] The substrate 1 includes a plurality of first trenches 111 spaced apart along a first direction x and extending along a second direction y, and a plurality of second trenches 112 spaced apart along the second direction y and extending along the first direction x, wherein the second direction y intersects the first direction x. Each of the first trenches 111 and the second trenches 112 divides a plurality of semiconductor pillars 113 within the substrate 1. The plurality of semiconductor pillar groups 110 form a plurality of semiconductor pillar groups 110 spaced apart along the second direction y. The semiconductor pillar groups 110 include a plurality of semiconductor pillars 113 spaced apart along the first direction x. In a direction parallel to the substrate 1, the cross-sectional dimensions of the semiconductor pillars 113 are uniform at all locations.

[0101] The bit line structure 2 is located below the semiconductor pillar 113 and extends along the second direction y;

[0102] The insulating layer 3 is located at the bottom of the first trench 111 and the second trench 112;

[0103] The gate dielectric layer 4 is located on the surface of the sidewall of each semiconductor column 113 in the semiconductor column group 110 that is not covered by the insulating layer 3;

[0104] The gate electrode layer 5 covers a portion of the surface of the gate dielectric layer 4 .

[0105] In the semiconductor structure disclosed herein, since the cross-sectional dimensions of the semiconductor pillar 113 are uniform in a direction parallel to the substrate 1, the sidewalls of the semiconductor pillar 113 are flat surfaces, and the gate dielectric layer 4 formed on the sidewalls has a flat formation reference, thereby making it easy to obtain a gate dielectric layer 4 with a relatively uniform thickness; the semiconductor pillar 113, the gate dielectric layer 4, and the gate electrode layer 5 can together constitute a transistor. In the transistor, since the thickness of different regions of the gate dielectric layer 4 is relatively uniform, the threshold voltages of different regions in the transistor are relatively stable, and local leakage is less likely to occur, the on-state current is improved, structural defects are fewer, and the product yield is higher. At the same time, because the plurality of semiconductor pillars 113 are formed by dividing the first trenches 111 and the second trenches 112, the bitline structure 2 is located below the semiconductor pillars 113, and the insulating layer 3 is located at the bottom of the first trenches 111 and the second trenches 112. The insulating layer 3 can insulate and isolate the bitline structure 2 below the semiconductor pillars 113 from the subsequently formed gate electrode layer 5, thereby reducing the risk of short circuit or coupling between the bitline structure 2 and the gate electrode layer 5, and helping to further improve product yield. In addition, because the bitline structure 2 is buried below the semiconductor pillars 113, there is no need to design a space to accommodate the bitline structure 2, which facilitates the miniaturization of the product design and improves the product integration.

[0106] The following describes in detail the various parts of the semiconductor structure disclosed herein and their specific details:

[0107] The substrate 1 may be a flat plate structure, which may be rectangular, circular, elliptical, polygonal or irregular in shape, and its material may be a semiconductor material, for example, its material may be silicon, but is not limited to silicon or other semiconductor materials. No special limitation is imposed on the shape and material of the substrate 1.

[0108] Please continue to see Figure 4 As shown, the substrate 1 includes a plurality of first trenches 111 and a plurality of second trenches 112. The first trenches 111 can be strip-shaped, spaced apart along a first direction x, and each first trench 111 can extend along a second direction y. The second trenches 112 can also be strip-shaped, extending along the first direction x, and spaced apart along the second direction y. The depth of the first trenches 111 can be greater than that of the second trenches 112, and the portion of the substrate 1 above the bottom of the second trenches 112 can serve as semiconductor pillars 113.

[0109] In some embodiments of the present disclosure, the first direction x may intersect with the second direction y; for example, the first direction x and the second direction y may be perpendicular to each other. It should be noted that perpendicularity can be absolutely perpendicular or approximately perpendicular. Deviations are inevitable during the manufacturing process. In the present disclosure, the angle deviation may be caused by manufacturing process limitations, resulting in a certain deviation in the angle between the first direction x and the second direction y. As long as the angular deviation between the first direction x and the second direction y is within a preset range, the first direction x and the second direction y can be considered perpendicular. For example, the preset range can be 10°, that is, the first direction x and the second direction y can be considered perpendicular when the angle between the first direction x and the second direction y is greater than or equal to 80° and less than or equal to 100°.

[0110] Each first trench 111 and each second trench 112 can separate a plurality of semiconductor pillars 113 within the substrate 1. The plurality of semiconductor pillars 113 can form a plurality of semiconductor pillar groups 110 distributed along the second direction y. Each semiconductor pillar group 110 can include a plurality of semiconductor pillars 113 spaced apart along the first direction x. The semiconductor pillars 113 can extend in a direction perpendicular to the substrate 1. In a direction parallel to the substrate 1, the cross-sections of the semiconductor pillars 113 have the same shape and uniform cross-section dimensions. That is, the sidewalls of the semiconductor pillars 113 are flat surfaces, and the semiconductor pillars 113 are straight cylinders.

[0111] After forming the semiconductor pillar 113, a bitline structure 2 can be embedded beneath the semiconductor pillar 113. That is, the bitline structure 2 is located beneath the semiconductor pillar 113. Because the bitline structure 2 is embedded beneath the semiconductor pillar 113, there is no need to design a space to accommodate the bitline structure 2, which facilitates product miniaturization and improves product integration. The bitline structure 2 can be strip-shaped and extend along the second direction y. There can be multiple bitline structures 2, and the multiple bitline structures 2 can be spaced apart along the first direction x.

[0112] like Figure 5-Figure 7 As shown, the insulating layer 3 can be located at the bottom of the first trench 111 and the second trench 112. The insulating layer 3 can be used to insulate and isolate the bit line structure 2 below the semiconductor pillar 113 from the subsequently formed gate electrode layer 5, thereby reducing the risk of short circuit or coupling between the bit line structure 2 and the gate electrode layer 5, and helping to further improve product yield.

[0113] In some embodiments of the present disclosure, the insulating layer 3 may include a first insulating material layer 31 and a second insulating material layer 32. The insulating layer 3 of the present disclosure is described in detail below through three embodiments:

[0114] In the first embodiment of the present disclosure, please continue to refer to Figure 5As shown, the first insulating material layer 31 is located at the bottom of the first trench 111 and the second trench 112, and the first insulating material layer 31 does not directly contact the bottom and sidewalls of the first trench 111 and / or the second trench 112. The material of the first insulating material layer 31 can be silicon nitride. The second insulating material layer 32 can conformally cover the bottom, sidewalls, and top surface of the first insulating material layer 31, that is, the first insulating material layer 31 is completely encapsulated by the second insulating material layer 32. The second insulating material layer 32 fills the gap between the first insulating material layer 31 and the bottom and sidewalls of the first trench 111. At the same time, the second insulating material layer 32 also fills the gap between the first insulating material layer 31 and the bottom and sidewalls of the second trench 112. The material of the second insulating material layer 32 is different from that of the first insulating material layer 31. For example, the material of the second insulating material layer 32 can be silicon oxide.

[0115] In the second embodiment of the present disclosure, please continue to refer to Figure 6 As shown, the first insulating material layer 31 is located at the bottom of the first trench 111 and the second trench 112, with no gap between it and the bottom of the first trench 111 and / or the second trench 112. The first insulating material layer 31 may cover a portion of the bottom surface of the first trench 111 and the second trench 112, and a first predetermined gap is formed between the first insulating material layer 31 and the sidewall of the semiconductor pillar 113. The material of the first insulating material layer 31 may be silicon nitride. The second insulating material layer 32 may cover the surface of the first insulating material layer 31 and may fill the first predetermined gap. The material of the second insulating material layer 32 is different from that of the first insulating material layer 31. For example, the material of the second insulating material layer 32 may be silicon oxide.

[0116] In the third embodiment of the present disclosure, please continue to refer to Figure 7 As shown, the first insulating material layer 31 can cover the entire bottom surface of the first trench 111 and the second trench 112. It can be a thin film covering the bottom surface of the first trench 111 and the second trench 112, or it can be a coating covering the bottom surface of the first trench 111 and the second trench 112. The specific form of the first insulating material layer 31 is not particularly limited herein. The second insulating material layer 32 can be located on the surface of the first insulating material layer 31, and a second predetermined gap can be formed between the second insulating material layer 32 and the sidewall of the semiconductor pillar 113. The second insulating material layer 32 and the first insulating material layer 31 can be made of the same material. For example, the second insulating material layer 32 and the first insulating material layer 31 can both be made of silicon nitride. It should be noted that in this embodiment, the insulating layer 3 can also include a third insulating material layer 33. The third insulating material layer 33 can cover the surface of the second insulating material layer 32 and fill the second predetermined gap. The material of the third insulating material layer 33 is different from that of the first insulating material layer 31 and the second insulating material layer 32. For example, the material of the third insulating material layer 33 can be silicon oxide.

[0117] Please continue to see Figure 5-Figure 7 As shown, the gate dielectric layer 4 is located on the surface of the sidewall of each semiconductor column 113 in the semiconductor column group 110 that is not covered by the insulating layer 3. In some embodiments of the present disclosure, such as Figure 6 As shown, the gate dielectric layer 4 may include a first gate dielectric layer 41 and a second gate dielectric layer 42. The first gate dielectric layer 41 may be located on the sidewall surface of the semiconductor pillar 113, and the second gate dielectric layer 42 may be located on the surface of the first gate dielectric layer 41. Both the first gate dielectric layer 41 and the second gate dielectric layer 42 may be made of silicon oxide. The second gate dielectric layer 42 may be formed on the surface of the semiconductor pillar 113 using an atomic layer deposition process. The thickness of the second gate dielectric layer 42 may be 2 nm to 3 nm. For example, the thickness may be 2 nm, 2.2 nm, 2.4 nm, 2.6 nm, 2.8 nm, or 3 nm. Of course, the second gate dielectric layer 42 may also have other thicknesses, which are not listed here. Subsequently, the first gate dielectric layer 41 may be formed between the second gate dielectric layer 42 and the sidewall of the semiconductor pillar 113 using an in-situ water vapor oxidation process. During the formation of the first gate dielectric layer 41, silicon ions in the semiconductor pillar 113 may be consumed, thereby thinning the semiconductor pillar 113. This can reserve a larger process window for subsequent processes and help reduce process complexity. It should be noted that since the side walls of the semiconductor column 113 are flat surfaces, during the in-situ water vapor oxidation process, each area of ​​the semiconductor column 113 is evenly consumed. Therefore, the probability of a corner structure appearing in a local area of ​​its surface (especially the area used to form the gate electrode layer 5) is low, so that the thickness of the gate dielectric layer 4 finally formed is relatively uniform.

[0118] In some embodiments of the present disclosure, the gate dielectric layer 4 may cover one side wall of the semiconductor column 113, or may cover the surfaces of two relatively distributed side walls in the semiconductor column 113, or may cover the entire side wall of the semiconductor column 113. No special limitation is imposed on the coverage area of ​​the gate dielectric layer 4.

[0119] Please continue to see Figure 5-Figure 7 As shown, the gate electrode layer 5 covers a portion of the surface of the gate dielectric layer 4. The gate electrode layer 5 may include a barrier layer and a conductive layer. The barrier layer is located between the conductive layer and the gate dielectric layer 4. The barrier layer may be made of titanium nitride, and the conductive layer may be made of tungsten. Titanium nitride can prevent tungsten from diffusing into the gate dielectric layer 4, thereby improving device stability. The semiconductor pillar 113, the gate dielectric layer 4, and the gate electrode layer 5 may together constitute a transistor. In the transistor, the relatively uniform thickness of the gate dielectric layer 4 in different regions makes the threshold voltage of different regions of the transistor relatively stable, and local leakage is less likely to occur. This improves the on-current, reduces structural defects, and improves product yield.

[0120] In some embodiments of the present disclosure, when the gate dielectric layer 4 covers the surfaces of two oppositely distributed sidewalls of the semiconductor pillar 113, the gate electrode layer 5 may cover the surfaces of two gate dielectric layers 4 located on two different sidewalls, thereby forming a dual-gate structure. When the gate dielectric layer 4 covers the entire sidewall of the semiconductor pillar 113, the gate electrode layer 5 may also surround the surface of the gate dielectric layer 4 on the sidewall of the semiconductor pillar 113, thereby forming a full-ring gate structure. It should be noted that in this embodiment, the gate electrode layer 5 may be strip-shaped and may extend along the first direction x, thereby covering the outer periphery of each semiconductor pillar 113 in the semiconductor pillar group 110.

[0121] In some embodiments of the present disclosure, please continue to refer to Figure 5-Figure 7 As shown, the semiconductor structure disclosed in the present invention may further include a passivation layer 7. The passivation layer 7 may be located on the surface of the gate electrode layer 5 and may fill the gap between the gate electrode layers 5 corresponding to two adjacent semiconductor column groups 110. The material of the passivation layer 7 may be an insulating material, for example, the material may be silicon nitride. The passivation layer 7 may be used to insulate and isolate the two adjacent gate electrode layers 5, thereby reducing the probability of short circuit or coupling between the two adjacent gate electrode layers 5.

[0122] The present disclosure also provides a method for forming a semiconductor structure, which is used to form the semiconductor structure in any of the above embodiments. Figure 8 A flow chart showing a method for forming a semiconductor structure of the present disclosure is shown in FIG. Figure 8 As shown, the forming method includes steps S110 to S160, wherein:

[0123] Step S110, forming a substrate 1, the substrate 1 including a plurality of first trenches 111 spaced apart along a first direction x and extending along a second direction y, and a plurality of second trenches 112 spaced apart along the second direction y and extending along the first direction x, wherein the second direction y intersects the first direction x; each of the first trenches 111 and each of the second trenches 112 divides a plurality of semiconductor pillars 113 in the substrate 1, and a plurality of semiconductor pillar groups 110 constitute a plurality of semiconductor pillar groups 110 spaced apart along the second direction y, wherein the semiconductor pillar groups 110 include a plurality of semiconductor pillars 113 spaced apart along the first direction x; and in a direction parallel to the substrate 1, the cross-sectional dimensions of the semiconductor pillars 113 are uniform everywhere.

[0124] Step S120 , forming a bit line structure 2 below the semiconductor pillar 113 , wherein the bit line structure 2 extends along the second direction y;

[0125] Step S130 , forming an insulating layer 3 at the bottom of the first trench 111 and the second trench 112 ;

[0126] Step S140 , forming a second gate dielectric layer 42 on the surface of the sidewall of each semiconductor pillar 113 in the semiconductor pillar group 110 that is not covered by the insulating layer 3 by an atomic layer deposition process;

[0127] Step S150 , forming a first gate dielectric layer 41 between the second gate dielectric layer 42 and the sidewall of the semiconductor pillar 113 by an in-situ water vapor oxidation process;

[0128] Step S160 , forming a gate electrode layer 5 covering a portion of the surface of the second gate dielectric layer 42 .

[0129] In the method for forming a semiconductor structure disclosed herein, the cross-sectional dimensions of the semiconductor pillar 113 are uniform in a direction parallel to the substrate 1, resulting in a flat sidewall surface for the semiconductor pillar 113. During the in-situ water vapor oxidation process, each region of the semiconductor pillar 113 is uniformly consumed. Consequently, the probability of corner structures forming in localized regions of its surface (particularly the region used to form the gate electrode layer 5) is low, resulting in a relatively uniform thickness of the ultimately formed gate dielectric layer 4 (including the first gate dielectric layer 41 and the second gate dielectric layer 42). The semiconductor pillar 113, the gate dielectric layer 4, and the gate electrode layer 5 can collectively constitute a transistor. In the transistor, the relatively uniform thickness of the gate dielectric layer 4 across different regions results in relatively stable threshold voltages across different regions, making local leakage less likely. This improves on-current, reduces structural defects, and improves product yield. Furthermore, during the formation of the second gate dielectric layer 42, silicon ions in the semiconductor pillar 113 are consumed, thereby thinning the semiconductor pillar 113. This can reserve a larger process window for subsequent processes and help reduce process complexity. At the same time, because the plurality of semiconductor pillars 113 are formed by dividing the first trenches 111 and the second trenches 112, the bitline structure 2 is located below the semiconductor pillars 113, and the insulating layer 3 is located at the bottom of the first trenches 111 and the second trenches 112. The insulating layer 3 can insulate and isolate the bitline structure 2 below the semiconductor pillars 113 from the subsequently formed gate electrode layer 5, thereby reducing the risk of short circuit or coupling between the bitline structure 2 and the gate electrode layer 5, and helping to further improve product yield. In addition, because the bitline structure 2 is buried below the semiconductor pillars 113, there is no need to design a space to accommodate the bitline structure 2, which facilitates the miniaturization of the product design and improves the product integration.

[0130] The following is a detailed description of the steps and details of the method for forming a semiconductor structure disclosed herein:

[0131] like Figure 8As shown, in step S110, a substrate 1 is formed, the substrate 1 including a plurality of first trenches 111 spaced apart along a first direction x and extending along a second direction y, and a plurality of second trenches 112 spaced apart along the second direction y and extending along the first direction x, wherein the second direction y intersects with the first direction x; each of the first trenches 111 and each of the second trenches 112 divides a plurality of semiconductor pillars 113 in the substrate 1, and the plurality of semiconductor pillar groups 110 are formed into a plurality of semiconductor pillar groups 110 spaced apart along the second direction y, and the semiconductor pillar groups 110 include a plurality of semiconductor pillars 113 spaced apart along the first direction x; in a direction parallel to the substrate 1, the cross-sectional dimensions of the semiconductor pillars 113 are equal everywhere.

[0132] like Figure 4 、 Figure 9 and Figure 10 As shown, substrate 1 may be plate-shaped and may include a plurality of first trenches 111 and a plurality of second trenches 112. Each first trench 111 and each second trench 112 may separate a plurality of semiconductor pillars 113 within substrate 1. The plurality of semiconductor pillars 113 may form a plurality of semiconductor pillar groups 110 distributed along a second direction y. Each semiconductor pillar group 110 may include a plurality of semiconductor pillars 113 spaced apart along a first direction x. The semiconductor pillars 113 may extend in a direction perpendicular to substrate 1. In a direction parallel to substrate 1, the cross-sections of the semiconductor pillars 113 may have the same shape and uniform dimensions. That is, the sidewalls of the semiconductor pillars 113 may be flat surfaces.

[0133] In some embodiments of the present disclosure, both the first direction x and the second direction y may be parallel to the substrate 1, and the first direction x may intersect with the second direction y; for example, the first direction x and the second direction y may be perpendicular to each other. It should be noted that perpendicularity can be absolutely perpendicular or approximately perpendicular, and deviations are inevitable during the manufacturing process. In the present disclosure, the angle deviation may be caused by manufacturing process limitations, resulting in a certain deviation in the angle between the first direction x and the second direction y. As long as the angular deviation between the first direction x and the second direction y is within a preset range, the first direction x and the second direction y may be considered perpendicular. For example, the preset range may be 10°, that is, the first direction x and the second direction y may be considered perpendicular when the angle between the first direction x and the second direction y is greater than or equal to 80° and less than or equal to 100°.

[0134] In an exemplary embodiment of the present disclosure, forming the substrate 1 may include steps S210 to S240, wherein:

[0135] Step S210: providing a substrate 11.

[0136] The substrate 11 may be a flat plate structure, which may be rectangular, circular, elliptical, polygonal or irregular in shape. Its material may be a semiconductor material, for example, its material may be silicon, but is not limited to silicon or other semiconductor materials. No special limitation is imposed on the shape and material of the substrate 11.

[0137] In step S220 , the substrate 11 is etched to form a plurality of first trenches 111 spaced apart along the first direction x and extending along the second direction y.

[0138] Please continue to see Figure 9 As shown, the substrate 11 can be etched by a dry etching process to form a plurality of first grooves 111 in the substrate 11. The first grooves 111 can be strip-shaped. The plurality of first grooves 111 can be spaced apart along the first direction x, and each first groove 111 can extend along the second direction y.

[0139] Step S230 , filling the first trench 111 with an insulating material 12 .

[0140] like Figure 11 As shown, the insulating material 12 can be filled into the first trenches 111 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Of course, other methods can also be used to fill the first trenches 111 with the insulating material 12, and the filling method of the insulating material 12 is not particularly limited here. The insulating material 12 can fill each first trench 111, and its surface can be flush with the surface of the substrate 11. In some embodiments of the present disclosure, the insulating material 12 can be silicon oxide.

[0141] In step S240 , the substrate 11 and the insulating material 12 are etched to form a plurality of second trenches 112 spaced apart along the second direction y and extending along the first direction x.

[0142] Please continue to see Figure 10 As shown, a dry etching process can be used to etch the structure formed by the substrate 11 and the insulating material 12, thereby forming a plurality of second trenches 112 extending along the first direction x and spaced apart along the second direction y. The depth of the second trenches 112 can be less than the depth of the first trenches 111. That is, after the second trenches 112 are formed, the insulating material 12 still remains at the bottom of the first trenches 111, and the portion of the substrate 11 above the bottom of the second trenches 112 can be used as the semiconductor pillars 113.

[0143] like Figure 8 As shown, in step S120 , a bit line structure 2 is formed below the semiconductor pillar 113 , and the bit line structure 2 extends along the second direction y.

[0144] After forming the semiconductor pillar 113, a bitline structure 2 can be embedded beneath the semiconductor pillar 113. Since the bitline structure 2 is embedded beneath the semiconductor pillar 113, there is no need to design a space to accommodate the bitline structure 2, which facilitates product miniaturization and improves product integration. The bitline structure 2 can be strip-shaped and extend along the second direction y. There can be multiple bitline structures 2, and the multiple bitline structures 2 can be spaced apart along the first direction x.

[0145] In some embodiments of the present disclosure, forming the bit line structure 2 may include steps S310 to S340, wherein:

[0146] Step S310 : forming bit line trenches (not shown in the figure) below the plurality of semiconductor pillars 113 distributed along the second direction y, wherein the bit line trenches extend along the second direction y.

[0147] The bottoms of the semiconductor pillar groups 110 distributed along the second direction y can be laterally etched through the second trenches 112 to form bitline trenches. The bitline trenches can be strip-shaped and penetrate the bottoms of the plurality of semiconductor pillars 113 in the second direction y. There can be multiple bitline trenches, and the plurality of bitline trenches can be spaced apart along the first direction x.

[0148] Step S320 , forming a bit line material layer in the bit line trench.

[0149] A bit line material layer (not shown) can be formed in the bit line trench by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The bit line material layer can be a composite film structure composed of multiple film layers. For example, it can include a conductive layer and a semiconductor layer, wherein the semiconductor layer is located between the conductive layer and the semiconductor pillar 113. For example, the material of the conductive layer can include tungsten, and the material of the semiconductor layer can be polysilicon.

[0150] Step S330 : forming a protection layer 6 on the sidewalls of the second trench 112 .

[0151] After forming the bit line material layer, a protective layer 6 may be formed on the sidewalls of the second trench 112. The protective layer 6 protects the sidewalls of the second trench 112 (i.e., the sidewalls of the semiconductor pillar 113) from damage during subsequent processes. The protective layer 6 may be made of the same material as the insulating material 12 remaining at the bottom of the first trench 111. For example, both the protective layer 6 and the insulating material 12 remaining at the bottom of the first trench 111 may be silicon oxide.

[0152] Step S340 , performing ion implantation into the bit line material layer through the second trench 112 to form a bit line structure 2 .

[0153] After forming the protection layer 6 , ion implantation may be performed on the bit line material layer to adjust the work function of the bit line material layer. The bit line material layer after ion implantation may be used as the bit line structure 2 .

[0154] In an exemplary embodiment of the present disclosure, before forming the insulating layer 3, the forming method of the present disclosure may further include step S410 and step S420, wherein:

[0155] Step S410 , filling the second trench 112 having the protection layer 6 with the insulating material 12 , so that the second trench 112 is completely filled with the insulating material 12 .

[0156] like Figure 13 As shown, the insulating material 12 can be deposited on the surface of the substrate 1 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition until the insulating material 12 fills the second trench 112, and then the surface of the insulating material 12 can be planarized. It should be noted that the insulating material 12 and the protective layer 6 are made of the same material, for example, silicon oxide.

[0157] In step S420 , the insulating material 12 and the protection layer 6 are etched using the bottom of the second trench 112 as a stop layer to expose sidewalls of the semiconductor pillar 113 adjacent to the first trench 111 and the second trench 112 .

[0158] The insulating material 12 in the first trench 111 and the second trench 112 can be etched by dry etching or wet etching. In this process, since the material of the protective layer 6 is the same as that of the insulating material 12, the protective layer 6 on the sidewall of the second trench 112 can be removed at the same time, thereby exposing the sidewalls of each semiconductor pillar 113. The structure after completing step S420 is the same as that of FIG. Figure 10 similar.

[0159] like Figure 8 As shown, in step S130 , an insulating layer 3 is formed at the bottom of the first trench 111 and the second trench 112 .

[0160] Please continue to see Figure 5-Figure 7 As shown, the insulating layer 3 can be located at the bottom of the first trench 111 and the second trench 112. The insulating layer 3 can insulate and isolate the bit line structure 2 below the semiconductor pillar 113 from the subsequently formed gate electrode layer 5, thereby reducing the risk of short circuit or coupling between the bit line structure 2 and the gate electrode layer 5, and helping to further improve product yield. The insulating layer 3 can be a single-layer film structure composed of a single material or a composite film structure composed of multiple materials, without particular limitation herein.

[0161] like Figure 8As shown, in step S140 , a second gate dielectric layer 42 is formed on the surface of the sidewall of each semiconductor pillar 113 in the semiconductor pillar group 110 that is not covered by the insulating layer 3 by an atomic layer deposition process.

[0162] Please continue to see Figure 5 and Figure 6 As shown, the second gate dielectric layer 42 may cover one sidewall of the semiconductor pillar 113, or may cover the surfaces of two oppositely distributed sidewalls of the semiconductor pillar 113, or may cover the entire sidewall of the semiconductor pillar 113. The coverage area of ​​the second gate dielectric layer 42 is not particularly limited herein. The material of the second gate dielectric layer 42 may be silicon oxide, and its thickness may be 2 nm to 3 nm. For example, its thickness may be 2 nm, 2.2 nm, 2.4 nm, 2.6 nm, 2.8 nm, or 3 nm. Of course, the second gate dielectric layer 42 may also have other thicknesses, which are not listed here.

[0163] like Figure 8 As shown, in step S150 , an in-situ water vapor oxidation process is used to form a first gate dielectric layer 41 between the second gate dielectric layer 42 and the sidewall of the semiconductor pillar 113 .

[0164] Please continue to see Figure 5 and Figure 6 As shown, the material of the first gate dielectric layer 41 is the same as that of the second gate dielectric layer 42. For example, the material of the first gate dielectric layer 41 and the second gate dielectric layer 42 can both be silicon oxide. In the process of forming the first gate dielectric layer 41, silicon ions in the semiconductor column 113 can be consumed, thereby thinning the semiconductor column 113, which can reserve a larger process window for subsequent processes and help reduce the difficulty of the process. It should be noted that since the sidewalls of the semiconductor column 113 are flat surfaces, during the in-situ water vapor oxidation process, each area of ​​the semiconductor column 113 is evenly consumed. Therefore, the probability of a corner structure appearing in a local area of ​​its surface (especially the area for forming the gate electrode layer 5) is low, so that the thickness of the finally formed gate dielectric layer 4 (including the first gate dielectric layer 41 and the second gate dielectric layer 42) is relatively uniform.

[0165] The following describes in detail the formation methods of the insulating layer 3, the first gate dielectric layer 41, and the second gate dielectric layer 42 of the present disclosure through three embodiments:

[0166] In the first embodiment of the present disclosure, forming the insulating layer 3, the first gate dielectric layer 41, and the second gate dielectric layer 42 includes steps S510 to S540, wherein:

[0167] Step S510, forming a second insulating layer 312 and a first insulating layer 311 in the first trench 111 and the second trench 112, the second insulating layer 312 conformally covering the bottom and side walls of the first trench 111 and the second trench 112, the top of the second insulating layer 312 is lower than the top surface of the semiconductor pillar 113, the first insulating layer 311 is located on the surface of the second insulating layer 312, and is flush with the top of the second insulating layer 312.

[0168] The first insulating layer 311 and the second insulating layer 312 can both be thin films formed in the first trench 111 and the second trench 112. The material of the first insulating layer 311 is different from the material of the second insulating layer 312. For example, the material of the first insulating layer 311 can be silicon nitride, and the material of the second insulating layer 312 can be silicon oxide. Figure 14 shown.

[0169] In the first embodiment of the present disclosure, forming the first insulating layer 311 and the second insulating layer 312 may include steps S5101 to S5103, wherein:

[0170] Step S5101 : forming a second insulating material 320 conformally covering the inner wall of the first trench 111 and the inner wall of the second trench 112 .

[0171] like Figure 15 As shown, the second insulating material 320 can be deposited in the first groove 111 and the second groove 112 by chemical vapor deposition, physical vapor deposition or atomic layer deposition. The second insulating material 320 can conformally cover the inner wall surfaces of the first groove 111 and the second groove 112. Of course, the second insulating material 320 can also be deposited by other methods. No special limitation is made to the deposition method of the second insulating material 320.

[0172] Step S5102 , forming a first insulating material 310 in the first trench 111 and the second trench 112 having the second insulating material 320 .

[0173] The first insulating material 310 may be continuously deposited in the first trench 111 and the second trench 112 having the second insulating material 320 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition until the first insulating material 310 fills the first trench 111 and the second trench 112. The first insulating material 310 is different from the second insulating material 320. For example, the first insulating material 310 may be silicon nitride, and the second insulating material 320 may be silicon oxide. After the first insulating material 310 is deposited, the surfaces of the first insulating material 310 and the second insulating material 320 may be chemically mechanically polished so that the surfaces of the first insulating material 310 and the second insulating material 320 are flush with the top surface of the semiconductor pillar 113. The structure after completing step S5102 in the first embodiment of the present disclosure is as follows: Figure 15 shown.

[0174] Step S5103 , etching back the first insulating material 310 to form the first insulating layer 311 ; etching back the second insulating material 320 to form the second insulating layer 312 .

[0175] The first insulating material 310 and the second insulating material 320 may be etched back so that the top surfaces of the first insulating material 310 and the second insulating material 320 are lower than the top surfaces of the semiconductor pillars 113, thereby exposing the sidewalls of each semiconductor pillar 113. It should be noted that the remaining first insulating material 310 may be used as the first insulating layer 311, and the remaining second insulating material 320 may be used as the second insulating layer 312.

[0176] In step S520 , the second insulating layer 312 between the first insulating layer 311 and the sidewall of the semiconductor pillar 113 is removed to form a first gap 301 .

[0177] The second insulating layer 312 between the first insulating layer 311 and the semiconductor pillar 113 can be removed, and the second insulating layer 312 below the first insulating layer 311 can be retained. The gap formed between the first insulating layer 311 and the semiconductor pillar 113 after the second insulating layer 312 is removed can be used as the first gap 301. In the first embodiment of the present disclosure, the structure after completing step S520 is as follows Figure 16 shown.

[0178] In step S530 , a second dielectric layer 420 is formed on the surface of the structure formed by the first insulating layer 311 and the semiconductor pillars 113 by using an atomic layer deposition process.

[0179] like Figure 17As shown, the material of the second dielectric layer 420 can be silicon oxide. After forming the first gap 301, the second dielectric layer 420 can be formed on the surface of the exposed sidewall of the semiconductor pillar 113 using atomic layer deposition. To facilitate the subsequent formation of the first dielectric layer 410 between the second dielectric layer 420 and the sidewall of the semiconductor pillar 113 through an in-situ water vapor oxidation process, the thickness of the second dielectric layer 420 can be set to 2 nm to 3 nm. This thickness range ensures that oxygen atoms can pass through the second dielectric layer 420 during the in-situ water vapor oxidation process. Conversely, if the second dielectric layer 420 is too thick, oxygen atoms cannot pass through the second dielectric layer 420 during the in-situ water vapor oxidation process, and the first dielectric layer 410 of the required thickness cannot be formed. In the above process, for process convenience, the second dielectric layer 420 can be formed simultaneously on the surface of the first insulating layer 311.

[0180] In step S540, a first dielectric layer 410 is formed between the second dielectric layer 420 and the sidewall of the semiconductor pillar 113 using an in-situ water vapor oxidation process. The first dielectric layer 410 and the second dielectric layer 420 fill the first gap 301. The first insulating layer 311, the first dielectric layer 410 and the second dielectric layer 420 located on the surface of the first insulating layer 311, the first dielectric layer 410 and the second dielectric layer 420 located between the first insulating layer 311 and the semiconductor pillar 113, and the second insulating layer 312 located at the bottom of the first insulating layer 311 serve as the insulating layer 3. The first dielectric layer 410 located on the side of the insulating layer 3 away from the bit line structure 2 serves as the first gate dielectric layer 41, and the second dielectric layer 420 located on the side of the insulating layer 3 away from the bit line structure 2 serves as the second gate dielectric layer 42.

[0181] In the process of forming the first dielectric layer 410, silicon ions in the semiconductor column 113 can be consumed, thereby thinning the semiconductor column 113, which can reserve a larger process window for subsequent processes and help reduce the difficulty of the process. It should be noted that since the sidewalls of the semiconductor column 113 are flat surfaces, during the in-situ water vapor oxidation process, each area of ​​the semiconductor column 113 is evenly consumed. Therefore, the probability of a corner structure appearing in a local area of ​​its surface (especially the area used to form the gate electrode layer 5) is low, so that the thickness of the first dielectric layer 410 finally formed is relatively uniform. The structure after completing step S540 in the first embodiment of the present disclosure is as follows: Figure 17 shown.

[0182] In the first embodiment of the present disclosure, the first insulating layer 311 can be used as the first insulating material layer 31, and the second insulating layer 312 remaining at the bottom of the first insulating layer 311, the first dielectric layer 410 and the second dielectric layer 420 located between the first insulating layer 311 and the semiconductor pillar 113, and the first dielectric layer 410 and the second dielectric layer 420 located on the top of the first insulating layer 311 can be used as the second insulating material layer 32. The first insulating material layer 31 and the second insulating material layer 32 together constitute the insulating layer 3.

[0183] In the second embodiment of the present disclosure, forming the insulating layer 3, the first gate dielectric layer 41, and the second gate dielectric layer 42 includes steps S610 to S650, wherein:

[0184] Step S610 : forming a second insulating layer 312 on sidewalls of the first trench 111 and the second trench 112 .

[0185] A second insulating layer 312 can be formed on the sidewalls of the first trench 111 and the second trench 112 by chemical vapor deposition, physical vapor deposition or atomic layer deposition. The second insulating layer 312 can conformally cover the bottom of the sidewalls of the first trench 111 and the second trench 112, that is, the top of the second insulating layer 312 is lower than the top surface of the semiconductor pillar 113. After the second insulating layer 312 is formed, part of the sidewall of the semiconductor pillar 113 can still be exposed.

[0186] Step S620 , forming a first insulating layer 311 in the first trench 111 having the second insulating layer 312 and in the second trench 112 , wherein the top of the second insulating layer 312 is lower than the top surface of the semiconductor pillar 113 , and the first insulating layer 311 is flush with the top of the second insulating layer 312 .

[0187] The first insulating layer 311 may be formed in the first trench 111 and the second trench 112 having the second insulating layer 312 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The material of the first insulating layer 311 is different from that of the second insulating layer 312. For example, the material of the first insulating layer 311 may be silicon nitride, and the material of the second insulating layer 312 may be silicon oxide. In the second embodiment of the present disclosure, the structure after completing step S620 is as follows: Figure 18 shown.

[0188] It should be noted that the specific formation method of the first insulating layer 311 and the second insulating layer 312 is similar to the formation method of the first insulating layer 311 and the second insulating layer 312 in the first embodiment of the present disclosure, and therefore, it is not repeated here.

[0189] In step S630 , the second insulating layer 312 is removed to form a second gap 302 .

[0190] After forming the first insulating layer 311, the second insulating layer 312 can be removed by wet etching or dry etching, and the gap formed between the first insulating layer 311 and the semiconductor pillar 113 after removing the second insulating layer 312 can be used as the second gap 302. In the second embodiment of the present disclosure, the structure after completing step S630 is as follows Figure 19 shown.

[0191] In step S640 , a second dielectric layer 420 is formed on the surface of the structure formed by the first insulating layer 311 and the semiconductor pillars 113 by using an atomic layer deposition process.

[0192] In step S650, an in-situ water vapor oxidation process is used to form a first dielectric layer 410 between the second dielectric layer 420 and the sidewall of the semiconductor pillar 113. The first dielectric layer 410 and the second dielectric layer 420 fill the second gap 302. The first insulating layer 311, the first dielectric layer 410 and the second dielectric layer 420 located on the surface of the first insulating layer 311, and the first dielectric layer 410 and the second dielectric layer 420 located between the first insulating layer 311 and the semiconductor pillar 113 serve as the insulating layer 3. The first dielectric layer 410 located on the side of the insulating layer 3 away from the bit line structure 2 serves as the first gate dielectric layer 41, and the second dielectric layer 420 located on the side of the insulating layer 3 away from the bit line structure 2 serves as the second gate dielectric layer 42.

[0193] It should be noted that, in the second embodiment of the present disclosure, the specific details of forming the first dielectric layer 410 and the second dielectric layer 420 are similar to the process of forming the first dielectric layer 410 and the second dielectric layer 420 in the first embodiment of the present disclosure, and therefore, they will not be repeated here. In the second embodiment of the present disclosure, the first insulating layer 311 serves as the first insulating material layer 31, and the second insulating layer 312 is not provided at the bottom of the first insulating layer 311. The first dielectric layer 410 and the second dielectric layer 420 located between the first insulating layer 311 and the semiconductor pillar 113 and the first dielectric layer 410 and the second dielectric layer 420 located on the top of the first insulating layer 311 together constitute the second insulating material layer 32, and the first insulating material layer 31 and the second insulating material layer 32 together constitute the insulating layer 3. The structure after completing step S650 in the second embodiment of the present disclosure is as follows: Figure 20 shown.

[0194] In the third embodiment of the present disclosure, forming the insulating layer 3, the first gate dielectric layer 41, and the second gate dielectric layer 42 includes steps S710 to S730, wherein:

[0195] In step S710, a first insulating layer 311 is formed at the bottom of the first trench 111 and the second trench 112, wherein the first insulating layer 311 includes a first portion 3111 and a second portion 3112 adjacent to each other, wherein the first portion 3111 covers the entire bottom surface of the first trench 111 and the second trench 112, and the second portion 3112 is located on a surface of the first portion 3111 away from the bit line structure 2, and a third gap 303 is provided between the second portion 3112 and the semiconductor pillar 113.

[0196] The first portion 3111 and the second portion 3112 are made of the same material. For example, the first portion 3111 and the second portion 3112 can both be made of silicon nitride. The first portion 3111 can fill the area with a curvature or corner at the bottom of the first trench 111 and the second trench 112. The second portion 3112 is located on the surface of the first portion 3111 and has no contact with the sidewall of the semiconductor pillar 113. In the second embodiment of the present disclosure, the structure after completing step S710 is as follows: Figure 21 shown.

[0197] In the third embodiment of the present disclosure, forming the first insulating layer 311 may include steps S810 to S850, wherein:

[0198] In step S810 , a first insulating material 310 is formed at the bottom of the first trench 111 and the second trench 112 to serve as a first portion 3111 of the first insulating layer 311 .

[0199] The first insulating material 310 can be deposited on the surface of the substrate 1 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. At the same time, the first insulating material 310 can fill the first trench 111 and the second trench 112. The first insulating material 310 can then be etched back to only retain the first insulating material 310 at the bottom of the first trench 111 and the second trench 112. The first insulating material 310 that is finally retained is used as the first portion 3111 of the first insulating layer 311. In the third embodiment of the present disclosure, the structure after completing step S810 is as follows: Figure 22 shown.

[0200] Step S820 , forming a second insulating material 320 conformally covering the sidewalls of the first trench 111 and the second trench 112 .

[0201] like Figure 23As shown, a second insulating material 320 is formed in the first trench 111 and the second trench 112 having the first portion 3111 of the first insulating layer 311. Subsequently, the second insulating material 320 can be etched back to remove the second insulating material 320 located on the surface of the first portion 3111 of the first insulating layer 311, leaving only the second insulating material 320 located on the sidewalls of the first trench 111 and the second trench 112. The second insulating material 320 is different from the first insulating material 310. For example, the second insulating material 320 can be silicon oxide.

[0202] Step S830 , forming a third insulating material 330 on the surface of the structure formed by the first insulating material 310 and the second insulating material 320 .

[0203] The third insulating material 330 is different from the second insulating material 320. For example, the third insulating material 330 may be silicon nitride. The third insulating material 330 may be deposited in the first trench 111 and the second trench 112 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The third insulating material 330 may fill the remaining space in the first trench 111 and the second trench 112. The tops of the third insulating material 330 and the second insulating material 320 may be chemically mechanically polished to make the tops of the first insulating material 310 and the second insulating material 320 flush. In the third embodiment of the present disclosure, the structure after completing step S830 is as follows. Figure 23 shown.

[0204] In step S840 , the second insulating material 320 and the third insulating material 330 are etched back so that the tops of the second insulating material 320 and the third insulating material 330 are lower than the surface of the semiconductor pillar 113 .

[0205] The second insulating material 320 and the third insulating material 330 can be etched back by a dry etching process to expose the sidewalls of the semiconductor pillar 113. The etching gas can be set according to the second insulating material 320 and the third insulating material 330, as long as the second insulating material 320 and the third insulating material 330 can be removed without damaging the surface of the semiconductor pillar 113. In the third embodiment of the present disclosure, the structure after completing step S840 is as follows: Figure 24 shown.

[0206] Step S850 , removing the second insulating material 320 , and using the remaining third insulating material 330 as the second portion 3112 of the first insulating layer 311 .

[0207] Please continue to see Figure 21As shown, the second insulating layer 312 can be removed by wet etching or dry etching, and the gap between the second portion 3112 of the first insulating layer 311 and the semiconductor pillar 113 after removing the second insulating material 320 is used as the third gap 303 .

[0208] In step S720 , a second dielectric layer 420 is formed on the surface of the structure formed by the first insulating layer 311 and the semiconductor pillars 113 by using an atomic layer deposition process.

[0209] In step S730, a first dielectric layer 410 is formed between the second dielectric layer 420 and the sidewall of the semiconductor pillar 113 using an in-situ water vapor oxidation process. The first dielectric layer 410 and the second dielectric layer 420 fill the third gap 303. The first insulating layer 311, the first dielectric layer 410 and the second dielectric layer 420 located on the surface of the first insulating layer 311, and the first dielectric layer 410 and the second dielectric layer 420 located between the first insulating layer 311 and the semiconductor pillar 113 serve as the insulating layer 3. The first dielectric layer 410 located on the side of the insulating layer 3 away from the bit line structure 2 serves as the first gate dielectric layer 41, and the second dielectric layer 420 located on the side of the insulating layer 3 away from the bit line structure 2 serves as the second gate dielectric layer 42.

[0210] It should be noted that in the third embodiment of the present disclosure, the specific details of forming the first dielectric layer 410 and the second dielectric layer 420 are similar to the process of forming the first dielectric layer 410 and the second dielectric layer 420 in the second embodiment of the present disclosure, and therefore, are not further described here. In the third embodiment of the present disclosure, the remaining first portion 3111 can be used as the first insulating material layer 311, the remaining second portion can be used as the second insulating material layer 312, and the first dielectric layer 410 and the second dielectric layer 420 located on the surface of the second insulating material layer 312 and the first dielectric layer 410 and the second dielectric layer 420 located between the second insulating material layer 312 and the semiconductor pillar 113 can be used as the third insulating material layer 33. The first insulating material layer 31, the second insulating material layer 32, and the third insulating material layer 33 together constitute the insulating layer 3.

[0211] like Figure 8 As shown, in step S160 , a gate electrode layer 5 is formed to cover a portion of the surface of the second gate dielectric layer 42 .

[0212] Please continue to see Figure 5-Figure 7As shown, the material of the gate electrode layer 5 may be a conductive material, for example, it may include titanium nitride, tungsten or polysilicon. The gate electrode layer 5 may be formed on the surface of the second gate dielectric layer 42 by chemical vapor deposition, physical vapor deposition or atomic layer deposition. Of course, the gate electrode layer 5 may also be formed by other methods. The formation method of the gate electrode layer 5 is not particularly limited here. In some embodiments of the present disclosure, when the second gate dielectric layer 42 covers the surfaces of two oppositely distributed side walls in the semiconductor column 113, the gate electrode layer 5 may respectively cover the surfaces of the two second gate dielectric layers 42, thereby forming a dual-gate structure; or, when the second gate dielectric layer 42 covers the side walls of the semiconductor column 113, the gate electrode layer 5 may extend along the first direction x and wrap around the outer periphery of each semiconductor column 113 in the semiconductor column group 110 distributed along the first direction x, thereby forming a full-ring gate structure.

[0213] In an exemplary embodiment of the present disclosure, the forming method of the present disclosure may further include:

[0214] In step S170 , a passivation layer 7 is formed on the surface of the gate electrode layer 5 , and the passivation layer 7 fills the gap between the gate electrode layers 5 corresponding to two adjacent semiconductor column groups 110 .

[0215] After forming the gate electrode layer 5, a passivation layer 7 may be formed on the surface of the gate electrode layer 5. The material of the passivation layer 7 is the same as that of the first insulating layer 311. For example, the material of the passivation layer 7 and the first insulating layer 311 may both be silicon nitride. The surface of the gate electrode layer 5 may be insulated and isolated by the passivation layer 7, which may help reduce the risk of short circuits between the gate electrode layer 5 and other subsequently formed structures, thereby improving product yield. Figure 4 The cross-section taken in the bb' direction is as follows Figure 25 In the third embodiment of the present disclosure, step S170 is completed along the back edge. Figure 4 The cross-section taken in the bb' direction is as follows Figure 26 shown.

[0216] It should be noted that although the steps of the method for forming a semiconductor structure in the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all steps must be performed to achieve the desired results. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps.

[0217] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A semiconductor structure, characterized in that include: a substrate comprising a plurality of first grooves spaced apart along a first direction and extending along a second direction, and a plurality of second grooves spaced apart along the second direction and extending along the first direction, wherein the second direction intersects the first direction; Each of the first trenches and each of the second trenches divides a plurality of semiconductor pillars in the substrate, the plurality of semiconductor pillars forming a plurality of semiconductor pillar groups distributed along the second direction, the semiconductor pillar groups including a plurality of semiconductor pillars spaced apart and distributed along the first direction; in a direction parallel to the substrate, the cross-sectional dimensions of the semiconductor pillars are uniform everywhere; a bit line structure, located below the semiconductor pillar and extending along the second direction; an insulating layer, located at the bottom of the first trench and the second trench; a gate dielectric layer, located on a surface of a sidewall of each semiconductor column in the semiconductor column group that is not covered by the insulating layer; a gate electrode layer, covering a portion of the surface of the gate dielectric layer; Wherein, the insulating layer at least includes: a first insulating layer, located at the bottom of the first trench and the second trench; a third insulating layer, comprising a portion of the second dielectric layer located on a top surface of the first insulating layer and between the first insulating layer and the semiconductor pillar; The gate dielectric layer includes: a second gate dielectric layer, including a portion of the second dielectric layer located on a side of the insulating layer away from the bit line structure; The second dielectric layer is located on the surface of the structure formed by the first insulating layer and the semiconductor pillar.

2. The semiconductor structure according to claim 1, wherein: The insulating layer further comprises: a second insulating layer, located at the bottom of the first trench and the second trench, and at the bottom of the first insulating layer; The second insulating layer and the third insulating layer conformally cover the bottom, sidewall and top surface of the first insulating layer.

3. The semiconductor structure according to claim 1, wherein: In the insulating layer: The first insulating layer covers a portion of the bottom surface of the first trench and the second trench, and has a first preset gap with the semiconductor column; The third insulating layer covers the surface of the first insulating layer and fills the first preset gap.

4. The semiconductor structure according to claim 2, wherein: The material of the first insulating layer is silicon nitride, and the material of the second insulating layer is silicon oxide.

5. The semiconductor structure according to claim 1, wherein: In the insulating layer: The first insulating layer includes a first portion and a second portion, the first portion covers the entire bottom surface of the first trench and the second trench; the second portion is located on the surface of the first portion and has a second preset gap with the semiconductor pillar; The third insulating layer covers the surface of the first insulating layer and fills the second preset gap.

6. The semiconductor structure according to claim 5, wherein: The first portion of the first insulating layer and the second portion of the first insulating layer are both made of silicon nitride, and the third insulating layer is made of silicon oxide.

7. The semiconductor structure according to any one of claims 1 to 6, wherein: The third insulating layer further includes: a portion of a first dielectric layer located on a top surface of the first insulating layer and between the first insulating layer and the semiconductor pillar; The gate dielectric layer further includes: a first gate dielectric layer, including a portion of the first dielectric layer located on a side of the insulating layer away from the bit line structure; Wherein, the first dielectric layer is located between the second dielectric layer and the sidewall of the semiconductor column.

8. A method for forming a semiconductor structure, characterized in that: include: forming a substrate comprising a plurality of first trenches spaced apart along a first direction and extending along a second direction, and a plurality of second trenches spaced apart along the second direction and extending along the first direction, wherein the second direction intersects the first direction; Each of the first trenches and each of the second trenches divides a plurality of semiconductor pillars in the substrate, the plurality of semiconductor pillars forming a plurality of semiconductor pillar groups distributed along the second direction, the semiconductor pillar groups including a plurality of semiconductor pillars spaced apart and distributed along the first direction; in a direction parallel to the substrate, the cross-sectional dimensions of the semiconductor pillars are uniform everywhere; forming a bit line structure below the semiconductor pillar, wherein the bit line structure extends along the second direction; forming an insulating layer at the bottom of the first trench and the second trench, the insulating layer comprising at least a first insulating layer and a third insulating layer, wherein a gap is formed between a sidewall of the first insulating layer and a sidewall of the semiconductor pillar; forming a second dielectric layer on a surface of a structure formed by the first insulating layer and the semiconductor pillar using an atomic layer deposition process; using a portion of the second dielectric layer located on a top surface of the first insulating layer and between the first insulating layer and the semiconductor pillar as the third insulating layer, and using a portion of the second dielectric layer located on a side of the insulating layer away from the bit line structure as a second gate dielectric layer; A gate electrode layer is formed to cover a portion of the surface of the second gate dielectric layer.

9. The forming method according to claim 8, wherein: The thickness of the second gate dielectric layer is 2 nm to 3 nm.

10. The forming method according to claim 8 or 9, characterized in that: Forming the substrate includes: providing a substrate; Etching the substrate to form a plurality of first grooves spaced apart along a first direction and extending along a second direction; filling the first trench with an insulating material; Etching the substrate and the insulating material to form a plurality of second trenches spaced apart along the second direction and extending along the first direction; Forming the bit line structure includes: forming a bit line trench below the plurality of semiconductor pillars distributed along the second direction, wherein the bit line trench extends along the second direction; forming a bit line material layer in the bit line trench; forming a protective layer on sidewalls of the second trench; Ions are implanted into the bit line material layer through the second trench to form a bit line structure.

11. The forming method according to claim 10, wherein: Before forming the insulating layer, the forming method further includes: Filling the second trench having the protection layer with the insulating material so that the second trench is completely filled with the insulating material; The insulating material and the protection layer are etched with the bottom of the second trench as a stop layer to expose sidewalls of the semiconductor pillar adjacent to the first trench and the second trench.

12. The forming method according to claim 11, wherein: An insulating layer is formed at the bottom of the first trench and the second trench, the insulating layer comprising at least a first insulating layer and a third insulating layer, wherein a gap is formed between a sidewall of the first insulating layer and a sidewall of the semiconductor pillar, comprising: A second insulating layer and the first insulating layer are formed in the first trench and the second trench, the second insulating layer conformally covering the bottom and sidewalls of the first trench and the second trench, the top of the second insulating layer is lower than the top surface of the semiconductor column, the first insulating layer is located on the surface of the second insulating layer and is flush with the top of the second insulating layer, and the second insulating layer located between the first insulating layer and the sidewall of the semiconductor column is removed to form a first gap.

13. The forming method according to claim 12, wherein: Forming the first insulating layer and the second insulating layer includes: forming a second insulating material conformally covering an inner wall of the first trench and an inner wall of the second trench; forming a first insulating material in the first trench having the second insulating material and in the second trench; The first insulating material is etched back to form the first insulating layer; and the second insulating material is etched back to form the second insulating layer.

14. The forming method according to claim 11, wherein: An insulating layer is formed at the bottom of the first trench and the second trench, the insulating layer comprising at least a first insulating layer and a third insulating layer, wherein a gap is formed between a sidewall of the first insulating layer and a sidewall of the semiconductor pillar, comprising: forming a second insulating layer on sidewalls of the first trench and the second trench; forming the first insulating layer in the first trench having the second insulating layer and in the second trench, wherein the top of the second insulating layer is lower than the top surface of the semiconductor pillar, and the top of the first insulating layer is flush with the top of the second insulating layer; The second insulating layer is removed to form a second gap.

15. The forming method according to claim 11, wherein: An insulating layer is formed at the bottom of the first trench and the second trench, the insulating layer comprising at least a first insulating layer and a third insulating layer, wherein a gap is formed between a sidewall of the first insulating layer and a sidewall of the semiconductor pillar, comprising: The first insulating layer is formed at the bottom of the first trench and the second trench, and the first insulating layer includes a first portion and a second portion adjacent to each other, the first portion covers the entire bottom surface of the first trench and the second trench, and the second portion is located on the surface of the first portion away from the bit line structure, and a third gap is provided between the second portion and the semiconductor pillar.

16. The forming method according to any one of claims 12 to 15, characterized in that: The material of the first insulating layer is silicon nitride, and the material of the second dielectric layer is silicon oxide.

17. The forming method according to claim 8 or 9, characterized in that: The forming method further comprises: An in-situ water vapor oxidation process is used to form a first dielectric layer between the second dielectric layer and the sidewall of the semiconductor pillar, and a portion of the first dielectric layer located on the top surface of the first insulating layer and between the first insulating layer and the semiconductor pillar is used as the third insulating layer, and a portion of the first dielectric layer located on a side of the insulating layer away from the bit line structure is used as the first gate dielectric layer.

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