Semiconductor structure and preparation method thereof

Abstract

Embodiments of the present disclosure provide a semiconductor structure and a method for fabricating the same, relating to the field of semiconductor technology and designed to address the technical issue of leakage between adjacent bit lines. The method includes: forming a plurality of active pillars arranged in an array along a first direction and a second direction within a substrate, wherein the first direction and the second direction intersect and are perpendicular to the extension direction of the active pillars; forming a plurality of bit line trenches and a bit line isolation structure for separating the bit line trenches; wherein each bit line trench exposes the outer peripheral surfaces of the plurality of active pillars arranged along the second direction, and the bottom of the bit line trench is higher than the bottom surface of the bit line isolation structure; and forming a bit line within each bit line trench, wherein the bit line extends along the second direction and wraps around at least a portion of the outer peripheral surfaces of the plurality of active pillars arranged along the second direction. The present disclosure is used to increase the height of the bit line isolation structure, thereby preventing leakage between adjacent bit lines.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] As semiconductor structures develop towards greater integration, their size is shrinking. For example, in the fabrication process of dynamic random access memory (DRAM), when a vertical gate-all-around (GAA) transistor is used as an access transistor, the area occupied by it can reach 4F2, increasing the number of memory cells per unit area and thus improving the arrangement density.

[0003] However, leakage is likely to occur between adjacent bit lines in the above-mentioned semiconductor structure, thereby reducing the yield of the semiconductor structure. Summary of the Invention

[0004] In view of the above problems, embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, which are used to prevent leakage between adjacent bit lines and improve the yield of the semiconductor structure.

[0005] A first aspect of the present disclosure provides a method for preparing a semiconductor structure, comprising:

[0006] Providing a substrate, forming a plurality of active pillars arranged in an array along a first direction and a second direction in the substrate, wherein the first direction intersects the second direction, and the first direction and the second direction are both perpendicular to the extension direction of the active pillars;

[0007] forming a plurality of bit line trenches and a bit line isolation structure for separating the bit line trenches, wherein the plurality of bit line trenches are spaced apart along the first direction and extend along the second direction; wherein each of the bit line trenches exposes the outer peripheral surfaces of the plurality of active pillars arranged along the second direction, and the bottom of the bit line trench is higher than the bottom surface of the bit line isolation structure;

[0008] A bit line is formed in each of the bit line trenches. The bit line extends along the second direction and wraps around at least a portion of outer peripheral surfaces of a plurality of active pillars arranged along the second direction.

[0009] In some embodiments, the step of providing the substrate comprises:

[0010] The substrate is patterned to form a plurality of first grooves arranged at intervals along the first direction and a plurality of second grooves arranged at intervals along the second direction in the substrate, wherein the first grooves and the second grooves separate the substrate into a plurality of active pillars; wherein the first grooves extend along the second direction, the second grooves extend along the first direction; and the groove width of the first groove is greater than the groove width of the second groove.

[0011] In some embodiments, the step of forming a plurality of the bit line trenches and the bit line isolation structures includes:

[0012] forming a sacrificial layer, the sacrificial layer covering the inner wall of the first trench and filling the area between the active pillars adjacent to each other in the second direction; the sacrificial layer enclosing a third trench in the first trench;

[0013] removing the sacrificial layer on the bottom wall of the third trench and a portion of the thickness of the substrate below the bottom wall of the third trench to form a bit line isolation trench;

[0014] forming the bit line isolation structure in the bit line isolation trench;

[0015] The remaining sacrificial layer is removed to form the bit line trench, wherein the bottom wall of the bit line trench is higher than the bottom surface of the bit line isolation structure.

[0016] In some embodiments, the step of removing the sacrificial layer on the bottom wall of the third trench includes:

[0017] Injecting plasma into the third trench through a plasma etching process to remove the sacrificial layer on the bottom wall of the third trench and a portion of the thickness of the substrate below the bottom wall of the third trench;

[0018] Wherein, the injection direction of the plasma is perpendicular to the top surface of the substrate.

[0019] In some embodiments, the bit line isolation structure and the sacrificial layer have a large etching selectivity ratio, so that the bit line isolation structure serves as an etching stop layer during the process of removing the remaining sacrificial layer.

[0020] In some embodiments, the step of forming a bit line in the bit line trench includes:

[0021] forming a barrier material layer on an inner wall of the bit line trench, wherein the barrier material layer also covers a top surface of the active pillar;

[0022] forming a metal conductive material layer on the barrier material layer, wherein the metal conductive material layer completely fills the area surrounded by the barrier material layer;

[0023] The barrier material layer and the metal conductive material layer are etched back to form the bit line, and the top surface of the bit line is lower than the top surface of the substrate; wherein the bit line includes a barrier layer and a metal conductive layer, the retained barrier material layer forms the barrier layer, the retained metal conductive material layer forms the metal conductive layer, and the barrier layer is wrapped around the bottom and side surfaces of the metal conductive layer.

[0024] In some embodiments, the width of the first trench is 1.5-3 times the width of the second trench.

[0025] In some embodiments, after the step of forming the bit line in the bit line trench, the preparation method further includes:

[0026] Etching back a portion of the thickness of the bit line isolation structure so that a top surface of the remaining bit line isolation structure is lower than a top surface of the substrate and higher than a top surface of the bit line;

[0027] forming a first isolation layer in a region enclosed by the bit line and the bit line isolation structure;

[0028] forming a plurality of word lines, the plurality of word lines being spaced apart along the second direction; each of the word lines extending along the first direction and wrapping around at least a portion of the outer circumference of a plurality of active pillars arranged along the first direction;

[0029] A second isolation layer is formed on the word line and the first isolation layer, wherein a top surface of the second isolation layer is flush with a top surface of the substrate.

[0030] A second aspect of the present disclosure provides a semiconductor structure, comprising:

[0031] a substrate, the substrate comprising a plurality of active pillars arranged in an array along a first direction and a second direction, wherein the first direction intersects the second direction, and the first direction and the second direction are both perpendicular to an extension direction of the active pillars;

[0032] a plurality of bit lines, the plurality of bit lines being spaced apart in the substrate along the first direction, and each of the bit lines extending along the second direction and wrapping around at least a portion of an outer peripheral surface of a plurality of active pillars arranged along the second direction;

[0033] A plurality of bit line isolation structures are provided in the substrate, wherein one of the bit line isolation structures is located between adjacent bit lines to isolate adjacent bit lines; wherein the bottom surface of the bit line isolation structure is lower than the bottom surface of the bit line.

[0034] In some embodiments, in the first direction, the distance between adjacent active pillars is a first preset distance; in the second direction, the distance between adjacent active pillars is a second preset distance;

[0035] The first preset distance is greater than the second preset distance.

[0036] In some embodiments, the bit line includes a barrier layer and a metal conductive layer, wherein the barrier layer wraps around the bottom and side surfaces of the metal conductive layer; wherein the top surface of the bit line is lower than the top surface of the bit line isolation structure.

[0037] In some embodiments, the semiconductor structure further includes a plurality of word lines, a first isolation layer and a second isolation layer;

[0038] The first isolation layer covers the plurality of bit lines, and a top surface of the first isolation layer is flush with a top surface of the bit line isolation structure;

[0039] A plurality of word lines are located above the first isolation layer and are spaced apart along the second direction; each word line extends along the first direction and wraps around at least a portion of the outer peripheral surface of a plurality of active pillars arranged along the first direction;

[0040] The second isolation layer is disposed in an area enclosed by portions of the active pillars located above the word lines, and a top surface of the second isolation layer is flush with a top surface of the substrate.

[0041] In the semiconductor structure and preparation method provided by the embodiments of the present disclosure, a bit line isolation structure is first formed, and then a bit line is formed in a bit line trench. The bottom surface of the bit line isolation structure is lower than the bottom of the bit line trench, so that the bottom surface of the bit line isolation structure is lower than the bottom surface of the bit line, thereby improving the isolation effect of the bit line isolation structure, reducing the risk of leakage between adjacent bit lines, and improving the yield of the semiconductor structure.

[0042] In addition to the technical problems solved by the embodiments of the present disclosure, the technical features that constitute the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions described above, other technical problems that can be solved by the semiconductor structure and the preparation method thereof provided by the embodiments of the present disclosure, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further described in detail in the specific implementation methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0044] Figure 1 A process flow chart of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0045] Figure 2 A schematic diagram of forming a protective layer and a mask layer in the preparation method of the semiconductor structure provided in an embodiment of the present disclosure;

[0046] Figure 3 A schematic diagram of a semiconductor structure after forming a first trench and a second trench in a method for preparing the semiconductor structure according to an embodiment of the present disclosure;

[0047] Figure 4 for Figure 3 Cross-sectional view in the AA direction;

[0048] Figure 5 A schematic diagram of a semiconductor structure after forming a sacrificial layer in a method for preparing the semiconductor structure according to an embodiment of the present disclosure;

[0049] Figure 6 for Figure 5 Cross-sectional view in the middle BB direction;

[0050] Figure 7 A schematic diagram of a semiconductor structure after forming a bit line isolation trench in a method of manufacturing the semiconductor structure according to an embodiment of the present disclosure;

[0051] Figure 8 A schematic diagram of a semiconductor structure after a bit line isolation structure is formed in the preparation method of the semiconductor structure provided by an embodiment of the present disclosure;

[0052] Figure 9 for Figure 8 Cross-sectional view in CC direction;

[0053] Figure 10 A schematic diagram of a semiconductor structure after forming a bit line trench in a method of manufacturing the semiconductor structure according to an embodiment of the present disclosure;

[0054] Figure 11 for Figure 10 Cross-sectional view in the middle DD direction;

[0055] Figure 12 A schematic diagram of the semiconductor structure preparation method according to an embodiment of the present disclosure after forming a barrier material layer and a metal conductive material layer;

[0056] Figure 13 for Figure 12 Cross-sectional view in the EE direction;

[0057] Figure 14 A schematic diagram of a semiconductor structure after bit lines are formed in a method for preparing the semiconductor structure according to an embodiment of the present disclosure;

[0058] Figure 15 for Figure 14 Cross-sectional view in the FF direction;

[0059] Figure 16 A schematic diagram of a semiconductor structure after word lines are formed in the preparation method of the semiconductor structure provided by an embodiment of the present disclosure;

[0060] Figure 17 A distribution diagram of word lines, bit lines, and active pillars provided in an embodiment of the present disclosure.

[0061] Reference numerals:

[0062] 100: substrate; 110: first trench; 120: second trench; 130: protection layer; 140: mask layer; 150: active pillar; 160: third trench; 170: bit line isolation trench; 180: bit line trench;

[0063] 200: sacrificial layer;

[0064] 300: bit line isolation structure;

[0065] 400: bit line; 410: barrier material layer; 420: metal conductive material layer; 430: barrier layer; 440: metal conductive layer;

[0066] 500: first isolation layer; 600: word line; 700: second isolation layer. DETAILED DESCRIPTION

[0067] As described in the background technology, the problem of leakage between adjacent bit lines in the semiconductor structure in the related art has been discovered by the inventors through research. The reason for this problem is that as the semiconductor structure develops in the direction of size, the spacing between adjacent bit lines becomes smaller and smaller, and the bottom surface of the bit line isolation structure is basically flush with the bottom surface of the bit line, resulting in poor isolation effect, which makes it easy for leakage to occur between adjacent bit lines, thereby reducing the yield of the semiconductor structure.

[0068] In response to the above technical problems, the embodiments of the present disclosure provide a semiconductor structure and a preparation method thereof, by first forming a bit line isolation structure and then forming a bit line in a bit line trench, and utilizing the bottom surface of the bit line isolation structure to be lower than the bottom of the bit line trench, so that the bottom surface of the bit line isolation structure is lower than the bottom surface of the bit line, thereby improving the isolation effect of the bit line isolation structure, reducing the risk of leakage between adjacent bit lines, and improving the yield of the semiconductor structure.

[0069] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present disclosure more obvious and easy to understand, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present disclosure.

[0070] This embodiment does not limit the semiconductor structure. The semiconductor structure will be described below using a dynamic random access memory (DRAM) as an example, but this embodiment is not limited thereto. The semiconductor structure in this embodiment may also be other structures.

[0071] Please refer to the attached Figure 1 , an embodiment of the present disclosure provides a method for preparing a semiconductor structure, comprising the following steps:

[0072] Step S100: providing a substrate, and forming a plurality of active pillars arranged in an array along a first direction and a second direction in the substrate, wherein the first direction intersects the second direction and the first direction and the second direction are perpendicular to the extension direction of the active pillars.

[0073] Please refer to the attached Figure 2 To the attached Figure 4 In this embodiment, the substrate 100 may be a semiconductor substrate for supporting a semiconductor device disposed thereon. The substrate 100 may be a silicon (Si) substrate, a germanium (Ge) substrate, a silicon-germanium (GeSi) substrate, a silicon carbide (SiC) substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate.

[0074] The substrate 100 is patterned using a patterning process to form a plurality of first grooves 110 and a plurality of second grooves 120 in the substrate 100. The plurality of first grooves 110 are arranged at intervals along the first direction, and each first groove 110 extends along the second direction. The plurality of second grooves 120 are arranged at intervals along the second direction, and each second groove 120 extends along the first direction. The first direction can be an attached Figure 3 The middle X direction, the second direction is the attached Figure 3 in the Y direction.

[0075] For example, please refer to the attached Figure 2A protective layer 130 and a mask layer 140 are sequentially stacked on the substrate 100 using a deposition process, and the mask layer 140 is patterned. The deposition process includes chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0076] It should be understood that when patterning the mask layer 140, an anti-reflective layer (not shown in the figure) and a photoresist layer (not shown in the figure) can be formed on the surface of the mask layer 140 facing away from the substrate 100. Thereafter, the photoresist layer is patterned, for example, by exposing the photoresist layer using a mask plate (not shown in the figure) having a mask pattern to transfer the mask pattern on the mask plate to the photoresist layer. Subsequently, the photoresist layer is developed to remove a portion of the photoresist layer to form a mask pattern in the photoresist layer. The patterning process can be a self-aligned double patterning (SADP) process or a self-aligned quadruple patterning (SAQP) process.

[0077] The anti-reflection layer and the mask layer are patterned using the photoresist layer having the mask pattern as a mask to transfer the mask pattern to the hard mask layer, and the remaining photoresist layer and the anti-reflection layer are removed using a cleaning solution or an etching process.

[0078] In this embodiment, the anti-reflective layer may include a nitride or an oxynitride. For example, the anti-reflective layer may include silicon nitride or silicon oxynitride. The anti-reflective layer can mitigate or eliminate the standing wave effect of the photoresist layer, thereby increasing the accuracy of the mask pattern transferred from the reticle to the photoresist, thereby improving the accuracy of the pattern transfer process.

[0079] Afterwards, please refer to the attached Figure 3 and attached Figure 4 Then, using the patterned mask layer 140 as a mask, a portion of the mask layer 140 , the protective layer 130 and the substrate 100 are etched to form a first trench 110 and a second trench 120 .

[0080] In this embodiment, the material of the mask layer 140 includes polysilicon, and the material of the mask layer 140 and the material of the substrate 100 both include silicon. Therefore, when forming the first trench 110 and the second trench 120, in addition to etching the mask layer 140 in the regions where the first trench 110 and the second trench 120 are located, the mask layer 140 in the remaining regions outside the first trench 110 and the second trench 120 is also removed simultaneously. For example, before patterning the mask layer 140, the thickness of the mask layer 140 is D1, and after patterning the mask layer 140, the thickness of the mask layer 140 is D2, where D2 is less than D1. This results in the first trench 110 and the second trench 120 having a lower aspect ratio, which can improve the accuracy of the first trench 110 and the second trench 120 formed, thereby improving the yield of the semiconductor structure.

[0081] The protective layer 130 may be made of, but not limited to, silicon oxide. The protective layer 130 may protect the substrate 100 and prevent damage to other semiconductor devices formed in the substrate 100 during subsequent fabrication of the first trench 110 and the second trench 120, thereby improving the yield of the semiconductor structure.

[0082] A plurality of first grooves 110 and a plurality of second grooves 120 divide the substrate 100 into a plurality of active pillars 150, and the plurality of active pillars 150 are arranged in an array along a first direction and a second direction. Each active pillar 150 extends in a direction perpendicular to the substrate 100. The first direction and the second direction are both perpendicular to the extension direction of the active pillar 150. It should be noted that, in the direction from the top surface of the substrate 100 to the bottom surface of the substrate 100, the width of each active pillar 150 can be equal or different. For example, the width of each active pillar 150 tends to gradually increase, so that each active pillar 150 presents a conical or right trapezoidal structure, so that the active pillar 150 can be prevented from tilting, thereby improving the yield of the semiconductor structure.

[0083] Each active pillar 150 includes a channel region and a source region and a drain region located on either side of the channel region, along a direction perpendicular to the substrate 100. One of the source region and the drain region is used to connect to a capacitor, and the other is used to connect to a bit line. The channel region is used to connect to a word line. The voltage signal on the word line can control the opening or closing of the transistor, thereby reading the data information stored in the capacitor through the bit line, or writing the data information into the capacitor through the bit line for storage.

[0084] The width of the first trench 110 is greater than the width of the second trench 120. The width of the first trench 110 can be understood as the width of the first trench 110 in the first direction, and the width of the second trench 120 can be understood as the width of the second trench 120 in the second direction. Part of the first trench 110 is used to form a bitline isolation structure. This increases the width of the bitline isolation structure in the first direction, thereby increasing the distance between adjacent bitlines, reducing the parasitic capacitance formed by adjacent bitlines, and improving the yield of the semiconductor structure.

[0085] Please continue to refer to the attached Figure 3 In one example, to facilitate description of the width of the first trench 110 and the width of the second trench 120, the width of the first trench 110 is denoted as L1 and the width of the second trench 120 is denoted as L2. The width of the first trench 110 is 1.5-3 times the width of the second trench 120. For example, the width of the first trench 110 is 2 times the width of the second trench 120. In this way, the parasitic capacitance formed by the bit lines formed by adjacent bit lines is reduced, thereby improving the yield of the semiconductor structure. At the same time, the size of the semiconductor structure is reduced, facilitating the development of semiconductor structures toward integration.

[0086] Step S200: forming a plurality of bit line trenches and a bit line isolation structure for separating the respective bit line trenches, wherein the plurality of bit line trenches are spaced apart along a first direction and extend along a second direction; wherein each bit line trench exposes the outer peripheral surface of a plurality of active pillars arranged along the second direction, and the bottom of the bit line trench is higher than the bottom surface of the bit line isolation structure.

[0087] For example, please refer to the attached Figure 5 and attached Figure 6 A sacrificial layer 200 is formed using an atomic layer deposition process, wherein the sacrificial layer 200 covers the inner wall of the first trench 110 and fills the area between adjacent active pillars 150 in the second direction. The sacrificial layer 200 encloses the third trench 160 within the first trench 110. It should be noted that the sacrificial layer 200 in this embodiment can also extend outside the first trench 110 and cover the top surface of the mask layer 140. The material of the sacrificial layer 200 includes silicon oxide, but is not limited thereto.

[0088] Afterwards, please refer to the attached Figure 7 The sacrificial layer 200 on the bottom wall of the third trench 160 and a portion of the substrate 100 below the bottom wall of the third trench 160 are removed to form a bit line isolation trench 170. In other words, the bottom of the bit line isolation trench 170 is located below the bottom of the first trench 110, so that the depth of the bit line isolation trench 170 is greater than the depth of the first trench 110.

[0089] Illustratively, plasma is injected into the third trench 160 through a plasma etching process to remove the sacrificial layer 200 on the bottom wall of the third trench 160 and a partial thickness of the substrate 100 located below the bottom wall of the third trench 160; wherein the plasma injection direction is perpendicular to the top surface of the substrate 100.

[0090] The plasma injection direction is perpendicular to the top surface of the substrate 100, which can reduce damage to the sacrificial layer 200 located on the side wall of the first trench 110, so that after the bit line isolation trench 170 is formed, the thickness of the sacrificial layer 200 located on the side wall of the first trench 110 does not change substantially, thereby ensuring that the subsequently formed bit line trench has a sufficient width, and further ensuring that the formed bit line has a sufficient width, thereby ensuring the conductive performance of the bit line.

[0091] It should be noted that in the step of removing the sacrificial layer 200 located on the bottom wall of the third trench 160, the sacrificial layer 200 located on the remaining mask layer 140 will also be removed synchronously, and the remaining mask layer 140 will be removed, leaving only the sacrificial layer 200 located on the side wall of the first trench 110.

[0092] Afterwards, please refer to the attached Figure 8 and attached Figure 9 , an insulating material is deposited in the bit line isolation trench 170 using a deposition process to form a bit line isolation structure 300 in the bit line isolation trench 170 .

[0093] Afterwards, please refer to the attached Figure 10 and attached Figure 11 The remaining sacrificial layer 200 is removed by dry etching or wet etching to form a bit line trench 180. It should be understood that the bit line trench 180 includes the second trench 120 and a portion of the first trench 110, that is, the bit line trench 180 includes the entire second trench 120 and the area occupied by the subsequently formed sacrificial layer 200.

[0094] The bitline isolation structure 300 has a large etching selectivity with the sacrificial layer 200. Specifically, under the same etching conditions, such as the same etching gas, etching time, and etching gas concentration, the etching rate of the bitline isolation structure 300 is lower than the etching rate of the sacrificial layer 200. In one example, the material of the bitline isolation structure 300 includes silicon nitride or a material with a low dielectric constant, so that the bitline isolation structure 300 serves as an etch stop layer during the removal of the remaining sacrificial layer 200. This reduces damage to the bitline isolation structure 300, ensures the width of the bitline isolation structure 300, and further ensures the isolation effect of the bitline isolation structure 300. Furthermore, the low dielectric constant of the material of the bitline isolation structure 300 reduces parasitic capacitance between adjacent bitlines, thereby improving the yield of the semiconductor structure.

[0095] It should be noted that during the step of removing the remaining sacrificial layer 200 to form the bitline trench 180, the protective layer 130 is also removed simultaneously to expose the top surface of the substrate 100, facilitating the electrical connection between the subsequently formed capacitor and the source or drain of the active pillar 150. During the process of removing the remaining sacrificial layer 200, the protective layer 130 covers the top surface of the active pillar 150, thereby preventing etching of the top surface of the active pillar 150. Accordingly, the top surface of the active pillar 150 is prevented from forming a curved surface, thereby preventing a reduction in the contact area between the capacitor and the active pillar 150, reducing the contact resistance between the capacitor and the active pillar, and improving the yield of the semiconductor structure.

[0096] Step S300 : forming a bit line in each bit line trench, wherein the bit line extends along the second direction and wraps around at least a portion of the outer circumference of a plurality of active pillars arranged along the second direction.

[0097] Please refer to the attached Figure 12 and attached Figure 13 A barrier material layer 410 is formed on the inner wall of the bit line trench 180 using an atomic layer deposition process. The barrier material layer 410 also covers the top surface of the active pillar 150. The barrier material layer 410 has a good step coverage.

[0098] Thereafter, a metal conductive material layer 420 is formed on the barrier material layer 410 , and the metal conductive material layer 420 completely fills the area surrounded by the barrier material layer 410 .

[0099] Afterwards, please refer to the attached Figure 14 and attached Figure 15 Then, barrier material layer 410 and metal conductive material layer 420 are etched back. The remaining barrier material layer 410 forms barrier layer 430, and the remaining metal conductive material layer 420 forms metal conductive layer 440. Barrier layer 430 wraps around the bottom and side surfaces of metal conductive layer 440, and the top surface of barrier layer 430 is flush with the top surface of metal conductive layer 440. Barrier layer 430 and metal conductive layer 440 constitute bit line 400.

[0100] In this embodiment, the metal conductive layer 440 is made of tungsten. Compared to related art solutions in which the conductive layer of the bit line is made of a semiconductor material (e.g., polysilicon), this reduces the resistance of the bit line 400 and improves the electrical performance of the bit line 400. The barrier layer 430 is made of titanium nitride. The barrier layer 430 has both conductive and barrier properties. For example, titanium nitride can prevent the conductive material in the metal conductive layer 440 from penetrating into the active pillar 150 and substrate 100, thereby ensuring the conductive performance of the bit line 400.

[0101] In a possible implementation, after the step of forming a bit line in the bit line trench, the method for preparing the semiconductor structure further includes:

[0102] By using dry etching or wet etching, a portion of the thickness of the bit line isolation structure 300 is etched back so that the top surface of the remaining bit line isolation structure 300 is lower than the top surface of the substrate 100 and higher than the height of the bit line 400, while ensuring the insulation between adjacent bit lines 400, providing space for the subsequent formation of word lines or other devices.

[0103] Then, a first isolation layer 500 is formed in the area enclosed by the bit line 400 and the bit line isolation structure 300. The top surface of the first isolation layer 500 is flush with the top surface of the bit line isolation structure 300. The material of the first isolation layer 500 includes silicon oxide or silicon nitride.

[0104] Afterwards, please refer to the attached Figure 16 and attached Figure 17 , forming a plurality of word lines 600, and the plurality of word lines 600 are spaced apart along the second direction; each word line 600 extends along the first direction and wraps at least a portion of the outer peripheral surface of a plurality of active pillars 150 arranged along the first direction.

[0105] Exemplarily, a gate dielectric layer is formed on the exposed portion of each active pillar 150, and the gate dielectric layer surrounds the active pillar 150 and covers at least the channel region of the active pillar 150. The gate dielectric layer has a high dielectric constant, which can effectively prevent electrons from directly tunneling through the gate dielectric layer and generating gate leakage current, thereby facilitating thinning the thickness of the gate dielectric layer, meeting the requirements of process size reduction, and providing a guarantee for the development of memory cells toward integration. The material of the gate dielectric layer includes a high dielectric constant material, and the material of the gate dielectric layer includes hafnium silicon oxide (HfSiO2), aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), or strontium titanium oxide (SrTiO3).

[0106] Next, a wordline conductive layer is formed. The wordline conductive layer extends along a first direction and wraps around at least a portion of the outer periphery of the plurality of active pillars 150 arranged along the first direction. In one example, the wordline conductive layer wraps around the entire outer periphery of the plurality of active pillars 150 arranged along the first direction, so that the resulting transistor is a full-all-around gate transistor. In another example, the wordline conductive layer wraps around a portion of the outer periphery of the plurality of active pillars 150 arranged along the first direction, so that the resulting transistor is a half-all-around gate transistor.

[0107] Afterwards, a second isolation layer 700 is formed on the word lines 600 and the first isolation layer 500. The top surface of the second isolation layer 700 is flush with the top surface of the substrate 100. The first isolation layer 500 and the second isolation layer 700 constitute the entire isolation layer, which is used to achieve mutual insulation between adjacent word lines 600. The material of the first isolation layer 500 and the second isolation layer 700 is the same, and both can include silicon oxide.

[0108] Please refer to the attached Figure 16 and attached Figure 17 The embodiment of the present disclosure further provides a semiconductor structure including a substrate 100 , a plurality of bit lines 400 and a plurality of bit line isolation structures 300 .

[0109] The substrate 100 includes a plurality of active pillars 150, each extending perpendicularly to the substrate 100. The plurality of active pillars 150 are arranged in an array along a first direction and a second direction. The first direction intersects the second direction, and both the first direction and the second direction are perpendicular to the extending direction of the active pillars 150.

[0110] A plurality of bit lines 400 are spaced apart along the first direction within the substrate 100. Each bit line 400 extends along the second direction and wraps around at least a portion of the outer circumference of a plurality of active pillars 150 arranged along the second direction.

[0111] A plurality of bit line isolation structures 300 are disposed in the substrate 100 , wherein one bit line isolation structure 300 is located between adjacent bit lines 400 to isolate the adjacent bit lines 400 ; wherein a bottom surface of the bit line isolation structure 300 is lower than a bottom surface of the bit line 400 .

[0112] In this embodiment, by making the bottom surface of the bitline isolation structure 300 lower than the bottom surface of the bitline 400, the isolation effect of the bitline isolation structure 300 is improved, the risk of leakage between adjacent bitlines 400 is reduced, and the yield of the semiconductor structure is improved. In addition, the distance between adjacent bitlines 400 is greater than the distance between adjacent wordlines 600. This arrangement can reduce the parasitic capacitance formed between adjacent bitlines 400 and improve the performance of the semiconductor structure.

[0113] In one possible embodiment, in the first direction, the distance between adjacent active pillars 150 is a first preset distance; in the second direction, the distance between adjacent active pillars 150 is a second preset distance; the first preset distance is greater than the second preset distance. For example, the first preset distance is twice the second preset distance. In the first direction, the area between adjacent active pillars 150 is used to accommodate the bit lines 400 and the bit line isolation structure 300. The larger first preset distance can, on the one hand, increase the distance between adjacent bit lines 400, thereby reducing the parasitic capacitance formed between adjacent bit lines 400 and improving the performance of the semiconductor structure. On the other hand, it can increase the width of the bit line isolation structure 300 in the first direction, thereby improving the isolation effect of the bit line isolation structure 300.

[0114] In one possible embodiment, the bit line 400 includes a barrier layer 430 and a metal conductive layer 440. The barrier layer 430 wraps around the bottom and side surfaces of the metal conductive layer 440, and the top surface of the barrier layer 430 is flush with the top surface of the metal conductive layer 440. The top surface of the bit line 400 is lower than the top surface of the substrate 100 and lower than the top surface of the bit line isolation structure 300.

[0115] The material of the barrier layer 430 includes silicon nitride to ensure that the barrier layer 430 has both conductive and barrier properties. For example, titanium nitride can prevent the conductive material in the metal conductive layer 440 from penetrating between the active pillar 150 and the substrate 100, thereby ensuring the conductive performance of the bit line 400.

[0116] The metal conductive layer 440 includes a metal conductive material, such as tungsten. Compared with the related art where the conductive layer of the bit line is made of a semiconductor material (such as polysilicon), the resistance of the bit line 400 can be reduced and the conductivity of the bit line 400 can be improved.

[0117] In a possible implementation, the semiconductor structure further includes a plurality of word lines 600 , a first isolation layer 500 , and a second isolation layer 700 .

[0118] The first isolation layer 500 covers multiple bit lines and wraps around the entire periphery of the bit line isolation structure 300. The top surface of the first isolation layer 500 is flush with the top surface of the bit line isolation structure 300. The first isolation layer 500 and the bit line isolation structure 300 cooperate to provide insulation between the bit lines 400 and the word lines 600. This also prevents electrical connection between the bit lines 400 and the channel regions of the active pillars 150, improving the yield of the semiconductor structure.

[0119] A plurality of word lines 600 are located above the first isolation layer 500 and spaced apart along the second direction. Each word line 600 extends along the first direction and wraps around at least a portion of the outer periphery of a plurality of active pillars 150 arranged along the first direction. Each word line 600 may include a gate dielectric layer and a word line conductive layer. The gate dielectric layer surrounds the outer periphery of each active pillar 150 arranged along the first direction and covers at least the channel region of each active pillar 150. The word line conductive layer extends along the first direction, wraps around at least a portion of the outer periphery of the gate dielectric layer, and connects each active pillar 150 arranged along the first direction.

[0120] In this embodiment, the gate dielectric layer and the word line conductive layer surrounding the active pillar 150 , and the active pillar constitute a transistor, wherein the word line conductive layer surrounding the active pillar 150 constitutes a gate of the transistor.

[0121] The second isolation layer 700 is disposed in an area enclosed by portions of the active pillars 150 above the word lines 600 , and a top surface of the second isolation layer 700 is flush with a top surface of the substrate 100 , or in other words, a top surface of the second isolation layer 700 is flush with a top surface of the active pillars 150 .

[0122] The material of the second isolation layer 700 is the same as that of the first isolation layer 500, and is used to achieve insulation settings for adjacent word lines 600 and prevent the word lines 600 from being electrically connected to the source region or drain region of the active pillar 150 located above the word lines 600, thereby improving the yield of the semiconductor structure.

[0123] The various embodiments or implementation methods in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced to each other.

[0124] In the description of this specification, reference to terms such as "one embodiment", "some embodiments", "illustrative embodiment", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure.

[0125] In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any suitable manner in any one or more embodiments or examples.

[0126] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A method for preparing a semiconductor structure, characterized in that: The steps include: Providing a substrate, forming a plurality of active pillars arranged in an array along a first direction and a second direction in the substrate, wherein the first direction intersects the second direction, and the first direction and the second direction are both perpendicular to the extension direction of the active pillars; forming a plurality of bit line trenches and a bit line isolation structure for separating the bit line trenches, wherein the plurality of bit line trenches are spaced apart along the first direction and extend along the second direction; wherein each of the bit line trenches exposes the outer peripheral surfaces of the plurality of active pillars arranged along the second direction, and the bottom of the bit line trench is higher than the bottom surface of the bit line isolation structure; A bit line is formed in each of the bit line trenches. The bit line extends along the second direction and wraps around at least a portion of outer peripheral surfaces of a plurality of active pillars arranged along the second direction.

2. The method for preparing a semiconductor structure according to claim 1, wherein: The step of providing the substrate comprises: The substrate is patterned to form a plurality of first grooves arranged at intervals along the first direction and a plurality of second grooves arranged at intervals along the second direction in the substrate, wherein the first grooves and the second grooves separate the substrate into a plurality of active pillars; wherein the first grooves extend along the second direction, the second grooves extend along the first direction; and the groove width of the first groove is greater than the groove width of the second groove.

3. The method for preparing a semiconductor structure according to claim 2, wherein: The step of forming a plurality of the bit line trenches and the bit line isolation structure comprises: forming a sacrificial layer, the sacrificial layer covering the inner wall of the first trench and filling the area between the active pillars adjacent to each other in the second direction; the sacrificial layer enclosing a third trench in the first trench; removing the sacrificial layer on the bottom wall of the third trench and a portion of the thickness of the substrate below the bottom wall of the third trench to form a bit line isolation trench; forming the bit line isolation structure in the bit line isolation trench; The remaining sacrificial layer is removed to form the bit line trench, wherein the bottom wall of the bit line trench is higher than the bottom surface of the bit line isolation structure.

4. The method for preparing a semiconductor structure according to any one of claims 1 to 3, wherein: The step of forming a bit line in the bit line trench comprises: forming a barrier material layer on an inner wall of the bit line trench, wherein the barrier material layer also covers a top surface of the active pillar; forming a metal conductive material layer on the barrier material layer, wherein the metal conductive material layer completely fills the area surrounded by the barrier material layer; The barrier material layer and the metal conductive material layer are etched back to form the bit line, and the top surface of the bit line is lower than the top surface of the substrate; wherein the bit line includes a barrier layer and a metal conductive layer, the retained barrier material layer forms the barrier layer, the retained metal conductive material layer forms the metal conductive layer, and the barrier layer is wrapped around the bottom and side surfaces of the metal conductive layer.

5. The method for preparing a semiconductor structure according to claim 2 or 3, wherein: The width of the first groove is 1.5-3 times the width of the second groove.

6. The method for preparing a semiconductor structure according to any one of claims 1 to 3, wherein: After the step of forming a bit line in the bit line trench, the preparation method further includes: Etching back a portion of the thickness of the bit line isolation structure so that a top surface of the remaining bit line isolation structure is lower than a top surface of the substrate and higher than a top surface of the bit line; forming a first isolation layer in a region enclosed by the bit line and the bit line isolation structure; forming a plurality of word lines, the plurality of word lines being spaced apart along the second direction; each of the word lines extending along the first direction and wrapping around at least a portion of the outer circumference of a plurality of active pillars arranged along the first direction; A second isolation layer is formed on the word line and the first isolation layer, wherein a top surface of the second isolation layer is flush with a top surface of the substrate.

7. A semiconductor structure, characterized in that include: a substrate, the substrate comprising a plurality of active pillars arranged in an array along a first direction and a second direction, wherein the first direction intersects the second direction, and the first direction and the second direction are both perpendicular to an extension direction of the active pillars; a plurality of bit lines, the plurality of bit lines being spaced apart in the substrate along the first direction, and each of the bit lines extending along the second direction and wrapping around at least a portion of an outer peripheral surface of a plurality of active pillars arranged along the second direction; a plurality of bit line isolation structures, wherein the plurality of bit line isolation structures are disposed in the substrate, wherein one of the bit line isolation structures is located between adjacent bit lines to isolate adjacent bit lines; wherein a bottom surface of the bit line isolation structure is lower than a bottom surface of the bit line; In the first direction, the distance between adjacent active pillars is a first preset distance; in the second direction, the distance between adjacent active pillars is a second preset distance; The first preset distance is greater than the second preset distance; The bit line includes a barrier layer and a metal conductive layer, wherein the barrier layer wraps around the bottom surface and side surfaces of the metal conductive layer; wherein the top surface of the bit line is lower than the top surface of the bit line isolation structure.

8. The semiconductor structure according to claim 7, wherein: The semiconductor structure further includes a plurality of word lines, a first isolation layer and a second isolation layer; The first isolation layer covers the plurality of bit lines, and a top surface of the first isolation layer is flush with a top surface of the bit line isolation structure; A plurality of word lines are located above the first isolation layer and are spaced apart along the second direction; each word line extends along the first direction and wraps around at least a portion of the outer peripheral surface of a plurality of active pillars arranged along the first direction; The second isolation layer is disposed in a region enclosed by portions of the active pillars located above the word lines, and a top surface of the second isolation layer is flush with a top surface of the substrate.

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