Instruction construction method, device, equipment and medium

Abstract

In the embodiment of the present application, a method, device, equipment and medium for constructing instructions are provided, which relate to the field of computer technology. The method includes: obtaining an operand format; the operand format includes a source register identifier and a target register identifier; constructing a target instruction according to the source register identifier and the target register identifier; the target instruction is a digital signal processing DSP extension instruction based on the RISC‑V architecture, and the target instruction includes at least one of the following: byte extension instruction, fixed-point multiplication and accumulation instruction, absolute value and arithmetic operation instruction, shift and saturation instruction, data packing and unpacking instruction, and other special instructions; the target instruction is used to expand a 32-bit data path to a 64-bit data path. The scheme can expand a 32-bit data processing path to a 64-bit data path, provide a wider data path, and support higher-precision data types, thereby meeting the computing power requirements of DSP algorithms.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular, to an instruction construction method, device, equipment and medium. Background Art

[0002] With the continuous development of computer technology, RISC-V, as an open standard instruction set architecture, has been increasingly used in various application scenarios, such as embedded systems or high-performance computing, due to its modular, scalable and open source characteristics. With the continuous advancement of technology and the growth of application demand, the application and development of RISC-V in digital signal processing (DSP) design has attracted attention. RISC-V-based DSP chip products have been reflected in the design of communication DSP and the application of 5G RedCap baseband.

[0003] At present, for the RISC-V 32-bit processing architecture, the relevant technology can use the RISC-V P extension (also known as RV32P or RV64P) to enhance the capabilities of digital signal processing DSP. However, for some application scenarios with high-precision computing requirements, the 32-bit data path cannot meet the high performance requirements. Summary of the invention

[0004] The embodiments of the present application provide an instruction construction method, apparatus, device and medium.

[0005] A first aspect of an embodiment of the present application provides an instruction construction method, the instruction construction method comprising:

[0006] Obtaining an operand format; the operand format includes a source register identifier and a target register identifier;

[0007] A target instruction is constructed according to the source register identifier and the target register identifier; the target instruction is a digital signal processing DSP extension instruction based on the RISC-V architecture, and the target instruction includes at least one of the following: byte extension instructions, fixed-point multiplication and accumulation instructions, absolute value and arithmetic operation instructions, shift and saturation instructions, data packing and unpacking instructions, and other special instructions; the target instruction is used to expand a 32-bit data path to a 64-bit data path.

[0008] In an optional embodiment of the present application, when the target instruction is a byte extension instruction, constructing the target instruction according to the source register identifier and the target register identifier includes:

[0009] Get the byte extension flag;

[0010] According to the instruction encoding rules of RISC-V, the byte extension identifier, the target register identifier and the source register identifier are combined to obtain the byte extension instruction; the byte extension instruction is used to represent the expansion of the bytes of the source register and store them in the target register.

[0011] In an optional embodiment of the present application, when the target instruction is a fixed-point multiplication and accumulation instruction, constructing the target instruction according to the source register identifier and the target register identifier includes:

[0012] Get the fixed-point multiplication and accumulation flags;

[0013] According to the instruction encoding rules of RISC-V, the fixed-point multiplication and accumulation identifier, the target register identifier and the source register identifier are combined to obtain the fixed-point multiplication and accumulation instruction; the fixed-point multiplication and accumulation instruction includes a first multiplication instruction and a second multiplication instruction, the first multiplication instruction is used to represent the execution of fixed-point multiplication, and right-shift and saturate the result, and the second multiplication instruction is used to represent the execution of signed or unsigned multiplication, and saturate to a specific value and write it back to the target register pair.

[0014] In an optional embodiment of the present application, when the target instruction is an absolute value and arithmetic operation instruction, constructing the target instruction according to the source register identifier and the target register identifier includes:

[0015] Get the absolute value and arithmetic operation flag;

[0016] According to the instruction encoding rules of RISC-V, the absolute value and arithmetic operation identifier, the target register identifier and the source register identifier are combined to obtain the absolute value and arithmetic operation instruction; the absolute value and arithmetic operation instruction includes a first operation instruction and a second operation instruction, the first operation instruction is used to represent the calculation of the absolute values ​​of multiple numerical values, and the second operation instruction is used to represent the execution of addition and subtraction, and the result is saturated and written back to the target register pair.

[0017] In an optional embodiment of the present application, when the target instruction is a shift and saturation instruction, constructing the target instruction according to the source register identifier and the target register identifier includes:

[0018] Get the shift and saturation flags;

[0019] According to the instruction encoding rules of RISC-V, the shift and saturation flag, the target register flag and the source register flag are combined to obtain the shift and saturation instruction; the shift and saturation instruction is used to represent the execution of a logical left shift or an arithmetic right shift according to the number of bits specified in the register, and the result is saturated and written back to the target register pair.

[0020] In an optional embodiment of the present application, when the target instruction is a data packing and unpacking instruction, constructing the target instruction according to the source register identifier and the target register identifier includes:

[0021] Get data packing and unpacking identifiers;

[0022] According to the instruction encoding rules of RISC-V, the data packing and unpacking identifier, the target register identifier and the source register identifier are combined to obtain the data packing and unpacking instruction; the data packing and unpacking instruction is used to represent packing data blocks of different sizes into data units or decomposing data units into data blocks of different sizes and writing them back to the target register pair; the size of the data block is smaller than the size of the data unit.

[0023] In an optional embodiment of the present application, when the target instruction is other special instructions, constructing the target instruction according to the source register identifier and the target register identifier includes:

[0024] Get the special instruction identifier;

[0025] According to the instruction encoding rules of RISC-V, the special instruction identifier, the target register identifier and the source register identifier are combined to obtain the other special instructions; the other special instructions include a first special instruction, a second special instruction and a third special instruction, the first special instruction is used to represent the execution of cross addition and subtraction operations, and the results are right-shifted and saturated and written back to the target register pair, the second special instruction is used to represent the truncation according to the immediate number and the writing back to the target register pair, and the third special instruction is used to represent the execution of multiplication and addition and multiplication and subtraction operations and the writing back to the target register pair.

[0026] A second aspect of the embodiments of the present application provides an instruction construction method, the instruction construction method comprising:

[0027] An acquisition module, used for acquiring an operand format; the operand format includes a source register identifier and a target register identifier;

[0028] A construction module is used to construct a target instruction according to the source register identifier and the target register identifier; the target instruction is a digital signal processing DSP extension instruction based on the RISC-V architecture, and the target instruction includes at least one of the following: byte extension instruction, fixed-point multiplication and accumulation instruction, absolute value and arithmetic operation instruction, shift and saturation instruction, data packing and unpacking instruction, and other special instructions; the target instruction is used to expand a 32-bit data path to a 64-bit data path.

[0029] In a third aspect of an embodiment of the present application, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the above-mentioned instruction construction method when executing the computer program.

[0030] In a fourth aspect of the embodiments of the present application, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the above-mentioned instruction construction method are implemented.

[0031] The instruction construction method, device, equipment and medium in the embodiment of the present application include: obtaining the operand format; the operand format includes a source register identifier and a target register identifier; constructing a target instruction according to the source register identifier and the target register identifier; the target instruction is a digital signal processing DSP extension instruction based on the RISC-V architecture, and the target instruction includes at least one of the following: byte extension instruction, fixed-point multiplication and accumulation instruction, absolute value and arithmetic operation instruction, shift and saturation instruction, data packing and unpacking instruction, and other special instructions; the target instruction is used to expand the 32-bit data path to the 64-bit data path. The technical solution in the present application increases the support for register pairs by obtaining the operand format, and accurately constructs a variety of target instructions for digital signal processing DSP extension based on the RISC-V architecture according to the operand format, which can expand the 32-bit data processing path to the 64-bit data processing channel, thereby providing a wider data path and supporting higher-precision data types, thereby meeting the DSP algorithm's demand for computing power and being suitable for application scenarios with high-precision computing requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0033] Figure 1 A structural diagram of a computer device provided for one embodiment of the present application;

[0034] Figure 2 A flowchart of an instruction construction method provided in one embodiment of the present application;

[0035] Figure 3 A schematic diagram of the structure of an instruction construction method provided in one embodiment of the present application;

[0036] Figure 4 A schematic diagram of an instruction construction device provided for one embodiment of the present application. DETAILED DESCRIPTION

[0037] In the process of implementing the present application, the inventors discovered that for some application scenarios requiring high-precision computing, a 32-bit data path cannot meet high-performance requirements.

[0038] In order to make the technical solutions and advantages in the embodiments of the present application more clearly understood, the exemplary embodiments of the present application are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0039] At present, for the RISC-V 32-bit processing architecture, the relevant technology can use the RISC-V P extension (also known as RV32P or RV64P) to enhance the capabilities of digital signal processing DSP. However, for some application scenarios with high-precision computing requirements, the 32-bit data path cannot meet the high performance requirements.

[0040] Based on the above problems, the embodiments of the present application provide an instruction construction method, apparatus, device and medium, which increase support for register pairs by obtaining the operand format, and accurately construct a variety of target instructions for digital signal processing DSP extension based on the RISC-V architecture according to the operand format, which can expand the 32-bit data processing path to a 64-bit data processing channel, thereby providing a wider data path and supporting higher-precision data types, thereby meeting the computing power requirements of DSP algorithms and being suitable for application scenarios with high-precision computing requirements.

[0041] The solutions in the embodiments of the present application can be implemented using various computer languages, for example, the object-oriented programming language Java and the interpreted scripting language JavaScript.

[0042] See also Figure 1 , a schematic diagram of the structure of a computer device provided in an embodiment of the present application. Figure 1As shown, the computer device includes a processor, a memory, a network interface, a display screen and an input device connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium can be, for example, a disk. The non-volatile storage medium stores files (which can be files to be processed or processed files), an operating system and a computer program, etc. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a terminal information management method is implemented. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covered on the display screen, or a key, trackball or touchpad set on the computer device housing, or an external keyboard, touchpad or mouse, etc.

[0043] See also Figure 2 , Figure 2 The flowchart of the instruction construction method provided in the embodiment of the present application is as follows:

[0044] Step 201, obtain an operand format; the operand format includes a source register identifier and a target register identifier.

[0045] It should be noted that the above operand format is an instruction format that needs to correspond to the target instruction, which needs to follow the instruction encoding rules according to RISC-V, and the operand format may include a three-operand format or a single-operand format. Among them, the three-operand format includes two source register identifiers and one target register identifier, and the single-operand format includes one source register identifier and one target register identifier.

[0046] It can be understood that the above three-operand format may include: Rd, Rs1, Rs2, indicating the target register (Rd) and two source registers (Rs1, Rs2), and the above single-operand format may include: Rd, Rs1, indicating the target register (Rd) and one source register (Rs1), where Rd is the target register identifier, and Rs1, Rs2 are source register identifiers. Different target instructions correspond to different operand formats. Most target instructions use the three-operand format, and a small number of target instructions use the single-operand format.

[0047] Optionally, the operand format may be obtained according to a preset rule, or may be obtained from a preset database or blockchain. In this embodiment, no limitation is imposed on the method for obtaining the operand format.

[0048] Step 202, construct a target instruction according to the source register identifier and the target register identifier; the target instruction is a digital signal processing DSP extension instruction based on the RISC-V architecture, and the target instruction includes at least one of the following: byte extension instruction, fixed-point multiplication and accumulation instruction, absolute value and arithmetic operation instruction, shift and saturation instruction, data packing and unpacking instruction, and other special instructions; the target instruction is used to expand a 32-bit data path to a 64-bit data path.

[0049] It should be noted that the above-mentioned target instructions are DSP instructions based on the RISC-V architecture that need to be built. The target instructions can be divided into multiple types according to different functions. Each type corresponds to different target instructions. The type may include at least one of the following: byte extension and copy type, multiplication and saturation type, absolute value and shift type, addition and subtraction type, averaging and special operation type, data packing and unpacking type, and other special function types.

[0050] Specifically, after obtaining the source register identifier and the target register identifier, each different type of instruction identifier can be obtained, and then the source register identifier, the target register identifier and different types of instruction identifiers are analyzed and processed according to the RISC-V instruction encoding rules to construct the target instruction.

[0051] The above target instructions can be applied in different DSP scenarios, such as audio processing, video processing, communication systems, sensor data processing, etc. Among them, audio processing may include audio encoding and decoding, acoustic echo cancellation, noise suppression, etc.; video processing may include video compression / decompression, image enhancement, color space conversion, etc.; communication systems may include baseband signal processing, channel encoding / decoding, modulation and demodulation, etc.; sensor data processing may include data fusion, filtering and smoothing processing collected from multiple sensors, etc.

[0052] In this embodiment, after the target instructions are constructed, in order to efficiently execute these instructions, a hardware acceleration unit needs to be designed to support SIMD operations and saturated arithmetic, and corresponding compiler support can also be developed to enable these target instructions to be used. By constructing target instructions based on the RISC-V architecture, specialized hardware accelerators or instructions can be added according to the needs of specific DSP applications, thereby greatly improving the performance for specific algorithms.

[0053] See also Figure 3 As shown, Figure 3 A structural diagram of the instruction construction method provided in an embodiment of the present application first obtains an operand format, which includes a source register identifier and a target register identifier, and then constructs a target instruction based on the RISC-V instruction encoding rules.

[0054] The instruction construction method in the embodiment of the present application includes: obtaining the operand format; the operand format includes a source register identifier and a target register identifier; constructing a target instruction according to the source register identifier and the target register identifier; the target instruction is a digital signal processing DSP extension instruction based on the RISC-V architecture, and the target instruction includes at least one of the following: byte extension instruction, fixed-point multiplication and accumulation instruction, absolute value and arithmetic operation instruction, shift and saturation instruction, data packing and unpacking instruction, and other special instructions; the target instruction is used to expand the 32-bit data path to the 64-bit data path. The technical solution in the present application increases the support for register pairs by obtaining the operand format, and accurately constructs a variety of target instructions for digital signal processing DSP extension based on the RISC-V architecture according to the operand format, which can expand the 32-bit data processing path to the 64-bit data processing channel, thereby providing a wider data path and supporting higher-precision data types, thereby meeting the DSP algorithm's demand for computing power and being suitable for application scenarios with high-precision computing requirements.

[0055] In another embodiment of the present application, when the target instruction is a byte extension instruction, the process of constructing the target instruction according to the source register identifier and the target register identifier includes:

[0056] Get the byte extension identifier; according to the instruction encoding rules of RISC-V, combine the byte extension identifier, the target register identifier and the source register identifier to obtain the byte extension instruction; the byte extension instruction is used to represent the expansion of the bytes of the source register and store them in the target register.

[0057] It should be noted that the above byte extension instruction can be applied to process multi-channel audio data or other data that needs to be accessed by byte. The byte extension identifier can be EXPD. Using the instruction encoding rules of RISC-V, the byte extension identifier, the target register identifier (Rd) and the source register identifier (Rs1) are combined to obtain a byte extension instruction. The byte extension instruction can be EXPD8x, which can include EXPD80 to EXPD87, indicating that the specific bytes of the source register Rs1 are expanded and copied to 32 bits or 64 bits respectively under RV32 and RV64, and stored in the destination register Rd.

[0058] It can be understood that the above byte extension instruction EXPD80 can be: EXPD80 Rd, Rs1, RV32: EXPD80 instruction expands and copies Rs1 byte 0 to 32 bits; RV64: EXPD80 instruction expands and copies Rs1 byte 0 to 64 bits. The above EXPD81 can be: EXPD81 Rd, Rs1, RV32: EXPD81 instruction expands and copies Rs1 byte 1 to 32 bits; RV64: EXPD81 instruction expands and copies Rs1 byte 1 to 64 bits. The above EXPD82 can be: EXPD82 Rd, Rs1, RV32: EXPD82 instruction expands and copies Rs1 byte 2 to 32 bits; RV64: EXPD82 instruction expands and copies Rs1 byte 2 to 64 bits. The above EXPD83 can be: EXPD83 Rd, Rs1, RV32: EXPD83 instruction expands and copies Rs1 byte 3 to 32 bits; RV64: EXPD83 instruction expands and copies Rs1 byte 3 to 64 bits.

[0059] The above EXPD84 may be: EXPD84 Rd, Rs1, RV32: EXPD84 instruction expands and copies Rs1 byte 4 to 32 bits; RV64: EXPD84 instruction expands and copies Rs1 byte 4 to 64 bits. The above EXPD85 may be: EXPD85Rd, Rs1, RV32: EXPD85 instruction expands and copies Rs1 byte 5 to 32 bits; RV64: EXPD85 instruction expands and copies Rs1 byte 5 to 64 bits. The above EXPD86 may be: EXPD86 Rd, Rs1, RV32: EXPD86 instruction expands and copies Rs1 byte 6 to 32 bits; RV64: EXPD86 instruction expands and copies Rs1 byte 6 to 64 bits. The above EXPD87 can be: EXPD87 Rd, Rs1, RV32: EXPD87 instruction expands and copies Rs1 byte 7 to 32 bits; RV64: EXPD87 instruction expands and copies Rs1 byte 7 to 64 bits. In this application, RV32 refers to a 32-bit RISC-V processor; RV64 refers to a 64-bit RISC-V processor.

[0060] In the embodiment of the present application, by constructing a byte extension instruction based on the byte extension representation, a specific byte in a register can be expanded to the entire register width. By providing special instructions to perform byte extension operations, the assembly code or machine code generated by the compiler can be simplified, the code processing efficiency is improved, and the instruction execution time is reduced.

[0061] In an optional embodiment of the present application, when the target instruction is a fixed-point multiplication and accumulation instruction, the target instruction is constructed according to the source register identifier and the target register identifier, including:

[0062] Obtain a fixed-point multiplication and accumulation identifier; combine the fixed-point multiplication and accumulation identifier, the target register identifier, and the source register identifier according to the instruction encoding rule of RISC-V to obtain a fixed-point multiplication and accumulation instruction; the fixed-point multiplication and accumulation instruction includes a first multiplication instruction and a second multiplication instruction, the first multiplication instruction is used to represent the execution of a fixed-point multiplication, and right-shift and saturate the result, and the second multiplication instruction is used to represent the execution of a signed or unsigned multiplication, and saturate to a specific value and write it back to the target register pair.

[0063] It should be noted that the above-mentioned fixed-point multiplication and accumulation identifiers can be DKHM, DKHMX, DSMMUL, etc., which are customized according to actual needs. The above-mentioned fixed-point multiplication and accumulation instructions may include: DKHMx, DKHMXx, DSMMUL, wherein the first multiplication instruction may include DKHMx instructions and DKHMXx instructions, and the DKHMx instructions and DKHMXx instructions are used to perform fixed-point multiplication, and right-shift and saturate the results, which are suitable for applications such as digital filtering. The second multiplication instruction may include: DSMMUL instructions and their variants, which are used to perform signed or unsigned multiplication, and saturate to a specific value and write back to the target register pair.

[0064] It can be understood that the fixed-point multiplication and accumulation instruction is obtained by combining the target register identifier (Rd) and the source register identifier (Rs1, Rs2). The above DKHMx instructions may include: DKHM8 Rd, Rs1, Rs2 and DKHM16 Rd, Rs1, Rs2. For DKHM8 Rd, Rs1, Rs2, RV32 is used to characterize that the DKHM8 instruction simultaneously completes 8 Q7xQ7 multiplication operations, and shifts the calculated 8 Q14 right by 7 bits and saturates to the Q7 value, and finally writes to the destination register pair. If saturation occurs, the OV flag is set to 1. For DKHM16 Rd, Rs1, Rs2, RV32: The DKHM16 instruction simultaneously completes 4 Q15xQ15 multiplication operations, and shifts the calculated 4 Q31 right by 15 bits and saturates to the Q15 value, and finally writes to the destination register pair. If saturation occurs, the OV flag is set to 1.

[0065] DKHMXx instructions include DKHMX8 Rd, Rs1, Rs2 and DKHMX16 Rd, Rs1, Rs2. For DKHMX8Rd, Rs1, Rs2, RV32: DKHMX8 instruction simultaneously completes 8 Q7xQ7 cross multiplication operations, and shifts the calculated 8 Q14 right by 7 bits and saturates to Q7 value, and finally writes to the destination register pair. If saturation occurs, the OV flag is set to 1. For DKHMX16 Rd, Rs1, Rs2, RV32: DKHMX16 instruction simultaneously completes 4 Q15xQ15 cross multiplication operations, and shifts the calculated 4 Q31 right by 15 bits and saturates to Q15 value, and finally writes to the destination register pair. If saturation occurs, the OV flag is set to 1.

[0066] DSMMUL instructions include: DSMMUL Rd, Rs1, Rs2 and DSMMULU Rd, Rs1, Rs2. For DSMMULRd, Rs1, Rs2, RV32: DSMMUL instruction completes two 32-bit signed multiplications at the same time and writes the upper 32 bits of the two multiplication results to the register pair. For DSMMULU Rd, Rs1, Rs2, RV32: DSMMULU instruction completes two 32-bit unsigned multiplications at the same time and writes the upper 32 bits of the two multiplication results to the register pair.

[0067] DSMMUL instruction variants include: DKWMMUL Rd, Rs1, Rs2 and DKWMMUL.U Rd, Rs1, Rs2. For DKWMMUL Rd, Rs1, Rs2, RV32: The DKWMMUL instruction performs two 32-bit signed multiplications at the same time, multiplies the two multiplication results by 2, takes the upper 32 bits and saturates them to the Q31 value, and then writes them to the register pair. If saturation occurs, the OV flag is set to 1. For DKWMMUL.U Rd, Rs1, Rs2, RV32: The DKWMMULU instruction performs two 32-bit unsigned multiplications at the same time, multiplies the two multiplication results by 2, takes the upper 32 bits and saturates them to the Q31 value, and then writes them to the register pair. If saturation occurs, the OV flag is set to 1.

[0068] For DKCLIP64 Rd, Rs1, RV32: The DKCLIP64 instruction arithmetically shifts the 64-bit number in register pair Rs1 right by 15 bits, saturates to Q15 value, and writes to the destination register. It is usually used to perform arithmetic operations on data and saturate when the result exceeds the predetermined range. The function of the DKCLIP64 instruction is to arithmetically shift the 64-bit number in register pair Rs1 right by 15 bits, saturate to Q15 format, and write to the destination register Rd.

[0069] For DKMDA Rd, Rs1, Rs2, RV32: The DKMDA instruction performs two sequential 16-bit signed multiplications on the high and low 32 bits of the source register pair, then saturates the sum of the two multiplication results to the Q31 value and writes it to the destination register pair. This instruction can be used especially in scenarios where a large number of multiplication and accumulation operations need to be performed, such as filters, convolution operations, etc.

[0070] For DKMXDA Rd, Rs1, Rs2, RV32: The DKMDA instruction performs two interleaved 16-bit signed multiplications on the high and low 32 bits of the source register pair Rs1 and Rs2, then saturates the sum of the two multiplication results to the Q31 value, and finally writes the result to the destination register pair Rd,. For DSMDRS Rd, Rs1, Rs2, RV32: The DKMDA instruction performs two interleaved 16-bit signed multiplications on the high and low 32 bits of the source register pair Rs1 and Rs2, then saturates the difference of the two multiplication results to the Q31 value in reverse order, and finally writes the result to the destination register pair Rd. For DSMXDS Rd, Rs1, Rs2, RV32: The DKMDA instruction performs two interleaved 16-bit signed multiplications on the high and low 32 bits of the source register pair Rs1 and Rs2, then saturates the difference of the two multiplication results to the Q31 value, and finally writes the result to the destination register pair Rd. For DSMBB32 Rd, Rs1, Rs2, RV32: The DSMBB32 instruction performs a signed multiplication of the lower 32 bits of the source register pair Rs1 and Rs2, and then writes the 64-bit multiplication result back to the destination register pair Rd. For DSMBB32.sra14 Rd, Rs1, Rs2, RV32: The DSMBB32.sra14 instruction performs a signed multiplication of the lower 32 bits of the Rs1 and Rs2 register pairs, and then writes the 64-bit multiplication result back to the destination register pair after arithmetic shift right 14 bits. For DSMBB32.sra32 Rd, Rs1, Rs2, RV32: The DSMBB32.sra32 instruction performs a signed multiplication of the lower 32 bits of the Rs1 and Rs2 register pairs, and then writes the 64-bit multiplication result back to the destination register pair after arithmetic shift right 32 bits.

[0071] For DSMBB16 Rd, Rs1, Rs2, RV32: The DSMBB16 instruction performs a signed multiplication of the lower 16 bits of Rs1 and Rs2 in the upper and lower 32 bits of the register pair, and writes the two 32-bit multiplication results back to the destination register pair. For DSMBT16 Rd, Rs1, Rs2, RV32: The DSMBT16 instruction performs a signed multiplication of the lower 16 bits of Rs1 and the upper 16 bits of Rs2 in the upper and lower 32 bits of the register pair, and writes the two 32-bit multiplication results back to the destination register pair. For DSMTT16Rd, Rs1, Rs2, RV32: The DSMTT16 instruction performs a signed multiplication of the upper 16 bits of Rs1 and the upper 16 bits of Rs2 in the upper and lower 32 bits of the register pair, and writes the two 32-bit multiplication results back to the destination register pair.

[0072] In the embodiment of the present application, by setting fixed-point multiplication and accumulation instructions, multiple multiplication and accumulation operations can be performed simultaneously through a single instruction, which can make full use of hardware resources and improve data throughput. Compared with using multiple general instructions to implement the same operation, the number of instructions required is reduced, thereby improving the execution efficiency of the code, and further significantly improving the performance of computationally intensive tasks.

[0073] In an optional embodiment of the present application, when the target instruction is an absolute value and arithmetic operation instruction, the target instruction is constructed according to the source register identifier and the target register identifier, including:

[0074] Obtain an absolute value and arithmetic operation identifier; according to the instruction encoding rule of RISC-V, combine the absolute value and arithmetic operation identifier, the target register identifier and the source register identifier to obtain an absolute value and arithmetic operation instruction; the absolute value and arithmetic operation instruction includes a first operation instruction and a second operation instruction, the first operation instruction is used to represent the calculation of the absolute values ​​of multiple numerical values, and the second operation instruction is used to represent the execution of addition and subtraction, and the result is saturated and written back to the target register pair.

[0075] It should be noted that the above absolute value and arithmetic operation identifiers may be DKABS, DKABS, DKADD, DKSUB, etc., which are customized according to actual needs. The above absolute value and arithmetic operation instructions may include: DKABSx, DKADDx, DKSUBx. Among them, the first operation instruction may include: DKABSx, and the second operation instruction may include: DKADDx and DKSUBx.

[0076] It can be understood that the absolute value and arithmetic operation instructions are obtained by combining the target register identifier (Rd) and the source register identifier (Rs1, Rs2). The above DKABSx instructions may include: DKABS8 Rd, Rs1 and DKABS16 Rd, Rs1. For DKABS8 Rd, Rs1, RV32: The DKABS8 instruction simultaneously calculates the absolute value of 8 8-bit signed numbers and then writes them to the destination register pair. If saturation occurs, the OV flag is set to 1. For DKABS16 Rd, Rs1, RV32: The DKABS16 instruction simultaneously calculates the absolute value of 4 16-bit signed numbers and then writes them to the destination register pair. If saturation occurs, the OV flag is set to 1.

[0077] DKADDx instructions can include: DKADD8 Rd, Rs1, Rs2 and DKADD16 Rd, Rs1, Rs2. For DKADD8 Rd, Rs1, Rs2, RV32: DKADD8 simultaneously calculates 8 8-bit signed additions and saturates to obtain 8 Q7 values, and then writes them to the destination register pair. If saturation occurs, the OV flag is set to 1. For DKADD16 Rd, Rs1, Rs2, RV32: DKADD16 simultaneously calculates 4 16-bit signed additions and saturates to obtain 4 Q15 values, and then writes them to the destination register pair. If saturation occurs, the OV flag is set to 1.

[0078] DKSUBx instructions include: DKSUB8 Rd, Rs1, Rs2 and DKSUB16 Rd, Rs1, Rs2. For DKSUB8Rd, Rs1, Rs2, RV32: DKSUB8 simultaneously calculates 8 8-bit signed subtractions and saturates to obtain 8 Q7 values, and then writes them to the destination register pair. If saturation occurs, the OV flag is set to 1. For DKSUB16 Rd, Rs1, Rs2, RV32: DKSUB16 simultaneously calculates 4 16-bit signed subtractions and saturates to obtain 4 Q15 values, and then writes them to the destination register pair. If saturation occurs, the OV flag is set to 1.

[0079] The DKABS instruction includes: DKABS32 Rd, Rs1. RV32: If the high or low 32 bits of the register pair Rs1 is 0x8000_0000, then the operation result of the high or low 32 bits corresponding to the DKABS32 instruction is 0x7fff_fff, and the OV flag is set to 1; otherwise, the DKABS32 instruction completes the operation of calculating the absolute value of two 32 bits at the same time, and finally updates it to the destination register pair.

[0080] The DKADD instruction includes: DKADD32 Rd, Rs1, Rs2. For DKADD32 Rd, Rs1, Rs2, RV32: DKADD32 simultaneously calculates two 32-bit signed additions and saturates them to obtain two Q31 values, which are then written to the destination register pair. If saturation occurs, the OV flag is set to 1.

[0081] DKSUB instructions include: DKSUB32 Rd, Rs1, Rs2. For DKSUB32 Rd, Rs1, Rs2, RV32: DKSUB32 simultaneously calculates two 32-bit signed subtractions and saturates to obtain two Q31 values, which are then written to the destination register pair. If saturation occurs, the OV flag is set to 1.

[0082] The DRADD16 and DRADD32 instructions calculate the average of multiple 16-bit and 32-bit signed additions, respectively, and write them to the destination register pair. For DRADD16 Rd, Rs1, Rs2, RV32: DRADD16 calculates the average of four 16-bit signed additions simultaneously and writes them to the destination register pair. For DRADD32 Rd, Rs1, Rs2, RV32: DRADD32 calculates the average of two 32-bit signed additions simultaneously and writes them to the destination register pair.

[0083] The DRSUB16 and DRSUB32 instructions calculate the difference average. For DRSUB16 Rd, Rs1, Rs2, RV32: DRSUB16 calculates the difference average of four 16-bit signed subtractions simultaneously and writes it to the destination register pair. For DRSUB32Rd, Rs1, Rs2, RV32: DRSUB32 calculates the difference average of two 32-bit signed subtractions simultaneously and writes it to the destination register pair.

[0084] The DMSR16, DMSR17, DMSR33, and DMXSR33 instructions perform signed multiplications and specific right shift operations and write back to the destination register pair. For DMSR16 Rd, Rs1, Rs2, RV32: The DMSR16 instruction performs two sequential 16-bit signed multiplications on the lower 32 bits of the register pair. Two interleaved 16-bit signed multiplications are performed on the upper 32 bits of the register pair, and then the 4 multiplication results are arithmetic right shifted 16 bits and saturated to the Q15 value, and finally written to the destination register pair. For DMSR17 Rd,Rs1, Rs2, RV32: The DMSR16 instruction performs two sequential 16-bit signed multiplications on the lower 32 bits of the register pair. Two interleaved 16-bit signed multiplications are performed on the upper 32 bits of the register pair, and then the 4 multiplication results are arithmetic right shifted 17 bits and saturated to the Q15 value, and finally written to the destination register pair. For DMSR33 Rd, Rs1, Rs2, RV32: The DMSR33 instruction does two sequential 32-bit signed multiplications, then calculates the right shift of the two multiplication results by 33 bits, and finally writes them to the destination register pair. For DMXSR33 Rd, Rs1, Rs2, RV32: The DMSR33 instruction does two interleaved 32-bit signed multiplications, then calculates the right shift of the two multiplication results by 33 bits, and finally writes them to the destination register pair.

[0085] The DREDAS16 and DREDSA16 instructions perform specific addition and subtraction operations on registers and then write them to the destination register. For DREDAS16 Rd, Rs1, RV32: The DREDAS16 instruction performs a sequential 16-bit subtraction on the lower 32 bits of register pair Rs1, performs a sequential 16-bit addition on the upper 32 bits, and then writes them to the destination register. For DREDSA16 Rd, Rs1, RV32: The DREDAS16 instruction performs a sequential 16-bit addition on the lower 32 bits of register pair Rs1, performs a sequential 16-bit subtraction on the upper 32 bits, and then writes them to the destination register.

[0086] For DADD16 Rd, Rs1, Rs2, RV32: The DADD16 instruction performs four 16-bit signed additions simultaneously and writes the results back to the destination register pair. For DADD32 Rd, Rs1, Rs2, RV32: The DADD32 instruction performs two 32-bit signed additions simultaneously and writes the results back to the destination register pair. For DSUB16 Rd, Rs1, Rs2, RV32: The DSUB16 instruction performs four 16-bit signed subtractions simultaneously and writes the results back to the destination register pair. For DSUB32 Rd, Rs1, Rs2, RV32: The DSUB32 instruction performs two 32-bit signed subtractions simultaneously and writes the results back to the destination register pair.

[0087] For DSTSA32 Rd, Rs1, Rs2, RV32: DSTSA32 instruction performs 32-bit subtraction and addition on the upper and lower 32 bits of the register pair, and writes the difference and sum back to the destination register pair. For DSTAS32 Rd, Rs1, Rs2, RV32: DSTAS32 instruction performs 32-bit addition and subtraction on the upper and lower 32 bits of the register pair, and writes the sum and difference back to the destination register pair. In this application, RV32 refers to a 32-bit RISC-V processor; RV64 refers to a 64-bit RISC-V processor.

[0088] In the embodiments of the present application, by constructing absolute value and arithmetic operation instructions, absolute value or arithmetic operations can be performed on multiple data elements at the same time through a single instruction, which can significantly improve data throughput. Compared with using multiple general instructions to implement the same operation, dedicated absolute value and arithmetic operation instructions reduce the number of instructions required, thereby improving the execution efficiency of the code.

[0089] In an optional embodiment of the present application, when the target instruction is a shift and saturation instruction, the target instruction is constructed according to the source register identifier and the target register identifier, including:

[0090] Get the shift and saturation flag; according to the instruction encoding rules of RISC-V, combine the shift and saturation flag, the target register flag and the source register flag to obtain the shift and saturation instruction; the shift and saturation instruction is used to represent the execution of a logical left shift or an arithmetic right shift according to the number of bits specified in the register, and saturate the result and write it back to the target register pair.

[0091] It should be noted that the above shift and saturation flag may be DKSLRA, which is customized according to actual needs. The above shift and saturation instruction may include: DKSLRAx.

[0092] It can be understood that the shift and saturation instructions are obtained by combining the target register identifier (Rd) and the source register identifier (Rs1, Rs2). The above DKSLRAx instructions may include: DKSLRA8 Rd, Rs1, Rs2, DKSLRA16 Rd, Rs1, Rs2 and DKSLRA32 Rd, Rs1, Rs2. For DKSLRA8 Rd, Rs1, Rs2, RV32: If the lower 4 bits of register Rs2 are positive, then the DKSLRA8 instruction logically shifts left by Rs2[3:0] bits; if the lower 4 bits of register Rs2 are negative, then the DKSLRA8 instruction arithmetic shifts right by -Rs2[3:0] bits and saturates to Q7 value. The DKSLRA8 instruction calculates 8 of the above shift operations at the same time and writes the calculated 8 Q7 values ​​to the destination register pair. If saturation operation occurs, the OV flag is set to 1. For DKSLRA16 Rd, Rs1, Rs2, RV32: If the lower 5 bits of register Rs2 are positive, then the DKSLRA16 instruction logically shifts left by Rs2[4:0] bits; if the lower 5 bits of register Rs2 are negative, then the DKSLRA16 instruction arithmetic shifts right by -Rs2[4:0] bits and saturates to Q15 value. The DKSLRA16 instruction calculates 4 of the above shift operations simultaneously and writes the calculated 4 Q15 values ​​to the destination register pair. If saturation occurs, the OV flag is set to 1. For DKSLRA32 Rd, Rs1, Rs2, RV32: If the lower 6 bits of register Rs2 are positive, then the DKSLRA32 instruction logically shifts left by Rs2[5:0] bits; if the lower 6 bits of register Rs2 are negative, then the DKSLRA32 instruction arithmetic shifts right by -Rs2[5:0] bits and saturates to Q31 value. The DKSLRA32 instruction calculates the two shift operations mentioned above at the same time and writes the calculated two Q31 values ​​to the destination register pair. If a saturation operation occurs, the OV flag is set to 1.

[0093] For DSMBT32 Rd, Rs1, Rs2, RV32: The DSMBB32 instruction performs a signed multiplication of the lower 32 bits of the Rs1 register pair with the upper 32 bits of the Rs2 register pair, and then writes the 64-bit multiplication result back to the destination register pair. For DSMBT32.sra14 Rd, Rs1, Rs2, RV32: The DSMBB32.sra14 instruction performs a signed multiplication of the lower 32 bits of the Rs1 register pair with the upper 32 bits of the Rs2 register pair, and then writes the 64-bit multiplication result back to the destination register pair after arithmetic right shift 14 bits. For DSMBT32.sra32 Rd, Rs1, Rs2, RV32: The DSMBB32.sra32 instruction performs a signed multiplication of the lower 32 bits of the Rs1 register pair with the upper 32 bits of the Rs2 register pair, and then writes the 64-bit multiplication result back to the destination register pair after arithmetic right shift 32 bits. For DSMTT32 Rd, Rs1, Rs2, RV32: The DSMBB32 instruction performs a signed multiplication of the upper 32 bits of the Rs1 register pair with the upper 32 bits of the Rs2 register pair, and then writes the 64-bit multiplication result back to the destination register pair. For DSMTT32.sra14 Rd, Rs1, Rs2, RV32: The DSMBB32.sra14 instruction performs a signed multiplication of the upper 32 bits of the Rs1 register pair with the upper 32 bits of the Rs2 register pair, and then writes the 64-bit multiplication result back to the destination register pair after arithmetic right shift 14 bits. For DSMTT32.sra32 Rd, Rs1, Rs2, RV32: The DSMBB32.sra32 instruction performs a signed multiplication of the upper 32 bits of the Rs1 register pair with the upper 32 bits of the Rs2 register pair, and then writes the 64-bit multiplication result back to the destination register pair after arithmetic right shift 32 bits. For DSRA16 Rd, Rs1, Rs2, RV32: The DSRA16 instruction performs four 16-bit arithmetic right shifts on the Rs1 register pair to Rs2[3:0] simultaneously, obtains four 16-bit shift results and writes them back to the destination register pair.

[0094] For DRCRSA16 Rd, Rs1, Rs2, RV32: The DRCRSA16 instruction performs interleaved 16-bit addition and subtraction on the upper and lower 32 bits of the register pair, and then arithmetic shifts the 16-bit sums and differences right by 1 bit before writing them back to the destination register pair. For DRCRSA32 Rd, Rs1, Rs2, RV32: The DRCRSA32 instruction performs interleaved 32-bit addition and subtraction on the upper and lower 32 bits of the register pair, and then arithmetic shifts the 32-bit sums and differences right by 1 bit before writing them back to the destination register pair. For DRCRAS16 Rd,Rs1, Rs2, RV32: The DRCRAS16 instruction performs interleaved 16-bit subtraction and addition on the upper and lower 32 bits of the register pair, and then arithmetic shifts the 16-bit sums and differences right by 1 bit before writing them back to the destination register pair. For DRCRAS32 Rd, Rs1, Rs2, RV32: The DRCRAS32 instruction performs interleaved 32-bit subtraction and addition on the high and low 32 bits of the register pair, then arithmetic right shifts the 32-bit sum and difference by 1 bit and writes them back to the destination register pair.

[0095] For DKCRAS16 Rd, Rs1, Rs2, RV32: The DRCRAS16 instruction performs interleaved 16-bit subtraction and addition on the upper and lower 32 bits of the register pair, and then saturates the 16-bit sums and differences to the Q15 value before writing them back to the destination register pair. For DKCRSA16 Rd, Rs1, Rs2, RV32: The DRCRSA16 instruction performs interleaved 16-bit addition and subtraction on the upper and lower 32 bits of the register pair, and then saturates the 16-bit sums and differences to the Q15 value before writing them back to the destination register pair. For DRSUB16 Rd,Rs1, Rs2, RV32: The RSUB16 instruction performs four 16-bit signed subtractions simultaneously, and writes the subtraction results back to the destination register pair after arithmetic right shifting by 1 bit.

[0096] For DKCRSA32 Rd, Rs1, Rs2, RV32: DSTSA32 instruction performs 32-bit subtraction and addition on the upper and lower 32 bits of the register pair, saturates the difference and sum to Q31 value and writes back to the destination register pair. For DKCRAS32 Rd, Rs1, Rs2, RV32: DSTAS32 instruction performs 32-bit addition and subtraction on the upper and lower 32 bits of the register pair, saturates the sum and difference to Q31 value and writes back to the destination register pair. For DCRSA32 Rd, Rs1, Rs2, RV32: DSTSA32 instruction performs 32-bit cross subtraction and cross addition on the upper and lower 32 bits of the register pair, saturates the difference and sum to Q31 value and writes back to the destination register pair. For DCRAS32 Rd, Rs1, Rs2, RV32: DSTAS32 instruction performs 32-bit cross addition and cross subtraction on the upper and lower 32 bits of the register pair, and writes the sum and difference back to the destination register pair. For DKSTSA16 Rd, Rs1, Rs2, RV32: DSTSA16 instruction performs 16-bit subtraction and addition on the upper and lower 32 bits of the register pair, and saturates the difference and sum to the Q15 value and writes them back to the destination register pair. For DKSTAS16 Rd, Rs1, Rs2, RV32: DSTSA16 instruction performs 16-bit addition and subtraction on the upper and lower 32 bits of the register pair, and saturates the sum and difference to the Q15 value and writes them back to the destination register pair. In this application, RV32 refers to a 32-bit RISC-V processor; RV64 refers to a 64-bit RISC-V processor.

[0097] In the embodiment of the present application, by constructing shift and saturation instructions, shift operations can be performed on multiple data elements at the same time through a single instruction, which significantly improves data throughput. The use of shift and saturation instructions reduces the number of instructions required and improves the execution efficiency of the code.

[0098] In an optional embodiment of the present application, when the target instruction is a data packing and unpacking instruction, the target instruction is constructed according to the source register identifier and the target register identifier, including:

[0099] Obtain a data packing and unpacking identifier; combine the data packing and unpacking identifier, the target register identifier and the source register identifier according to the RISC-V instruction encoding rule to obtain a data packing and unpacking instruction; the data packing and unpacking instruction is used to represent packing data blocks of different sizes into data units or decomposing data units into data blocks of different sizes and writing them back to the target register pair; the size of the data block is smaller than the size of the data unit.

[0100] It should be noted that the above data packing and unpacking identifiers may be DPKBB, DPKBT, which are customized according to actual needs. The above data packing and unpacking instructions may include: DPKBB32, DPKBT32, DPKTT32, DPKTB32. Instructions such as DPKBB32, DPKBT32, DPKTT32, and DPKTB32 pack different bits of a register pair and write them back to the destination register pair.

[0101] It can be understood that the data packing and unpacking instructions are obtained by combining the target register identifier (Rd) and the source register identifier (Rs1, Rs2). The above DPKBB32 instructions may include: DPKBB32 Rd, Rs1, Rs2 and DPKBB16Rd, Rs1, Rs2. For DPKBB32 Rd, Rs1, Rs2, the RV32: DPKBB32 instruction packs the lower 32 bits of the Rs1 register pair and the lower 32 bits of the Rs2 register pair into a 64-bit number and writes it back to the destination register pair. For DPKBB16 Rd, Rs1, Rs2, the RV32: DPKBB16 instruction packs the lower 16 bits of Rs1 and the lower 16 bits of Rs2 in the upper and lower 32 bits of the register pair to obtain a 32-bit number and writes it back to the destination register pair. The above-mentioned DPKBT32 instructions include: DPKBT32 Rd, Rs1, Rs2. For DPKBT32 Rd, Rs1, Rs2, the RV32: DPKBT32 instruction packs the lower 32 bits of the Rs1 register pair and the upper 32 bits of the Rs2 register pair into a 64-bit number and writes it back to the destination register pair.

[0102] The DPKTT32 instruction includes: DPKTT32 Rd, Rs1, Rs2. For DPKTT32 Rd, Rs1, Rs2, RV32: DPKTT32 instruction packs the high 32 bits of Rs1 register pair and the high 32 bits of Rs2 register pair into 64 bits and writes them back to the destination register pair. The DPKTB32 instruction includes: DPKTB32 Rd, Rs1, Rs2 and DPKTB16 Rd, Rs1, Rs2. For DPKTB32 Rd, Rs1, Rs2, RV32: DPKTB32 instruction packs the high 32 bits of Rs1 register pair and the low 32 bits of Rs2 register pair into 64 bits and writes them back to the destination register pair. For DPKTB16 Rd, Rs1, Rs2, RV32: The DPKTB16 instruction packs the upper 16 bits of Rs1 and the lower 16 bits of Rs2 in the upper and lower 32 bits of the register pair to obtain a 32-bit number and then writes it back to the destination register pair.

[0103] For PKBT16 Rd, Rs1, Rs2, RV32: DPKBT16 instruction packs the lower 16 bits of Rs1 and the upper 16 bits of Rs2 in the upper and lower 32 bits of the register pair to get a 32-bit value and writes it back to the destination register pair. For DPKTT16 Rd, Rs1, Rs2, RV32: DPKTT16 instruction packs the upper 16 bits of Rs1 and the upper 16 bits of Rs2 in the upper and lower 32 bits of the register pair to get a 32-bit value and writes it back to the destination register pair.

[0104] DSCLIP8, DSCLIP16, and DSCLIP32 instructions perform operations based on truncated immediate values ​​and write them back to the destination register pair. DSCLIP8 instructions include: DSCLIP8 Rd, Rs1, imm3u[2:0]. For DSCLIP8 Rd, Rs1, imm3u[2:0], RV32: DSCLIP8 instructions perform eight 8-bit operations based on truncated immediate values ​​at the same time and write them back to the destination register pair. DSCLIP16 instructions include: DSCLIP16 Rd, Rs1, imm4u[3:0]. For DSCLIP16 Rd, Rs1,imm4u[3:0], RV32: DSCLIP16 instructions perform four 16-bit operations based on truncated immediate values ​​at the same time and write them back to the destination register pair. The DSCLIP32 instruction includes: DSCLIP32 Rd, Rs1, imm5u[3:0], for DSCLIP32 Rd, Rs1, imm5u[3:0], RV32: DSCLIP32 instruction performs two 32-bit immediate truncated operations at the same time, and then writes them back to the destination register pair. In this application, RV32 refers to a 32-bit RISC-V processor; RV64 refers to a 64-bit RISC-V processor.

[0105] In the embodiment of the present application, by constructing data packing and unpacking instructions, it is possible to facilitate the alignment of data to register boundaries, facilitate data alignment and format conversion operations, and facilitate the processing of multi-channel data, thereby meeting high-performance computing requirements.

[0106] In an optional embodiment of the present application, when the target instruction is other special instructions, the target instruction is constructed according to the source register identifier and the target register identifier, including:

[0107] Get a special instruction identifier; according to the instruction encoding rules of RISC-V, combine the special instruction identifier, the target register identifier and the source register identifier to obtain other special instructions; the other special instructions include a first special instruction, a second special instruction and a third special instruction, the first special instruction is used to represent the execution of cross addition and subtraction operations, and right shifting and saturating the results and writing them back to the target register pair, the second special instruction is used to represent the truncation processing based on the immediate number and writing them back to the target register pair, and the third special instruction is used to represent the execution of multiplication and addition and multiplication and subtraction operations and writing them back to the target register pair.

[0108] It should be noted that the above-mentioned special instruction identifier can be DPKBB, DPKBT, which is customized according to actual needs. The above-mentioned data packing and unpacking instructions can include a first special instruction, a second special instruction and a third special instruction, and the first special instruction can include: DKCRSAx, DRCRSAx, DKSTSAx. The second special instruction can include: DSCLIPx. The third special instruction can include: DKMMAC, DKMMSB, DKMADA. Instructions such as DKCRSAx, DRCRSAx, DKSTSAx perform cross addition and subtraction operations, and right shift and saturate the results. The DSCLIPx instruction truncates the data according to the immediate number, which can be used for the quantization process in signal processing. Instructions such as DKMMAC, DKMMSB, DKMADA perform complex multiplication and addition and multiplication and subtraction operations, and are widely used in digital filters and other signal processing algorithms.

[0109] DKMMAC instructions include: DKMMAC Rd, Rs1, Rs2 and DKMMACU Rd, Rs1, Rs2. For DKMMACRd, Rs1, Rs2, RV32: The DKMMAC instruction adds the upper 32 bits of the 32-bit signed multiplication result of Rd plus Rs1 and Rs2 to the upper and lower 32 bits of the register pair, then saturates to the Q31 value, and finally writes it back to the destination register pair. For DKMMACU Rd,Rs1, Rs2, RV32: The DKMMACU instruction adds the upper 32 bits of the 32-bit unsigned multiplication result of Rd plus Rs1 and Rs2 to the upper and lower 32 bits of the register pair, then saturates to the Q31 value, and finally writes it back to the destination register pair.

[0110] DKMMSB instructions include: DKMMSB Rd, Rs1, Rs2 and DKMMSBU Rd, Rs1, Rs2. For DKMMSBRd, Rs1, Rs2, RV32: The DKMMSB instruction performs the upper 32 bits of the 32-bit signed multiplication result of Rd minus Rs1 and Rs2 on the upper and lower 32 bits of the register pair, then saturates to the Q31 value, and finally writes it back to the destination register pair. For DKMMSBU Rd,Rs1, Rs2, RV32: The DKMMSBU instruction performs the upper 32 bits of the 32-bit unsigned multiplication result of Rd minus Rs1 and Rs2 on the upper and lower 32 bits of the register pair, then saturates to the Q31 value, and finally writes it back to the destination register pair.

[0111] DKMADA instructions include: DKMADA Rd, Rs1, Rs2 and DKMAXDA Rd, Rs1, Rs2. For DKMADARd, Rs1, Rs2, RV32: DKMADA instruction performs Rd plus two 16-bit signed multiplication results of Rs1 and Rs2 in the upper and lower 32 bits of the register pair at the same time, then saturates to the Q31 value, and finally writes back to the destination register pair. For DKMAXDA Rd, Rs1, Rs2, RV32: DKMADA instruction performs Rd plus two 16-bit signed cross multiplication results of Rs1 and Rs2 in the upper and lower 32 bits of the register pair at the same time, then saturates to the Q31 value, and finally writes back to the destination register pair.

[0112] Optionally, other special instructions are included. For DKMADS Rd, Rs1, Rs2, RV32: the DKMADS instruction performs the addition and subtraction of the two 16-bit signed multiplication results of Rs1 and Rs2 on the upper and lower 32 bits of the register pair, and then saturates to the Q31 value, and finally writes back to the destination register pair. For DKMADRS Rd, Rs1, Rs2, RV32: the DKMADRS instruction performs the subtraction and addition of the two 16-bit signed multiplication results of Rs1 and Rs2 on the upper and lower 32 bits of the register pair, and then saturates to the Q31 value, and finally writes back to the destination register pair. For DKMAXDS Rd, Rs1, Rs2, RV32: the DKMAXDS instruction performs the addition and subtraction of the two 16-bit signed cross multiplication results of Rs1 and Rs2 on the upper and lower 32 bits of the register pair, and then saturates to the Q31 value, and finally writes back to the destination register pair. For DKMSDA Rd, Rs1, Rs2, RV32: The DKMSDA instruction performs the two 16-bit signed multiplication results of Rd minus Rs1 and Rs2 on the upper and lower 32 bits of the register pair, then saturates to the Q31 value, and finally writes it back to the destination register pair. For DKMSXDA Rd, Rs1, Rs2, RV32: The DKMSXDA instruction performs the two 16-bit signed cross multiplication results of Rd minus Rs1 and Rs2 on the upper and lower 32 bits of the register pair, then saturates to the Q31 value, and finally writes it back to the destination register pair.

[0113] For DSMAQA Rd, Rs1, Rs2, RV32: The DSMAQA instruction performs the 4 8-bit signed multiplication results of Rd plus Rs1 and Rs2 on the upper and lower 32 bits of the register pair, and finally writes them back to the destination register pair. For DSMAQASURd, Rs1, Rs2, RV32: The DSMAQASU instruction performs the 4 8-bit signed multiplication results of Rd plus Rs1 and Rs2 on the upper and lower 32 bits of the register pair, and finally writes them back to the destination register pair. For DUMAQA Rd, Rs1,Rs2, RV32: The DUMAQA instruction performs the 4 8-bit unsigned multiplication results of Rd plus Rs1 and Rs2 on the upper and lower 32 bits of the register pair, and finally writes them back to the destination register pair. For DKMDA32 Rd, Rs1, Rs2, RV32: The DKMDA32 instruction adds the two 32-bit signed multiplication results and writes the added sum saturated to the Q63 value back to the destination register pair. For DKMXDA32 Rd, Rs1, Rs2, RV32: The DKMXDA32 instruction adds the two 32-bit signed cross multiplication results and writes the added sum saturated to the Q63 value back to the destination register pair.

[0114] For DKMADA32 Rd, Rs1, Rs2, RV32: The DKMADA32 instruction adds two 32-bit signed multiplication results to Rd and writes the added sum saturated to Q63 back to the destination register pair. For DKMAXDA32 Rd, Rs1, Rs2, RV32: The DKMAXDA32 instruction adds two 32-bit signed cross multiplication results to Rd and writes the added sum saturated to Q63 back to the destination register pair. For DKMADS32 Rd, Rs1, Rs2, RV32: The DKMADS32 instruction adds and subtracts two 32-bit signed multiplication results to Rd, respectively, and writes the added sum saturated to Q63 back to the destination register pair. For DKMADRS32 Rd, Rs1, Rs2, RV32: The DKMADRS32 instruction subtracts and adds the two 32-bit signed multiplication results to Rd, and writes the added sum saturated to Q63 value back to the destination register pair. For DKMAXDS32 Rd, Rs1, Rs2, RV32: The DKMAXDS32 instruction subtracts and adds the two 32-bit signed cross multiplication results to Rd, and writes the added sum saturated to Q63 value back to the destination register pair. For DKMAXDS32 Rd, Rs1, Rs2, RV32: The DKMAXDS32 instruction subtracts and adds the two 32-bit signed cross multiplication results to Rd, and writes the added sum saturated to Q63 value back to the destination register pair. For DKMSDA32 Rd, Rs1, Rs2, RV32: The DKMSDA32 instruction subtracts two 32-bit signed multiplication results from Rd and adds them together, and saturates the sum to the Q63 value and writes it back to the destination register pair. For DKMSXDA32 Rd, Rs1, Rs2, RV32: The DKMSXDA32 instruction subtracts two 32-bit signed cross multiplication results from Rd and adds them together, and saturates the sum to the Q63 value and writes it back to the destination register pair.

[0115] For DSMDS32 Rd, Rs1, Rs2, RV32: The DSMDS32 instruction subtracts the two 32-bit signed multiplication results in reverse order and writes the difference back to the destination register pair. For DSMDRS32 Rd, Rs1, Rs2, RV32: The DSMDS32 instruction subtracts the two 32-bit signed cross-multiplication results in reverse order and writes the difference back to the destination register pair. For DSMXDS32 Rd, Rs1, Rs2, RV32: The DSMXDS32 instruction subtracts the two 32-bit signed multiplication results and writes the difference back to the destination register pair. For DSMALDA Rd, Rs1, Rs2, RV32: The DSMALDA instruction adds four 16-bit signed multiplication results to Rd and writes the sum back to the destination register pair. For DSMALXDA Rd, Rs1, Rs2, RV32: The DSMALXDA instruction adds four 16-bit signed cross multiplication results to Rd and writes the added sum back to the destination register pair.

[0116] For DSMALDS Rd, Rs1, Rs2, the DSMALDS instruction adds, subtracts, adds and subtracts four 16-bit signed multiplication results to Rd and writes the added sum back to the destination register pair. For DSMALDRS Rd, Rs1, Rs2, the DSMALDRS instruction subtracts, adds, subtracts and adds four 16-bit signed multiplication results to Rd and writes the added sum back to the destination register pair. For DSMALXDS Rd, Rs1, Rs2, the DSMALXDS instruction adds, subtracts, adds and subtracts four 16-bit signed cross multiplication results to Rd and writes the added sum back to the destination register pair.

[0117] For DSMSLDA Rd, Rs1, Rs2, RV32: The DSMSLDA instruction subtracts four 16-bit signed multiplication results from Rd and writes the added sum back to the destination register pair. For DSMSLXDA Rd, Rs1, Rs2, RV32: The DSMSLXDA instruction subtracts four 16-bit signed cross multiplication results from Rd and writes the added sum back to the destination register pair. For DDSMAQA Rd, Rs1, Rs2, RV32: The DDSMAQA instruction adds eight 8-bit signed multiplication results to Rd and writes the added sum back to the destination register pair. For DDSMAQASU Rd, Rs1, Rs2, RV32: The DDSMAQASU instruction adds eight 8-bit signed by 8-bit unsigned multiplication results to Rd and writes the added sum back to the destination register pair. For DDUMAQA Rd, Rs1, Rs2, RV32: The DDSMAQA instruction adds eight 8-bit unsigned multiplication results to Rd and writes the added sum back to the destination register pair.

[0118] For DSMA32.u Rd, Rs1, Rs2, RV32: The DSMA32.u instruction adds the two 32-bit signed multiplication results, rounds them, shifts them right 32 bits, saturates them to the Q31 value, and writes them back to the destination register. For DSMXS32.u Rd, Rs1, Rs2, RV32: The DSMXS32.u instruction subtracts the two 32-bit signed cross multiplication results, rounds them, shifts them right 32 bits, saturates them to the Q31 value, and writes them back to the destination register. For DSMXA32.uRd, Rs1, Rs2, RV32: The DSMA32.u instruction adds the two 32-bit signed cross multiplication results, rounds them, shifts them right 32 bits, saturates them to the Q31 value, and writes them back to the destination register. For DSMS32.u Rd, Rs1, Rs2, RV32: The DSMS32.u instruction subtracts the two 32-bit signed multiplication results, rounds them, arithmetically shifts them right by 32 bits, saturates them to the Q31 value, and writes them back to the destination register.

[0119] For DSMADA16 Rd, Rs1, Rs2, RV32: The DSMADA16 instruction adds the sign extension of the result of the 4 16-bit signed multiplication to Rd, and writes the sum back to the destination register. For DSMAXDA16 Rd, Rs1, Rs2, RV32: The DSMADA16 instruction adds the sign extension of the result of the 4 16-bit signed cross multiplication to Rd, and writes the sum back to the destination register. For DKSMS32.u Rd, Rs1, Rs2, RV32: The DKSMS32.u instruction rounds the 32-bit signed multiplication result to [47:32] in the upper and lower 32 bits, then adds the 32 bits corresponding to Rd, and finally saturates to the Q31 value and writes it back to the destination register pair. For DMADA32 Rd, Rs1, Rs2, RV32: The DMADA32 instruction adds the two 32-bit signed multiplication results, saturates to the Q31 value and writes them back to the destination register. For DSMALBB Rd, Rs1, Rs2, RV32: The DSMALBB instruction multiplies the upper and lower 32 bits of the register pair by the lower 16 bits of Rs1 and Rs2, and sign-extends the two 32-bit multiplication results to 64 bits, adds Rd, and writes the added sum back to the destination register pair. For DSMALBT Rd, Rs1, Rs2, RV32: The DSMALBT instruction multiplies the upper and lower 32 bits of the register pair by the lower 16 bits of Rs1 and the upper 16 bits of Rs2, and sign-extends the two 32-bit multiplication results to 64 bits, adds Rd, and writes the added sum back to the destination register pair. For DSMALTT Rd, Rs1, Rs2, RV32: DSMALTT instruction multiplies the upper and lower 32 bits of the register pair by the upper 16 bits of Rs1 and the upper 16 bits of Rs2, and sign-extends the two 32-bit multiplication results to 64 bits, adds Rd, and writes the added sum back to the destination register pair. For DKMABB32 Rd, Rs1, Rs2, RV32: DKMABB32 adds Rd to the lower 32 bits of Rs1 and Rs2, saturates the added sum to the Q63 value, and writes it back to the destination register pair. For DKMABT32 Rd, Rs1, Rs2, RV32: DKMABT32 adds Rd to the lower 32 bits of Rs1 and the upper 32 bits of Rs2, and saturates the added sum to the Q63 value, and writes it back to the destination register pair. For DKMATT32 Rd, Rs1, Rs2, RV32: DKMATT32 adds Rd to the upper 32-bit signed multiplication result of Rs1 and Rs2, saturates the sum to the Q63 value, and writes it back to the destination register pair.In this application, RV32 refers to a 32-bit RISC-V processor; RV64 refers to a 64-bit RISC-V processor.

[0120] In the embodiments of the present application, by constructing other special instructions, it is possible to complete multiple complex operations within one clock cycle, and compared to using multiple general instructions to implement the same operation, the dedicated special instructions reduce the number of instructions required, thereby improving the execution efficiency of the code, and supporting a variety of efficient algorithms. For example, for many digital filters (such as FIR and IIR filters), specific data processing modes are required. Special instructions can directly support these operations and simplify the implementation of filters. For the fast Fourier transform (FFT), the FFT algorithm contains a large number of complex multiplications and additions, and special instructions can speed up these calculations. For image processing: In image processing, applications such as convolution operations and edge detection may require specific data processing modes, and special instructions can simplify these operations. For audio processing: In applications such as audio encoding / decoding, echo cancellation, and noise suppression, special instructions can optimize common audio processing tasks.

[0121] on the other hand, Figure 4 Schematic diagram of the structure of an instruction construction device provided in an embodiment of the present application. The instruction construction device may be a module in a terminal or a server, such as Figure 4 As shown, including:

[0122] The acquisition module 310 is used to acquire the operand format; the operand format includes a source register identifier and a target register identifier;

[0123] The construction module 320 is used to construct a target instruction according to the source register identifier and the target register identifier; the target instruction is a digital signal processing DSP extension instruction based on the RISC-V architecture, and the target instruction includes at least one of the following: byte extension instruction, fixed-point multiplication and accumulation instruction, absolute value and arithmetic operation instruction, shift and saturation instruction, data packing and unpacking instruction, and other special instructions; the target instruction is used to expand the 32-bit data path to a 64-bit data path.

[0124] Optionally, the building module 320 is specifically used for:

[0125] Get the byte extension flag;

[0126] According to the instruction encoding rules of RISC-V, the byte extension identifier, the target register identifier and the source register identifier are combined to obtain a byte extension instruction; the byte extension instruction is used to represent the expansion of the bytes of the source register and store them in the target register.

[0127] Optionally, the building module 320 is specifically used for:

[0128] Get the fixed-point multiplication and accumulation flags;

[0129] According to the instruction encoding rules of RISC-V, the fixed-point multiplication and accumulation identifier, the target register identifier and the source register identifier are combined to obtain the fixed-point multiplication and accumulation instruction; the fixed-point multiplication and accumulation instruction includes a first multiplication instruction and a second multiplication instruction. The first multiplication instruction is used to represent the execution of fixed-point multiplication, and right-shift and saturate the result. The second multiplication instruction is used to represent the execution of signed or unsigned multiplication, and saturate to a specific value and write it back to the target register pair.

[0130] Optionally, the building module 320 is specifically used for:

[0131] Get the absolute value and arithmetic operation flag;

[0132] According to the instruction encoding rules of RISC-V, the absolute value and arithmetic operation identifier, the target register identifier and the source register identifier are combined to obtain the absolute value and arithmetic operation instruction; the absolute value and arithmetic operation instruction includes a first operation instruction and a second operation instruction, the first operation instruction is used to represent the calculation of the absolute values ​​of multiple numerical values, and the second operation instruction is used to represent the execution of addition and subtraction, and the result is saturated and written back to the target register pair.

[0133] Optionally, the building module 320 is specifically used for:

[0134] Get the shift and saturation flags;

[0135] According to the instruction encoding rules of RISC-V, the shift and saturation flag, the target register flag and the source register flag are combined to obtain the shift and saturation instruction; the shift and saturation instruction is used to represent the execution of a logical left shift or an arithmetic right shift according to the number of bits specified in the register, and the result is saturated and written back to the target register pair.

[0136] Optionally, the building module 320 is specifically used for:

[0137] Get data packing and unpacking identifiers;

[0138] According to the instruction encoding rules of RISC-V, the data packing and unpacking identifier, the target register identifier and the source register identifier are combined to obtain the data packing and unpacking instructions; the data packing and unpacking instructions are used to represent the packing of data blocks of different sizes into data units or the decomposition of data units into data blocks of different sizes and writing them back to the target register pair; the size of the data block is smaller than the size of the data unit.

[0139] Optionally, the building module 320 is specifically used for:

[0140] Get the special instruction identifier;

[0141] According to the instruction encoding rules of RISC-V, the special instruction identifier, the target register identifier and the source register identifier are combined to obtain other special instructions; the other special instructions include a first special instruction, a second special instruction and a third special instruction. The first special instruction is used to represent the execution of cross addition and subtraction operations, and the results are right-shifted and saturated and written back to the target register pair. The second special instruction is used to represent the truncation processing based on the immediate number and writing it back to the target register pair. The third special instruction is used to represent the execution of multiplication and addition and multiplication and subtraction operations and writing them back to the target register pair.

[0142] It can be understood that the functions of each functional module of the ultrasonic radio frequency data feature extraction system of this embodiment can be specifically implemented according to the method in the above method embodiment, and its specific implementation process can refer to the relevant description of the above method embodiment, which will not be repeated here.

[0143] On the other hand, a computer device provided in an embodiment of the present application includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the instruction construction method as described above when executing the program.

[0144] As another aspect, the present application further provides a computer-readable storage medium, which may be included in the electronic device described in the above embodiment; or may exist independently without being assembled into the electronic device. The above computer-readable storage medium stores one or more programs, and when the above programs are used by one or more processors to execute the instruction construction method described in the present application.

[0145] It should be understood that, although the various steps in the flow chart are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the figure may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these sub-steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0146] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0147] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0148] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0149] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0150] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0151] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A method for constructing an instruction, characterized in that: The instruction construction method comprises: Obtain an operand format; the operand format includes a source register identifier and a target register identifier; the operand format is an instruction format corresponding to a target instruction and complies with instruction encoding rules according to RISC-V, and the operand format includes a three-operand format or a single-operand format; After obtaining the source register identifier and the target register identifier, obtaining each different type of instruction identifier, and then analyzing and processing the source register identifier, the target register identifier and the different types of instruction identifiers according to the instruction encoding rules of RISC-V to construct a target instruction, including: obtaining a fixed-point multiplication and accumulation identifier; combining the fixed-point multiplication and accumulation identifier, the target register identifier and the source register identifier according to the instruction encoding rules of RISC-V to obtain the fixed-point multiplication and accumulation instruction; the fixed-point multiplication and accumulation instruction includes a first multiplication instruction and a second multiplication instruction, the first multiplication instruction The first instruction is used to represent the execution of fixed-point multiplication, and right-shift and saturate the result, and the second multiplication instruction is used to represent the execution of signed or unsigned multiplication, and saturate to a specific value and write back to the target register pair; the target instruction is a digital signal processing DSP extension instruction based on the RISC-V architecture, and the target instruction includes at least one of the following: byte extension instruction, fixed-point multiplication and accumulation instruction, absolute value and arithmetic operation instruction, shift and saturation instruction, data packing and unpacking instruction, and other special instructions; the target instruction is used to expand the 32-bit data path to the 64-bit data path; the fixed-point multiplication and accumulation instructions include: DKHMx, DKHMXx, DSMMUL, wherein the first multiplication instruction may include DKHMx instruction and DKHMXx instruction, DKHMx instruction and DKHMXx instruction are used to execute fixed-point multiplication, and right-shift and saturate the result; the second multiplication instruction may include: DSMMUL instruction and its variants, which are used to execute signed or unsigned multiplication, and saturate to a specific value and write back to the target register pair; wherein: For DKHM8 Rd, Rs1, Rs2, RV32 is used to characterize that the DKHM8 instruction simultaneously completes 8 Q7xQ7 multiplication operations, and shifts the calculated 8 Q14s right by 7 bits and saturates them to the Q7 value, and finally writes them to the destination register pair; if saturation occurs, the OV flag is set to 1; for DKHM16 Rd, Rs1, Rs2, RV32: The DKHM16 instruction simultaneously completes 4 Q15xQ15 multiplication operations, and shifts the calculated 4 Q31s right by 15 bits and saturates them to the Q15 value, and finally writes them to the destination register pair; if saturation occurs, the OV flag is set to 1; DKHMXx instructions include DKHMX8 Rd, Rs1, Rs2 and DKHMX16 Rd, Rs1, Rs2; for DKHMX8 Rd, Rs1, Rs2, RV32: DKHMX8 instruction completes 8 Q7xQ7 cross multiplication operations at the same time, and shifts the calculated 8 Q14 right by 7 bits and saturates to Q7 value, and finally writes to the destination register pair; if saturation operation occurs, the OV flag is set to 1; for DKHMX16Rd, Rs1, Rs2, RV32: DKHMX16 instruction completes 4 Q15xQ15 cross multiplication operations at the same time, and shifts the calculated 4 Q31 right by 15 bits and saturates to Q15 value, and finally writes to the destination register pair; if saturation operation occurs, the OV flag is set to 1; The DSMMUL instructions include: DSMMUL Rd, Rs1, Rs2 and DSMMULU Rd, Rs1, Rs2. For DSMMUL Rd, Rs1, Rs2, RV32: the DSMMUL instruction simultaneously completes two 32-bit signed multiplications and writes the upper 32 bits of the two multiplication results to the register pair; for DSMMULU Rd, Rs1, Rs2, RV32: the DSMMULU instruction simultaneously completes two 32-bit unsigned multiplications and writes the upper 32 bits of the two multiplication results to the register pair.

2. The method according to claim 1, characterized in that When the target instruction is a byte extension instruction, constructing the target instruction according to the source register identifier and the target register identifier includes: Get the byte extension flag; According to the instruction encoding rules of RISC-V, the byte extension identifier, the target register identifier and the source register identifier are combined to obtain the byte extension instruction; the byte extension instruction is used to represent the expansion of the bytes of the source register and store them in the target register.

3. The method according to claim 1, characterized in that When the target instruction is an absolute value and arithmetic operation instruction, constructing the target instruction according to the source register identifier and the target register identifier includes: Get the absolute value and arithmetic operation flags; According to the instruction encoding rules of RISC-V, the absolute value and arithmetic operation identifier, the target register identifier and the source register identifier are combined to obtain the absolute value and arithmetic operation instruction; the absolute value and arithmetic operation instruction includes a first operation instruction and a second operation instruction, the first operation instruction is used to represent the calculation of the absolute values ​​of multiple numerical values, and the second operation instruction is used to represent the execution of addition and subtraction, and the result is saturated and written back to the target register pair.

4. The method according to claim 1, characterized in that When the target instruction is a shift and saturation instruction, constructing the target instruction according to the source register identifier and the target register identifier includes: Get the shift and saturation flags; According to the instruction encoding rules of RISC-V, the shift and saturation flag, the target register flag and the source register flag are combined to obtain the shift and saturation instruction; the shift and saturation instruction is used to represent the execution of a logical left shift or an arithmetic right shift according to the number of bits specified in the register, and the result is saturated and written back to the target register pair.

5. The method according to claim 1, characterized in that When the target instruction is a data packing and unpacking instruction, constructing the target instruction according to the source register identifier and the target register identifier includes: Get data packing and unpacking identifiers; According to the instruction encoding rules of RISC-V, the data packing and unpacking identifier, the target register identifier and the source register identifier are combined to obtain the data packing and unpacking instruction; the data packing and unpacking instruction is used to represent packing data blocks of different sizes into data units or decomposing data units into data blocks of different sizes and writing them back to the target register pair; the size of the data block is smaller than the size of the data unit.

6. The method according to claim 1, characterized in that When the target instruction is other special instructions, constructing the target instruction according to the source register identifier and the target register identifier includes: Get the special instruction identifier; According to the instruction encoding rules of RISC-V, the special instruction identifier, the target register identifier and the source register identifier are combined to obtain the other special instructions; the other special instructions include a first special instruction, a second special instruction and a third special instruction, the first special instruction is used to represent the execution of cross addition and subtraction operations, and the results are right-shifted and saturated and written back to the target register pair, the second special instruction is used to represent the truncation according to the immediate number and the writing back to the target register pair, and the third special instruction is used to represent the execution of multiplication and addition and multiplication and subtraction operations and the writing back to the target register pair.

7. An instruction construction device, characterized in that: The instruction construction device comprises: An acquisition module, used for acquiring an operand format; the operand format includes a source register identifier and a target register identifier; the operand format is an instruction format corresponding to a target instruction and complies with instruction encoding rules according to RISC-V, and the operand format includes a three-operand format or a single-operand format; A construction module is used to obtain each different type of instruction identifier after obtaining the source register identifier and the target register identifier, and then analyze and process the source register identifier, the target register identifier and the different types of instruction identifiers according to the instruction encoding rules of RISC-V to construct the target instruction, including: obtaining a fixed-point multiplication and accumulation identifier; combining the fixed-point multiplication and accumulation identifier, the target register identifier and the source register identifier according to the instruction encoding rules of RISC-V to obtain the fixed-point multiplication and accumulation instruction; the fixed-point multiplication and accumulation instruction includes a first multiplication instruction and a second multiplication instruction, the first The multiplication instruction is used to represent the execution of fixed-point multiplication, and right-shift and saturate the result, and the second multiplication instruction is used to represent the execution of signed or unsigned multiplication, and saturate to a specific value and write back to the target register pair; the target instruction is a digital signal processing DSP extension instruction based on the RISC-V architecture, and the target instruction includes at least one of the following: byte extension instruction, fixed-point multiplication and accumulation instruction, absolute value and arithmetic operation instruction, shift and saturation instruction, data packing and unpacking instruction, and other special instructions; the target instruction is used to expand the 32-bit data path to a 64-bit data path; the fixed-point multiplication and accumulation instructions include: DKHMx, DKHMXx, DSMMUL, wherein the first multiplication instruction may include DKHMx instruction and DKHMXx instruction, and the DKHMx instruction and DKHMXx instruction are used to execute fixed-point multiplication, and right-shift and saturate the result; the second multiplication instruction may include: DSMMUL instruction and its variants, which are used to execute signed or unsigned multiplication, and saturate to a specific value and write back to the target register pair; wherein: For DKHM8 Rd, Rs1, Rs2, RV32 is used to characterize that the DKHM8 instruction simultaneously completes 8 Q7xQ7 multiplication operations, and shifts the calculated 8 Q14s right by 7 bits and saturates them to the Q7 value, and finally writes them to the destination register pair; if saturation occurs, the OV flag is set to 1; for DKHM16 Rd, Rs1, Rs2, RV32: The DKHM16 instruction simultaneously completes 4 Q15xQ15 multiplication operations, and shifts the calculated 4 Q31s right by 15 bits and saturates them to the Q15 value, and finally writes them to the destination register pair; if saturation occurs, the OV flag is set to 1; DKHMXx instructions include DKHMX8 Rd, Rs1, Rs2 and DKHMX16 Rd, Rs1, Rs2; for DKHMX8 Rd, Rs1, Rs2, RV32: DKHMX8 instruction completes 8 Q7xQ7 cross multiplication operations at the same time, and shifts the calculated 8 Q14 right by 7 bits and saturates to Q7 value, and finally writes to the destination register pair; if saturation operation occurs, the OV flag is set to 1; for DKHMX16Rd, Rs1, Rs2, RV32: DKHMX16 instruction completes 4 Q15xQ15 cross multiplication operations at the same time, and shifts the calculated 4 Q31 right by 15 bits and saturates to Q15 value, and finally writes to the destination register pair; if saturation operation occurs, the OV flag is set to 1; The DSMMUL instructions include: DSMMUL Rd, Rs1, Rs2 and DSMMULU Rd, Rs1, Rs2. For DSMMUL Rd, Rs1, Rs2, RV32: the DSMMUL instruction simultaneously completes two 32-bit signed multiplications and writes the upper 32 bits of the two multiplication results to the register pair; for DSMMULU Rd, Rs1, Rs2, RV32: the DSMMULU instruction simultaneously completes two 32-bit unsigned multiplications and writes the upper 32 bits of the two multiplication results to the register pair.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 6 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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