Electronic component, electronic system and data processing method

Abstract

The present application discloses an electronic component, an electronic system and a data processing method, wherein the electronic component includes: an electronic component for outputting a first data signal based on a first clock signal; and further for receiving a second clock signal and a second data signal, and performing data latching on the second data signal based on the second clock signal; wherein the second clock signal is a signal of the first clock signal after a delay; and the second data signal is a feedback signal output by a receiver of the first data signal in response to the first clock signal, based on the synchronously received first clock signal, and the length of the delay is related to the transmission delay from the first clock signal to the receiver and the transmission delay from the second data signal to the electronic component.

Description

Technical Field

[0001] The present application relates to the technical field of data processing of electronic devices, and more particularly, to an electronic component, an electronic system, and a data processing method. Background Art

[0002] When an electronic component interacts with a data receiver and latches the interaction data, the data transmission line between the electronic component and the data receiver has a delay, resulting in a delay between the data signal received by the electronic component from the receiver and the clock signal of the electronic component. The timing between the data signal that the electronic component needs to latch and the clock signal is not synchronized, and the data signal cannot be accurately latched based on the clock signal. Summary of the Invention

[0003] In view of this, the present application provides an electronic component, an electronic system, and a data processing method, the solutions of which are as follows:

[0004] A first aspect of the present application provides an electronic component, the electronic component being configured to output a first data signal based on a first clock signal; and further configured to receive a second clock signal and a second data signal, and latch the second data signal based on the second clock signal;

[0005] Among them, the second clock signal is the signal of the first clock signal after the delay; the second data signal is the feedback signal output by the receiver of the first data signal in response to the first clock signal based on the synchronously received first clock signal, and the length of the delay is related to the transmission delay from the first clock signal to the receiver and the transmission delay from the second data signal to the electronic component.

[0006] Optionally, in the above electronic component, the electronic component includes:

[0007] A first clock port, configured to output a first clock signal;

[0008] A first data port, configured to output a first data signal;

[0009] A second data port, configured to receive a second data signal;

[0010] The second clock port is used to receive a second clock signal.

[0011] Optionally, in the above electronic component, the electronic component includes:

[0012] A first data storage module, configured to obtain a second clock signal and a second data signal;

[0013] The output module is configured to output a first clock signal and a first data signal synchronized with the first clock signal.

[0014] Optionally, in the above electronic assembly, the first data storage module includes:

[0015] a first data acquisition unit, configured to acquire a second data signal based on a second clock signal;

[0016] The first data storage unit stores the second data signal based on the first data acquisition unit.

[0017] A second aspect of the present application provides an electronic system, comprising:

[0018] an electronic component configured to output a first data signal based on a first clock signal;

[0019] A receiver, configured to respond to the first clock signal and synchronously output a second data signal after receiving the first clock signal;

[0020] The second clock signal is a signal obtained by delaying the first clock signal by a preset time; the electronic component is further used to receive the second clock signal and the second data signal, and latch the second data signal based on the second clock signal.

[0021] Optionally, in the above electronic system, a processing component is connected between the electronic component and the receiver;

[0022] The processing component is used to process the signals transmitted between the electronic component and the receiver, so as to process the first clock signal and the first data signal and then send them to the receiver, and process the second data signal and the second clock signal and then send them to the electronic component;

[0023] The processing component has a delay effect on the passing signal, wherein the processing component is also used to delay the first clock signal for a preset time and send the second clock signal formed after the delay to the electronic component.

[0024] Optionally, in the above electronic system, the processing component includes a level conversion component for performing level conversion on a signal transmitted between the electronic component and a receiver;

[0025] The processing component has a first delay for a first clock signal transmitted to a receiver and a second delay for a second data signal transmitted to the electronic component;

[0026] The preset time and the sum of the first delay and the second delay meet the same condition, so that the second data signal and the second clock signal meet the synchronization condition.

[0027] Optionally, in the above electronic system, the processing component includes:

[0028] a first clock line, wherein the first clock signal is transmitted to the receiver based on the first clock line;

[0029] A second clock circuit, used for performing a first delay on the first clock signal;

[0030] a third clock circuit, configured to delay the first clock signal for a second time to output a second clock signal;

[0031] a first data transmission line, wherein the first data signal is transmitted to a receiver based on the first data transmission line;

[0032] a second data transmission line, wherein the second data signal is transmitted to the electronic component based on the second data transmission line;

[0033] Among them, the sum of the delays of the second clock line and the third clock line to the first clock signal is equal to the preset time; the sum of the delay of the first clock signal in the first clock line and the delay of the second data signal in the second data transmission line meets the same condition as the preset time.

[0034] A third aspect of the present application provides a data processing method, comprising:

[0035] outputting, by the electronic component, a first data signal based on the first clock signal;

[0036] receiving a second clock signal and a second data signal through an electronic component, and performing data latching on the second data signal according to the second clock signal;

[0037] Among them, the second clock signal is the signal of the first clock signal after a preset time delay; the second data signal is the signal output by the receiver of the first data signal after responding to the first clock signal and synchronously receiving the first clock signal.

[0038] Optionally, the above data processing method further includes:

[0039] The first clock signal and the first data signal are level-converted by the processing component and then sent to the receiver;

[0040] The second data signal is level-converted by the processing component and then sent to the electronic component;

[0041] In which, the processing component has a first delay for the first data signal transmitted to the receiver and a second delay for the second data signal transmitted to the electronic component; the preset time and the sum of the first delay and the second delay meet the same condition, so that the second data signal and the second clock signal meet the synchronization condition.

[0042] It can be seen from the above description that in the electronic component, electronic system and data processing method provided in the embodiment of the present application, the electronic component can output the first data signal based on the first clock signal, and can also receive the second clock signal and the second data signal. The second data signal is a feedback signal output by the receiver of the first data signal in response to the first clock signal, based on the first clock signal received synchronously. The second clock signal is the signal after the first clock signal is delayed. Since the delay time of the second clock signal relative to the first clock signal is related to the transmission delay from the first clock signal to the receiver and the transmission delay from the second data signal to the electronic component, by controlling the delay time of the two clock signals, the electronic component can synchronously receive the second data signal and the second clock signal, and the electronic component can accurately latch the second data signal according to the second clock signal, thereby solving the timing problem caused by the signal transmission delay between the electronic component and the receiver. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without any creative work.

[0044] The structures, proportions, sizes, etc. depicted in the drawings of this specification are only used to match the contents disclosed in the specification so as to facilitate understanding and reading by persons familiar with this technology. They are not intended to limit the conditions under which this application can be implemented, and therefore have no substantive technical significance. Any structural modifications, changes in proportional relationships, or adjustments in size, without affecting the efficacy and objectives that can be achieved by this application, should still fall within the scope of the technical contents disclosed in this application.

[0045] Figure 1 A schematic diagram of the structure of an electronic system;

[0046] Figure 2 for Figure 1 A timing diagram of signals transmitted by each port in the electronic system shown;

[0047] Figure 3 for Figure 1 A schematic diagram of the chip architecture of the electronic component 11 in the electronic system shown;

[0048] Figure 4 A schematic diagram of the structure of an electronic component provided in an embodiment of the present application;

[0049] Figure 5 A schematic diagram of a chip architecture of an electronic component provided in an embodiment of the present application;

[0050] Figure 6 A schematic diagram of the structure of an electronic system provided in an embodiment of the present application;

[0051] Figure 7 A schematic diagram of the structure of an electronic system provided in an embodiment of the present application;

[0052] Figure 8 A schematic diagram of a chip architecture of a processing component 16 provided in an embodiment of the present application;

[0053] Figure 9 A flowchart of a data processing method provided in an embodiment of the present application.

[0054] Reference numerals:

[0055] 11-electronic component; 12-receiver; 13-level conversion component; 14-first data storage module; 141-first data acquisition unit; 142-first data storage unit; 15-output module; 151-clock control unit; 152-clock sending unit; 153-second data acquisition unit; 154-second data storage unit; 16-processing component; 161-first clock line; 162-second clock line; 163-first data transmission line; 164-second data transmission line; 165-third clock line. DETAILED DESCRIPTION

[0056] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0057] As system-on-chip (SoC) processes and peripheral device processes (such as flash memory and sensors) evolve out of sync, SoC input / output (I / O) voltages have dropped to as low as 1.2V, while peripheral I / O voltages remain at 1.8V or even 3.3V. This necessitates the use of level shifters to interface between SoCs and peripherals. However, due to the latency inherent in signal level conversion, these components significantly limit the bandwidth between the SoC and peripherals. For example, in some implementations, synchronous serial transmission between the SoC and peripherals is performed via a serial peripheral interface (SPI). SPI has no defined speed limit, and many current devices support operating frequencies up to 50MHz. However, due to the latency introduced by the level shifters, even with a lower speed limit, the SPI's operating bandwidth is still limited. Similar issues arise when using other types of transmission interfaces between SoCs and peripherals.

[0058] Taking the SPI interface as an example, conventional data latching schemes for electronic components with SPI use the same clock signal for both data input and output. The electronic component latches the data signal on one edge of the clock signal and transmits the data signal on the next adjacent edge. For example, an electronic component (such as a master) can latch data on the rising edge of the clock signal and transmit the data signal on the adjacent falling edge, or it can latch data on the falling edge of the clock signal and transmit the data signal on the adjacent rising edge.

[0059] Electronic components must transmit data signals within a certain timeframe from the time they latch the data signal. This timeframe is proportional to the clock signal's period. Specifically, the higher the rate, the shorter the clock signal period, and the lower the latency requirement. However, once the clock signal's frequency reaches a certain value, the switching delay introduced by the level shifter becomes significant, hindering bandwidth expansion. Consequently, when an electronic component latches and transmits data signals based on the same clock signal, the delay in the level shifter's circuitry can lead to a timing mismatch between the data signal being latched by the electronic component and the clock signal.

[0060] refer to Figure 1 and Figure 2 , Figure 1 A schematic diagram of the structure of an electronic system. Figure 2 for Figure 1 The timing diagram of the signals transmitted by each port in the electronic system is shown. The electronic system includes an electronic component 11 and a receiver 12, and a level conversion component 13 connected between the electronic component 11 and the receiver 12.

[0061] In the embodiment of the present application, the electronic component 11, the receiver 12 and the level conversion component 13 can be three independent chips, or three different functional modules in the same chip, or the level conversion component 13 and the electronic component 11 can be integrated in the same chip, and the receiver 12 is a peripheral device of another chip.

[0062] The electronic component 11 and the receiver 12 both have a first clock port SCK, a first data port MOSI, and a second data port MISO. The electronic component 11 is a master device, and the receiver 12 is a slave device. The slave device has a chip select signal port NSS ( Figure 1 The master device (not shown) provides a control signal to the slave device to control its enabled state. When the control signal is low, the corresponding slave device is selected and can communicate with the master device; when the control signal is high, the slave device is unselected and cannot communicate with the master device.

[0063] The level shifter 13 includes: a first clock input port IN1 and a first clock output port OUT1; a first data input port IN3 and a first data output port OUT3; a second data input port IN4 and a second data output port OUT4. The first clock input port IN1, the first data input port IN3, and the second data output port OUT4 are all located on a first side of the level shifter 13 (hereinafter referred to as Side A); the first clock output port OUT1, the first data output port OUT3, and the second data input port IN4 are all located on a second side of the level shifter 13 (hereinafter referred to as Side B). Sides A and B are used by the level shifter 13 to connect different voltage domains on either side.

[0064] exist Figure 1 In the electronic system shown, the electronic component 11 can synchronously output a first clock signal through the first clock port SCK and a first data signal through the first data port MOSI. The first clock signal is input to the level shifting component 13 through the first clock input port IN1. The first data signal is input to the level shifting component 13 through the first data input port IN3.

[0065] The first clock signal undergoes level conversion in the level conversion component 13 and is then output through the first clock output port OUT1. The first clock signal undergoing level conversion is input to the first clock port SCK of the receiver 12. The first data signal undergoes level conversion in the level conversion component 13 and is then output through the first data output port OUT3. The first data terminal MOSI of the receiver 12 receives the first data signal undergoing level conversion. Both the first clock signal and the first data signal undergo level conversion in the level conversion component 13 and are then transmitted to the receiver 12. Therefore, the delays of the two signals in the transmission line are the same, and the receiver 12 can synchronously receive the first data signal after level conversion.

[0066] After receiving the first data signal and the first data signal, the receiver 12 synchronously outputs the second data signal through the second data port MISO. The second data signal is input to the level conversion component 13 through the second data input port IN4, and after undergoing level conversion in the level conversion component 13, is output through the second data output port OUT4.

[0067] The second data port MISO of the electronic component 11 obtains the second data signal output by the second data output port OUT4 and performs data latching on the second data signal according to the first data signal.

[0068] When the SPI of the electronic component 11 has a full-duplex mode, it can simultaneously output a first data signal through the first data port MOSI and receive a second data signal through the second data port MISO.

[0069] refer to Figure 3 , Figure 3 for Figure 1 The chip architecture diagram of the electronic component 11 in the electronic system shown is as follows. The electronic component 11 includes: a first data acquisition unit 141, which acquires a second data signal based on a first clock signal; a first data storage unit 142, which stores the second data signal based on the first data acquisition unit 141 to realize data latching of the second data acquisition signal; a clock sending unit 152, which is used to generate a first clock signal; a clock control unit 151, which is used to be turned on under the control of a synchronous clock signal Sync to output the first clock signal; and a second data acquisition unit 153, which is used to synchronously acquire and output the first data signal from the second data storage unit 154 based on the first clock signal.

[0070] Based on the above description, it can be seen that the electronic component 11 is in full-duplex mode and can output the first data signal through the first data port MOSI at the falling edge of the first clock signal. It is necessary to collect the second data signal returned by the receiver 12 through the second data port MISO at the next rising edge of the first clock signal. If the receiver 12 fails to respond in time, the electronic component 11 will receive an erroneous data signal.

[0071] If the electronic component 11 outputs the first data signal at the falling edge of the first clock signal and receives the second data signal at the next rising edge of the first clock signal, the data signal must have a valid and correctly readable phase (DATA VALID) between the electronic component 11 and the receiver 12. Figure 2 As shown, the receiver 12 needs to receive the falling edge of the first clock signal at t V The second data signal is sent to the second data port MISO of the electronic component 11 within a time period of t V The end point cannot exceed the next rising edge of the first clock signal, that is, t V Need to meet:

[0072] (1)

[0073] Among them, t SCK is the period of the first clock signal.

[0074] t SCK The duration of the high level phase is t SCKH , t SCK The low level phase duration is t SCKL . t SCK Equal to t SCKH With t SCKL Optionally, you can set t SCKH With t SCKL are equal, and are both half a cycle of the first clock signal.

[0075] About t V , t V It includes: the delay when the receiver 12 receives the falling edge of the first clock signal (the first part of the delay); the delay when the receiver 12 outputs the second data signal when it receives the falling edge of the first clock signal (the second part of the delay); the transmission delay of the second data signal from the receiver 12 to the electronic component 11 (the third part of the delay).

[0076] The first part of the delay is approximately equal to the transmission delay t of the signal from side A to side B in the level conversion component 13. pdAB The third part of the delay is approximately equal to the transmission delay t of the signal from side B to side A in the level conversion component 13. pdBAThe second part of the delay is equal to the inherent response delay t of the receiver 12 to the clock signal SLAVEDELAY .

[0077] t SLAVEDELAY Related to the inherent bandwidth capability of the receiver 12, for a given receiver, t SLAVEDELAY is a determined time constant. Currently, since the signal transmission rate of the receiver 12 can reach or even exceed 50Mbps, t SLAVEDELAY It is an extremely small constant and can be ignored when considering the timing delay problem of electronic systems.

[0078] Compared with the electronic component 11 and the receiver 12, the signal transmission rate of the level conversion component 13 is often lower, which results in t pdAB and tp dBA Taking the level conversion component 13 of model SN74AXC4T774 as an example, based on its calibration performance parameters, it can be concluded that t pdAB and tp dBA They are 221ns and 9nm respectively, so the total delay time of these two parts is 230ns.

[0079] Therefore, to satisfy equation (1), the half-period of the first clock signal must be greater than 230ns, which translates to a rate of only about 2.1Mbps. Consequently, even if the receiver 12 is a 1.8V device, the level shifter 13 can only support a rate of 7.3Mbps. Currently, it is difficult to implement fixed delay compensation using the level shifter 13.

[0080] In order to solve the above problems, an embodiment of the present application provides an electronic component, which can output a first data signal based on a first clock signal, and can also receive a second clock signal and a second data signal. The second data signal is a feedback signal output by the receiver of the first data signal in response to the first clock signal, based on the first clock signal received synchronously. The second clock signal is the signal after the first clock signal is delayed. Since the delay length of the second clock signal relative to the first clock signal is related to the transmission delay from the first clock signal to the receiver and the transmission delay from the second data signal to the electronic component, by controlling the delay length of the two clock signals, the electronic component can synchronously receive the second data signal and the second clock signal, and the electronic component can accurately latch the second data signal according to the second clock signal, thereby solving the timing problem caused by the signal transmission delay between the electronic component and the receiver.

[0081] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0082] refer to Figure 4 , Figure 4 This is a structural diagram of an electronic component provided in an embodiment of the present application, where the electronic component 11 is used to output a first data signal DATA1 based on a first clock signal CLK1; it is also used to receive a second clock signal CLK2 and a second data signal DATA2, and latch the second data signal DATA2 based on the second clock signal CLK2.

[0083] Among them, the second clock signal CLK2 is the signal of the first clock signal CLK1 after delay; the second data signal DATA2 is the feedback signal output by the receiver of the first data signal DATA1 in response to the first clock number based on the synchronously received first clock signal, and the length of the delay is related to the transmission delay from the first clock signal to the receiver and the transmission delay from the second data signal to the electronic component 11.

[0084] In the embodiment of the present application, the electronic component 11 can synchronously output the first data signal DATA1 based on its own first clock signal CLK1, and can also synchronously receive the second clock signal CLK2 and the second data signal DATA2 after delaying the first clock signal CLK1.

[0085] In this way, in full-duplex mode, the electronic component can synchronously send the first data signal DATA1 based on the first clock signal CLK1, and synchronously receive the second data signal DATA2 based on the second clock signal CLK2, so that the reception and output of the data signal are synchronized with the corresponding clock signals respectively. Not only can the transmission of the first data signal DATA1 be synchronized with the clock signal, but the reception of the second data signal DATA2 can also be synchronized with the clock signal. The second data signal DATA2 can be accurately latched, solving the timing problem caused by the signal transmission delay between the electronic component 11 and the receiver 12.

[0086] like Figure 4 As shown, the electronic component 11 includes: a first clock port SCK, the first clock port SCK is used to output the first clock signal CLK1; a first data port MOSI, the first data port MOSI is used to output the first data signal DATA1; a second data port MISO, the second data port MISO is used to receive the second data signal DATA2; a second clock port SCK_FB, the second clock port SCK_FB is used to receive the second clock signal CLK2.

[0087] Relative to Figure 1 As shown, Figure 4In the shown method, a second clock port SCK_FB is added to the electronic component 11, which is used to realize delayed feedback of the clock signal outside the electronic component 11, so that the electronic component 11 can synchronously receive the second clock signal CLK2 and the second data signal DATA2. In this way, the electronic component 11 can accurately latch the second data signal DATA2 according to the second clock signal CLK2, solving the timing problem caused by the signal transmission delay between the electronic component 11 and the receiver.

[0088] refer to Figure 5 , Figure 5 A chip architecture diagram of an electronic component provided in an embodiment of the present application, wherein the electronic component 11 includes: a first data storage module 14, the first data storage module 14 is used to obtain a second clock signal CLK2 and a second data signal DATA2; an output module 15, the output module 15 is used to output a first clock signal CLK1 and a first data signal DATA1 synchronized with the first clock signal CLK1.

[0089] exist Figure 5 In the illustrated embodiment, the first data storage module 14 can synchronously acquire the second clock signal CLK2 and the second data signal DATA2 to latch the second data signal DATA2 based on the second clock signal CLK2. The output module 15 can synchronously output the first data signal DATA1 based on the first clock signal CLK1, so that the reception and output of the data signal are synchronized with the corresponding clock signal, respectively. This not only synchronizes the transmission of the first data signal DATA1 with the clock signal, but also synchronizes the reception of the second data signal DATA2 with the clock signal.

[0090] Combine Figure 4 and Figure 5 As shown, the first data storage module 14 can be connected to the second clock port SCK_FB and the second data port MISO respectively, and obtain the second clock signal CLK2 through the second clock port SCK_FB and obtain the second data signal DATA2 through the second data port MISO. The output module 15 can be connected to the first clock port SCK and the first data port MOSI respectively, and output the first clock signal CLK1 through the first clock port SCK and output the first data signal DATA1 through the first data port MOSI.

[0091] like Figure 5 As shown, the first data storage module 14 includes: a first data acquisition unit 141, which acquires a second data signal based on a second clock signal; and a first data storage unit 142, which stores the second data signal based on the first data acquisition unit.

[0092] Relative to Figure 3 As shown, Figure 5 In the illustrated method, there is no need to change the internal circuit structure of the first data acquisition unit 141 and the first data storage unit 142 in the first data storage module 14. It is only necessary to add a second clock port SCK_FB to the outside of the electronic component 11 for connecting to the original clock signal access terminal of the first data acquisition unit 141, so that the first data acquisition unit 141 can synchronously obtain the second clock signal CLK2 and the second data signal DATA2, so that data can be latched based on the synchronized clock signal and data signal. In this case, it is no longer necessary to provide the first clock signal CLK1 from the clock control unit 151 to the first data acquisition unit 141. In addition, as Figure 5 As shown, for the output module 15, it is possible to maintain Figure 3 Same circuit structure.

[0093] contrast Figure 3 and Figure 5 As can be seen from the chip architecture diagram shown, based on the technical solution of the embodiment of the present application, it is only necessary to cut off the connection between the clock control unit 151 and the first data acquisition unit 141, and add a second clock port SCK_FB on the outside of the electronic component 11 to change the access clock signal of the first data acquisition unit 141 from the first clock signal CLK1 to the second clock signal CLK2. There is no need to change the internal circuit module and other circuit connection relationships in the electronic component 11. The implementation method is simple and the production cost is low.

[0094] Based on the electronic component 11 provided in the above embodiment, another embodiment of the present application further provides an electronic system, the structure of which is as follows: Figure 6 shown.

[0095] refer to Figure 6 , Figure 6 This is a schematic diagram of the structure of an electronic system provided in an embodiment of the present application, wherein the electronic system includes:

[0096] The electronic component 11 is configured to output a first data signal DATA1 based on a first clock signal CLK1; the electronic component 11 may be a solution provided by any of the implementations of the above embodiments;

[0097] The receiver 12 is configured to respond to the first clock signal CLK1 and synchronously output the second data signal DATA2 after receiving the first clock signal CLK1;

[0098] The second clock signal CLK2 is a signal obtained by delaying the first clock signal CLK1 by a preset time. The electronic component 11 is further configured to receive the second clock signal CLK2 and the second data signal DATA2 and perform data latching on the second data signal DATA2 based on the second clock signal CLK2.

[0099] exist Figure 6 In the electronic system shown, the electronic component 11 can synchronously send the first data signal DATA1 based on the first clock signal CLK1, and can also synchronously receive the second data signal DATA2 based on the second clock signal CLK2, so that the reception and output of the data signal are synchronized with the corresponding clock signals respectively. Not only can the transmission of the first data signal DATA1 be synchronized with the clock signal, but the reception of the second data signal DATA2 can also be synchronized with the clock signal. The second data signal DATA2 can be accurately latched, solving the timing problem caused by the signal transmission delay between the electronic component 11 and the receiver 12.

[0100] Electronic component 11 includes: a first clock port SCK for outputting a first clock signal CLK1; a first data port MOSI for outputting a first data signal DATA1; a second data port MISO for receiving a second data signal DATA2; and a second clock port SCK_FB for receiving a second clock signal CLK2. Correspondingly, receiver 12 includes: a first clock port SCK for receiving the first clock signal CLK1; a first data port MOSI for receiving the first data signal DATA1; and a second data port MISO for outputting a second data signal DATA2.

[0101] In one embodiment, if the I / O port voltages between the electronic component 11 and the receiver 12 are consistent, the corresponding ports between the electronic component 11 and the receiver 12 can be directly connected, and a delay circuit that can be used to implement clock signal delay is added between the first clock port SCK and the second clock port SCK_FB of the electronic component 11 to delay the first clock signal CLK1 and generate the second clock signal CLK2.

[0102] If the I / O port voltages of the electronic component 11 and the receiver 12 are inconsistent, for example, the I / O port voltage of the electronic component 11 is 1.2V and the I / O port voltage of the receiver 12 is 3.3V, the structure of the electronic system can be as follows: Figure 7 shown.

[0103] refer to Figure 7 , Figure 7This is a schematic diagram of the structure of an electronic system provided in an embodiment of the present application. Based on the above implementation, Figure 7 In the illustrated embodiment, a processing component 16 may be connected between the electronic component 11 and the receiver 12 .

[0104] Processing component 16 is used to process signals transmitted between electronic component 11 and receiver 12, processing first clock signal CLK1 and first data signal DATA1 before sending them to receiver 12, and processing second data signal DATA2 and second clock signal CLK2 before sending them to electronic component 11. Processing component 16 has a delay effect on the passing signals, and is further used to delay first clock signal CLK1 by a preset time and send the resulting second clock signal CLK2 to electronic component 11.

[0105] The processing component 16 can not only convert the level of the signal transmitted between the electronic component 11 and the receiver 12 , but also perform delay processing on the first clock signal CLK1 to output the second clock signal CLK2 to the electronic component 11 .

[0106] The processing component 16 includes a level conversion component (such as a level shifting component) for performing level conversion on the signal transmitted between the electronic component 11 and the receiver 12; the processing component 16 has a first delay t1 for the first clock signal CLK1 transmitted to the receiver 12, and has a second delay t2 for the second data signal DATA2 transmitted to the electronic component 11;

[0107] The preset time and the sum of the first delay and the second delay meet the same condition, so that the second data signal DATA2 and the second clock signal CLK2 meet the synchronization condition. Set the preset time as t0, then t0 = t1 + t2.

[0108] Among them, the processing component 16 may include a level conversion component, and a clock delay circuit may be added on the basis of the level conversion component 13 provided in the above embodiment. The circuit can delay the first clock signal CLK1 to output the second clock signal CLK2, without changing the circuit structure and port connection method of the level conversion component 13 originally used to transmit the first clock signal CLK, the first data signal DATA1 and the second data signal DATA2D between the electronic component 11 and the receiver 12.

[0109] refer to Figure 8 , Figure 8 A schematic diagram of a chip architecture of a processing component 16 provided in an embodiment of the present application, combined with Figure 7 and Figure 8 As shown, the processing component 16 includes:

[0110] A first clock line 161 , wherein a first clock signal is transmitted to the receiver 12 based on the first clock line 161 ;

[0111] A second clock circuit 162, the second clock circuit 162 is used to delay the first clock signal CLK1 for the first time;

[0112] A third clock circuit 165, the third clock circuit 165 is used to delay the first clock signal CLK1 for a second time to output a second clock signal CLK2;

[0113] a first data transmission line 163 , through which the first data signal DATA1 is transmitted to the receiver 12 ;

[0114] A second data transmission line 164 , through which the second data signal DATA2 is transmitted to the electronic component 11 ;

[0115] Among them, the sum of the delays of the second clock line 162 and the third clock line 165 for the first clock signal CLK1 is equal to the preset time t0; the sum of the delay of the first clock signal CLK1 in the first clock line 161 and the delay of the second data signal DATA2 in the second data transmission line 164 meets the same condition as the preset time, that is, the sum of the delay of the first clock signal CLK1 in the first clock line 161 and the delay of the second data signal DATA2 in the second data transmission line 164 is equal to or approximately equal to t0.

[0116] The second clock line 162 and the third clock line 165 serve as clock delay circuits added to the processing component 16, which can delay the first clock signal CLK1 to output the second clock signal CLK2 without changing the circuit structure and port connection method of the original first data transmission line 163, the first clock line 161 and the second data transmission line 164.

[0117] Alternatively, as Figure 8 As shown, the first clock line 161 connects the first clock input port IN1 and the first clock output port OUT1, inputs the first clock signal CLK1 through the first clock input port IN1, and outputs the processed first clock signal CLK1 through the first clock output port OUT1.

[0118] Alternatively, as Figure 8 As shown, the second clock line 162 is connected to the second clock input port IN2 and the second clock output port OUT2, the first clock signal CLK1 is input through the second clock input port IN2, and the first clock signal CLK1 after the first delay is output through the second clock output port OUT2.

[0119] Alternatively, as Figure 8 As shown, the first data transmission line 163 connects the first data input port IN3 and the first data output port OUT3, inputs the first data signal DATA1 through the first data input port IN3, and outputs the processed first data signal DATA1 through the first data output port OUT3.

[0120] Alternatively, as Figure 8 As shown, the second data transmission line 164 connects the second data input port IN4 and the second data output port OUT4, receives the second data signal DATA2 through the second data input port IN4, and outputs the processed second data signal DATA2 through the second data output port OUT4.

[0121] Alternatively, as Figure 8 As shown, the third clock line 165 connects the third clock input port IN5 and the third clock output port OUT5, and the first clock signal CLK1 after the first delay is input through the third clock input port IN5, and the first clock signal CLK1 after the second delay is output through the third clock output port OUT5. The first clock signal CLK1 after the second delay is the second clock signal CLK2.

[0122] In order to facilitate the connection between the ports in the processing component 16 and the corresponding ports between the receiver 12 and the electronic component 11, ports IN1, IN2, IN3, OUT4 and OUT5 can be set to be located on the A side of the processing component 16, and ports OUT1, OUT2, OUT3, IN4 and IN5 can be set to be located on the B side of the processing component 16.

[0123] In the embodiment of the present application, when the electronic system performs signal transmission, the first clock signal CLK1 can be transmitted from the A side to the B side in the processing component 16 first, so as to undergo the first delay (the delay time is t pdAB ), and then in the processing component 16, the B side is transmitted to the A side to undergo a second delay (the delay time is tp dBA The duration of the two delays of the first clock signal CLK1 in the processing component 16 is t pdAB +tp dBA Since the delay of the circuit board trace in the processing component 16 is extremely small and can be ignored, t V Will only be SLAVEDELAY At this time, the bandwidth of the electronic system is determined only by the inherent response delay of the electronic component 11 and the receiver 12, and is unrelated to the signal delay of the transmission line between the two.

[0124] Taking the receiver 12 with a transmission rate of 50Mbps as an example, based on the embodiment of the present application, the transmission rate that was originally only 7.3Mbps can be increased to its performance upper limit of 50Mbps.

[0125] As can be seen from the above description, in the embodiment of the present application, a second clock port SCK_FB can be added to the outside of the electronic component 11 to implement delayed feedback of the clock signal outside the electronic component 11, thereby enabling the electronic component 11 to synchronously receive the second clock signal CLK2 and the second data signal DATA2. Specifically, the processing component 16 can add a clock delay circuit for clock signal delay to delay the first clock signal CLK1 to form the second clock signal CLK2. Therefore, the electronic component 11 can accurately latch the second data signal DATA2 based on the second clock signal CLK2, solving the timing problem caused by the signal transmission delay between the electronic component 11 and the receiver 12.

[0126] It should be noted that the embodiments of the present application are not limited to electronic systems with an SPI bus architecture and can also be used in JTA (Java Transaction API) bus architectures, SDIO (Transaction) bus architectures, and I2S (Inter-IC Sound) bus architectures. In an electronic system, electronic component 11, acting as a master device, can use its own clock to synchronize data it sends and latch data returned from slave devices.

[0127] Based on the above embodiment, another embodiment of the present application further provides a data processing method, which can be as follows Figure 9 shown.

[0128] refer to Figure 9 , Figure 9 A flowchart of a data processing method provided in an embodiment of the present application is provided. The data processing method shown includes:

[0129] Step S11 : Outputting a first data signal DATA1 based on a first clock signal CLK1 through the electronic component 11 .

[0130] Step S12: Receive the second clock signal CLK2 and the second data signal DATA2 through the electronic component 11, and latch the second data signal according to the second clock signal CLK2.

[0131] The second clock signal CLK2 is a signal of the first clock signal CLK1 after a preset time delay; the second data signal DATA2 is a signal output by the receiver 12 of the first data signal DATA1 after responding to the first clock signal CLK1 and synchronously receiving the first clock signal CLK1.

[0132] Optionally, the data processing method further includes: performing level conversion on the first clock signal CLK1 and the first data signal DATA1 by the processing component 16 and sending the resulting signals to the receiver 12; and performing level conversion on the second data signal DATA2 by the processing component 16 and sending the resulting signals to the electronic component 11. The processing component 16 may delay the first clock signal CLK1 to generate a second clock signal that is sent to the electronic component 11.

[0133] Among them, the processing component 16 has a first delay for the first data signal DATA1 transmitted to the receiver 12, and has a second delay for the second data signal DATA2 transmitted to the electronic component 11; the preset time and the sum of the first delay and the second delay meet the same condition, so that the second data signal DATA2 and the second clock signal CLK2 meet the synchronization condition.

[0134] In the data processing method provided in the embodiment of the present application, the electronic component 11 can synchronously send the first data signal DATA1 based on the first clock signal CLK1, and can also synchronously receive the second data signal DATA2 based on the second clock signal CLK2, so that the reception and output of the data signal are synchronized with the corresponding clock signals respectively. Not only can the transmission of the first data signal DATA1 be synchronized with the clock signal, but the reception of the second data signal DATA2 can also be synchronized with the clock signal. The second data signal DATA2 can be accurately latched, solving the timing problem caused by the signal transmission delay between the electronic component 11 and the receiver 12.

[0135] The various embodiments in the specification of this application are described in a progressive, parallel, or progressive and parallel manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced. The implementation methods provided in the embodiments of this application can be combined with each other if there is no contradiction.

[0136] It should be noted that in the description of this application, it should be understood that the description of the drawings and embodiments is illustrative rather than restrictive. The same figure numbers throughout the embodiments of the specification identify the same structure. In addition, for the purpose of understanding and ease of description, the drawings may exaggerate the thickness of some layers, films, panels, regions, etc. It is also understood that when an element such as a layer, film, region or substrate is referred to as "on" another element, the element may be directly on the other element or there may be an intermediate element. In addition, "on" refers to positioning an element on or below another element, but does not essentially mean positioning on the upper side of another element according to the direction of gravity.

[0137] The terms "upper," "lower," "top," "bottom," "inner," "outer," and the like, indicating positions or locations, are based on the positions or locations shown in the accompanying drawings and are intended solely to facilitate and simplify the description of this application. They are not intended to indicate or imply that the devices or elements referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. When a component is considered to be "connected" to another component, it may be directly connected to the other component or there may be a centrally located component.

[0138] It should also be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such article or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the article or device comprising the aforementioned elements.

[0139] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present application. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application is not limited to the embodiments shown herein, but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An electronic system comprising: an electronic component configured to output a first data signal based on a first clock signal; a receiver, configured to respond to the first clock signal and synchronously output a second data signal after receiving the first clock signal; A processing component is connected between the electronic component and the receiver, the processing component including a level conversion component, the processing component being configured to perform level conversion on the first clock signal and the first data signal and then transmit them to the receiver; the processing component being configured to perform level conversion on the second data signal and then transmit them to the electronic component; the processing component being configured to delay the first clock signal for a preset time and transmit the second clock signal formed after the delay to the electronic component; The electronic component is further configured to receive the second clock signal and the second data signal, and latch the second data signal based on the second clock signal.

2. The electronic system according to claim 1, wherein the electronic component comprises: A first clock port, configured to output the first clock signal; a first data port, configured to output the first data signal; a second data port, configured to receive the second data signal; The second clock port is used to receive the second clock signal.

3. The electronic system according to claim 1, wherein the electronic component comprises: a first data storage module, configured to obtain the second clock signal and the second data signal; An output module is configured to output the first clock signal and the first data signal synchronized with the first clock signal.

4. The electronic system according to claim 3, wherein the first data storage module comprises: a first data acquiring unit, configured to acquire the second data signal based on the second clock signal; The first data storage unit stores the second data signal based on the first data acquisition unit.

5. The electronic system according to claim 1, wherein the processing component is further used to process the signal transmitted between the electronic component and the receiver, so as to process the first clock signal and the first data signal and then send them to the receiver, and process the second data signal and the second clock signal and then send them to the electronic component.

6. The electronic system according to claim 5, wherein the processing component comprises a level conversion component for performing level conversion on a signal transmitted between the electronic component and the receiver; The processing component has a first delay for the first clock signal transmitted to the receiving party and a second delay for the second data signal transmitted to the electronic component; in, The preset time and the sum of the first delay and the second delay meet the same condition, so that the second data signal and the second clock signal meet a synchronization condition.

7. The electronic system according to claim 5, wherein the processing component comprises: a first clock line, the first clock signal being transmitted to the receiver based on the first clock line; a second clock circuit, configured to perform a first delay on the first clock signal; a third clock circuit, configured to delay the first clock signal for a second time to output the second clock signal; a first data transmission line, the first data signal being transmitted to the receiving party based on the first data transmission line; a second data transmission line, wherein the second data signal is transmitted to the electronic component based on the second data transmission line; Wherein, the sum of the delays of the second clock circuit and the third clock circuit to the first clock signal is equal to the preset time; The sum of the delay of the first clock signal in the first clock line and the delay of the second data signal in the second data transmission line meets the same condition as the preset time.

8. A data processing method, comprising: outputting, by the electronic component, a first data signal based on the first clock signal; The first clock signal and the first data signal are level-converted by a processing component and then sent to a receiver; the processing component includes a level conversion component; The processing component performs level conversion on the second data signal and then sends it to the electronic component; wherein the second data signal is a signal output by the receiver of the first data signal after responding to the first clock signal and synchronously receiving the first clock signal; Delaying the first clock signal for a preset time by the processing component, and sending a second clock signal formed after the delay to the electronic component; The second clock signal and the second data signal are received by an electronic component, and data of the second data signal is latched according to the second clock signal.

9. The data processing method according to claim 8, comprising: The processing component has a first delay for the first clock signal transmitted to the recipient and a second delay for the second data signal transmitted to the electronic component; the preset time and the sum of the first delay and the second delay meet the same condition, so that the second data signal and the second clock signal meet the synchronization condition.

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