IGBT devices

Abstract

The present invention discloses an IGBT device, in which a portion of the trench structure serves as a gate trench structure and another portion of the trench structure serves as a source trench structure. The gate conductive material layer of the gate trench structure is connected to a gate composed of a front metal layer. The source conductive material layer of the source trench structure is connected to a source composed of a front metal layer. Each trench structure passes through a channel region. A source region self-aligned with the trench structure is formed on the surface of the channel region. A drift region is formed at the bottom of the channel region. A collector region is formed at the bottom of the drift region. When the IGBT device is in the on state, the gate-source voltage causes the source trench structure to attract second conductive type carriers greater than the gate trench structure, causing the path of the second conductive type current to be closer to the source trench structure. The present invention can prevent the gate capacitance from decreasing due to an increase in the second conductive type current during device turn-on, and can improve the controllability of the rate of change of the current over time.

Description

Technical Field

[0001] The present invention relates to a semiconductor power device, in particular to an IGBT device. Background Art

[0002] Traditional unipolar power devices, such as MOSFETs, have an on-resistance that is proportional to the concentration in the drift region. A higher concentration in the drift region results in a lower on-resistance; however, a high concentration in the drift region reduces the breakdown voltage. The IGBT, on the other hand, is a bipolar device with a low doping concentration in the drift region, resulting in a high breakdown voltage. However, during conduction, electrons and holes are injected, significantly increasing the doping concentration in the drift region by tens or even hundreds of times. This decouples the breakdown voltage and on-resistance. Therefore, IGBTs can achieve higher breakdown voltages and significantly higher current densities than MOSFETs.

[0003] The following example uses an N-type IGBT. Because an IGBT conducts both electron and hole currents during conduction, the hole current is absorbed along the gate and into the source. As the hole current increases, the number of holes increases, and the gate capacitance decreases, even becoming a negative capacitance in severe cases. This reduced gate capacitance increases the IGBT's turn-on speed, leading to an increase in the rate of change of current over time, or di / dt. More seriously, this di / dt is not limited by the external drive resistor; this can have the following negative effects:

[0004] 1. The source of the device typically has a parasitic inductance, Ls, ranging from 1nH to 10nH. The voltage generated by the parasitic inductance, Ls*di / dt, increases the IGBT source potential, leading to an increase in the gate potential. This gate voltage spike can also interfere with the drive circuit.

[0005] 2. IGBTs generally operate in bridge circuits. As di / dt increases, the maximum reverse recovery current (Irrm) of the conducting diode (usually a silicon FRD, or fast recovery diode, but also a SiC Schottky diode) will increase.

[0006] 3. If the IGBT's turn-on di / dt is too large, it will increase the risk of circuit oscillation and increase system crosstalk.

[0007] like Figure 1 FIG. 1 is a schematic diagram of the structure of an existing IGBT device. Taking an N-type device as an example, the existing IGBT device includes: a plurality of parallel-arranged gate trench structures, namely trench gates.

[0008] The gate trench structure includes a gate trench, a gate dielectric layer 104 formed on the inner surface of the gate trench, and a polysilicon gate 105 filled in the gate trench.

[0009] The gate dielectric layer 104 is usually made of an oxide layer such as silicon dioxide. The polysilicon gate 105 needs to be highly doped.

[0010] The polysilicon gate 105 is connected to a gate electrode (not shown) formed of a front metal layer 111 .

[0011] Each gate trench structure passes through the P-type doped channel region 107 ; the surface of the channel region 107 covered by the side surface of the polysilicon gate 105 is used to form an N-type conductive channel.

[0012] An N-type heavily doped source region 110 is formed on the surface of the channel region 107 and is self-aligned with the gate trench structure.

[0013] The top of the source region 110 is connected to a source electrode formed by a front metal layer 111 through a through hole 108. The source region 110 is also an emitter region, and the source electrode is also an emitter. Figure 1 Only the front metal layer 111 constituting the source is shown.

[0014] The via hole 108 passes through the interlayer film.

[0015] The through hole 108 at the top of the source region 110 also passes through the source region 110 and contacts the channel region 107. A P-type heavily doped contact region 109 is formed at the bottom of the through hole 108. The contact region 109 is implemented by through hole implantation. In order to form a better ohmic contact between the channel region 107 and the through hole 108, the implanted impurity of the through hole implantation of the contact region 109 is BF2, and the implanted dose is 1e15cm -2 ~1e16cm -2 between.

[0016] An N-type doped drift region 103 is formed at the bottom of the channel region 107. The drift region 103 is formed using an N-type substrate; the lower the doping concentration of the substrate and the thicker the substrate, the higher the breakdown voltage of the IGBT.

[0017] A heavily P-type doped collector region 101 is formed at the bottom of the drift region 103. This region is formed by backside P-type implantation of an impurity, typically boron. To increase electron extraction speed, the junction depth of collector region 101 is typically made very shallow. This is achieved through low-energy boron implantation.

[0018] When the IGBT device is a field stop (FS) type IGBT, i.e., an FS-IGBT device, an N-type heavily doped buffer layer 102 is also included between the drift region 103 and the collector region 101. The buffer layer 102 can cut off the electric field, i.e., reduce the electric field to 0 in the buffer layer 102, thereby preventing the depletion region from widening to the collector region 101. If the depletion region widens to the collector region 101, punch-through will be formed, resulting in increased leakage. The buffer layer 102 can be formed by high-energy phosphorus (Phosphorus) injection or hydrogen (Hydrogen) injection.

[0019] An N-type heavily doped carrier storage layer 106 is further formed at the top of the drift region 103. The carrier storage layer 106 is used to increase the concentration of surface carriers, thereby reducing the on-state voltage drop.

[0020] When the IGBT is turned on, hole current flows along the surface of the trench gate and is then collected by the through-hole 108. When the hole current flows along the surface of the trench gate, the gate capacitance is reduced, thereby reducing the rate of change of the current over time. Summary of the Invention

[0021] The technical problem to be solved by the present invention is to provide an IGBT device that can prevent the gate capacitance from decreasing due to the increase in the second conductive type current during the device turn-on process, thereby preventing the turn-on speed from increasing due to the reduction in gate capacitance and the rate of change of current over time due to the increase in the turn-on speed, thereby improving the controllability of the rate of change of current over time.

[0022] To solve the above technical problems, the IGBT device provided by the present invention includes: a plurality of trench structures arranged in parallel, a portion of the trench structures serving as gate trench structures and another portion of the trench structures serving as source trench structures.

[0023] The gate trench structure includes a gate trench, a gate dielectric layer formed on an inner surface of the gate trench, and a gate conductive material layer filled in the gate trench.

[0024] The source trench structure includes a source trench, a source dielectric layer formed on an inner surface of the source trench, and a source conductive material layer filled in the source trench.

[0025] The gate conductive material layer is connected to the gate composed of the front metal layer.

[0026] The source conductive material layer is connected to the source electrode composed of the front metal layer.

[0027] Each of the trench structures passes through a channel region doped with the second conductivity type; a surface of the channel region covered by a side surface of the gate conductive material layer is used to form a conductive channel of the first conductivity type.

[0028] A heavily doped source region of the first conductivity type is formed on the surface of the channel region and is self-aligned with the trench structure.

[0029] A drift region doped with a first conductive type is formed at the bottom of the channel region.

[0030] A collector region heavily doped with the second conductivity type is formed at the bottom of the drift region.

[0031] When the IGBT device is in the on state, the absolute value of the gate-source voltage is greater than the absolute value of the threshold voltage and it has a first conductive type current and a second conductive type current at the same time, and the second conductive type current flows from the collector region and through the drift region and the channel region to the source region; the gate-source voltage makes the attraction of the source trench structure to the second conductive type carriers greater than the attraction of the gate trench structure to the second conductive type carriers, so that the path of the second conductive type current is close to the source trench structure and away from the gate trench structure.

[0032] A further improvement is that the gate dielectric layer and the source dielectric layer are made of the same material.

[0033] A further improvement is that the thickness of the source dielectric layer is thinner than that of the gate dielectric layer.

[0034] A further improvement is that the gate conductive material layer and the source conductive material layer are made of the same material and include polysilicon.

[0035] A further improvement is that the depth of the source trench is greater than the depth of the gate trench.

[0036] A further improvement is that the arrangement structure of the groove structure includes:

[0037] One or more source trench structures are provided on both sides of each gate trench structure.

[0038] Alternatively, one or more gate trench structures are provided between the two source trench structures.

[0039] A further improvement is that the gate trench structure further includes a shielding dielectric layer and a shielding conductive material layer.

[0040] The shielding conductive material layer is connected to the source electrode.

[0041] An inter-gate dielectric layer is provided between the gate conductive material layer and the shielding conductive material layer.

[0042] The shielding dielectric layer is located on the bottom surface and the bottom area of ​​the side surfaces of the gate trench.

[0043] The gate dielectric layer is located in a top region of a side surface of the gate trench.

[0044] The shielding dielectric layer is separated from the shielding conductive material layer and the gate trench.

[0045] The gate dielectric layer is separated from the gate conductive material layer and the gate trench.

[0046] A further improvement is that a carrier storage layer heavily doped with the first conductivity type is formed in the top area of ​​the drift region.

[0047] A further improvement is that the materials of the gate dielectric layer and the source dielectric layer both include an oxide layer.

[0048] A further improvement is that the gate dielectric layer is formed by stacking a first oxide layer and a second oxide layer, and the source dielectric layer is composed of the second oxide layer.

[0049] Alternatively, the gate dielectric layer is composed of a third oxide layer, and the source dielectric layer is composed of a thinned third oxide layer.

[0050] A further improvement is that the thickness of the gate dielectric layer is The thickness of the source dielectric layer is Alternatively, the thickness of the gate dielectric layer is The thickness of the source dielectric layer is

[0051] A further improvement is that the depth of the source trench is 5 μm or 6 μm, and the depth of the gate trench is 4 μm or 3 μm.

[0052] A further improvement is that the gate dielectric layer and the source dielectric layer are made of different materials and the dielectric constant of the gate dielectric layer is smaller than the dielectric constant of the source dielectric layer.

[0053] A further improvement is that the top of the source region is connected to the source electrode through a through hole.

[0054] The through hole on the top of the source region also passes through the source region and contacts the channel region.

[0055] A further improvement is that the IGBT device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type.

[0056] Alternatively, the IGBT device is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0057] The present invention divides the trench structure into a gate trench structure and a source trench structure. The gate conductive material layer of the gate trench structure is connected to the gate, and the source conductive material layer of the source trench structure is connected to the source. In this way, when the device is turned on, the voltage difference between the gate and the source, that is, the gate-source voltage, makes the attraction of the source trench structure to the second conductive type carriers greater than the attraction of the gate trench structure to the second conductive type carriers. Taking an N-type device as an example, the gate-source voltage is positive and greater than the threshold voltage, the source voltage is 0V, the gate voltage is greater than the threshold voltage, and the second conductive type carriers are holes, which obviously have a lower potential. The source voltage has a greater attraction for holes; in this way, the path of the second conductive type current will be close to the source trench structure and away from the gate trench structure. Since the path of the second conductive type current is away from the gate trench structure, the impact on the gate capacitance becomes smaller, thereby preventing the gate capacitance from decreasing. Therefore, the present invention can prevent the gate capacitance from decreasing due to the increase in the second conductive type current during the device turn-on process, thereby preventing the turn-on speed from increasing due to the reduction in gate capacitance and the increase in the rate of change of current over time due to the increase in the turn-on speed, thereby improving the controllability of the rate of change of current over time.

[0058] The gate trench structure and the source trench structure of the present invention can adopt the same structure except for different electrode connections, which can reduce process costs.

[0059] The present invention can also independently configure the source trench structure to further improve and reduce the rate of change of current over time, including:

[0060] The present invention can also set the source dielectric layer of the source trench structure to be thinner than the gate dielectric layer of the gate trench structure, so that the coupling effect of the source conductive material layer on the area outside the source trench is increased, which can further increase the attraction of the source trench structure to the second conductive type carriers, thereby further reducing the gate capacitance and reducing the rate of change of current over time.

[0061] The present invention can also set the depth of the source trench to be greater than the depth of the gate trench, which can also increase the coupling effect of the source conductive material layer on the area outside the source trench, and can further increase the attraction of the source trench structure to the second conductive type carriers, thereby further reducing the gate capacitance and reducing the rate of change of current over time.

[0062] The present invention can also set the dielectric constant of the source dielectric layer to be higher than the dielectric constant of the gate trench structure, thereby increasing the coupling effect of the source conductive material layer on the area outside the source trench, and further increasing the attraction of the source trench structure to the second conductive type carriers, thereby further reducing the gate capacitance and reducing the rate of change of current over time. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0064] Figure 1 It is a structural diagram of an existing IGBT device;

[0065] Figure 2 1 is a schematic structural diagram of an IGBT device according to a first embodiment of the present invention;

[0066] Figure 3 1 is a schematic structural diagram of an IGBT device according to a second embodiment of the present invention;

[0067] Figure 4 1 is a schematic structural diagram of an IGBT device according to a third embodiment of the present invention;

[0068] Figure 5 It is a schematic structural diagram of an IGBT device according to a fourth embodiment of the present invention. DETAILED DESCRIPTION

[0069] like Figure 2 FIG. 1 is a schematic structural diagram of an IGBT device according to a first embodiment of the present invention. The IGBT device according to the first embodiment of the present invention comprises: a plurality of trench structures arranged in parallel, a portion of the trench structures serving as gate trench structures 201a, and another portion of the trench structures serving as source trench structures 201b. Figure 2 Only three trench structures are shown, including a gate trench structure 201 a and two source trench structures 201 b located on both sides of the gate trench structure 201 a .

[0070] The gate trench structure 201 a includes a gate trench 202 a , a gate dielectric layer 4 a formed on the inner surface of the gate trench 202 a , and a gate conductive material layer 5 a filled in the gate trench 202 a .

[0071] The source trench structure 201 b includes a source trench 202 b , a source dielectric layer 4 b formed on the inner surface of the source trench 202 b , and a source conductive material layer 5 b filled in the source trench 202 b .

[0072] The gate conductive material layer 5 a is connected to a gate (not shown) composed of a front metal layer 11 .

[0073] The source conductive material layer 5b is connected to the source electrode composed of the front metal layer 11. Figure 2 The front metal layer 11 serving as the source is shown in FIG.

[0074] Each trench structure passes through the channel region 7 doped with the second conductivity type; the surface of the channel region 7 covered by the side surface of the gate conductive material layer 5 a is used to form a conductive channel of the first conductivity type.

[0075] A heavily doped source region 10 of the first conductivity type is formed on the surface of the channel region 7 and is self-aligned with the trench structure. In this application, the source region 10 is also referred to as the emitter region, and the source electrode is also referred to as the emitter electrode.

[0076] A drift region 3 doped with the first conductivity type is formed at the bottom of the channel region 7 .

[0077] A collector region 1 heavily doped with the second conductivity type is formed at the bottom of the drift region 3 .

[0078] In the first embodiment of the present invention, the IGBT device is a FS-IGBT device, which further includes a buffer layer 2 heavily doped with the first conductivity type between the drift region 3 and the collector region 1. The buffer layer 2 can cut off the electric field, that is, reduce the electric field to 0 in the buffer layer 2.

[0079] When the IGBT device is in the on state, the absolute value of the gate-source voltage is greater than the absolute value of the threshold voltage and it has a first conductive type current and a second conductive type current at the same time. The second conductive type current flows from the collector region 1 and passes through the drift region 3 and the channel region 7 to the source region 10; the gate-source voltage makes the attraction of the source trench structure 201b to the second conductive type carriers greater than the attraction of the gate trench structure 201a to the second conductive type carriers, so that the path of the second conductive type current is close to the source trench structure 201b and away from the gate trench structure 201a.

[0080] In the first embodiment of the present invention, the gate dielectric layer 4a and the source dielectric layer 4b are made of the same material.

[0081] The thickness of the source dielectric layer 4b is thinner than that of the gate dielectric layer 4a. Under the condition that the gate dielectric layer 4a and the source dielectric layer 4b are made of the same material, if the thickness of the source dielectric layer 4b is thinner, the coupling effect of the source conductive material layer 5b on the area outside the source trench 202b will increase, thereby further increasing the attraction of the second conductivity type carriers. In other embodiments, the thickness of the source dielectric layer 4b can also be the same as that of the gate dielectric layer 4a. In this way, the source dielectric layer 4b and the gate dielectric layer 4a can be formed simultaneously using the same process, which will reduce process costs.

[0082] In the first embodiment of the present invention, the materials of the gate dielectric layer 4a and the source dielectric layer 4b both include an oxide layer.

[0083] In some embodiments, the gate dielectric layer 4a is formed by stacking a first oxide layer and a second oxide layer, and the source dielectric layer 4b is formed by the second oxide layer. In this case, the second oxide layer is formed after the first oxide layer. After the first oxide layer is formed and before the second oxide layer is formed, the first oxide layer on the inner surface of the source trench 202b needs to be patterned and removed.

[0084] In some embodiments, the gate dielectric layer 4a may be formed of a third oxide layer, and the source dielectric layer 4b may be formed of a thinned third oxide layer. That is, after the third oxide layer is formed, a patterned etching process is required to thin the third oxide layer on the inner surface of the source trench 202b alone.

[0085] In some embodiments, the thickness of the gate dielectric layer 4a is The thickness of the source dielectric layer 4b is Alternatively, the thickness of the gate dielectric layer 4a is The thickness of the source dielectric layer 4b is

[0086] In the first embodiment of the present invention, the gate conductive material layer 5a and the source conductive material layer 5b are made of the same material and are both polysilicon. In other embodiments, the gate conductive material layer 5a and the source conductive material layer 5b can also be made of different materials or a conductive material different from polysilicon, such as metal or amorphous silicon.

[0087] In the first embodiment of the present invention, the arrangement structure of the trench structures includes: a gate trench structure 201 a is disposed between two source trench structures 201 b.

[0088] A source trench structure 201 b is disposed on both sides of each gate trench structure 201 a .

[0089] In other embodiments, one or more source trench structures 201 b may be provided on both sides of each gate trench structure 201 a .

[0090] In the first embodiment of the present invention, a carrier storage layer 6 heavily doped with the first conductivity type is further formed in the top region of the drift region 3 .

[0091] In the first embodiment of the present invention, the top of the source region 10 is connected to the source electrode through a through hole 8. The through hole 8 passes through the interlayer film.

[0092] The through hole 8 on the top of the source region 10 also passes through the source region 10 and contacts the channel region 7. In some embodiments, a contact region 9 heavily doped with the second conductivity type is formed at the bottom of the through hole 8.

[0093] In the first embodiment of the present invention, the IGBT device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type. In other embodiments, the IGBT device can also be a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0094] In the first embodiment of the present invention, the trench structure is divided into a gate trench structure 201a and a source trench structure 201b. The gate conductive material layer 5a of the gate trench structure 201a is connected to the gate, and the source conductive material layer 5b of the source trench structure 201b is connected to the source. In this way, when the device is turned on, the voltage difference between the gate and the source, that is, the gate-source voltage, makes the attraction of the source trench structure 201b to the second conductive type carriers greater than the attraction of the gate trench structure 201a to the second conductive type carriers. Taking an N-type device as an example, the gate-source voltage is positive and greater than the threshold voltage, the source voltage is 0V, the gate voltage is greater than the threshold voltage, and the second conductive type carriers are holes. , it is obvious that the source voltage with a lower potential has a greater attraction to holes; in this way, the path of the second conductive type current will be close to the source trench structure 201b and away from the gate trench structure 201a. Since the path of the second conductive type current is away from the gate trench structure 201a, the impact on the gate capacitance becomes smaller, thereby preventing the gate capacitance from decreasing. Therefore, the first embodiment of the present invention can prevent the gate capacitance from decreasing due to the increase of the second conductive type current during the device turn-on process, thereby preventing the turn-on speed from increasing due to the reduction of the gate capacitance and the increase in the rate of change of the current over time due to the increase in the turn-on speed, thereby improving the controllability of the rate of change of the current over time.

[0095] In the first embodiment of the present invention, the source dielectric layer 4b of the source trench structure 201b can be set to be thinner than the gate dielectric layer 4a of the gate trench structure 201a, so that the coupling effect of the source conductive material layer 5b on the area outside the source trench 202b is increased, and the attraction of the source trench structure 201b to the second conductive type carriers can be further increased, thereby further reducing the gate capacitance and reducing the rate of change of current over time.

[0096] In the first embodiment of the present invention, the gate trench structure 201 a and the source trench structure 201 b can be configured to have the same structure, with only the electrode connections being different, thereby reducing process costs.

[0097] like Figure 3 , which is a schematic structural diagram of an IGBT device according to a second embodiment of the present invention; the difference from the IGBT device according to the first embodiment of the present invention is that in the IGBT device according to the second embodiment of the present invention, the depth of the source trench 202b is greater than the depth of the gate trench 202a.

[0098] The second embodiment of the present invention sets the depth of the source trench 202b to be greater than the depth of the gate trench 202a, which can also increase the coupling effect of the source conductive material layer 5b on the area outside the source trench 202b, and can further increase the attraction of the source trench structure 201b to the second conductive type carriers, thereby further reducing the gate capacitance and reducing the rate of change of current over time.

[0099] As an example, in some embodiments, the depth of the source trench 202 b is 5 μm or 6 μm, and the depth of the gate trench 202 a is 4 μm or 3 μm.

[0100] like Figure 4 FIG2 is a schematic structural diagram of an IGBT device according to a third embodiment of the present invention. The difference from the IGBT device according to the first embodiment of the present invention is that, in the IGBT device according to the third embodiment of the present invention, two gate trench structures 201a are disposed between two source trench structures 201b. In other embodiments, three or more gate trench structures 201a may be disposed between two source trench structures 201b.

[0101] Because the IGBT device is composed of multiple device unit structures connected in parallel, each including a gate trench structure 201a, the number of gate trench structures 201a included in the two source trench structures 201b increases, and the number of device unit structures connected in parallel in the entire IGBT device increases. When the device is turned on, the current in the first conductivity type conduction channel controlled by the gate trench structures 201a increases. At the same time, the source trench structures 201b can still ensure the magnitude of the second conductivity type current near each gate trench structure 201a, thereby maintaining the gate capacitance of the entire IGBT device at a desired maximum value. Therefore, the structure of the third embodiment of the present invention facilitates flexible configuration of the arrangement of the trench structures 201a to meet different application requirements.

[0102] like Figure 5 , which is a schematic structural diagram of an IGBT device according to a fourth embodiment of the present invention; the difference from the IGBT device according to the first embodiment of the present invention is that in the IGBT device according to the fourth embodiment of the present invention, the gate trench structure 201a further includes a shielding dielectric layer 203 and a shielding conductive material layer 204.

[0103] The shielding conductive material layer 204 is connected to the source.

[0104] An inter-gate dielectric layer 205 is separated between the gate conductive material layer 5 a and the shielding conductive material layer 204 .

[0105] The shielding dielectric layer 203 is located on the bottom surface and the bottom area of ​​the side surfaces of the gate trench 202 a .

[0106] The gate dielectric layer 4 a is located at the top region of the side surface of the gate trench 202 a .

[0107] A shielding dielectric layer 203 is separated from the shielding conductive material layer 204 and the gate trench 202 a .

[0108] A gate dielectric layer 4a is separated from the gate conductive material layer 5a and the gate trench 202a.

[0109] In some embodiments, the shielding conductive material layer 204 includes polysilicon.

[0110] The material of the inter-gate dielectric layer 205 includes an oxide layer.

[0111] The material of the shielding dielectric layer 203 includes an oxide layer.

[0112] In the fourth embodiment of the IGBT device, the gate trench structure 201a is a shielded gate trench (SGT) gate structure. The thickness of the intergate dielectric layer 205 is typically greater than that of the gate dielectric layer 4a. The shielding conductive material layer 204 is connected to the source electrode to reduce the gate-to-drain capacitance Cgd, thereby improving the switching speed of the device.

[0113] The fifth embodiment of the present invention is an IGBT device:

[0114] The difference from the IGBT device of the first embodiment of the present invention is that in the IGBT device of the fifth embodiment of the present invention, the gate dielectric layer 4a and the source dielectric layer 4b are made of different materials and the dielectric constant of the gate dielectric layer 4a is smaller than that of the source dielectric layer 4b.

[0115] In the fifth embodiment of the present invention, by setting the dielectric constant of the source dielectric layer 4b to be higher than the dielectric constant of the gate trench structure 201a, the coupling effect of the source conductive material layer 5b on the area outside the source trench 202b is increased, thereby further increasing the attraction of the source trench structure 201b to the second conductive type carriers, thereby further reducing the gate capacitance and reducing the rate of change of current over time.

[0116] The present invention has been described in detail above by means of specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principles of the present invention, those skilled in the art may make many variations and improvements, which should also be considered as the scope of protection of the present invention.

Claims

1. An IGBT device, characterized in that: include: Multiple parallel groove structures; A portion of the trench structure is used as a gate trench structure and another portion of the trench structure is used as a source trench structure; The gate trench structure includes a gate trench, a gate dielectric layer formed on the inner surface of the gate trench, and a gate conductive material layer filled in the gate trench; The source trench structure includes a source trench, a source dielectric layer formed on the inner surface of the source trench, and a source conductive material layer filled in the source trench; The gate conductive material layer is connected to the gate composed of the front metal layer; The source conductive material layer is connected to the source electrode composed of the front metal layer; Each of the trench structures passes through a channel region doped with the second conductivity type; a surface of the channel region covered by a side surface of the gate conductive material layer is used to form a conductive channel of the first conductivity type; A heavily doped source region of the first conductivity type is formed on the surface of the channel region and is self-aligned with the trench structure; A drift region doped with a first conductive type is formed at the bottom of the channel region; A collector region heavily doped with a second conductivity type is formed at the bottom of the drift region; When the IGBT device is in an on state, an absolute value of a gate-source voltage is greater than an absolute value of a threshold voltage and the device simultaneously has a first conductivity type current and a second conductivity type current, wherein the second conductivity type current flows from the collector region and through the drift region and the channel region to the source region; the gate-source voltage causes the attraction of the source trench structure to the second conductivity type carriers to be greater than the attraction of the gate trench structure to the second conductivity type carriers, thereby causing the path of the second conductivity type current to be close to the source trench structure and away from the gate trench structure; The gate dielectric layer and the source dielectric layer are made of the same material; The thickness of the source dielectric layer at the bottom and sidewalls of the source trench is thinner than the thickness of the gate dielectric layer at the bottom and sidewalls of the gate trench.

2. The IGBT device according to claim 1, wherein: The gate conductive material layer and the source conductive material layer are made of the same material and include polysilicon.

3. The IGBT device according to claim 1, wherein: The depth of the source trench is greater than the depth of the gate trench.

4. The IGBT device according to claim 1, wherein: The arrangement structure of the groove structure includes: One or more source trench structures are provided on both sides of each gate trench structure; Alternatively, one or more gate trench structures are provided between the two source trench structures.

5. The IGBT device according to claim 1, wherein: The gate trench structure further includes a shielding dielectric layer and a shielding conductive material layer; The shielding conductive material layer is connected to the source electrode; An inter-gate dielectric layer is provided between the gate conductive material layer and the shielding conductive material layer; The shielding dielectric layer is located at the bottom surface and the bottom area of ​​the side surface of the gate trench; The gate dielectric layer is located in a top area of ​​a side surface of the gate trench; The shielding dielectric layer is separated from the gate trench by the shielding conductive material layer; The gate dielectric layer is separated from the gate conductive material layer and the gate trench.

6. The IGBT device according to claim 1, wherein: A carrier storage layer heavily doped with the first conductivity type is also formed in the top area of ​​the drift region.

7. The IGBT device according to claim 1, wherein: The materials of the gate dielectric layer and the source dielectric layer both include an oxide layer.

8. The IGBT device according to claim 7, wherein: The gate dielectric layer is formed by stacking a first oxide layer and a second oxide layer, and the source dielectric layer is formed by the second oxide layer; Alternatively, the gate dielectric layer is composed of a third oxide layer, and the source dielectric layer is composed of a thinned third oxide layer.

9. The IGBT device according to claim 8, wherein: The thickness of the gate dielectric layer is 1200Å, and the thickness of the source dielectric layer is 600Å; alternatively, the thickness of the gate dielectric layer is 1000Å, and the thickness of the source dielectric layer is 500Å.

10. The IGBT device according to claim 3, wherein: The depth of the source trench is 5 μm or 6 μm, and the depth of the gate trench is 4 μm or 3 μm.

11. The IGBT device according to claim 1, wherein: Connecting to the source electrode through a through hole on the top of the source region; The through hole on the top of the source region also passes through the source region and contacts the channel region.

12. The IGBT device according to any one of claims 1 to 11, characterized in that: The IGBT device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; Alternatively, the IGBT device is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

13. An IGBT device, characterized in that: include: Multiple parallel groove structures; A portion of the trench structure is used as a gate trench structure and another portion of the trench structure is used as a source trench structure; The gate trench structure includes a gate trench, a gate dielectric layer formed on the inner surface of the gate trench, and a gate conductive material layer filled in the gate trench; The source trench structure includes a source trench, a source dielectric layer formed on the inner surface of the source trench, and a source conductive material layer filled in the source trench; The gate conductive material layer is connected to the gate composed of the front metal layer; The source conductive material layer is connected to the source electrode composed of the front metal layer; Each of the trench structures passes through a channel region doped with the second conductivity type; a surface of the channel region covered by a side surface of the gate conductive material layer is used to form a conductive channel of the first conductivity type; A heavily doped source region of the first conductivity type is formed on the surface of the channel region and is self-aligned with the trench structure; A drift region doped with a first conductive type is formed at the bottom of the channel region; A collector region heavily doped with a second conductivity type is formed at the bottom of the drift region; When the IGBT device is in an on state, an absolute value of a gate-source voltage is greater than an absolute value of a threshold voltage and the device simultaneously has a first conductivity type current and a second conductivity type current, wherein the second conductivity type current flows from the collector region and through the drift region and the channel region to the source region; the gate-source voltage causes the attraction of the source trench structure to the second conductivity type carriers to be greater than the attraction of the gate trench structure to the second conductivity type carriers, thereby causing the path of the second conductivity type current to be close to the source trench structure and away from the gate trench structure; The gate dielectric layer and the source dielectric layer are made of different materials, and the dielectric constant of the gate dielectric layer is smaller than the dielectric constant of the source dielectric layer.

14. The IGBT device according to claim 13, wherein: The IGBT device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; Alternatively, the IGBT device is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

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