An LED chip and its manufacturing method

Abstract

An LED chip and its fabrication method are disclosed. The second type semiconductor layer of the LED chip includes a first region facing a second electrode and the remaining second region. A current-blocking protective layer assembly includes a blocking layer and a protective layer. The blocking layer is located in the first region. The protective layer at least covers the second region and conducts electricity between a transparent conductive layer and the second type semiconductor layer. The transparent conductive layer is only stacked on the protective layer in the second region. The second electrode is connected to the second type semiconductor layer through the transparent conductive layer and / or the protective layer. The current-blocking protective layer assembly completely covers the second type semiconductor layer, preventing plasma bombardment of the second type semiconductor layer during the fabrication of the transparent conductive layer and thus avoiding defects. By regionally arranging the blocking layer and the protective layer, the current-blocking protective layer assembly can both protect the second type semiconductor layer and block current.

Description

Technical Field

[0001] This invention relates to the field of light-emitting diode technology, and more specifically, to an LED chip and its manufacturing method. Background Technology

[0002] With the continuous development of science and technology, LED (Light Emitting Diode) has become the most popular light source, with an increasingly higher market share and a wider range of applications. Compared with traditional light-emitting devices, LED chips have many advantages such as low power consumption, high color purity, long life, small size, fast response time, energy saving and environmental protection.

[0003] As is well known, a transparent conductive layer is deposited on the surface of a semiconductor layer to achieve better current spread. Currently, magnetron sputtering is the preferred method for depositing most transparent conductive layers because ITO deposited by magnetron sputtering exhibits good density, film uniformity, strong film-substrate adhesion, and fewer defects. However, during magnetron sputtering, the plasma bombards the semiconductor layer, causing defects on the semiconductor surface that affect the reliability of the LED chip. Furthermore, ln from ITO can enter the semiconductor layer, reducing not only the transmittance of ITO and affecting luminous efficiency but also decreasing the chip's ESD capability.

[0004] This case arose to avoid the aforementioned problems when fabricating ITO layers using magnetron sputtering. Summary of the Invention

[0005] In view of this, the present invention provides an LED chip and a method for manufacturing the same, which can avoid defects on the surface of the semiconductor layer when using magnetron sputtering to fabricate the ITO layer, and can also prevent In from ITO from entering the semiconductor layer.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0007] An LED chip, characterized in that it comprises:

[0008] Substrate;

[0009] An epitaxial structure disposed on one side surface of the substrate; the epitaxial structure includes a first type semiconductor layer, an active layer, a second type semiconductor layer, a current barrier layer group, and a transparent conductive layer disposed sequentially along a direction away from the substrate;

[0010] A first electrode electrically connected to the first type of semiconductor layer;

[0011] The second electrode is electrically connected to the second type of semiconductor layer;

[0012] The second type semiconductor layer includes a first region facing the second electrode and a remaining second region; the current blocking protection layer group includes a blocking layer and a protective layer; the blocking layer is located in the first region; the protective layer at least covers the second region and conducts through the transparent conductive layer and the second type semiconductor layer;

[0013] The transparent conductive layer is stacked only on the protective layer of the second region, and the second electrode is connected to the second type semiconductor layer through the transparent conductive layer and / or the protective layer.

[0014] Preferably, both the barrier layer and the protective layer are deposited using atomic layer deposition (ALD), and a temporary barrier layer exposing the first region is deposited on the second type semiconductor layer using chemical vapor deposition (CVD) before depositing the barrier layer and the protective layer; and after the barrier layer is formed by atomic layer deposition and dry etching, the temporary barrier layer is removed by wet etching, and then the protective layer is deposited.

[0015] Preferably, the protective layer is made of a conductive material or an insulating tunneling material.

[0016] Preferably, the thickness of the insulating tunneling material is no greater than 5 nm.

[0017] Preferably, the refractive index of the protective layer is greater than that of the transparent conductive layer and less than that of the second type semiconductor layer.

[0018] Preferably, it further includes a passivation layer and a microsphere anti-reflective coating stacked on the transparent conductive layer;

[0019] The microsphere anti-reflective coating at least covers the exposed surface of the transparent conductive layer;

[0020] The transparent conductive layer is ITO;

[0021] The passivation layer is made of SiO2 material, which covers the exposed surfaces of the epitaxial structure, the first electrode, the second electrode, and the microsphere anti-reflective coating, and has through holes for exposing the electrodes.

[0022] Preferably, the microsphere antireflective coating contains at least two types of microspheres with different diameters.

[0023] Preferably, the microsphere anti-reflective coating is made of SiO2 microspheres.

[0024] Preferably, the microsphere antireflective coating comprises SiO2 microspheres no larger than 2 μm, SiO2 microspheres no larger than 20 nm, sodium dodecyl sulfate, and anhydrous ethanol; wherein the volume ratio of SiO2 microspheres no larger than 2 μm: SiO2 microspheres no larger than 20 nm: sodium dodecyl sulfate: anhydrous ethanol is 1:10:10:10.

[0025] This invention also provides a method for manufacturing an LED chip, characterized by comprising the following steps:

[0026] Provide a substrate;

[0027] An epitaxial structure is grown on one side surface of the substrate; the growth of the epitaxial structure includes sequentially growing a first type semiconductor layer, an active layer, a second type semiconductor layer, a current barrier layer group, and a transparent conductive layer along a direction away from the substrate;

[0028] Fabricate a first electrode that is electrically connected to the first type of semiconductor layer;

[0029] Fabricate a second electrode that is electrically connected to the second type of semiconductor layer;

[0030] The second type semiconductor layer includes a first region facing the second electrode and a remaining second region; fabricating the current blocking protective layer assembly includes fabricating a blocking layer and a protective layer; the blocking layer is located in the first region; the protective layer at least covers the second region and conducts through the transparent conductive layer and the second type semiconductor layer;

[0031] The transparent conductive layer is stacked only on the protective layer of the second region, and the second electrode is connected to the second type semiconductor layer through the transparent conductive layer and / or the protective layer.

[0032] Preferably, when fabricating the current blocking protective layer assembly, the blocking layer is fabricated first, followed by the protective layer.

[0033] Before fabricating the barrier layer, a temporary barrier material layer covering the second type semiconductor layer is deposited using chemical vapor deposition, and the temporary barrier material layer is subjected to photolithography and wet etching to form a temporary barrier layer exposing the first region.

[0034] A barrier material layer is fabricated on the temporary barrier layer using atomic layer deposition, and the barrier material layer is then subjected to photolithography and inductively coupled plasma (ICP) etching to form a barrier layer covering the first region.

[0035] The aforementioned LED chip semi-finished product was placed in a BOE etching tank for wet etching to remove the temporary barrier layer.

[0036] A protective layer covering at least the second region is deposited using atomic layer deposition.

[0037] Preferably, the protective layer is made of a conductive material or an insulating tunneling material.

[0038] Preferably, the refractive index of the protective layer is greater than that of the transparent conductive layer and less than that of the second type semiconductor layer.

[0039] Preferably, it further includes forming a microsphere anti-reflective coating that at least covers the exposed surface of the transparent conductive layer;

[0040] The transparent conductive layer is ITO;

[0041] After fabricating the first and second electrodes, a passivation layer is also fabricated. The passivation layer is made of SiO2 material and covers the exposed surfaces of the epitaxial structure, the first electrode, the second electrode, and the microsphere anti-reflective coating, and has through holes for exposing the electrodes.

[0042] Preferably, the microsphere antireflective coating contains at least two types of microspheres with different diameters.

[0043] Compared with the prior art, the technical solution provided by the present invention has at least the following advantages:

[0044] 1. The current barrier protection layer group of the LED chip in this application completely covers the second-type semiconductor layer. When the transparent conductive layer is fabricated using magnetron sputtering, the second-type semiconductor layer and the transparent conductive layer are isolated, preventing plasma bombardment of the second-type semiconductor layer from causing defects, increasing the chip's reliability, improving the transmittance of the transparent conductive layer, and increasing the chip's ESD capability. Furthermore, by setting the barrier layer and protective layer in different regions, the current barrier protection layer group can both protect the second-type semiconductor layer and block current.

[0045] 2. Both the barrier layer and the protective layer are deposited using atomic layer deposition (ALD), which will not cause defects in the type II semiconductor layer. A temporary barrier layer is added, and after the barrier layer is formed by atomic layer deposition and dry etching, the temporary barrier layer is removed by wet etching. This avoids defects in the type II semiconductor layer caused by dry etching during barrier layer formation. The removal of the temporary barrier layer using wet etching will not cause defects in the type II semiconductor layer.

[0046] 3. The refractive index of the protective layer is greater than that of the transparent conductive layer and less than that of the type II semiconductor layer, which can play a role in enhancing light transmission and increasing the light output of the LED chip.

[0047] 4. Since the SiO2 passivation layer is typically fabricated using chemical vapor deposition (CVD), the reactant gas used is SiH4. During deposition, the H radicals generated can reduce the inn2O3 in the transparent conductive layer (ITO) to In metal, affecting the ITO's transmittance and reducing the LED chip's luminous efficacy. Furthermore, an overly smooth and dense passivation layer surface can limit the chip's light extraction efficiency due to reflection, further reducing its luminous efficacy. Layering a microsphere anti-reflective coating that at least covers the exposed surface of the transparent conductive layer can, on the one hand, prevent H radicals from contacting the transparent conductive layer; on the other hand, the rough surface of the microsphere anti-reflective coating can increase the scattering effect, reduce reflection, increase the critical angle, and allow more light to refract, thus increasing the LED chip's light extraction efficiency.

[0048] 5. The microsphere anti-reflective coating contains at least two types of microspheres with different diameters, which can increase its surface roughness and increase the light extraction efficiency of the LED chip.

[0049] 6. The anti-reflective coating uses SiO2 microspheres, which are the same material as the passivation layer. When patterning the anti-reflective coating and the passivation layer, they can be photolithographically ... Attached Figure Description

[0050] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0051] Figure 1 This is a schematic diagram of the LED chip structure in this application;

[0052] Figure 2 -10 is a structural schematic diagram of the LED chip manufacturing process in this application.

[0053] Figure label:

[0054] Substrate 1; Type I semiconductor layer 2; Active layer 3; Type II semiconductor layer 4; Current blocking protection layer group 5; Blocking layer 51; Protective layer 52; Transparent conductive layer 6; Microsphere anti-reflection coating 7; Passivation layer 8; First electrode 9; Second electrode 10; Temporary barrier layer 20. Detailed Implementation

[0055] To make the content of this invention clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0056] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0057] Secondly, this application provides a detailed description in conjunction with schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not adhering to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In addition, actual fabrication should include three-dimensional spatial dimensions of length, width, and depth.

[0058] This invention provides an LED chip, such as... Figure 1 As shown, it includes a substrate 1, an epitaxial structure disposed on one side surface of the substrate 1, a first electrode 9 electrically connected to a first type semiconductor layer 2, and a second electrode 10 electrically connected to a second type semiconductor layer 4.

[0059] The epitaxial structure includes a first-type semiconductor layer 2, an active layer 3, a second-type semiconductor layer 4, a current barrier layer group 5, and a transparent conductive layer 6, sequentially disposed along a direction away from the substrate 1. One of the first-type semiconductor layer 2 and the second-type semiconductor layer 4 is a P-type semiconductor layer, and the other is an N-type semiconductor layer. This application uses an example where the first-type semiconductor layer 2 is an N-type semiconductor layer and the second-type semiconductor layer 4 is a P-type semiconductor layer. The N-type semiconductor layer can be N-type GaN, and the P-type semiconductor layer can be P-type GaN.

[0060] like Figure 1 , 7 As shown, the second type semiconductor layer 4 includes a first region facing the second electrode 10 and the remaining second region. The current blocking protective layer group 5 includes a blocking layer 51 and a protective layer 52; the blocking layer 51 is located in the first region; the protective layer 52 at least covers the second region and conducts electricity between the transparent conductive layer 6 and the second type semiconductor layer 4.

[0061] The transparent conductive layer 6 is stacked only on the protective layer located in the second region, and the second electrode 10 is connected to the second type semiconductor layer 4 through the transparent conductive layer 6 and / or the protective layer.

[0062] The current barrier layer 5 of this application completely covers the second-type semiconductor layer 4, isolating the second-type semiconductor layer 4 and the transparent conductive layer 6. When the transparent conductive layer 6 is fabricated using magnetron sputtering, plasma bombardment of the second-type semiconductor layer 4 is avoided, thus preventing defects and increasing chip reliability, improving the transmittance of the transparent conductive layer, and enhancing the chip's ESD capability. Furthermore, by dividing the current barrier layer 5 into regions with barrier layers 51 and protective layers 52, the current barrier layer 5 can both protect the second-type semiconductor layer 4 and block current.

[0063] Preferably, the thickness of the protective layer 52 is less than the thickness of the barrier layer 51, and the transparent conductive layer 6 only covers the protective layer 52, reducing the increased thickness of the LED chip caused by protecting the second type semiconductor layer 4.

[0064] Furthermore, both the barrier layer 51 and the protective layer 52 are deposited using atomic layer deposition (ALD). Before depositing the barrier layer 51 and the protective layer 52, a temporary barrier layer 20 exposing the first region is deposited on the second type semiconductor layer 4 using chemical vapor deposition (CVD). After forming the barrier layer 51 by atomic layer deposition and dry etching, the temporary barrier layer 20 is removed by wet etching, and then the protective layer 52 is deposited. In this application, the temporary barrier layer 20 includes, but is not limited to, SiO2, and its thickness can be set to 100nm-300nm, including the endpoint values. The protective layer 52 covers the second region of the second type semiconductor layer 4 and the barrier layer 51.

[0065] Both the barrier layer 51 and the protective layer 52 are deposited using atomic layer deposition (ALD), which will not cause defects in the second type semiconductor layer 4. A temporary barrier layer 20 is added, and after the barrier layer 51 is formed by atomic layer deposition and dry etching, the temporary barrier layer 20 is removed by wet etching to prevent defects in the second type semiconductor layer 4 caused by the dry etching process of forming the barrier layer 51. The removal of the temporary barrier layer 20 using wet etching will not cause defects in the second type semiconductor layer 4.

[0066] In a preferred embodiment, the protective layer 52 is made of a conductive material or an insulating tunneling material.

[0067] Among them, insulating tunneling material refers to insulating material that allows current to tunnel through when a certain thickness is met. The thickness of the insulating tunneling layer is no greater than 5 nm. When the protective layer 52 uses insulating tunneling material, it can be the same material as the barrier layer 51.

[0068] For example, the barrier layer 51 includes, but is not limited to, Al2O3. The protective layer 52 can be made of Al2O3, HfO2, SnO2, AZO, ZrO2, etc.

[0069] Preferably, the thickness of the barrier layer 51 ranges from 50nm to 200nm, including the endpoint values.

[0070] The protective layer 52 is made of insulating tunneling material and its thickness is set to no more than 5nm to meet the requirements of current tunneling. When the protective layer 52 is made of conductive material, its thickness range can be set to 5nm-10nm, including the endpoint value.

[0071] For example, when the protective layer 52 is selected from HfO2, Al2O3, or ZrO2, its thickness is no greater than 5 nm. When the protective layer 52 is selected from SnO2 or AZO, its thickness range can be set to 5 nm–10 nm.

[0072] In a preferred embodiment, the refractive index of the protective layer 52 is greater than that of the transparent conductive layer 6 and less than that of the second-type semiconductor layer 4. This greater refractive index of the protective layer 52 compared to the transparent conductive layer 6 and less than that of the second-type semiconductor layer 4 serves to enhance light transmission and increase the light output of the LED chip. In this application, the second-type semiconductor is P-GaN, and the transparent conductive layer is ITO; therefore, the refractive index A of the protective layer 52 ranges from 1.8 < A < 2.3. When the protective layer 52 is made of HfO2, SnO2, AZO, or ZrO2, its refractive index is greater than that of the transparent conductive layer 6 and less than that of the second-type semiconductor layer 4.

[0073] In a preferred embodiment, such as Figure 1 As shown, the LED chip also includes a passivation layer 8 and a microsphere anti-reflective coating 7 stacked on the transparent conductive layer 6. The microsphere anti-reflective coating 7 at least covers the exposed surface of the transparent conductive layer 6. The passivation layer 8 is made of SiO2 material, which covers the exposed surfaces of the epitaxial structure, the first electrode 9, the second electrode 10, and the microsphere anti-reflective coating 7, and has through holes exposing the electrodes. The transparent conductive layer 6 is made of ITO.

[0074] Since the SiO2 passivation layer 8 is typically fabricated using chemical vapor deposition (CVD), the reaction gas used during deposition is SiH4. During deposition, the H radicals generated can reduce the in₂O₃ in the transparent conductive layer 6 and ITO to In metal, affecting the ITO's transmittance and reducing the LED chip's luminous efficacy. Furthermore, the overly smooth and dense surface of the passivation layer 8 can limit the chip's light extraction efficiency due to reflection, further reducing its luminous efficacy. Layering a microsphere anti-reflective coating 7, which at least covers the exposed surface of the transparent conductive layer 6, can prevent H radicals from contacting the transparent conductive layer 6. Additionally, the rough surface of the microsphere anti-reflective coating 7 increases the scattering effect, reduces reflection, increases the critical angle, and allows more light to refract, thus increasing the LED chip's light extraction efficiency.

[0075] Preferably, the microsphere anti-reflective coating 7 contains at least two types of microspheres with different diameters. This arrangement can increase its surface roughness and increase the light extraction efficiency of the LED chip.

[0076] Preferably, the microsphere anti-reflective coating 7 is made of SiO2 microspheres, and the material of the microspheres is the same as that of the passivation layer 8. When the microsphere anti-reflective coating 7 and the passivation layer 8 are patterned, they can be photolithographically ...

[0077] Specifically, such as Figure 1 As shown, the microsphere anti-reflective coating 7 of this application also covers the exposed surfaces of the epitaxial structure, the first electrode 9, and the second electrode 10, and has through holes exposing the electrodes. In this way, the through holes exposing the electrodes can be processed together after the microsphere anti-reflective coating 7 and the passivation layer 8 are both fabricated. In this application, taking a horizontally mounted LED chip as an example, it is necessary to process through holes exposing the first electrode 9 and the second electrode 10.

[0078] Preferably, the microsphere antireflective coating 7 comprises SiO2 microspheres no larger than 2 μm, SiO2 microspheres no larger than 20 nm, sodium dodecyl sulfate, and anhydrous ethanol; wherein the volume ratio of SiO2 microspheres no larger than 2 μm: SiO2 microspheres no larger than 20 nm: sodium dodecyl sulfate: anhydrous ethanol is 1:10:10:10.

[0079] This application also provides a method for manufacturing an LED chip, such as... Figure 2 As shown in Figure 10, it includes the following steps:

[0080] S01: Provide a substrate 1.

[0081] S02: An epitaxial structure is grown on one side of the substrate 1; the growth of the epitaxial structure includes growing a first type semiconductor layer 2, an active layer 3, a second type semiconductor layer 4, a current blocking protection layer group 5, and a transparent conductive layer 6 in sequence along a direction away from the substrate 1.

[0082] S03: Fabricate a first electrode 9 that is electrically connected to the first type of semiconductor layer 2.

[0083] S04: Fabricate a second electrode 10 that is electrically connected to the second type semiconductor layer 4.

[0084] like Figure 7 As shown, the second type semiconductor layer 4 includes a first region facing the second electrode 10 and the remaining second region; the fabrication of the current blocking protective layer group 5 includes fabricating a blocking layer 51 and a protective layer 52; the blocking layer 51 is located in the first region; the protective layer 52 at least covers the second region and conducts the transparent conductive layer 6 and the second type semiconductor layer 4.

[0085] like Figure 8 As shown, the transparent conductive layer 6 is only stacked on the protective layer 52 of the second region, and the second electrode 10 is connected to the second type semiconductor layer 4 through the transparent conductive layer 6 and / or the protective layer 52.

[0086] In this embodiment, one of the first type semiconductor layer 2 and the second type semiconductor layer 4 is a P-type semiconductor layer, and the other is an N-type semiconductor layer. This application uses an example where the first type semiconductor layer 2 is an N-type semiconductor layer and the second type semiconductor layer 4 is a P-type semiconductor layer. The N-type semiconductor layer can be N-type GaN, and the P-type semiconductor layer can be P-type GaN.

[0087] In step S02, after growing the first type semiconductor layer 2, the active layer 3, and the second type semiconductor layer 4 on the substrate, a groove exposing the N-type semiconductor layer is fabricated through photolithography and etching steps. The etching method is inductively coupled plasma etching, and the etching gases used are chlorine (Cl2), boron trichloride (BCl3), and argon (Ar). The etching depth is 0.5µm–4µm, including the endpoint values. After the groove is fabricated, the current blocking protective layer group 5 and the transparent conductive layer 6 are then fabricated.

[0088] Preferably, the thickness of the protective layer 52 is less than the thickness of the barrier layer 51.

[0089] Furthermore, in step S02, when fabricating the current blocking protective layer group 5, the blocking layer 51 is fabricated first, and then the protective layer 52 is fabricated.

[0090] Before fabricating the barrier layer 51, a temporary barrier material layer covering the second type semiconductor layer 4 is deposited by chemical vapor deposition. The temporary barrier material layer is then subjected to photolithography and wet etching to form a temporary barrier layer 20 exposing the first region. The thickness of the temporary barrier layer 20 is 100nm-300nm.

[0091] A barrier material layer is fabricated on the temporary barrier layer 20 using atomic layer deposition, and the barrier material layer is then subjected to photolithography and inductively coupled plasma (ICP) etching to form a barrier layer 51 covering the first region; specifically, as shown... Figure 5 As shown, a photoresist layer covering only the first region is formed on the barrier material layer, such as... Figure 6 As shown, a barrier layer 51 is formed by further etching. Preferably, when etching the barrier material layer using inductively coupled plasma (ICP), the reaction gases are CF4 and O2, the reaction chamber pressure is 5-10 mTorr (including the endpoint value), and the radio frequency power of the upper electrode and the lower electrode is 1000-1200W (including the endpoint value) and 300-800W (including the endpoint value), respectively.

[0092] like Figure 6 As shown, the above-mentioned LED chip semi-finished product is placed in the BOE etching tank for wet etching to remove the temporary barrier layer 20; specifically, after removing the temporary barrier layer 20, it is also necessary to remove the photoresist layer on the barrier layer 51.

[0093] like Figure 7 As shown, an atomic layer deposition method is used to deposit a protective layer 52 that at least covers the second region. In this application, the protective layer 52 covers the second region and the barrier layer 51.

[0094] In the process of fabricating the transparent conductive layer 6, a transparent conductive layer material layer is first deposited on the protective layer 52 by magnetron sputtering. Then, through photolithography and etching, a via corresponding to the first region of the second type semiconductor layer 4 is fabricated. After the resist is removed, the transparent conductive layer 6 is obtained.

[0095] Preferably, the protective layer 52 is made of a conductive material or an insulating tunneling material.

[0096] Among them, insulating tunneling material refers to insulating material that allows current to tunnel through when a certain thickness is met.

[0097] Furthermore, the thickness of the insulating tunneling material is no greater than 5 nm. When the protective layer 52 is made of an insulating tunneling material, it can be the same material as the barrier layer 51.

[0098] For example, the barrier layer 51 includes, but is not limited to, Al2O3. The protective layer 52 can be made of Al2O3, HfO2, SnO2, AZO, ZrO2, etc.

[0099] Preferably, the thickness of the barrier layer 51 ranges from 50nm to 200nm, including the endpoint values.

[0100] When the protective layer 52 is made of insulating tunneling material with a thickness of no more than 5 nm, it is to meet the requirements of current tunneling. When the protective layer 52 is made of conductive material, the thickness range can be set to 5 nm to 10 nm, including the endpoint value.

[0101] For example, when the protective layer 52 is selected from HfO2, Al2O3, or ZrO2, its thickness is no greater than 5 nm. When the protective layer 52 is selected from SnO2 or AZO, its thickness range can be set to 5 nm–10 nm.

[0102] Preferably, the refractive index of the protective layer 52 is greater than that of the transparent conductive layer 6 and less than that of the second type semiconductor layer 4. This greater refractive index of the protective layer 52 compared to the transparent conductive layer 6, and less than that of the second type semiconductor layer 4, effectively enhances light transmission and increases the light output of the LED chip. In this application, when the second type semiconductor is P-GaN and the transparent conductive layer is ITO, the refractive index A of the protective layer 52 ranges from 1.8 < A < 2.3. When the protective layer 52 is made of HfO2, SnO2, AZO, or ZrO2, its refractive index is greater than that of the transparent conductive layer 6 and less than that of the second type semiconductor layer 4.

[0103] Furthermore, such as Figure 9 As shown, the method for fabricating an LED chip further includes fabricating a microsphere anti-reflective coating 7 that at least covers the exposed surface of the transparent conductive layer 6. The transparent conductive layer 6 is ITO. After fabricating the first electrode 9 and the second electrode 10, a passivation layer 8 is also fabricated; the passivation layer 8 is made of SiO2 material, which covers the exposed surfaces of the epitaxial structure, the first electrode 9, the second electrode 10, and the microsphere anti-reflective coating 7, and has through holes exposing the electrodes.

[0104] Preferably, the microsphere antireflective coating 7 contains at least two types of microspheres with different diameters.

[0105] Preferably, the microsphere anti-reflective coating 7 is made of SiO2 microspheres. Specifically, as shown in the example... Figure 9 As shown, the microsphere anti-reflective coating 7 of this application also covers the exposed surfaces of the epitaxial structure, the first electrode 9, and the second electrode 10, and has through holes exposing the electrodes. This allows the through holes exposing the electrodes to be fabricated together after both the microsphere anti-reflective coating 7 and the passivation layer 8 are fabricated. In this application, a horizontally mounted LED chip is used as an example. Figure 10 As shown, through holes need to be machined to expose the first electrode 9 and the second electrode 10, forming... Figure 1 The chip structure shown.

[0106] Preferably, the microsphere antireflective coating 7 comprises SiO2 microspheres no larger than 2 μm, SiO2 microspheres no larger than 20 nm, sodium dodecyl sulfate, and anhydrous ethanol; wherein the volume ratio of SiO2 microspheres no larger than 2 μm: SiO2 microspheres no larger than 20 nm: sodium dodecyl sulfate: anhydrous ethanol is 1:10:10:10.

[0107] Preferably, in steps S03 and S04, the first electrode 9 and the second electrode 10 are deposited by metal vapor deposition, and their thicknesses are 0.5um-8um, including the endpoint values.

[0108] The method for manufacturing the LED chip in this application corresponds to the LED chip described above and has all the beneficial effects mentioned in the LED chip description, which will not be repeated here. For any parts not mentioned in the LED chip manufacturing method, please refer to the content settings of the LED chip described above.

[0109] Those skilled in the art should understand that, in the disclosure of this invention, the terms "lateral", "longitudinal", "upper", "lower", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the above terms should not be construed as limiting this invention.

[0110] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0111] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An LED chip, characterized in that, include: Substrate; An epitaxial structure disposed on one side surface of the substrate; the epitaxial structure includes a first type semiconductor layer, an active layer, a second type semiconductor layer, a current barrier layer group, and a transparent conductive layer disposed sequentially along a direction away from the substrate; A first electrode electrically connected to the first type of semiconductor layer; The second electrode is electrically connected to the second type of semiconductor layer; The second type semiconductor layer includes a first region facing the second electrode and a remaining second region; the current blocking protection layer group includes a blocking layer and a protective layer; the blocking layer is located in the first region; the protective layer at least covers the second region and conducts the transparent conductive layer and the second type semiconductor layer; the protective layer is deposited using atomic layer deposition (ALD). The transparent conductive layer is stacked only on the protective layer of the second region, and the second electrode is connected to the second type semiconductor layer through the transparent conductive layer and / or the protective layer.

2. The LED chip as described in claim 1, characterized in that, The barrier layer is deposited using atomic layer deposition (ALD), and prior to depositing the barrier layer and the protective layer, a temporary barrier layer exposing the first region is deposited on the second type semiconductor layer using chemical vapor deposition (CVD). After forming the barrier layer by atomic layer deposition and dry etching, the temporary barrier layer is removed by wet etching, and then a protective layer is deposited.

3. The LED chip as described in claim 1, characterized in that, The protective layer is made of either a conductive material or an insulating tunneling material.

4. An LED chip as described in claim 3, characterized in that, The thickness of the insulating tunneling material is no greater than 5 nm.

5. An LED chip as described in claim 1, characterized in that, The refractive index of the protective layer is greater than that of the transparent conductive layer, but less than that of the second type semiconductor layer.

6. An LED chip as described in claim 1, characterized in that, It also includes a passivation layer and a microsphere anti-reflective coating stacked on the transparent conductive layer; The microsphere anti-reflective coating at least covers the exposed surface of the transparent conductive layer; The transparent conductive layer is ITO; The passivation layer is made of SiO2 material, which covers the exposed surfaces of the epitaxial structure, the first electrode, the second electrode, and the microsphere anti-reflective coating, and has through holes for exposing the electrodes.

7. An LED chip as described in claim 6, characterized in that, The microsphere anti-reflective coating contains at least two types of microspheres with different diameters.

8. An LED chip as described in claim 6, characterized in that, The anti-reflective coating is made of SiO2 microspheres.

9. An LED chip as described in claim 7, characterized in that, The microsphere antireflective coating comprises SiO2 microspheres no larger than 2 μm, SiO2 microspheres no larger than 20 nm, sodium dodecyl sulfate, and anhydrous ethanol; wherein the volume ratio of SiO2 microspheres no larger than 2 μm: SiO2 microspheres no larger than 20 nm: sodium dodecyl sulfate: anhydrous ethanol is 1:10:10:

10.

10. A method for manufacturing an LED chip, characterized in that, Includes the following steps: Provide a substrate; An epitaxial structure is grown on one side surface of the substrate; the growth of the epitaxial structure includes sequentially growing a first type semiconductor layer, an active layer, a second type semiconductor layer, a current barrier layer group, and a transparent conductive layer along a direction away from the substrate; Fabricate a first electrode that is electrically connected to the first type of semiconductor layer; Fabricate a second electrode that is electrically connected to the second type of semiconductor layer; The second type semiconductor layer includes a first region facing the second electrode and a remaining second region; fabricating the current blocking protective layer assembly includes fabricating a blocking layer and a protective layer; the blocking layer is located in the first region; the protective layer at least covers the second region and conducts through the transparent conductive layer and the second type semiconductor layer; the protective layer is deposited using atomic layer deposition (ALD). The transparent conductive layer is stacked only on the protective layer of the second region, and the second electrode is connected to the second type semiconductor layer through the transparent conductive layer and / or the protective layer.

11. The method for manufacturing an LED chip as described in claim 10, characterized in that, When fabricating the current blocking protective layer assembly, the blocking layer is fabricated first, followed by the protective layer. Before fabricating the barrier layer, a temporary barrier material layer covering the second type semiconductor layer is deposited using chemical vapor deposition, and the temporary barrier material layer is subjected to photolithography and wet etching to form a temporary barrier layer exposing the first region. A barrier material layer is fabricated on the temporary barrier layer by atomic layer deposition, and the barrier material layer is then subjected to photolithography and inductively coupled plasma (ICP) etching to form a barrier layer covering the first region. The aforementioned LED chip semi-finished product was placed in a BOE etching tank for wet etching to remove the temporary barrier layer. A protective layer covering at least the second region is deposited using atomic layer deposition.

12. The method for manufacturing an LED chip as described in claim 10, characterized in that, The protective layer is made of either a conductive material or an insulating tunneling material.

13. The method for manufacturing an LED chip as described in claim 10, characterized in that, The refractive index of the protective layer is greater than that of the transparent conductive layer, but less than that of the second type semiconductor layer.

14. The method for manufacturing an LED chip as described in claim 10, characterized in that, It also includes forming a microsphere anti-reflective coating that at least covers the exposed surface of the transparent conductive layer; The transparent conductive layer is ITO; After fabricating the first and second electrodes, a passivation layer is also fabricated. The passivation layer is made of SiO2 material and covers the exposed surfaces of the epitaxial structure, the first electrode, the second electrode, and the microsphere anti-reflective coating, and has through holes for exposing the electrodes.

15. The method for manufacturing an LED chip as described in claim 14, characterized in that, The microsphere anti-reflective coating contains at least two types of microspheres with different diameters.

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