Network topology and routing optimization design method for chiplet chiplet interconnection

Abstract

The application relates to a network topology and routing optimization design method for Chiplet chiplet interconnection. The method comprises the following steps: determining input coding and output coding of data to be exchanged in a chiplet interface of a chiplet according to address information of the data to be exchanged; determining control codes of a plurality of switches of a chiplet interconnection network in the chiplet interface based on a preset output mutual exclusion pair relationship, the input coding and the output coding; and controlling the data to be exchanged to be interconnected between adjacent chiplets through the control codes of the switches. The method can reduce the interconnection cost between different chiplets.

Description

TECHNICAL FIELD

[0001] The application relates to the chip technology field, in particular to a network topology and routing optimization design method for Chiplet chiplet interconnection. BACKGROUND

[0002] With the slowing down of the cost reduction speed of transistors, the manufacturing yield challenge is also increasing, and the design and manufacturing cost of a single large-scale multi-core chip is increasing.

[0003] In the related art, in order to reduce the cost of a single large-scale multi-core chip without affecting its function, a large-scale single multi-core chip can be split into small chiplets, and the reuse of the chiplets can be realized through packaging integration technology. However, the interconnection between the split chiplets needs to be realized through a chiplet interface, which increases the chiplet interface area overhead compared with a single large chip, resulting in an increase in the interconnection cost between different chiplets.

[0004] Therefore, how to reduce the interconnection cost between different chiplets has become a technical problem to be solved. SUMMARY

[0005] Therefore, it is necessary to provide a network topology and routing optimization design method for Chiplet chiplet interconnection, which can reduce the interconnection cost between different chiplets.

[0006] In a first aspect, the application provides a network topology and routing optimization design method for Chiplet chiplet interconnection, which is applied to a chiplet and includes the following steps:

[0007] According to the address information of the data to be exchanged, the input code and the output code of the data to be exchanged in the chiplet interface of the chiplet are determined;

[0008] Based on the preset output mutual exclusion pair relationship, the input code and the output code, the control code of the plurality of switches of the chiplet interconnection network in the chiplet interface is determined;

[0009] The control code of each switch is used to control the interconnection of the data to be exchanged between adjacent chiplets.

[0010] In one of the embodiments, the chiplet interconnection network includes an input switch group, an output switch group and a plurality of sub-network topologies, and the plurality of sub-network topologies are connected to the input switch group and the output switch group through inter-layer connections.

[0011] Based on the preset output mutual exclusion pair relationship, the input code and the output code, the control code of the plurality of switches of the chiplet interconnection network in the chiplet interface is determined, including:

[0012] Based on the preset output mutually exclusive pair relationship, input encoding and output encoding, a first control code of the plurality of switches in the input switch group and the output switch group is obtained;

[0013] Based on the first control code and the inter-level connection line, a second control code of the plurality of switches in the plurality of sub-network topologies is determined.

[0014] In one embodiment, based on the preset output mutually exclusive pair relationship, input encoding and output encoding, a first control code of the plurality of switches in the input switch group and the output switch group is obtained, including:

[0015] Based on the output mutually exclusive pair relationship, input encoding and output encoding, a target connection mode inside all switches in the output switch group and the input switch group is obtained.

[0016] Based on the target connection mode, a first control code of the plurality of switches in the output switch group and the input switch group is determined.

[0017] In one embodiment, the two input encodings of each input switch in the input switch group are an input mutually exclusive pair;

[0018] Based on the output mutually exclusive pair relationship, input encoding and output encoding, a target connection mode inside all switches in the output switch group and the input switch group is obtained, including:

[0019] Based on the output mutually exclusive pair relationship, the number of output mutually exclusive pairs of any one group of input encodings in the reference set of points to be mutually exclusive is obtained.

[0020] Based on the number of output mutually exclusive pairs, a target connection mode inside all switches in the output switch group and the input switch group is determined.

[0021] In one embodiment, based on the number of output mutually exclusive pairs, a target connection mode inside all switches in the output switch group and the input switch group is determined, including:

[0022] Based on the number of output mutually exclusive pairs of any one group of input encodings in the reference set of points to be mutually exclusive, an initial connection mode inside the switch corresponding to the input encoding is adjusted once to obtain a candidate connection mode;

[0023] Based on the number of output mutually exclusive pairs, a second adjustment is made to each candidate connection mode to obtain a target connection mode inside all switches.

[0024] In one of the embodiments, the chiplet interface of the chiplet comprises a chiplet interconnection network, a network topology of the chiplet interconnection network is composed of an input switch group, an output switch group and a plurality of sub-network topologies, any one of the sub-network topologies comprises an input sub-switch group and an output sub-switch group, the input sub-switch group comprises a plurality of groups of adjacent input switches, and an intra-layer channel is arranged between each group of adjacent input switches; the intra-layer channel is used for data interaction of the adjacent input switches.

[0025] In one of the embodiments, each of the adjacent input switches comprises an inter-layer interface and an intra-layer interface, the inter-layer interface is connected with a plurality of switches of the output sub-switch group; and the intra-layer interface is used for connection with another switch of the adjacent input switches.

[0026] In a second aspect, the present application further provides a network topology and routing optimization design device for Chiplet chiplet interconnection, comprising:

[0027] The encoding determination module is configured to determine input encoding and output encoding of the to-be-exchanged data in the chiplet interface of the chiplet according to address information of the to-be-exchanged data;

[0028] The control code determination module is configured to determine control codes of a plurality of switches of the chiplet interconnection network in the chiplet interface based on the preset output mutual exclusion relationship, the input encoding and the output encoding;

[0029] The control module is configured to control the to-be-exchanged data to be interconnected between adjacent chiplets through the control codes of the switches.

[0030] In a third aspect, the present application further provides a computer device, comprising a memory and a processor, the memory stores a computer program, and the processor implements the content of any one of the embodiments of the network topology and routing optimization design method for Chiplet chiplet interconnection in the first aspect when executing the computer program.

[0031] In a fourth aspect, the present application further provides a computer readable storage medium, which stores a computer program, and the computer program implements the content of any one of the embodiments of the network topology and routing optimization design method for Chiplet chiplet interconnection in the first aspect when executed by a processor.

[0032] In a fifth aspect, the present application further provides a computer program product, comprising a computer program, and the computer program implements the content of any one of the embodiments of the network topology and routing optimization design method for Chiplet chiplet interconnection in the first aspect when executed by a processor.

[0033] The network topology and the routing optimization design method for Chiplet chiplet interconnection described above, according to the address information of the data to be exchanged, determine the input code and the output code of the data to be exchanged in the chiplet interface of the chiplet; based on the preset output mutually exclusive pair relationship, the input code and the output code, the control code of the plurality of switches of the chiplet interconnection network in the chiplet interface is determined; the control code of each switch is used to control the interconnection of the data to be exchanged between adjacent chiplets. In the process of determining the control code, the specific content of the input data and the output data in the chiplet interface is not considered, the input number corresponding to the input data and the output number corresponding to the output data are analyzed based on the preset output mutually exclusive pair relationship, the calculation amount in the analysis process can be greatly reduced, then the area of the chiplet interface is also correspondingly reduced, thereby reducing the interconnection cost between different chiplets. BRIEF DESCRIPTION OF DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related art, the drawings needed to be used in the description of the embodiments of the present application or the related art will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other related drawings can also be obtained without creative labor.

[0035] Figure 1 An application environment diagram of the network topology and the routing optimization design method for Chiplet chiplet interconnection in an embodiment;

[0036] Figure 2 A flowchart of the network topology and the routing optimization design method for Chiplet chiplet interconnection in an embodiment;

[0037] Figure 3 An input code diagram of an input switch in an embodiment;

[0038] Figure 4 An output mutually exclusive pair relationship diagram in an embodiment;

[0039] Figure 5 A flowchart of the network topology and the routing optimization design method for Chiplet chiplet interconnection in an embodiment;

[0040] Figure 6 A flowchart of the network topology and the routing optimization design method for Chiplet chiplet interconnection in an embodiment;

[0041] Figure 7 A flowchart of the network topology and the routing optimization design method for Chiplet chiplet interconnection in an embodiment;

[0042] Figure 8 Flowchart of network topology and routing optimization design method for Chiplet interconnect in an embodiment;

[0043] Figure 9 Flowchart of network topology and routing optimization design method for Chiplet interconnect in an embodiment;

[0044] Figure 10 Schematic diagram of 8x8 BENES network architecture in an embodiment;

[0045] Figure 11 Data routing schematic diagram of sub-network topology with blocking in an embodiment;

[0046] Figure 12 Data routing schematic diagram of sub-network topology with blocking in an embodiment;

[0047] Figure 13 Data routing schematic diagram of sub-network topology without blocking in an embodiment;

[0048] Figure 14 Data routing schematic diagram of sub-network topology without blocking in an embodiment;

[0049] Figure 15 Circuit schematic diagram of conventional 4x4 BENES network in an embodiment;

[0050] Figure 16 Circuit schematic diagram of 4x4 Butterfly network in an embodiment;

[0051] Figure 17 Output condition schematic diagram of 4x4 Butterfly network in an embodiment;

[0052] Figure 18 Schematic diagram of improved 8x8 BENES network architecture in an embodiment;

[0053] Figure 19 Structural block diagram of network topology and routing optimization design device for Chiplet interconnect in an embodiment. DETAILED DESCRIPTION

[0054] In order to make the purpose, technical scheme and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0055] Before the technical scheme of the present application is described in detail, the background art of the present application will be briefly described.

[0056] To provide high computing throughput and on-chip memory, the area of Artificial Intelligence (AI) oriented Deep Neural Networks (DNN) multi-core processors is increasing. However, in the face of the end of Moore's Law, the cost reduction speed of transistors slows down, and the challenge of manufacturing yield is also increasing. Therefore, the design and manufacturing cost of a single large-scale multi-core chip has increased dramatically.

[0057] Compared with a single large chip, Chiplet architecture technology can split a single large-scale multi-core chip into small Chiplets, and realize the reuse of Chiplets through advanced packaging integration technology, which has the advantages of shorter design and development cycle, lower manufacturing cost, and easier customization.

[0058] However, the interconnection between the split Chiplets needs to be realized through Chiplet interfaces, which increases the Chiplet interface area overhead compared with a single large chip, resulting in an increase in the interconnection cost between different Chiplets. The on-chip interconnection network of the Chiplet interface cannot reduce the interconnection cost between different Chiplets. For example, the on-chip interconnection network can be a wireless mesh network (MESH network) and a non-blocking network (BENES network) in a multi-level interconnection network.

[0059] Taking the BENES network as an example, in the related art, the algorithm for the BENES network is mainly optimized by using an iterative method to reduce the Chiplet interface area. Specifically, the algorithm first sets that in the same 2x2 switch, two inputs are mutually exclusive, two outputs are mutually exclusive, and the inputs or outputs of any different switches are not mutually exclusive. Starting from the leftmost and rightmost two levels of switches, (1) input the bit sequence to be replaced 1, 2, 3,..., N-1, N; output . Define the permutation transformation relationship. According to the setting, obtain (2) input mutually exclusive pairs: ; (3) output mutually exclusive pairs: ; (4) construct two mutually exclusive point sets and, each of which contains elements, which satisfies the condition , The specific operation is: randomly select a P i from all P i . Select an element a from P i as an element in X, and ensure that a belongs to O j , and then find O j that satisfies the condition. Next, select another element b except a, and let b belong to P k . Please note that b cannot be selected as an element of X, but only from P kThe other element is selected as the element of X. Each P is in turn selected i ( ) is filtered, and the cycle is repeated to obtain the set X. The set Y is composed of elements not in X. (5) X and Y are used to determine the state of the two stages of 2x2 switches that are left-right symmetric, i.e., to determine whether they are cross or pass. For the left stage of 2x2 switches, the elements in X connect the upper output of the two outputs of the switch, and the elements in Y connect the lower output of the two outputs of the switch. For the right stage of switches, the elements in X connect the upper input of the two inputs of the switch, and the elements in Y connect the lower input of the two inputs of the switch, thereby determining the state of the left and right columns of switches. (6) Using the two columns of switches determined in step (5), the bits to be transposed are passed through the switches and sent to the inputs and outputs of the intermediate two stages of switches through the inter-stage links. This generates new pairs of mutual exclusion. Then steps (4) and (5) are repeatedly executed until the states of all switches are determined. In addition, the BENES network is a high-efficiency switching network topology, which is commonly used to build large-scale communication systems or computer networks. Its characteristics are compact structure and simple routing algorithm, and it has the characteristics of rearrangeable non-blocking. The BENES network is usually composed of multiple stages of switching networks, where each stage has a group of 2x2 switches, and each switch is responsible for data exchange between the input and output ports.

[0060] However, from the perspective of hardware implementation, the algorithm requires a large number of comparators to compare the addresses when searching for input and output mutual exclusion pairs, and the implementation process is complex, requiring a large number of data selectors to select and process the results after each comparison, resulting in large area and power consumption overhead. At the same time, the simplest 4x4 BENES network can be regarded as an intermediate stage switch of a larger-scale BENES network, but the traditional 4x4 BENES network has resource redundancy, thereby increasing the area and power consumption overhead. That is, the existing routing algorithm of the BENES network is not suitable for hardware programming design and implementation, and the logic has large area and power consumption overhead for designing special hardware modules, which is not conducive to optimizing the chiplet interface overhead required for interconnecting Chiplets. Secondly, the traditional 4x4 BENES network currently adopted has resource redundancy in hardware implementation, and has certain optimization space.

[0061] Therefore, the application provides a network topology and routing optimization design method for Chiplet chiplet interconnection, which optimizes from the routing algorithm of the BENES network and the network topology of the chiplet interconnection network, and can reduce the interconnection cost between different chiplets. Of course, the technical solutions provided in the embodiments of the application are not limited to solving only the above problems, but also have other technical effects. For details, please refer to the following embodiment description. Next, the technical solutions of the application will be described in detail.

[0062] The network topology and routing optimization design method for Chiplet chiplet interconnection provided in the embodiments of the application can be applied to an application environment as shown in Figure 1 The chiplet in the application environment can be a computer device, which can be a server, a personal computer, a notebook computer, a smart phone, a tablet computer, a smart mobile phone, etc. The computer device can include a processor, a memory and a network interface connected by a system bus or connected by a wireless manner. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device can include a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store data in the chiplet interconnection process. The network interface of the computer device is used to communicate with an external terminal through network connection. The computer program is executed by the processor to implement a network topology and routing optimization design method for Chiplet chiplet interconnection.

[0063] In an exemplary embodiment, as shown in Figure 2 A network topology and routing optimization design method for Chiplet chiplet interconnection is provided. Taking the chiplet in Figure 1 as an example, the method includes the following steps 201 to 203. Wherein:

[0064] S201, according to the address information of the data to be exchanged, determining the input code and the output code of the data to be exchanged in the chiplet interface of the chiplet.

[0065] The data to be exchanged refers to the data that needs to be interconnected between adjacent chiplets. Each chiplet has a chiplet interface, which is connected to the interface of its adjacent chiplet through wired or wireless means to interconnect with its adjacent chiplet.

[0066] When the to-be-exchanged data needs to be interconnected between the cores, the address information carried by the to-be-exchanged data includes the cores involved in the exchange process of the to-be-exchanged data and the positions of the core interconnection network in the core interface of each core. The address information of the to-be-exchanged data can be manually configured by the user according to the data routing requirements. Alternatively, the address information of the to-be-exchanged data can also be obtained through automatic allocation.

[0067] In the embodiment of the present application, when the core obtains the address information of the to-be-exchanged data, the core can analyze the address information to determine the output encoding mode of the to-be-exchanged data. And based on the output encoding mode, the output encoding of the to-be-exchanged data in the core interface of the core is determined. It should be noted that the input encoding in the core interface is a predetermined encoding. For example, for an 8x8 core interconnection network, the core interconnection network includes 4 input switches, and each input switch includes two input encodings. Therefore, the encoding of the input switch of the core interconnection network can be 0, 1, 2, 3, 4, 5, 6 and 7.

[0068] It should be noted that for any input switch on the core interconnection network in the core interface, the two input encodings on the input switch are an input exclusive pair. Figure 3 The schematic diagram for representing the input encoding of the input switch, X and Y are two exclusive point sets, the diagram includes four input switches, each input switch includes an X value and a Y value, each dashed box in the diagram represents the input encoding of an input switch, and the four switches are G0, G1, G2 and G3. The input encoding of the first switch G0 is 0 and 1, the input encoding of the second switch G1 is 2 and 3, the input encoding of the third switch G2 is 4 and 5, and the input encoding of the fourth switch G4 is 6 and 7.

[0069] S202, determining the control code of the multiple switches of the core interconnection network in the core interface based on the preset output exclusive pair relationship, the input encoding and the output encoding.

[0070] The preset output exclusive pair relationship can be set in advance based on the user's requirements. Figure 4 The schematic diagram for representing the output exclusive pair relationship, as can be seen from the diagram, 0 and 4 are an output exclusive pair, 1 and 2 are an output exclusive pair, 3 and 6 are an output exclusive pair, and 5 and 7 are an output exclusive pair.

[0071] The above control code refers to the identification code of whether the internal connection relationship of the switch needs to be adjusted. For example, if the internal connection relationship of the switch does not need to be adjusted, the control code of the switch is 0; if the internal connection relationship of the switch needs to be adjusted, the control code of the switch is 1. The internal connection relationship of the switch includes straight-through connection and cross connection.

[0072] In the embodiment of the present application, the corelet can obtain the number of output mutual exclusion pairs of any one group of input codes in the reference set of points to be mutually excluded according to the output mutual exclusion pair relationship. And the connection relationship inside the plurality of switches of the corelet interconnection network in the corelet interface is judged whether it needs to be adjusted by using the number of each output mutual exclusion pair. Based on the judgment result, the control code of the plurality of switches is determined. Or, the corelet can also input the preset output mutual exclusion pair relationship, input code and output code into the preset control code determination model, and the control code determination model analyzes the input code and the output code by using the output mutual exclusion pair relationship, and outputs the control code of the plurality of switches of the corelet interconnection network in the corelet interface. The specific way of determining the control code of the plurality of switches of the corelet interconnection network in the corelet interface based on the preset output mutual exclusion pair relationship, input code and output code is not limited in the embodiment of the present application.

[0073] S203, the control code of each switch is used to control the interconnection of the data to be exchanged between adjacent corelets.

[0074] In the embodiment of the present application, after the control code of the plurality of switches of the corelet interconnection network in the corelet interface is determined, the corelet can determine the data exchange path of the data to be exchanged in the corelet interconnection network based on the plurality of control codes. Through the data exchange path, the transmission of the data to be exchanged between adjacent corelets is realized, so as to realize the corelet interconnection.

[0075] In the above network topology and routing optimization design method for Chiplet corelet interconnection, the input code and the output code of the data to be exchanged in the corelet interface of the corelet are determined according to the address information of the data to be exchanged; the control code of the plurality of switches of the corelet interconnection network in the corelet interface is determined based on the preset output mutual exclusion pair relationship, input code and output code; and the control code of each switch is used to control the interconnection of the data to be exchanged between adjacent corelets. In the process of determining the control code, the specific content of the input data and the output data in the corelet interface is not considered, the input number corresponding to the input data and the output number corresponding to the output data are analyzed based on the preset output mutual exclusion pair relationship, which can greatly reduce the calculation amount in the analysis process, reduce the complexity of the hardware resources, and accordingly reduce the area of the corelet interface, thereby reducing the interconnection cost between different corelets.

[0076] The corelet interconnection network on the corelet interface includes an input switch group, an output switch group and a plurality of sub-network topologies, and the plurality of sub-network topologies are connected with the input switch group and the output switch group through inter-layer connection lines. In one embodiment, as shown in Figure 5 The specific content of determining the control code of the plurality of switches of the corelet interconnection network in the corelet interface based on the preset output mutual exclusion pair relationship, input code and output code includes:

[0077] S301, based on the preset output mutual exclusion pair relationship, input encoding and output encoding, obtains the first control code of multiple switches in the input switch group and the output switch group.

[0078] In this context, the input switch group refers to the outermost switch group at the input layer of the core-core interconnect network, and the output switch group refers to the outermost switch group at the output layer. In other words, both the input and output switch groups are located at the outermost layer of the core-core interconnect network. For an 8×8 core-core interconnect network, the core-core interconnect network includes an input switch group, an output switch group, and two 4×4 sub-network topologies, with each input and output switch group consisting of four switches.

[0079] In this embodiment, the chip can analyze the input and output codes using a preset output mutual exclusion pair relationship to determine whether the internal connection relationship of multiple switches in the input and output switch groups needs to be adjusted. Based on the determination result, the first control code of the multiple switches is determined.

[0080] S302, based on the first control code and the inter-level connections, determine the second control code of multiple switches in multiple sub-network topologies.

[0081] In this embodiment, after obtaining the first control codes of multiple switches in the outermost input switch group and output switch group, the core can determine the input and output codes of the outermost layer of the sub-network topology based on the inter-layer connections. Then, based on the input and output codes and output mutual exclusion pairs of the outermost layer of the sub-network topology, the control codes of multiple switches in the outermost input and output switch groups of the sub-network topology are determined. If the sub-network topology is a 4×4 network topology, the control codes of multiple switches in the input and output switch groups are used as the second control codes of multiple switches in the sub-network topology.

[0082] In the aforementioned network topology and routing optimization design method for Chiplet interconnects, the first control codes of multiple switches in the input and output switch groups are obtained based on preset output mutual exclusion pairs, input codes, and output codes. Then, based on the first control codes and inter-layer connections, the second control codes of multiple switches in multiple sub-network topologies are determined. This method analyzes the input and output codes through output mutual exclusion pairs, starting from the outer layer of the Chiplet interconnect network and progressively obtaining the control codes of multiple switches in the Chiplet interconnect network.

[0083] The following section describes the specific process of obtaining the first control code, such as... Figure 6As shown, the specific steps for obtaining the first control code of multiple switches in the input switch group and output switch group based on the preset output mutual exclusion pair relationship, input encoding, and output encoding include the following:

[0084] S401, based on the output mutual exclusion pair relationship, input encoding and output encoding, obtains the target connection mode inside all switches in the output switch group and the input switch group.

[0085] For any given switch, the internal connection methods include cut-through connections and cross-connects. The target connection method refers to the interaction path of the data to be exchanged within the core interconnect network during data exchange.

[0086] In this embodiment, any set of input codes is an input mutual exclusion pair. Therefore, for any set of input codes, the chip can obtain the number of output mutual exclusion pairs of that set of input codes in the reference set of points to be mutually excluded, based on a preset output mutual exclusion pair relationship. And based on the number of output mutual exclusion pairs, the first control codes of the input switch and output switch corresponding to that set of input codes are determined. For other input codes, the first control codes of the input switch and output switch corresponding to other sets of input codes can also be obtained in the above manner.

[0087] S402, based on the target connection method, determines the first control code of multiple switches in the output switch group and the input switch group.

[0088] In this embodiment, a mapping relationship exists between the connection methods and control codes within the switches. After obtaining the connection methods of multiple input and output switches, for any given switch, the core can analyze the target connection method based on the mapping relationship to determine the corresponding control code. The control codes corresponding to the target connection methods of all switches are then used as the first control code.

[0089] In the aforementioned network topology and routing optimization design method for Chiplet interconnects, the target connection method within all switches in the output and input switch groups is obtained based on output mutual exclusion pairs, input codes, and output codes. Based on the target connection method, the first control codes of multiple switches in the output and input switch groups are determined. This method, through output mutual exclusion pairs, can accurately analyze input and output codes to determine the target connection method within all switches in the output and input switch groups. Then, based on the target connection method of all switches, it can accurately obtain the first control codes of multiple switches.

[0090] Assuming that the two input codes of each input switch in the input switch group form a mutually exclusive pair, then in one embodiment, as follows:Figure 7 As shown, the specific steps for obtaining the target connection method within all switches in the input and output switch groups based on output mutual exclusion pairs, input encoding, and output encoding include the following:

[0091] S501, based on the output mutual exclusion pair relationship, obtains the number of output mutual exclusion pairs of any set of input codes in the reference set of points to be mutually exclusive.

[0092] Continue to refer to Figure 4 The reference set of points to be mutually exclusive refers to Figure 4 The set of mutually exclusive points X in the reference set of points to be mutually exclusive includes 0, 2, 4 and 6.

[0093] In this embodiment, for any set of input codes, the chip can obtain the output mutex codes corresponding to the two input codes respectively. For example, when the input code is 0, the corresponding output mutex code is 4; when the input code is 1, the corresponding output mutex code is 2. It then determines whether each of the two output mutex codes is in the reference set of points to be mutually exclusive. Based on the determination result, it determines the number of output mutex pairs of this set of input codes in the reference set of points to be mutually exclusive. For example, by determining whether 0 and 4, and 1 and 2 are in the reference set of points to be mutually exclusive, it can be determined that 0 and 4 are in the reference set of points to be mutually exclusive, while 1 and 2 are not. Therefore, the number of output mutex pairs of this set of input codes in the reference set of points to be mutually exclusive is 1.

[0094] S502 determines the target connection method within all switches in the input switch group and the output switch group based on the number of output mutual exclusion pairs.

[0095] In this embodiment of the application, after obtaining the number of output mutex pairs corresponding to any switch, the chip can compare the number of output mutex pairs with a preset threshold. If the number of output mutex pairs is greater than or equal to the preset threshold, it is determined that the connection method inside the switch needs to be adjusted, and the adjusted connection method is taken as the target connection method inside the switch. If the number of output mutex pairs is less than the preset threshold, it is determined that the connection method inside the switch does not need to be adjusted, and the default connection method inside the switch is directly taken as the target connection method.

[0096] In the aforementioned network topology and routing optimization design method for Chiplet interconnects, the number of output mutual exclusion pairs for any set of input codes in the reference set of points to be mutually exclusive is obtained based on the output mutual exclusion pair relationship. Based on the number of output mutual exclusion pairs, the target connection method within all switches in the input and output switch groups is determined. This method, based on the output mutual exclusion pair relationship, can accurately obtain the number of output mutual exclusion pairs for each input code in the reference set of points to be mutually exclusive, thus enabling the accurate determination of the target connection method within all switches in the input and output switch groups based on this number of output mutual exclusion pairs.

[0097] The following example illustrates the specific details of determining the target connection method within all switches in the input and output switch groups based on the number of output mutual exclusion pairs. Figure 8 As shown, the specific content includes:

[0098] S601, based on the number of output mutual exclusion pairs of any set of input codes in the reference set of points to be mutually exclusive, adjust the initial connection mode inside the switch corresponding to the input code once to obtain the candidate connection mode.

[0099] In this embodiment, after obtaining the number of output mutex pairs in the reference set of points to be mutually exclusive for any set of input codes, the core can compare the number of output mutex pairs with a preset threshold, and based on the comparison result, determine whether the initial connection method inside the switch needs to be adjusted. If it is determined that adjustment is needed, the initial connection method inside the switch is adjusted to obtain a candidate connection method. For example, when the initial connection method is a pass-through connection, the candidate connection method is a cross-connection; when the initial connection method is a cross-connection, the candidate connection method is a pass-through connection.

[0100] S602, based on the number of each output mutual exclusion pair, performs a secondary adjustment on each candidate connection method to obtain the target connection method within all switches.

[0101] In this embodiment, each adjustment is based on the number of output mutex pairs for each group of input codes, i.e., adjustment is performed from a local perspective. After all switches have undergone an initial adjustment, to further ensure the accuracy of the connection method, the connection method can be further adjusted from a global perspective. Specifically, the core can comprehensively consider the number of output mutex pairs and perform a secondary adjustment on the candidate connection methods of each switch from an overall perspective. Through this secondary adjustment, under the target connection method within all switches, the data to be exchanged will not be blocked when interacting in the core interconnection network.

[0102] In the aforementioned network topology and routing optimization design method for Chiplet interconnects, the initial connection method within the switch corresponding to any input code is adjusted once based on the number of output mutual exclusion pairs in the reference set of points to be mutually exclusive, resulting in candidate connection methods. Then, based on the number of each output mutual exclusion pair, each candidate connection method is adjusted a second time to obtain the target connection method within all switches. This method adjusts the connection method from a local perspective based on the number of output mutual exclusion pairs for each set of input codes, and then further adjusts it from a global perspective using the number of each output mutual exclusion pair. That is, the adjustment process starts from both local and global perspectives, enabling a more comprehensive adjustment of the connection method and resulting in a more accurate target connection method within all switches. Simultaneously, the operation process for the reference set of points to be mutually exclusive only involves swapping the internal connection relationships of the switches, ensuring that there are no input mutual exclusion pairs in the two sets of mutually exclusive points, thus simplifying the calculation logic and reducing the overhead of the chip interface.

[0103] In one specific embodiment, such as Figure 9 As shown, the network topology and routing optimization design method for Chiplet interconnects includes the following steps:

[0104] S701 determines the input and output codes of the data to be exchanged in the chip interface based on the address information of the data to be exchanged.

[0105] S702, based on the output mutual exclusion pair relationship, obtain the number of output mutual exclusion pairs of any set of input codes in the reference set of points to be mutually exclusive;

[0106] S703, based on the number of output mutual exclusion pairs of any set of input codes in the reference set of points to be mutually exclusive, adjusts the initial connection mode inside the switch corresponding to the input code once to obtain the candidate connection mode;

[0107] S704, based on the number of each output mutual exclusion pair, performs a secondary adjustment on each candidate connection method to obtain the target connection method inside all switches;

[0108] S705, based on the target connection method, determines the first control code of multiple switches in the output switch group and the input switch group;

[0109] S706, based on the first control code and the inter-level connections, determines the second control code of multiple switches in multiple sub-network topologies;

[0110] The S707 controls the interconnection of data to be exchanged between adjacent cores through the control codes of each switch.

[0111] Next, from an overall perspective, the specific steps of the control code determination process described above will be introduced. Input mutexes are initialized to two mutex point sets, X and Y. Elements in each input mutex pair are traversed sequentially, and it is determined whether the output mutex element corresponding to the current element in the mutex pair is located in the mutex point set X. Based on the determination result, a 4-bit mutex flag MUTEX is obtained. Each bit in MUTEX corresponds to the element in each of the four input mutex pairs located in the mutex point set, where 0 represents an even element and 1 represents an odd element. For the left-hand first-level switch, the elements in the mutex point set X are connected to the upper output of the switch's two output terminals; for the right-hand first-level switch, the elements in the mutex point set X are connected to the upper input of the switch's two input terminals. The control codes for the outermost two-level switches are generated using the MUTEX mutex flag, without needing to consider the mutex point set. Then, using the generated control codes and inter-level connections, the bits to be replaced are routed to the intermediate level to generate new mutual exclusion pairs and a new outermost layer. The previous steps are repeated to generate the control code for the current outermost switch, and so on, until the middle-level switch. This allows the acquisition of control codes for multiple switches in the core interconnect network. Based on these control codes, the interconnection of data to be exchanged between adjacent cores can be controlled.

[0112] Figure 10This diagram illustrates an 8x8 BENES network architecture. It's based on the traditional 8x8 BENES network architecture, without any modifications to the traditional architecture. The improvement focuses solely on the core-to-core interconnect algorithm to generate control codes for multiple switches within the BENES network. The routing calculation module (BENES_Route_Algo) in the diagram calculates the control codes for the 2x2 switches in the 8x8 BENES network based on the address information (ADDRESS_IN) of the data to be exchanged. A control code of 0 indicates a pass-through connection, while a control code of 1 indicates a cross-connection. The first mutex flag calculation module (Comp_MUTEX_FLAG_Algo_p0) and the second mutex flag calculation module (Comp_MUTEX_FLAG_Algo_p1) calculate mutex flags. These mutex flags are input into the first control code calculation module (Gen_Outermost_Ctrl_Bits_p0) and the second control code calculation module (Gen_Outermost_Ctrl_Bits_p1) to calculate the control codes for the outermost two-level switches and the next outermost two-level switches in the 8x8 BENES network. The middle 2x2 switch requires special handling, with its control code calculated by the third control code calculation module (Gen_Middle_Ctrl_Bits_p2). The input mutex pair determination module (New_Output_Address_L1_p1) and the output mutex pair determination module (New_Output_Address_L2_p2) generate new input and output mutex pairs based on the current state of the outermost switch and the inter-level connections; these represent the address information for the new data to be exchanged.

[0113] The above embodiments all describe the algorithm optimization process for the chip interconnection process. Based on the algorithm optimization, the topology of the chip interconnection network at the chip interface can be improved to further reduce the area of ​​the chip interface and lower the interconnection cost between different chips. In one embodiment, the specific content of the topology improvement process of the chip interconnection network includes:

[0114] The core interface of the core includes the core interconnection network. The network topology of the core interconnection network consists of input switch groups, output switch groups, and multiple sub-network topologies. Any sub-network topology includes input sub-switch groups and output sub-switch groups. The input sub-switch groups include multiple adjacent input switches, and intra-layer channels are set between adjacent input switches. Intra-layer channels are used for data interaction between adjacent input switches.

[0115] Taking a dynamic multi-stage blocking network (Butterfly network) with two sub-network topologies of 4×4 in a chip interconnect network as an example, Figure 11 and Figure 12This diagram illustrates data routing in a congested subnetwork topology. The thick lines represent data transmission paths, and the black dots indicate port congestion on a switch. In other words, two inputs from the same switch in the left-hand level need to be switched to two outputs from the same switch in the right-hand level.

[0116] Figure 13 and Figure 14 This diagram illustrates data routing in a non-blocking subnetwork topology. By establishing an intra-layer channel between the two input switches in the subnetwork topology, the number of data paths between the input and output switches is increased, thus avoiding congestion. Compared to... Figure 11 and Figure 12 In this regard, the chip interconnect network with added intra-layer channels is non-blocking, just like the traditional non-blocking 4×4 BENES network. However, it reduces two 2-to-1 data selectors and one bit of control code, thus significantly reducing the required hardware resources and control logic. This improved 4x4 Butterfly network can serve as an intermediate stage in an 8x8 BENES network, reducing both the network's topology area and the hardware resource overhead of the control code generation logic.

[0117] Figure 15 A circuit diagram showing a traditional 4×4 BENES network. Figure 16 This diagram illustrates a 4×4 Butterfly network. In the diagram, 0.0 and 0.1 represent the switch numbers closest to the input, and 1.0 and 1.1 represent the switch numbers closest to the output. Figure 17 The diagram illustrates the output of a 4×4 Butterfly network. The first and second output scenarios corresponding to the subgraphs in the upper left and upper right corners can be directly fixed based on the first 3 bits of the control code from the original input. The output scenario corresponding to the subgraph in the lower left corner is consistent with that of a traditional blocking 4x4 Butterfly network. Based on this characteristic, the calculation logic of the control code of this 4x4 Butterfly network can be optimized separately.

[0118] Specifically, in one embodiment, each input switch in the adjacent input switches includes an inter-layer interface and an intra-layer interface. The inter-layer interface is connected to multiple switches in the output sub-switch group; the intra-layer interface is used to connect to another switch in the adjacent input switches.

[0119] Continue to refer to Figure 13 and Figure 14 As shown in the diagram, each of the adjacent input switches includes four interfaces. Two of these interfaces are inter-layer interfaces, which connect to the two output switches. The other two interfaces are intra-layer interfaces, used for communication between the two input switches.

[0120] In the aforementioned network topology and routing optimization design method for Chiplet interconnects, the chip interface includes the chip interconnect network. The network topology of the chip interconnect network consists of input switch groups, output switch groups, and multiple sub-network topologies. Each sub-network topology includes input sub-switch groups and output sub-switch groups. Each input sub-switch group includes multiple adjacent input switches, and intra-layer channels are established between adjacent input switches for data exchange. Each adjacent input switch includes an inter-layer interface and an intra-layer interface. The inter-layer interface connects to multiple switches in the output sub-switch group; the intra-layer interface connects to another switch in the adjacent input switch group. By adding intra-layer interfaces to the input switches in the sub-network topology, the number of switches in the sub-network topology can be reduced. Simultaneously, this process also reduces the number of control codes. Based on this, the control code generation logic is simplified for the improved sub-network topology, thereby reducing the overhead of the chip interface area and lowering the cost of chip interconnects.

[0121] Figure 18 This diagram illustrates the improved 8x8 BENES network architecture. As shown, the 8x8 BENES network consists of two non-blocking 4x4 Butterfly networks, input switch groups, and output switch groups. The change in the topology of the non-blocking 4x4 Butterfly network also leads to optimization of the control code generation logic. For the 4x4 Butterfly network, it is only necessary to determine whether the current output situation corresponds to a blocking situation in a 4x4 Butterfly network based on the output addresses corresponding to the two inputs on any input switch, and directly determine the control codes for some switches. The control codes for the remaining switches only need to be generated according to the addressing characteristics of the original blocking Butterfly network.

[0122] In the specific design process, the code corresponding to the chip-particle interaction method was written using appropriate software. Synthesizing under 40nm process technology, it was found that the area overhead of the 8x8 BENES network after optimizing only the chip-particle interaction method was 78.30% of that before optimization, and the power consumption was 97.32% of that before optimization. This indicates that the chip-particle interaction method mentioned in this application can reduce the hardware resource overhead of the switch control code generation logic from an algorithmic perspective. Combining the chip-particle interaction method and network topology, the area overhead of the 8x8 BENES network after optimization was 65.94% of that before optimization, and the power consumption was 93.78% of that before optimization. Therefore, optimizing the network topology also effectively reduced the hardware resource overhead of the 8x8 BENES network. It is evident that by optimizing the chip-particle interaction method in terms of both algorithm and network topology, the area of ​​the chip-particle interface can be significantly reduced, thereby reducing the interconnection cost between different chips.

[0123] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0124] Based on the same inventive concept, this application also provides a chiplet-oriented network topology and routing optimization design apparatus for implementing the above-described chiplet-oriented network topology and routing optimization design method. The solution provided by this apparatus is similar to the implementation scheme described in the above-described method. Therefore, the specific limitations of one or more chiplet-oriented network topology and routing optimization design apparatus embodiments provided below can be found in the limitations of the chiplet-oriented network topology and routing optimization design method described above, and will not be repeated here.

[0125] In one exemplary embodiment, such as Figure 19 As shown, a network topology and routing optimization design device for Chiplet interconnect is provided, including: an encoding determination module 11, a control code determination module 12, and a control module 13, wherein:

[0126] The encoding determination module 11 is used to determine the input encoding and output encoding of the data to be exchanged in the core interface of the core based on the address information of the data to be exchanged.

[0127] The control code determination module 12 is used to determine the control codes of multiple switches in the core interconnection network in the core interface based on the preset output mutual exclusion pair relationship, input encoding and output encoding.

[0128] The control module 13 is used to control the interconnection of data to be exchanged between adjacent cores through the control codes of each switch.

[0129] In one embodiment, the control code determination module includes: an acquisition unit and a control code determination unit, wherein:

[0130] The acquisition unit is used to acquire the first control code of multiple switches in the input switch group and the output switch group based on the preset output mutual exclusion pair relationship, input code and output code;

[0131] The control code determination unit is used to determine the second control code of multiple switches in multiple sub-network topologies based on the first control code and the inter-level connections.

[0132] In one embodiment, the acquisition unit is further configured to acquire the target connection method within all switches in the output switch group and the input switch group based on the output mutual exclusion pair relationship, the input encoding, and the output encoding; and determine the first control code of multiple switches in the output switch group and the input switch group based on the target connection method.

[0133] In one embodiment, the acquisition unit is further configured to acquire the number of output mutual exclusion pairs of any set of input codes in the reference set of points to be mutually exclusive based on the output mutual exclusion pair relationship; and determine the target connection method within all switches in the input switch group and the output switch group based on the number of output mutual exclusion pairs.

[0134] In one embodiment, the acquisition unit is further configured to adjust the initial connection method inside the switch corresponding to the input code once based on the number of output mutual exclusion pairs in the reference mutual exclusion point set of any set of input codes, to obtain candidate connection methods; and adjust each candidate connection method a second time based on the number of each output mutual exclusion pair, to obtain the target connection method inside all switches.

[0135] In one embodiment, the core interface of the core includes a core interconnection network. The network topology of the core interconnection network consists of an input switch group, an output switch group, and multiple sub-network topologies. Any sub-network topology includes an input sub-switch group and an output sub-switch group. The input sub-switch group includes multiple adjacent input switches, and an intra-layer channel is set between adjacent input switches. The intra-layer channel is used for data interaction between adjacent input switches.

[0136] In one embodiment, each input switch in an adjacent input switch includes an inter-layer interface and an intra-layer interface. The inter-layer interface is connected to multiple switches in the output sub-switch group; the intra-layer interface is used to connect to another switch in an adjacent input switch.

[0137] The modules in the aforementioned network topology and routing optimization design device for Chiplet interconnects can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the memory of a computer device as software, so that the processor can call and execute the corresponding operations of each module.

[0138] In one exemplary embodiment, a computer device is provided, including a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement any of the embodiments of the above-described network topology and routing optimization design method for Chiplet interconnects.

[0139] In one embodiment, a computer-readable storage medium is provided that stores a computer program thereon, which, when executed by a processor, implements the content of any embodiment of the network topology and routing optimization design method for Chiplet interconnects.

[0140] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the content of any embodiment of the network topology and routing optimization design method for Chiplet interconnects.

[0141] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0142] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, database, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0143] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0144] The above embodiments merely illustrate several implementation methods of this application, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of this application's patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A network topology and routing optimization design method for Chiplet interconnects, characterized in that, The method is applied to a core, and the method includes: Based on the address information of the data to be exchanged, determine the input encoding and output encoding of the data to be exchanged in the core interface of the core; Based on a preset output mutual exclusion pair relationship, the input code, and the output code, the control codes of multiple switches in the core interconnect network of the core interface are determined; this includes obtaining the number of output mutual exclusion pairs in a reference set of points to be mutually exclusive based on the output mutual exclusion pair relationship; determining whether the connection relationship within multiple switches in the core interconnect network of the core interface needs to be adjusted based on the number of each output mutual exclusion pair; and determining the control codes of multiple switches based on the determination result; the reference set of points to be mutually exclusive is a preset subset of numbers containing output codes; The control codes of each switch control the interconnection of the data to be exchanged between adjacent cores.

2. The method according to claim 1, characterized in that, The core interconnect network includes an outermost input switch group, an outermost output switch group, and multiple sub-network topologies. The multiple sub-network topologies are connected to the input switch group and the output switch group through inter-level connections. The method for determining the control codes of multiple switches in the chip interconnect network within the chip interface, based on preset output mutual exclusion pairs, the input encoding, and the output encoding, includes: Based on the preset output mutual exclusion pair relationship, the input code and the output code, the first control code of multiple switches in the input switch group and the output switch group is obtained; Based on the first control code and the inter-layer connections, the second control code of multiple switches in the multiple sub-network topologies is determined, including: after obtaining the first control codes of multiple switches in the outermost input switch group and output switch group, determining the input code and output code of the outermost layer of the sub-network topology based on the inter-layer connections; determining the control codes of multiple switches in the outermost input switch group and output switch group of the sub-network topology based on the input code and output code and the output mutual exclusion pair relationship of the outermost layer of the sub-network topology; and using the control codes of multiple switches in the input switch group and output switch group as the second control codes of multiple switches in the sub-network topology.

3. The method according to claim 2, characterized in that, The process of obtaining the first control code of multiple switches in the input switch group and the output switch group based on the preset output mutual exclusion pair relationship, the input code, and the output code includes: Based on the output mutual exclusion pair relationship, the input encoding, and the output encoding, the target connection method within all switches in the output switch group and the input switch group is obtained; the target connection method is a pass-through connection or a cross connection. Based on the target connection method, a first control code is determined for multiple switches in the output switch group and the input switch group. The first control code is set to 0 when the internal connection relationship of the switches does not need to be adjusted, and is set to 1 when the internal connection relationship of the switches needs to be adjusted.

4. The method according to claim 3, characterized in that, The two input codes of each input switch in the input switch group are an input mutual exclusion pair; The step of obtaining the target connection method within all switches in the input switch group and the output switch group based on the output mutual exclusion pair relationship, the input encoding, and the output encoding includes: Based on the output mutual exclusion pair relationship, obtain the number of output mutual exclusion pairs of any set of input codes in the reference set of points to be mutually exclusive; Based on the number of output mutual exclusion pairs, the target connection method within all switches in the input switch group and the output switch group is determined.

5. The method according to claim 4, characterized in that, The step of determining the target connection method within all switches in the input switch group and the output switch group based on the number of output mutual exclusion pairs includes: Based on the number of output mutex pairs in the reference set of points to be mutually exclusive for any set of input codes, the initial connection method inside the switch corresponding to the input code is adjusted once to obtain a candidate connection method; each adjustment is based on the number of output mutex pairs for each set of input codes. Based on the number of each output mutex pair, the candidate connection methods are adjusted a second time to obtain the target connection methods within all switches; the second adjustment is based on the number of output mutex pairs to adjust the candidate connection methods of each switch.

6. The method according to any one of claims 1-5, characterized in that, The core interface of the core includes a core interconnection network. The network topology of the core interconnection network consists of an input switch group, an output switch group, and multiple sub-network topologies. Any sub-network topology includes an input sub-switch group and an output sub-switch group. The input sub-switch group includes multiple groups of adjacent input switches. An intra-layer channel is set between each group of adjacent input switches. The intra-layer channel is used for data interaction between the adjacent input switches.

7. The method according to claim 6, characterized in that, Each of the adjacent input switches includes an inter-layer interface and an intra-layer interface. The inter-layer interface is connected to multiple switches in the output sub-switch group. The intra-layer interface is used to connect to another switch in the adjacent input switch group.

8. A network topology and routing optimization design device for Chiplet interconnects, characterized in that, The device includes: The encoding determination module is used to determine the input encoding and output encoding of the data to be exchanged in the core interface of the core based on the address information of the data to be exchanged; The control code determination module is used to determine the control codes of multiple switches in the core-core interconnect network of the core-core interface based on a preset output mutual exclusion pair relationship, the input code, and the output code; including obtaining the number of output mutual exclusion pairs of any set of input codes in a reference set of points to be mutually exclusive according to the output mutual exclusion pair relationship; determining whether the connection relationship within the multiple switches of the core-core interconnect network in the core-core interface needs to be adjusted according to the number of each output mutual exclusion pair; and determining the control codes of the multiple switches based on the determination result; wherein the reference set of points to be mutually exclusive is a preset subset of numbers containing the output codes; The control module is used to control the interconnection of the data to be exchanged between adjacent cores through the control codes of each of the switches.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 7.

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