Semiconductor structure and preparation method thereof

Abstract

A semiconductor structure and a method for fabricating the same, comprising: providing a substrate and forming a stacked structure on the substrate, the stacked structure comprising a first dielectric layer and a second dielectric layer stacked vertically; forming a through hole vertically extending through the stacked structure, the through hole comprising a first hole and a second hole, the through hole exposing a portion of the substrate surface, the bottom surface of the through hole being flush with or lower than the top surface of the substrate; forming a sidewall protection layer within the through hole; forming a bottom protection layer on the portion of the substrate surface exposed by the through hole; filling the through hole with an isolation layer; removing the isolation layer and a portion of the sidewall protection layer within the first hole, and forming a transistor structure within the first hole; removing the isolation layer and a portion of the sidewall protection layer within the second hole, and forming a capacitor structure within the second hole, the capacitor structure being electrically connected to the transistor structure. The above-described method for fabricating a semiconductor structure can improve the performance stability of the semiconductor structure.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] The development of dynamic random access memory (DRAM) pursues performance indicators such as high speed, high integration density, and low power consumption. As semiconductor device structures shrink in size, the technical barriers encountered by existing structures are becoming increasingly apparent. Therefore, developing more novel structures based on existing structures is an effective means to break through existing technical barriers.

[0003] The emergence of three-dimensional dynamic random access memory (3D DRAM), especially 3D DRAM including multilayer horizontal cells (MHC), which generally includes multiple transistors and multiple capacitors stacked on a substrate, meets the above needs.

[0004] However, in the process of manufacturing structures such as transistors and capacitors, the etching process is prone to cause substrate damage or the risk of impurity peeling, thereby affecting the device performance of structures such as transistors and capacitors and reducing the stability of dynamic memory. Summary of the Invention

[0005] According to a first aspect of an embodiment of the present disclosure, a method for preparing a semiconductor structure is provided, comprising: providing a substrate and forming a stacked structure on the substrate, the stacked structure comprising a first dielectric layer and a second dielectric layer stacked in a vertical direction; forming a through hole penetrating the stacked structure in a vertical direction, the through hole comprising a first hole and a second hole, the through hole exposing a portion of the surface of the substrate, the bottom surface of the through hole being flush with or lower than the top surface of the substrate; forming a sidewall protection layer inside the through hole; forming a bottom protection layer on the portion of the surface of the substrate exposed by the through hole; filling an isolation layer in the through hole; removing the isolation layer and a portion of the sidewall protection layer in the first hole, and forming a transistor structure in the first hole; removing the isolation layer and a portion of the sidewall protection layer in the second hole, and forming a capacitor structure in the second hole, the capacitor structure being electrically connected to the transistor structure.

[0006] In some embodiments, the bottom surface of the through hole is lower than the top surface of the substrate, and forming a bottom protective layer on the portion of the surface of the substrate exposed by the through hole includes: using a first epitaxial growth process to form a single crystal silicon layer on the portion of the surface of the substrate exposed by the through hole, and the top surface of the single crystal silicon layer is lower than the top surface of the substrate; using a second epitaxial growth process to form a silicon germanium layer on the single crystal silicon layer, and the thickness of the single crystal silicon layer is less than the thickness of the silicon germanium layer.

[0007] In some embodiments, a transistor structure is formed in the first hole, including: forming a channel layer on the sidewall of the first hole corresponding to the second dielectric layer; forming a gate dielectric layer covering the channel layer, the gate dielectric layer covering the top surface of the bottom protective layer at the bottom of the first hole; forming a gate structure filling the first hole, the projection of the channel layer in the vertical direction being a ring surrounding the gate structure.

[0008] In some embodiments, a capacitor structure is formed in the second hole, including: removing a portion of the second dielectric layer laterally along the second hole to form a capacitor groove; forming a lower electrode layer covering the inner wall of the capacitor groove; forming a capacitor dielectric layer covering the lower electrode layer, and the capacitor dielectric layer covers the bottom protective layer at the bottom of the second hole; and forming an upper electrode layer covering the capacitor dielectric layer and filling the second hole.

[0009] In some embodiments, the through hole includes a plurality of through hole groups arranged along the second direction, each through hole group includes a first hole and a second hole arranged along the first direction; the transistor structure in each first hole includes a plurality of transistor units spaced apart along the vertical direction; the capacitor structure in each second hole includes a plurality of capacitor units spaced apart along the vertical direction; the method further includes: forming a linear groove on one side of the through hole along the first direction; removing a portion of the second dielectric layer laterally along the linear groove to form a bit line groove; forming a bit line structure filling the bit line groove, the bit line structure extending along the second direction, and the plurality of bit line structures spaced apart along the vertical direction, and each bit line structure is electrically connected to the plurality of transistor units located on the same layer.

[0010] According to a second aspect of an embodiment of the present disclosure, a semiconductor structure is provided, comprising: a substrate and a stacked structure located on a surface of the substrate, the stacked structure comprising a first dielectric layer and a second dielectric layer stacked in a vertical direction; a through hole penetrating the stacked structure in a vertical direction, the through hole comprising a first hole and a second hole; a bottom protective layer located at the bottom of the through hole and a sidewall protective layer surrounding the bottom protective layer, the bottom protective layer being in contact with the substrate; a transistor structure located in the first hole; and a capacitor structure located in the second hole, the capacitor structure being electrically connected to the transistor structure.

[0011] In some embodiments, the through holes include a plurality of through hole groups arranged along the second direction, each through hole group includes a first hole and a second hole arranged along the first direction; the transistor structure in each first hole includes a plurality of transistor units spaced apart along the vertical direction; the capacitor structure in each second hole includes a plurality of capacitor units spaced apart along the vertical direction; the semiconductor structure also includes a bit line structure, the bit line structure extends along the second direction, and the plurality of bit line structures are spaced apart along the vertical direction, and each bit line structure is electrically connected to the plurality of transistor units located on the same layer.

[0012] In some embodiments, the transistor structure includes: a channel layer located on the sidewall of the first hole corresponding to the second dielectric layer; a gate dielectric layer covering the channel layer, the sidewall of the first hole corresponding to the second dielectric layer, and the top surface of the bottom protective layer; a gate structure extending in the vertical direction and filling the first hole, and the projection of the channel layer in the vertical direction is a ring surrounding the gate structure.

[0013] In some embodiments, the capacitor structure includes: a lower electrode layer, located on the side wall of the second hole corresponding to the second dielectric layer, and the projection of the lower electrode layer in the vertical direction is ring-shaped; a capacitor dielectric layer, the capacitor dielectric layer covers the bottom protective layer at the bottom of the second hole; and an upper electrode layer, covering the capacitor dielectric layer and filling the second hole.

[0014] In some embodiments, the bottom protective layer includes a single crystal silicon layer and a silicon germanium layer located on the single crystal silicon layer, the top surface of the single crystal silicon layer is lower than the top surface of the substrate, the top surface of the silicon germanium layer is lower than the top surface of the first dielectric layer located closest to the substrate, and the thickness of the single crystal silicon layer is less than the thickness of the silicon germanium layer.

[0015] In the embodiment of the present disclosure, a bottom protective layer and a side wall protective layer are provided at the bottom of the through hole, and the bottom protective layer and the side wall protective layer are utilized to protect the substrate, thereby avoiding damage to the substrate when removing the isolation layer, and reducing the possibility of leakage of the transistor structure and the capacitor structure, thereby improving the performance stability of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a flow chart showing a method for preparing a semiconductor structure according to an exemplary embodiment;

[0017] Figure 2-Figure 5 is a schematic diagram showing a process for preparing a semiconductor structure for forming a through hole according to an exemplary embodiment;

[0018] Figure 6-Figure 7 is a schematic diagram illustrating a semiconductor structure preparation process for forming a bottom protection layer and an isolation layer in a through hole according to an exemplary embodiment;

[0019] Figures 8-10 is a schematic diagram illustrating a semiconductor structure preparation process for forming a bottom protection layer and an isolation layer in a through hole according to another exemplary embodiment;

[0020] Figure 11-13 is a schematic diagram of a semiconductor structure preparation process for forming a bottom protection layer and an isolation layer in a through hole according to another exemplary embodiment;

[0021] Figures 14-21 The figure is a schematic diagram of a semiconductor structure preparation process for forming a transistor structure and a capacitor structure in a through hole according to an exemplary embodiment.

[0022] Description of reference numerals:

[0023] 10-semiconductor structure; 110-substrate; 110R-substrate recess; 120-stacked structure; 121-first dielectric layer; 122-second dielectric layer; 130-through hole; 131-first hole; 132-second hole; 130G-through hole group; 210-sidewall protection material layer; 211-sidewall protection layer; 311-bottom protection layer; 311a-single crystal silicon layer; 311b-silicon germanium layer; 320-isolation layer; 411-mask layer; 411T-line trench; 412-bit line structure; 412T-bit line trench; 413- Third dielectric layer; 510-capacitor structure; 510C-capacitor unit; 510T-capacitor slot; 511-lower electrode layer; 511a upper parallel portion; 511b lower parallel portion; 511c-vertical portion; 512-capacitor dielectric layer; 513-upper electrode layer; 513a-first upper electrode layer; 513b-second upper electrode layer; 610-transistor structure; 610C-transistor unit; 611-channel layer; 612-gate dielectric layer; 613-gate structure; X-first direction; Y-second direction; Z-vertical direction. DETAILED DESCRIPTION

[0024] The technical solutions of the present disclosure will be further described in detail below with reference to the accompanying drawings and examples. Although the accompanying drawings illustrate exemplary implementations of the present disclosure, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0025] The following paragraphs describe the present disclosure in more detail by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more apparent from the following description and claims. It should be noted that the drawings are highly simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the embodiments of the present disclosure.

[0026] It will be understood that the meanings of “on,” “over,” and “over” throughout this disclosure should be interpreted in the broadest manner, such that “on” not only means being “on” something with no intervening features or layers (i.e., directly on something), but also includes being “on” something with intervening features or layers.

[0027] In the embodiments of the present disclosure, the terms "first," "second," "third," etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0028] In the embodiments of the present disclosure, the term "layer" refers to a portion of a material including an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent that is smaller than the extent of the lower or upper structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure having a thickness that is smaller than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0029] It should be noted that the technical solutions described in the embodiments of the present disclosure can be arbitrarily combined without conflict.

[0030] In some embodiments, during the process of fabricating structures such as transistors and capacitors on a substrate, a dielectric layer and a sacrificial material are formed on the substrate, and the sacrificial material in the dielectric layer is removed by an etching process to form a through-hole exposing the substrate surface. However, the inventors of the present application have discovered that, during actual fabrication, since the sacrificial material needs to have a high etching selectivity with the dielectric layer, the etching selectivity of the commonly used sacrificial material and the substrate is close. However, during the process of removing the sacrificial material in the through-hole or during the process of cleaning the through-hole, there is a risk of damaging the substrate or causing impurities to peel off from the sidewall of the substrate at the bottom of the through-hole, thereby affecting the device performance of structures such as transistors and capacitors subsequently formed on the damaged substrate surface, and reducing the performance stability and structural stability of the overall semiconductor structure.

[0031] Based on this, in order to solve the above problems, an embodiment of the present disclosure provides a method for preparing a semiconductor structure 10 .

[0032] Figure 1 is a flow chart showing a method for preparing a semiconductor structure according to an exemplary embodiment. Figure 2-7 and Figure 14-21 is a schematic diagram showing a process for preparing a semiconductor structure according to an exemplary embodiment. Figure 8-10 is a schematic diagram showing a process for preparing a semiconductor structure according to another exemplary embodiment. Figure 11-13 This is a schematic diagram of a semiconductor structure preparation process according to another exemplary embodiment. Figure 1 and Figures 2 to 21 The semiconductor structure 10 and its manufacturing process are described.

[0033] It is understandable that Figures 2 to 21, the first direction X and the second direction Y are horizontal directions parallel to the plane where the substrate 110 is located, and the first direction X intersects with the second direction Y. For example, the first direction X may be perpendicular to the second direction Y. The vertical direction Z is a direction intersecting with the plane where the substrate 110 is located. For example, the vertical direction Z is perpendicular to the plane where the substrate 110 is located.

[0034] Reference Figure 1 As shown, the method for preparing a semiconductor structure provided by the present disclosure comprises at least the following steps:

[0035] Step S101: providing a substrate and forming a stacked structure on the substrate, the stacked structure comprising a first dielectric layer and a second dielectric layer stacked in a vertical direction;

[0036] Step S102: forming a through hole penetrating the stacked structure in a vertical direction, the through hole including a first hole and a second hole, the through hole exposing a portion of the surface of the substrate, and the bottom surface of the through hole being flush with or lower than the top surface of the substrate;

[0037] Step S103: forming a sidewall protection layer inside the through hole;

[0038] Step S104: forming a bottom protection layer on the portion of the surface of the substrate exposed by the through hole;

[0039] Step S105: filling the isolation layer in the through hole;

[0040] Step S106: removing the isolation layer and part of the sidewall protection layer in the first hole, and forming a transistor structure in the first hole;

[0041] Step S107: removing the isolation layer and a portion of the sidewall protection layer in the second hole, and forming a capacitor structure in the second hole, wherein the capacitor structure is electrically connected to the transistor structure.

[0042] It should be understood that Figure 1 The steps shown in the operation are not exclusive, and other steps may be performed before, after, or between any steps in the operation shown; Figure 1 The steps shown in the figure can be adjusted in sequence according to actual needs.

[0043] Reference Figure 2 As shown, a stacked structure 120 is formed on a substrate 110 , and the stacked structure 120 includes a first dielectric layer 121 and a second dielectric layer 122 stacked along a vertical direction Z. The material of the substrate 110 may include silicon, for example, single crystal silicon, polycrystalline silicon, or amorphous silicon.

[0044] The first dielectric layer 121 and the second dielectric layer 122 are made of different materials and can be two of insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide. The first dielectric layer 121 and the second dielectric layer 122 can be formed alternately using deposition processes. The deposition processes can include chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced ALD, physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), or low-pressure chemical vapor deposition (LPCVD). In one example, the first dielectric layer 121 covers the top surface of the substrate 110, i.e., the bottom layer of the stacked structure 120 is the first support 121, and the top layer of the stacked structure 120 can be the second dielectric layer 122.

[0045] Reference Figure 3 As shown, a through hole 130 is formed along the vertical direction Z through the stacked structure 120. The bottom of the through hole 130 exposes a portion of the surface of the substrate 110. The bottom surface of the through hole 130 can be flush with the top surface of the substrate 110. In other examples, a portion of the substrate 110 can be removed so that the bottom surface of the through hole 130 is lower than the top surface of the substrate 110.

[0046] The through-hole 130 includes a first hole 131 and a second hole 132. The first hole 131 is used to form a transistor, and the second hole 132 is used to form a capacitor. The cross-section of the first hole 131 and the second hole 132 in the through-hole 130 on the horizontal plane defined by the first direction X and the second direction Y can be circular, elliptical, or rectangular. The plurality of first holes 131 can be arranged at intervals along the second direction Y, and the plurality of second holes 132 can be arranged at intervals along the second direction Y. In some examples, the plurality of first holes 131 can be arranged at equal intervals along the second direction Y, and the plurality of second holes 132 can be arranged at equal intervals along the second direction Y. The columns formed by the plurality of first holes 131 and the columns formed by the plurality of second holes 132 can be arranged at intervals along the first direction X. In one example, a first hole 131 and a second hole 132 adjacent along the first direction X may have the same central axis, and the central axis is parallel to the first direction X. A first hole 131 and a second hole 132 adjacent along the first direction X may constitute a through-hole group 130G, and multiple through-hole groups 130G are arranged at intervals along the second direction Y. The spacing between the first hole 131 and the second hole 132 in a through-hole group 130G is smaller than the spacing between two adjacent through-hole groups 130G.

[0047] In some embodiments, a patterned mask layer (not shown) may be formed on the stacked structure 120. Using the patterned mask layer as a mask, a dry etching process may be used to partially remove the stacked structure 120 to simultaneously form the first hole 131 and the second hole 132. In other examples, the first hole 131 may be formed in the stacked structure 120 using a patterned first mask layer, and then the patterned first mask layer may be removed. The second hole 132 may then be formed in the stacked structure 120 using a patterned second mask layer.

[0048] Reference Figure 4 and Figure 5 As shown, a deposition process is used to form a conformal sidewall protection material layer 210 on the exposed surface of the stacked structure 120 having the through-hole 130 formed therein. After removing a portion of the sidewall protection material layer 210 located on the top surface of the stacked structure 120 and at the bottom of the through-hole 130, a sidewall protection layer 211 located on the inner wall of the through-hole 130 remains. The material of the sidewall protection layer 211 can be silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or other insulating materials. The sidewall protection layer 211 is used to improve the uniformity of the material and profile of the inner wall of the through-hole 130 during subsequent processing and to reduce impurity peeling.

[0049] In some embodiments, reference Figure 6 As shown, a bottom protection layer 311 is formed on the surface of the substrate 110 exposed at the bottom of the through hole 130, referring to Figure 7 As shown, an isolation layer 320 is filled in the through hole 130. The thickness of the bottom protection layer 311 is less than the thickness of the first dielectric layer 121, that is, the top surface of the bottom protection layer 311 is lower than the top surface of the bottom-most first dielectric layer 121. The bottom-most first dielectric layer 121 is the first dielectric layer 121 closest to the substrate 110.

[0050] The bottom protective layer 311 can be formed through an epitaxial growth process or a deposition process. For example, if the substrate 110 is a single crystal silicon layer, the bottom protective layer 311 can be a silicon germanium (SiGe) layer formed by epitaxially growing the single crystal silicon layer using an epitaxial growth process. The epitaxial growth process can selectively form the SiGe layer on the exposed portion of the substrate 110 surface, effectively reducing the amount of SiGe layer formed and its coverage area, thereby reducing germanium contamination caused by the SiGe layer. Furthermore, the SiGe layer formed through the epitaxial growth process has good adhesion to the single crystal silicon layer, effectively preventing the SiGe layer from peeling off.

[0051] The isolation layer 320 covers the sidewall protection layer 211 and the bottom protection layer 311 and completely fills the through hole 130. A deposition process can be used to form a deposited isolation material layer, and a portion of the isolation material layer located on the top surface of the stacked structure 120 is removed by a chemical mechanical polishing process, leaving only the isolation material layer located in the through hole 130 as the isolation layer 320. The top surface of the isolation layer 320 can be flush with the top surface of the stacked structure 120. The material of the isolation layer 320 is a material that has a high etching selectivity with the first dielectric layer 121 and the second dielectric layer 122, as well as the bottom protection layer 311 and the sidewall protection layer 211. For example, the material of the isolation layer 320 can be polysilicon. The etching selectivity of polysilicon is close to that of the substrate 110. If the isolation layer 320 is directly formed on the substrate 110, the substrate 110 may be damaged during the removal of the isolation layer 320, causing a depression in the substrate 110 and increasing the risk of leakage.

[0052] In some other embodiments, referring to Figure 8 As shown, when forming the through hole 130, part of the substrate 110 can be removed to form a substrate recess 110R on the surface of the substrate 110, that is, the bottom surface of the through hole 130 is lower than the top surface of the substrate 110. The height of the substrate recess 110R can be less than the thickness of the first dielectric layer 121 or the second dielectric layer 122. Figure 9 As shown, a bottom protection layer 311 is formed on the surface of the substrate 110 exposed at the bottom of the through hole 130, referring to Figure 10 As shown, the isolation layer 320 is filled in the through hole 130 , and the top surface of the bottom protection layer 311 is lower than the top surface of the first dielectric layer 121 .

[0053] In some other embodiments, referring to Figure 11 As shown, when forming the through hole 130, a portion of the substrate 110 may be removed to form a substrate recess 110R on the surface of the substrate 110. The bottom surface of the through hole 130 is lower than the top surface of the substrate 110. The bottom protection layer 311 is formed on the portion of the surface of the substrate 110 exposed by the through hole 130, including: forming a single crystal silicon layer 311a on the portion of the surface of the substrate 110 exposed by the through hole 130 using a first epitaxial growth process, wherein the top surface of the single crystal silicon layer 311a is lower than the top surface of the substrate 110. Figure 12 As shown, a silicon germanium layer 311b is formed on the single crystal silicon layer 311a using a second epitaxial growth process. The thickness of the single crystal silicon layer 311a is less than that of the silicon germanium layer 311b. For example, the thickness of the single crystal silicon layer 311a ranges from 1 nm to 3 nm, and the thickness of the silicon germanium layer 311b ranges from 3 nm to 6 nm. The single crystal silicon layer 311a and the silicon germanium layer 311b constitute the bottom protective layer 311, and the single crystal silicon layer 311a helps to improve the adhesion between the silicon germanium layer 311b and the substrate 110, thereby preventing the silicon germanium layer 311b from peeling off. Figure 13As shown, an isolation layer 320 is filled in the through hole 130, and the isolation layer 320 covers the top surface of the silicon-germanium layer 311b. The precursor gas used in the first epitaxial growth process can be a silane-based semiconductor precursor gas, such as silane or disilane. The precursor gas used in the second epitaxial growth process can be a semiconductor precursor gas containing germanium, such as disilane and germane.

[0054] In some embodiments, the bit line structure 412 may be formed first and then the transistor structure 610 and the capacitor structure 510 are formed, or the transistor structure 610 and the capacitor structure 510 may be formed first and then the bit line structure 412 is formed. The present disclosure does not limit the order of forming the bit line structure 412, the transistor structure 610 and the capacitor structure 510. Figure 2-7 And refer to Figure 14-21 As shown, the present disclosure is described by taking the formation of the bit line structure first and then the formation of the transistor structure and the capacitor structure as an example.

[0055] Reference Figure 14 As shown, a patterned mask layer 411 is formed on the stacked structure 120, and the patterned mask layer 411 has an etching opening. A portion of the stacked structure 120 is removed along the etching opening to form a linear groove 411T on one side of the through hole 130 along the first direction X. The linear groove 411T extends along the second direction Y, penetrates the stacked structure 120 along the vertical direction Z, and exposes a portion of the surface of the substrate 110.

[0056] Reference Figure 15 As shown, a portion of the second dielectric layer 122 is laterally removed along the linear trench 411T to form a bit line trench 412T. The bit line trench 412T communicates with the linear trench 411T and may be located on both sides of the linear trench 411T along the first direction X. A plurality of bit line trenches 412T are arranged at intervals in the vertical direction Z, with the first dielectric layer 121 separating adjacent bit line trenches 412T along the vertical direction Z. The sidewalls of the bit line trench 412T may expose the spacer protection layer 211 located at one end of the inner wall of the first hole 131 in the through hole 130.

[0057] Reference Figure 16 As shown, a bit line structure 412 is formed to fill a bit line trench 412T. The bit line structure 412 extends along the second direction Y, and a third dielectric layer 413 is filled in the linear trench 411T. The material of the third dielectric layer 413 can be at least one of insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide.

[0058] In some embodiments, the bitline structure 412 may be made of a conductive material. The conductive material may include one or more of the following: metals (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), cobalt (Co), nickel (Ni)); alloys (e.g., Co-based alloys, Ti-based alloys, Co and Ni-based alloys, Fe and Co-based alloys); conductive metal-containing materials (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides); and conductive doped semiconductor materials (e.g., conductive doped polysilicon, conductive doped silicon germanium). The bitline structure 412 may be a single-layer structure or a multi-layer structure. For example, the bitline structure 412 may be a multi-layer structure consisting of a conductive metal silicide layer, a titanium nitride layer, and a tungsten layer, wherein the conductive metal silicide layer is disposed in direct contact with the spacer protection layer 211 to subsequently reduce the contact resistance between the bitline structure 412 and the transistor structure.

[0059] In some embodiments, reference Figure 17-20 As shown, a capacitor structure 510 is formed in the second hole 132, including: removing a portion of the second dielectric layer 122 laterally along the second hole 132 to form a capacitor groove 510T; forming a lower electrode layer 511 covering the inner wall of the capacitor groove 510T; forming a capacitor dielectric layer 512 covering the lower electrode layer 511, and the capacitor dielectric layer 512 covers the bottom protection layer 311 at the bottom of the second hole 132; and forming an upper electrode layer 513 covering the capacitor dielectric layer 512 and filling the second hole 132.

[0060] Reference Figure 17 As shown, after removing the mask layer 411, an etching process is used to remove the isolation layer 320 located in the second hole 132, exposing the sidewall protection layer 211 and the bottom protection layer 311 located in the second hole 132. The etching process includes a dry etching process or a wet etching process. In one example, the isolation layer 320 is polycrystalline silicon, and an ammonia-water mixture (ADM) and / or tetramethylammonium hydroxide (TMAH, (CH3)4NOH) are used to remove the isolation layer 320. Because the ammonia-water mixture and TMAH have low etching selectivity for silicon nitride, silicon oxide, silicon germanium, etc., the etching selectivity ratio of the isolation layer 320 to the bottom protection layer 311 and the sidewall protection layer 211 is greater than 10:1. Therefore, during the removal of the isolation layer 320 in the second hole 132, damage to the sidewall protection layer 211, the bottom protection layer 311, and the substrate 110 can be avoided.

[0061] Reference Figure 18As shown, a portion of the sidewall protection layer 211 within the second hole 132 is removed, while a portion of the sidewall protection layer 211 covered by the bottom protection layer 311 remains. The second hole 132 exposes the first dielectric layer 121 and the second dielectric layer 122. Portions of the second dielectric layer 122 are removed laterally along the second hole 132 to form capacitor trenches 510T. The sidewalls of the capacitor trenches 510T expose the sidewall protection layer 211 located at the other end of the inner wall of the first hole 131 in the through-hole 130. The capacitor trenches 510T arranged along the second direction Y are isolated from each other.

[0062] Reference Figure 19 As shown, an initial lower electrode layer is formed covering the inner wall of capacitor trench 510T, followed by a lower electrode protection layer 521 covering the initial lower electrode and filling capacitor trench 510T. A portion of the initial lower electrode layer is removed, leaving only the lower electrode layer 511 located on the inner wall of capacitor trench 510T. Multiple lower electrode layers 511 are arranged in a vertical direction Z with intervals between them. The projection of lower electrode layer 511 on substrate 110 is annular. Lower electrode layer 511 may include an upper parallel portion 511a, a lower parallel portion 511b, and a vertical portion 511c connecting the upper and lower parallel portions 511a, 511b. The projections of upper and lower parallel portions 511a, 511b on substrate 110 form overlapping annular shapes. Vertical portion 511c connects the outer edges of upper and lower parallel portions 511a, 511b. The thickness of upper and lower parallel portions 511a, 511b in the vertical direction Z may be equal to the thickness of vertical portion 511c in the horizontal direction. The vertical portion 511 c contacts the sidewall protection layer 211 located in the first hole 131 .

[0063] Reference Figure 20 As shown, the lower electrode protection layer 521 is removed, and a capacitor dielectric layer 512 is conformally deposited to cover the lower electrode layer 511. The capacitor dielectric layer 512 covers the bottom protection layer 311 at the bottom of the second hole 132 and the retained sidewall protection layer 211. The upper electrode layer 513 is conformally deposited to cover the capacitor dielectric layer 512 and fill the second hole 132. The upper electrode layer 513 may include a first upper electrode layer 513a and a second upper electrode layer 513b. The first upper electrode layer 513a conformally covers the capacitor dielectric layer 512, and the second upper electrode layer 513b covers the first upper electrode layer 513a and fills the second hole 132. The second upper electrode layer 513b may have a columnar portion extending along the vertical direction Z and a protrusion protruding horizontally along the sidewall of the columnar portion. The columnar portion extends through the stacked structure 120, and the protrusion is embedded in the capacitor trench 510T. The lower electrode layer 511, the capacitor dielectric layer 512 and the upper electrode layer 513 in each capacitor slot 510T together constitute a capacitor unit 510C. The capacitor structure 510 in each second hole 132 includes a plurality of capacitor units 510C spaced apart along the vertical direction Z.

[0064] The lower electrode layer 511, the first upper electrode layer 513a, and the second upper electrode layer 513b can be made of a conductive material. The first upper electrode layer 513a and the second upper electrode layer 513b can be different. For example, the second upper electrode layer 513b can be a conductive doped polysilicon layer or a conductive doped silicon germanium layer. The capacitor dielectric layer 512 can be made of a high dielectric constant material. High dielectric constant materials can include one or more of the following: hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, etc.

[0065] In some embodiments, reference Figure 21 As shown, a transistor structure 610 is formed in the first hole 131, including: forming a channel layer 611 on the sidewall of the first hole 131 corresponding to the second dielectric layer 122; forming a gate dielectric layer 612 covering the channel layer 611, and the gate dielectric layer 612 covers the top surface of the bottom protection layer 311 at the bottom of the first hole 131; forming a gate structure 613 filling the first hole 131, and the projection of the channel layer 611 in the vertical direction Z is a ring surrounding the gate structure 613.

[0066] Reference Figure 20-21 As shown, an etching process is used to remove the isolation layer 320 located in the first hole 131, exposing the sidewall protection layer 211 and the bottom protection layer 311 located in the first hole 131. In one example, the isolation layer 320 is polysilicon, and an ammonia-water-ultrapure water mixture and / or tetramethylammonium hydroxide are used to remove the isolation layer 320. Because the ammonia-water-ultrapure water mixture and tetramethylammonium hydroxide have low etching selectivity for silicon nitride, silicon oxide, silicon germanium, etc., damage to the sidewall protection layer 211, the bottom protection layer 311, and the substrate 110 can be avoided during the removal of the isolation layer 320 in the first hole 131.

[0067] Reference Figure 21 As shown, a portion of the sidewall protection layer 211 within the first hole 131 is removed, while a portion of the sidewall protection layer 211 covered by the bottom protection layer 311 remains. The first hole 131 exposes the bitline structure 412 and the lower electrode layer 511 of the capacitor structure 510 located on the layer where the second dielectric layer 122 is located. The bitline structure 412 and the lower electrode layer 511 are respectively located at two ends of the first hole 131 along the first direction X. A channel layer 611 is formed on the sidewalls of the first hole 131. The channel layer 611, the gate dielectric layer 612, and the gate structure 613 collectively constitute a transistor structure 610. The transistor structure 610 in each first hole 131 includes a plurality of transistor cells 610C spaced apart along the vertical direction Z. The transistor cells 610C and the capacitor cells 510C are electrically connected in a one-to-one correspondence to form a 1T1C (one-transistor, one-capacitor) horizontal memory cell.

[0068] In some embodiments, the channel layer 611 may completely cover the sidewalls of the first hole 131 .

[0069] In some embodiments, reference Figure 21 As shown, after depositing the channel material layer to completely cover the sidewalls of the first hole 131, it is necessary to remove a portion of the channel material layer located on the sidewalls of the first hole 131 corresponding to the first dielectric layer 121. The remaining channel layer 611 is only located on the sidewalls of the first hole 131 corresponding to the second dielectric layer 122, thereby reducing coupling between adjacent transistor units 610C in the vertical direction Z. In addition, the second dielectric layer 122 corresponding to the first hole 131 may be partially removed, so that the subsequently formed gate structure 613 has a sawtooth profile, that is, the size of the first portion of the gate structure 613 surrounded by the channel layer 611 is smaller than the size of the second portion between the first portion, and the second portion is not surrounded by the channel layer 611. As a result, the facing area between the gate structure 613 and the channel layer 611 can be increased, thereby enhancing the control capability of the gate structure 613 over the channel layer 611.

[0070] In some embodiments, the gate dielectric layer 612 may only cover the channel layer 611 , or the gate dielectric layer 612 may cover the channel layer 611 and the sidewall of the first dielectric layer 121 exposed by the first hole 131 .

[0071] Based on the above-mentioned method for preparing the semiconductor structure 10 , an embodiment of the present disclosure further provides a semiconductor structure 10 . Figure 21 is a schematic diagram of a semiconductor structure 10 according to an embodiment of the present disclosure.

[0072] Reference Figure 21 As shown, the semiconductor structure 10 includes: a substrate 110 and a stacked structure 120 located on the surface of the substrate 110, the stacked structure 120 including a first dielectric layer 121 and a second dielectric layer 122 stacked along a vertical direction Z; a through hole 130 penetrating the stacked structure 120 along the vertical direction Z, the through hole 130 including a first hole 131 and a second hole 132; a bottom protective layer 311 located at the bottom of the through hole 130 and a sidewall protective layer 211 surrounding the bottom protective layer 311, the bottom protective layer 311 being in contact with the substrate 110; a transistor structure 610 located in the first hole 131; and a capacitor structure 510 located in the second hole 132, the capacitor structure 510 being electrically connected to the transistor structure 610.

[0073] By providing a bottom protective layer 311 located at the bottom of the transistor structure 610 and the capacitor structure 510, and a sidewall protective layer 211 surrounding the bottom protective layer 311, leakage between the transistor structure 610 and the capacitor structure 510 and the substrate can be effectively reduced, thereby improving the electrical stability of the semiconductor structure. Because the sidewall protective layer 211 of the bottom protective layer 311 is located only on a portion of the surface of the substrate 110 rather than on the entire surface of the substrate 110, it does not introduce significant stress to the entire semiconductor structure, and can prevent substrate over-etching and impurity peeling during the semiconductor structure formation process, thereby improving the structural stability of the semiconductor structure.

[0074] In some embodiments, the top surface of the spacer protection layer 211 is flush with or higher than the top surface of the bottom protection layer 311. The bottom protection layer 311 can be formed by an epitaxial growth process, and the material of the bottom protection layer 311 can include silicon germanium.

[0075] In some embodiments, combined Figure 8 or Figure 11 As shown, a substrate recess 110R is formed on the surface of the substrate 110 , and a bottom protection layer 311 and a sidewall protection layer 211 are located on the substrate recess 110R.

[0076] In some embodiments, combined Figure 13 As shown, bottom protective layer 311 includes a single crystal silicon layer 311a and a silicon germanium layer 311b located on single crystal silicon layer 311a. The top surface of single crystal silicon layer 311a is lower than the top surface of the substrate, and the top surface of silicon germanium layer 311b is lower than the top surface of first dielectric layer 121 located closest to substrate 110. The thickness of single crystal silicon layer 311a is less than the thickness of silicon germanium layer 311b. For example, the top surface of bottom protective layer 311 is located between 0.3 and 0.6 of the height of first dielectric layer 121 located closest to substrate 110, ensuring protection for substrate 110 while avoiding spatial impact on transistor structure 610 and capacitor structure 510.

[0077] In some embodiments, combined Figure 3 and Figure 21 As shown, the through hole 130 includes a plurality of through hole groups 130G arranged along the second direction Y, and each through hole group 130G includes a first hole 131 and a second hole 132 arranged along the first direction X; the transistor structure 610 in each first hole 131 includes a plurality of transistor units 610C spaced apart along the vertical direction Z; the capacitor structure 510 in each second hole 132 includes a plurality of capacitor units 510C spaced apart along the vertical direction Z; the semiconductor structure 10 also includes a bit line structure 412, the bit line structure 412 extends along the second direction Y, and the plurality of bit line structures 412 are spaced apart along the vertical direction Z, and each bit line structure 412 is electrically connected to the plurality of transistor units 610C located on the same layer.

[0078] In some embodiments, reference Figure 21 As shown, the transistor structure 610 includes: a channel layer 611, located on the sidewall of the first hole 131 corresponding to the second dielectric layer 122; a gate dielectric layer 612, covering the channel layer, the sidewall of the first hole 131 corresponding to the second dielectric layer 122, and the top surface of the bottom protection layer 311; a gate structure 613, extending along the vertical direction Z and filling the first hole 131, and the projection of the channel layer 611 in the vertical direction Z is a ring surrounding the gate structure 613.

[0079] The two ends of the channel layer 611 along the first direction X are electrically connected to the bit line structure 412 and the capacitor structure 510 respectively. The material of the channel layer 611 can be single crystal silicon, polycrystalline silicon, germanium, silicon germanium and oxide semiconductor materials (for example, zinc tin oxide (ZnO) x Sn y O, commonly known as "ZTO"), indium zinc oxide (In x Zn y O, commonly known as "IZO"), zinc oxide (Zn x O), indium gallium zinc oxide (In x Ga y Zn z O, commonly known as "IGZO"), indium gallium silicon oxide (In x Ga y Si z O, commonly known as "IGSO"), indium tin oxide (In x Sn y O, commonly known as "ITO") and one or more of other similar materials).

[0080] The transistor structure 610 in each first hole 131 includes a plurality of transistor units 610C spaced apart along the vertical direction Z. The plurality of transistor units 610C are located in the layer of the stacked structure 120 where the second dielectric layer 122 is located. The gate structure 613 extends along the vertical direction Z and penetrates the stacked structure 120. The bottom surface of the gate structure 613 is lower than the top surface of the bottommost first dielectric layer 121.

[0081] In some embodiments, reference Figure 21 As shown, the capacitor structure 510 includes: a lower electrode layer 511, located on the side wall of the second hole 132 corresponding to the second dielectric layer 122, and the projection of the lower electrode layer 511 in the vertical direction Z is annular; a capacitor dielectric layer 512, the capacitor dielectric layer 512 covers the bottom protection layer 311 at the bottom of the second hole 132; and an upper electrode layer 513, covering the capacitor dielectric layer 512 and filling the second hole 132.

[0082] The capacitor structure 510 in each second hole 132 includes a plurality of capacitor units 510C spaced apart along the vertical direction Z. The plurality of capacitor units 510C are respectively located in the layer where the second dielectric layer 122 of the stacked structure 120 is located. The transistor units 610C and the capacitor units 510C are electrically connected in a one-to-one correspondence to form a 1T1C horizontal storage unit.

[0083] In some embodiments, combined Figure 19 As shown, the projection of the lower electrode layer 511 on the substrate 110 is annular. The lower electrode layer 511 may include an upper parallel portion 511a, a lower parallel portion 511b, and a vertical portion 511c connecting the upper parallel portion 511a and the lower parallel portion 511b. The projections of the upper parallel portion 511a and the lower parallel portion 511b on the substrate 110 are annular, overlapping with each other. The vertical portion 511c connects the outer edges of the upper parallel portion 511a and the lower parallel portion 511b. The thickness of the upper parallel portion 511a and the lower parallel portion 511b in the vertical direction Z may be equal to the thickness of the vertical portion 511c in the horizontal direction. The vertical portion 511c contacts the channel layer 611 located in the first hole 131.

[0084] In some embodiments, the first top electrode layer 513a conformally covers the capacitor dielectric layer 512, and the second top electrode layer 513b covers the first top electrode layer 513a and fills the second hole 132. The second top electrode layer 513b may have a columnar portion extending along the vertical direction Z and a protruding portion protruding horizontally along the sidewall of the columnar portion. The columnar portion extends through the stacked structure 120, and the protruding portion is embedded in the capacitor trench 510T. The bottom surface of the second top electrode layer 513b is lower than the top surface of the bottommost first dielectric layer 121.

[0085] In some embodiments, the semiconductor structure 10 includes a memory, which may be a dynamic random access memory, such as a three-dimensional memory, 3D DRAM. The memory may also be a memory known in the art, such as a phase change memory or a ferroelectric memory.

[0086] It should be noted that the active pillar in the embodiment of the present disclosure can be located in the array area and / or the peripheral area. When the active pillar is located in the array area, the transistor and storage structure including the active pillar together constitute a storage unit; when the active pillar is located in the peripheral area, the transistor including the active pillar and electronic components such as capacitors and resistors constitute a peripheral circuit.

[0087] The various semiconductor structures shown in this embodiment can be used in electronic devices with storage functions. The electronic devices can be terminal devices such as mobile phones, tablet computers, smart bracelets, or personal computers (PCs), servers, workstations, etc. The storage function in the electronic devices can be implemented using the following memories: dynamic random access memory (DRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), magnetic random access memory (MRAM), or resistive random access memory (RRAM).

[0088] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate and forming a stacked structure on the substrate, wherein the stacked structure includes a first dielectric layer and a second dielectric layer stacked in a vertical direction; forming a through hole penetrating the stacked structure along the vertical direction, the through hole comprising a first hole and a second hole, wherein the first hole and the second hole extend along the vertical direction, the through hole exposes a portion of the surface of the substrate, and the bottom surface of the through hole is flush with or lower than the top surface of the substrate; forming a sidewall protection layer inside the through hole; forming a bottom protection layer on the portion of the surface of the substrate exposed by the through hole; filling an isolation layer in the through hole; removing the isolation layer and a portion of the sidewall protection layer in the first hole, and forming a transistor structure in the first hole; removing the isolation layer and a portion of the sidewall protection layer in the second hole, and forming a capacitor structure in the second hole, wherein the capacitor structure is electrically connected to the transistor structure; The bottom surface of the through hole is lower than the top surface of the substrate, and forming a bottom protection layer on the portion of the surface of the substrate exposed by the through hole comprises: forming a single crystal silicon layer on the portion of the surface of the substrate exposed by the through hole using a first epitaxial growth process, wherein the top surface of the single crystal silicon layer is lower than the top surface of the substrate; A silicon germanium layer is formed on the single crystal silicon layer by adopting a second epitaxial growth process, and the thickness of the single crystal silicon layer is smaller than the thickness of the silicon germanium layer.

2. The preparation method according to claim 1, characterized in that The forming of a transistor structure in the first hole comprises: forming a channel layer on a sidewall of the first hole corresponding to the second dielectric layer; forming a gate dielectric layer covering the channel layer, wherein the gate dielectric layer covers a top surface of the bottom protection layer at the bottom of the first hole; A gate structure filling the first hole is formed, and a projection of the channel layer in the vertical direction is in a ring shape surrounding the gate structure.

3. The preparation method according to claim 1, characterized in that The forming of a capacitor structure in the second hole comprises: removing a portion of the second dielectric layer laterally along the second hole to form a capacitor groove; forming a lower electrode layer covering the inner wall of the capacitor groove; forming a capacitor dielectric layer covering the lower electrode layer, wherein the capacitor dielectric layer covers the bottom protection layer at the bottom of the second hole; An upper electrode layer is formed to cover the capacitor dielectric layer and fill the second hole.

4. The preparation method according to claim 1, characterized in that The through holes include a plurality of through hole groups arranged along the second direction, each through hole group includes a first hole and a second hole arranged along the first direction; the transistor structure in each first hole includes a plurality of transistor units spaced apart along the vertical direction; The capacitor structure in each of the second holes includes a plurality of capacitor units spaced apart along the vertical direction; the method further comprising: forming a linear groove on one side of the through hole along the first direction; removing a portion of the second dielectric layer laterally along the linear trench to form a bit line trench; A bit line structure filling the bit line groove is formed, the bit line structure extends along the second direction, and a plurality of the bit line structures are arranged at intervals along the vertical direction, and each of the bit line structures is electrically connected to a plurality of the transistor units located in the same layer.

5. A semiconductor structure, characterized in that include: A substrate and a stacked structure located on a surface of the substrate, wherein the stacked structure includes a first dielectric layer and a second dielectric layer stacked in a vertical direction; a through hole penetrating the stacked structure along the vertical direction, the through hole comprising a first hole and a second hole, wherein the first hole and the second hole extend along the vertical direction; a bottom protection layer located at the bottom of the through hole and a sidewall protection layer surrounding the bottom protection layer, wherein the bottom protection layer is in contact with the substrate; a transistor structure located in the first hole; a capacitor structure located in the second hole, the capacitor structure being electrically connected to the transistor structure; The bottom protective layer includes a single crystal silicon layer and a silicon germanium layer located on the single crystal silicon layer, the top surface of the single crystal silicon layer is lower than the top surface of the substrate, the top surface of the silicon germanium layer is lower than the top surface of the first dielectric layer located closest to the substrate, and the thickness of the single crystal silicon layer is less than the thickness of the silicon germanium layer.

6. The semiconductor structure according to claim 5, wherein: The through holes include a plurality of through hole groups arranged along the second direction, and each through hole group includes a first hole and a second hole arranged along the first direction; The transistor structure in each of the first holes includes a plurality of transistor units spaced apart along the vertical direction; The capacitor structure in each of the second holes includes a plurality of capacitor units spaced apart along the vertical direction; The semiconductor structure further includes a bit line structure, which extends along the second direction. A plurality of the bit line structures are arranged at intervals along the vertical direction, and each of the bit line structures is electrically connected to a plurality of the transistor units located in the same layer.

7. The semiconductor structure according to claim 6, wherein: The transistor structure comprises: a channel layer, located on a sidewall of the first hole corresponding to the second dielectric layer; a gate dielectric layer covering the channel layer, a sidewall of the first hole corresponding to the second dielectric layer, and a top surface of the bottom protection layer; A gate structure extends along the vertical direction and fills the first hole, and a projection of the channel layer in the vertical direction is in a ring shape surrounding the gate structure.

8. The semiconductor structure according to claim 5, wherein: The capacitor structure comprises: a lower electrode layer, located on a sidewall of the second hole corresponding to the second dielectric layer, wherein a projection of the lower electrode layer in the vertical direction is annular; a capacitor dielectric layer, wherein the capacitor dielectric layer covers the bottom protection layer at the bottom of the second hole; The upper electrode layer covers the capacitor dielectric layer and fills the second hole.

Images