Method for performing netlist-level fault injection test on user register

Abstract

The invention provides a method for performing netlist-level fault injection test on a user register. The method comprises the following steps: using an LUT2 with a specific truth table as a fault injection test point; randomly inserting the fault injection test points into user design for fault injection test; different from the prior art in which only fault injection testing can be carried out on a configuration register, the invention provides a method for carrying out fault injection testing on a user register, the method and the prior art are in complementary relation essentially, and the reliability of a tested circuit can be tested more completely by simultaneously applying the two methods.

Description

Technical Field

[0001] The invention belongs to the technical field of FPGA design reliability verification, and in particular relates to a method for performing a netlist-level fault injection test on a user register. Background Art

[0002] In the field of FPGA design reliability, it is necessary to verify the reliability of FPGA design in order to obtain some experimental data to prove the probability that the design will not fail. At present, the main fault injection method is implemented through ICAP (Internal Configuration Access Port). ICAP is an interface in FPGA (field programmable gate array) that allows users to access and manage the configuration of FPGA at runtime. ICAP provides a mechanism that allows users to dynamically read and modify the configuration bitstream of FPGA, thereby realizing various advanced applications such as local reconfiguration, dynamic configuration management, and system debugging. By adding ICAP to the design and connecting its port to the external port or other places inside the FPGA for providing control signals through appropriate logic, users can design fault injection logic by themselves and test where they want to test.

[0003] In the existing technology of fault injection through ICAP, the registers in the FPGA are divided into two categories. One category is the configuration registers configured when burning the code stream. These registers determine the state of each configuration unit inside the FPGA and also determine the connection relationship between the configuration units. Generally speaking, the values ​​of these registers will not change after the code stream is configured; the other category of registers is called user registers. These registers store the states generated when the FPGA is working. It is these states that constitute the user's operation logic. Therefore, the values ​​of these registers will change at any time during operation. Therefore, only the state of the configuration register can be modified, and the user register cannot be modified numerically. Therefore, the fault injection test performed by this technology cannot fully test the reliability of the circuit. Summary of the invention

[0004] In view of this, the purpose of the present invention is to provide a method for performing netlist-level fault injection testing on user registers, by inserting some fault injection test points in the circuit. These test points will not affect the working logic of the circuit when not activated, but will simulate a circuit fault state similar to SEU after activation, thereby achieving the purpose of testing the reliability of the user design.

[0005] A method for performing a fault injection test on a user register, comprising:

[0006] A fault injection test point is inserted at the output side of at least one register of the circuit to be tested, and a lookup table LUT is deployed at the fault injection test point, one input of the lookup table LUT is connected to the output end of the register, and the other output ends of the lookup table LUT are connected to the control signal; the output end of the lookup table LUT is used as the output of the register and is sent to the device originally connected to the register; wherein the lookup table LUT of each fault injection test point is configured with a truth table, and the truth table represents all possible input combinations of the lookup table LUT and their corresponding output results;

[0007] During the test, the control signal input to the lookup table LUT is controlled to cause the circuit to produce an SEU phenomenon, and the function of the circuit is tested; after multiple tests, the reliability of the circuit is statistically calculated.

[0008] Preferably, the lookup table LUT has two or more input terminals.

[0009] Preferably, a fault injection controller is further provided for controlling the input of the control signal of the lookup table LUT.

[0010] Preferably, registers are selected in the circuit to be tested according to a random probability model.

[0011] The present invention has the following beneficial effects:

[0012] The present invention provides a method for performing a netlist-level fault injection test on a user register, using a LUT2 with a specific truth table as a fault injection test point; the fault injection test point is randomly inserted into a user design for a fault injection test; different from the prior art that can only perform a fault injection test on a configuration register, the present invention provides a method for performing a fault injection test on a user register, which is essentially complementary to the prior art, and the two are applied simultaneously to perform a more complete test on the reliability of a circuit under test. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] FIG. 1( a ) is a schematic diagram of the output of a fault injection test point in Normal State and Fault State when a fault injection test point is set between two registers of the present invention;

[0014] Figure 1(b) is a schematic diagram of the truth representation of the lookup table LUT configuration;

[0015] Figure 2 A schematic diagram of a method for performing a netlist-level fault injection test on a user register provided by the present invention. DETAILED DESCRIPTION

[0016] The present invention is described in detail below with reference to the accompanying drawings and embodiments.

[0017] The present invention provides a method for performing a netlist-level fault injection test on a user register, as shown in FIG1 . The “fault injection test point” in the present invention is essentially a LUT2, i.e., a LUT with two input ports. LUT (Look-Up Table) is a data structure or storage unit widely used in computer science, digital circuits, and signal processing. Its basic concept is to pre-store the results required for calculation or search so that the results can be quickly searched and returned when needed, rather than recalculating each time they are needed. This can greatly improve efficiency in many applications.

[0018] A fixed truth table is configured in the test point. The truth table is a commonly used tool in logic and digital circuit design. It is used to represent all possible input combinations of logic circuits or Boolean expressions and their corresponding output results. Through the truth table, the behavior of the logic circuit or logic function under different input conditions can be intuitively viewed and analyzed. As shown in Figure 1(b), the truth table usually consists of the following parts:

[0019] 1) Input columns: Each column represents an input variable, and the number of columns depends on the number of input variables. For each input variable, the possible values ​​are usually 0 (false) and 1 (true).

[0020] 2) Output column: The output column represents the output result of the logic function or circuit, and the output value is also 0 or 1.

[0021] 3) Rows: Each row represents a specific input combination and its corresponding output. For n input variables, the truth table will contain 2n rows, covering all possible input combinations.

[0022] This truth table can realize that when the control terminal (I1) is 0 (i.e., the Normal State in Figure 1(a)), the output value of the test point output port (O) is consistent with the value of the data terminal (I0) (t); and when the control terminal (I1) is 1 (i.e., the Fault State in Figure 1(a)), the output value of the test point output port (O) is the inverse of the value of the data terminal (I0) (~t).

[0023] The behavior after activating the fault injection test point (output value flipping) is simulating the occurrence of SEU (Single Event Upset). When SEU occurs in register A in Figure 1(a), its output value will flip instantly. Therefore, the scheme of attempting to modify its data through the data input port of register A is not feasible, because the working principle of the register determines that it will only synchronize the data of the input port to the output port at the clock edge (generally configured as the rising edge in engineering) (not satisfying the characteristic that SEU occurs instantly). There is no other way to set the value of the register in the FPGA, so this scheme is the only feasible scheme.

[0024] In actual use, in the user design, according to a certain random probability model (arbitrarily specified by the user according to actual needs), some registers (similar to register A in the above figure) are found, and fault injection test points are inserted on their output sides. The output of the test points is used to replace the output of the original registers and sent to the device originally connected to the current register A under test; and the control end (I1) of the fault injection test point is connected to the fault injection controller (such as Figure 2 shown).

[0025] The function of the fault injection controller is to receive control signals from the outside, or according to a certain fault injection logic (the specific control method can be arbitrarily designed according to the test requirements), automatically activate one or some fault injection test points at the appropriate time to simulate the occurrence of SEU phenomena.

[0026] During the test, the user controls the fault injection controller to cause the circuit to produce SEU phenomenon and verify the function of the system. If the function is normal, it means that this SEU will not cause system failure; if the function is abnormal, it means that this SEU causes system failure. After multiple tests, the reliability of the current user design can be statistically calculated, and this data helps users to further improve the reliability of the design.

[0027] The specific usage of the truth table is as follows: The function of the truth table is to view the output values ​​under different input combinations. For a LUTN with N input ports, its truth table will have (N+1) columns. Taking the truth table of LUT2 in Figure 1(b) as an example, there are 3 columns in total. The first 2 columns represent the input values ​​of its 2 input ports (I1 and I0), and the third column represents the output value (O). When using the truth table, you need to check it row by row. For example, when I1=0 and I0=1, find the corresponding row, which is the output truth value. In Figure 1(b), the second row is found, and its output value (O) is 1.

[0028] In summary, the above are only preferred embodiments of the present invention and are not intended to limit the protection scope of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for performing a fault injection test on a user register, characterized in that: include: A fault injection test point is inserted at the output side of at least one register of the circuit to be tested, and a lookup table LUT is deployed at the fault injection test point, one input of the lookup table LUT is connected to the output end of the register, and the other output ends of the lookup table LUT are connected to the control signal; the output end of the lookup table LUT is used as the output of the register and is sent to the device originally connected to the register; wherein the lookup table LUT of each fault injection test point is configured with a truth table, and the truth table represents all possible input combinations of the lookup table LUT and their corresponding output results; During the test, the control signal input to the lookup table LUT is controlled to cause the circuit to produce an SEU phenomenon, and the function of the circuit is tested; after multiple tests, the reliability of the circuit is statistically calculated.

2. A method for performing a fault injection test on a user register as claimed in claim 1, characterized in that: The lookup table LUT has two or more input terminals.

3. A method for performing a fault injection test on a user register as claimed in claim 1, characterized in that: A fault injection controller is also provided for controlling the input of the control signal of the lookup table LUT.

4. A method for performing a fault injection test on a user register as claimed in claim 1, characterized in that: Registers are selected in the circuit under test based on a random probability model.

Images