Verification method and verification device of storage controller and virtual verification device

Abstract

The invention discloses a verification method, a verification device and a virtual verification device of a storage controller. The verification method comprises the steps that when a to-be-verified storage controller is verified, after excitation content of to-be-verified operation is input into the to-be-verified storage controller, a corresponding interface time sequence is generated; generating a result event after monitoring that the interface time sequence of the to-be-verified operation conforms to the interface time sequence specification of the corresponding operation of the memory; storing the result event into a result queue; comparing and analyzing the result queue and an expected queue to identify whether the to-be-verified storage controller passes verification or not; the expected event corresponding to the excitation content is stored in the expected queue. According to the verification method of the storage controller, the interface time sequence of the storage controller is converted into the event queue, the expected queue and the result queue of the storage controller are directly verified, dependence on a storage behavior model is reduced, and observability of function verification is improved.

Description

Technical Field

[0001] The present application relates to the field of chip verification technology, and in particular to a verification method and a verification device for a storage controller. Background Art

[0002] With the development of the chip industry, different chips have different storage requirements, which leads to frequent replacement of FLASH, SDRAM and other memories in the chip system. The memory behavior model also changes accordingly, which leads to the adjustment of test cases. Traditional storage controllers rely on behavioral models during verification, and inaccurate behavioral models will cover up design errors.

[0003] It is difficult to verify the accuracy of the storage controller output timing. When encountering timing that is not supported by the behavioral model, manual inspection is required, and all test cases cannot be automatically covered. When dynamic verification is performed on functional points such as the timing of converting the storage controller's commands to the memory interface, there is no immediate feedback on whether the storage controller function is correct, resulting in a longer verification cycle and late functional convergence, which affects the progress of chip development. Summary of the invention

[0004] The purpose of the present invention is to provide a verification method, a verification device and a virtual verification device for a storage controller, so as to realize dynamic and automatic inspection of the storage controller function, reduce the dependence of the memory simulation on the behavior model, and increase the portability and reusability of the test cases.

[0005] The technical solution provided by the present invention is as follows: The present invention provides a storage controller verification method, comprising: When verifying a storage controller to be verified, after inputting the stimulus content of the operation to be verified into the storage controller to be verified, a corresponding interface timing is generated; after monitoring that the interface timing of the operation to be verified complies with the interface timing specification of the corresponding operation of the memory, a result event is generated; the result event is stored in a result queue; the result queue is compared and analyzed with the expected queue to identify whether the storage controller to be verified has passed the verification; the expected queue stores the expected event corresponding to the stimulus content.

[0006] Specifically, the storage controller verification method proposed in the present invention can directly convert the interface timing generated by the storage controller to be verified into a result event, thereby improving the observability and efficiency of the verification.

[0007] Further, the result queue is compared and analyzed with the expected queue to identify whether the storage controller to be verified has passed the verification, including: Compare the result events stored in the result queue with the expected events stored in the expected queue one by one to see if they are consistent; if they are consistent, the storage controller to be verified passes the verification; otherwise, the storage controller to be verified fails the verification; the storage controller to be verified includes an instance of storage controller verification, an instance of SOC verification, and an instance of Netlist verification.

[0008] Specifically, through the verification method of the storage controller proposed in the present invention, by comparing the events in the result queue and the expected queue, all memory operations that occur can be monitored, and unexpected operations generated by the memory controller can be effectively discovered. Such errors improve the coverage and adequacy of verification.

[0009] Further, comparing and analyzing the result queue with the expected queue to identify whether the storage controller to be verified has passed the verification, further comprising: Whether the number of occurrences of the same result event in the result queue exceeds the preset number; if it does not exceed the preset number, the storage controller to be verified passes the verification; otherwise, the storage controller to be verified fails the verification.

[0010] Specifically, the verification method of the storage controller proposed in the present invention can solve the problem of invalid memory access and other operation errors (such as low pre-fetching efficiency) occurring in the storage controller.

[0011] Furthermore, before verifying the storage controller to be verified, the following steps are included: A plurality of first timing parameters and a plurality of first timing parameter relationships are extracted from the interface timing specification; the first timing parameters and the first timing parameter relationships are the conditions that need to be satisfied when the item to be verified performs any operation.

[0012] Specifically, the verification method of the storage controller proposed by the present invention is based on the timing interface specification specified in the storage data manual as a trigger condition, is universal for different memories, and is suitable for script generation.

[0013] Further, after monitoring that the interface timing of the operation to be verified complies with the interface timing specification of the corresponding operation of the memory, a result event is generated, including: Obtain a second timing parameter of the interface timing to be detected from the interface timing, and detect whether the second timing parameters correspond to the first timing parameters respectively; when the second timing parameter corresponds to the first timing parameter, obtain a second timing parameter relationship of the interface timing to be detected, and detect whether the second timing parameter relationship is consistent with the corresponding first timing parameter relationship; when the second timing parameter relationship corresponds to and is consistent with the first timing parameter relationship, generate a result event; otherwise, generate an error prompt message.

[0014] Specifically, the verification method of the storage controller proposed in the present invention makes the function of converting the interface timing into the result event more standardized and unified, thereby improving the verification efficiency.

[0015] Furthermore, before comparing the result cohort with the expected cohort, the expected cohort included: The expectation generation module is used to generate the expected event according to the stimulus content and store it in the expectation queue; or, the result queue generated after the operation to be verified passes the preliminary verification is used as the expectation queue for the subsequent verification.

[0016] Specifically, through the storage controller verification method proposed in the present invention, in conjunction with dynamic configuration, the code logic of automated inspection in verification use cases can be unified, thereby improving the readability and reusability of verification use cases in different projects; in conjunction with static configuration, the result queue of the verification output can be directly used as the expected queue for subsequent verification, thereby performing consistency checks on the memory controller functions.

[0017] Furthermore, when comparing and analyzing the result event in the result queue with the expected event in the expected queue, the method further includes: Check whether the storage update time of the result queue has timed out. If timeout occurs, shut down the verification storage controller and print out the timeout detection error.

[0018] Specifically, through the verification method of the storage controller proposed in the present invention, the events in the expected queue and the result queue configured in a dynamically configured manner are compared and analyzed to achieve the delay of monitoring the stimulus output to the timing interface through the memory controller.

[0019] The present invention also proposes a verification device for a storage controller, which is generated by a hardware description language code file and includes a processor and a storage unit, and is used to call instructions stored in the storage unit. When the instructions are executed, they are executed to implement any operation performed by the above-mentioned verification method for the storage controller.

[0020] The present invention also provides a virtual verification device for a storage controller, comprising: The first queue module is used to store the expected events generated according to the stimulus content; the timing conversion module is used to convert the interface timing generated by the storage controller to be verified according to the stimulus content into result events; the second queue module is used to store the result events generated by the timing conversion module; the queue comparison module is used to compare and analyze the expected events with the result events one by one to identify whether the storage controller to be verified has passed the verification.

[0021] Furthermore, the virtual verification device of the storage controller also includes: The first queue module is also used to store the result events generated after the previous verification, and use the result events as expected events for the later verification; And / or, a timeout detection module, used to detect whether the storage update time of the result event of the second queue module has timed out.

[0022] Through the verification method, verification device and virtual verification device of the storage controller proposed in the present invention, the interface timing output by the storage controller is directly converted into result events, and the consistency of the result event queue and the expected event queue is compared to determine whether the function and timing of the storage controller meet the design expectations, thereby improving the observability of the storage controller during verification. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0024] Figure 1 It is a structural schematic diagram of an embodiment of a virtual verification device of a storage controller of the present invention; Figure 2 It is a structural relationship diagram of an embodiment of a timing conversion module in a verification device of a storage controller of the present invention; Figure 3 is a timing diagram of a storage controller dynamically executing a write operation according to an embodiment of the present invention; Figure 4 It is a structural schematic diagram of a specific embodiment of a storage controller for IP verification according to the present invention; Figure 5 It is a verification flow chart of an embodiment of a storage controller performing IP verification according to the present invention; Figure 6 is a verification flow chart of another embodiment of a storage controller performing IP verification according to the present invention; Figure 7 It is a structural schematic diagram of a specific embodiment of a storage controller for SOC / Netlist verification according to the present invention; Figure 8 is a verification flow chart of an embodiment of a storage controller performing SOC verification according to the present invention; Fig. 9 is a flow chart of an embodiment of a verification method of a storage controller of the present invention; Fig.10 is a flow chart of another embodiment of a storage controller verification method of the present invention; Fig.11 It is a flow chart of another embodiment of a storage controller verification method of the present invention. DETAILED DESCRIPTION

[0025] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0026] It should be understood that when used in this specification and the appended claims, the term "comprising" indicates the presence of the described features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or collections.

[0027] It should be further understood that the term “and / or” used in the specification and appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0028] In addition, in the description of the present application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0029] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the specific implementation methods of the present invention will be described below with reference to the accompanying drawings. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings and other implementation methods can be obtained based on these drawings without creative work.

[0030] The storage controller is a hardware component that manages the memory. It is responsible for processing data transfer requests, performing data read and write operations, and managing the physical characteristics of the memory. The storage controller can be independent hardware or integrated into the motherboard, memory, or processor to act as an interface between the system on chip (SOC) and the memory. For example, it converts the I / O requests of the system on chip into commands that the memory can understand and execute.

[0031] The correct operation of the storage controller is the prerequisite for the stable operation of the entire on-chip system. The storage controller essentially converts the configured commands into the timing corresponding to the datasheet. When verifying the correctness of the storage controller, a corresponding memory behavior model is generally required for auxiliary verification.

[0032] The current storage controller has the following shortcomings during verification: The storage controller relies on feedback from the behavioral model, and inaccurate behavioral models can mask design errors in the storage controller. When the memory is frequently replaced, the test cases for verification are not portable. When the interface timing requirements that are not supported by the behavioral model require manual inspection, all test cases cannot be automatically covered. The operation observability of the storage controller output is poor, and it is impossible to directly verify the interface timing of the storage controller command converted into the memory interface, resulting in a low degree of consistency verification. During dynamic verification, the storage controller function cannot get immediate feedback, resulting in a longer verification cycle and late functional convergence, which affects the progress of chip development.

[0033] Therefore, the present application proposes a verification method for a storage controller, which can cover all test cases by converting the interface timing into an event queue and directly verifying the expected queue and result queue of the storage controller, thereby improving the adequacy and observability of the verification. Based on the verification method proposed by the present invention, the result event corresponding to the current operation of the memory is dynamically obtained and loaded into the result queue, the correctness of all result queues is verified, the dependence on the behavior model during the simulation of the memory controller is reduced, and all verification cases can be covered.

[0034] The following is a description with reference to the accompanying drawings: In one embodiment of the present invention, please refer to Figure 1 , which shows a schematic diagram of the structure of a virtual verification device 100 of a storage controller provided in some embodiments of the present disclosure. The verification device 100 of the storage controller may be a virtual device generated by a hardware description language code file, and the virtual verification device 100 includes: a timing conversion module 110, a queue comparison module 120, a first queue module 130, a second queue module 140 and a timeout detection module 150.

[0035] The timing conversion module 110 is used to convert the interface timing generated by the storage controller to be verified according to the stimulus content into a result event.

[0036] The queue comparison module 120 is used to compare and analyze the expected events with the result events one by one to identify whether the storage controller to be verified has passed the verification.

[0037] The first queue module 130 is used to store the expected events generated according to the incentive content; or to store the result events generated after the previous verification and use the result events as the expected events for the later verification.

[0038] The second queue module 140 is used to store the result events generated by the timing conversion module.

[0039] The timeout detection module 150 is used to detect whether the storage update time of the result event of the second queue module has timed out.

[0040] Specifically, the instance to be verified includes a storage controller, SOC, and Netlist. After the instance to be verified receives the stimulus content, the internal storage controller generates a response interface timing, and the interface timing is sent to the virtual verification device 100 for verification.

[0041] In the virtual verification device 100, the timing conversion module 110 converts the interface timing into the result event, and converts the timing verification into the event verification. In the queue comparison module 120, the expected event of the first queue module 130 and the result event of the second queue module 140 are compared one by one to see if they are consistent, thereby verifying the correctness of the storage controller inside the device to be verified in actual application.

[0042] The working principle of the timing conversion module 110 is described below in conjunction with the accompanying drawings. Figure 2 , is a structural relationship diagram of the timing conversion module 110.

[0043] The timing conversion module 110 includes a monitoring assertion group, a timing parameter verification function library, and a trigger and event output process block. The timing conversion module 110 abstracts the judgment function of different memory behavior models on the interface timing, abandons the specific storage function inside the behavior model, and is universal for different memories.

[0044] The data sheet of the memory contains the interface timing specifications for any operation of the memory. The timing parameter requirements corresponding to the interface timing specifications of any operation can correspond to a monitoring assertion. The monitoring assertion is triggered when the interface timing output by the memory controller contains the corresponding timing relationship during simulation. Different memories can be organized into a monitoring assertion group with a unified format through all the timing parameter requirements, which is conducive to script automation processing.

[0045] Timing parameters include: setup time, hold time, maximum pulse width time, etc. Timing parameters can be abstracted into a timing parameter verification function that returns whether the interval time is greater than or less than a certain value. All timing parameter verification functions constitute a timing parameter verification function library, which is called by monitoring assertions when triggered to determine whether the triggered timing relationship meets the corresponding timing parameter requirements. Since the functions of this library can be used for one type of inspection, they can be reused and expanded efficiently.

[0046] Each operation in the memory data sheet corresponds to a unique level combination (refer to the truth table in the data sheet, which lists the high and low input level combinations corresponding to all modes). When the level combination changes to enter a new operation, by checking the monitoring assertion results corresponding to all timing parameter requirements of the interface specification of the operation, it can be determined that the memory controller has correctly issued the operation. In this way, different memories can be organized into trigger and event process blocks with a unified format through their truth tables, which is conducive to script automation processing.

[0047] For example, see Figure 3 , the interface timing specification of programming operation is specified in the example Flash datasheet. The script can extract the corresponding level combination to generate the trigger and event output process block, such as when the level combination is CE=1, WE=1, PROG=1, it will trigger the process block of checking the relevant monitoring assertion results and outputting the event; extract the timing parameter requirements of the timing interface specification to generate the monitoring assertion group, generate the monitoring assertions corresponding to the timing parameters Tcp_setup (the time required for CE to stabilize in advance to the WE rising edge), Tap_setup (the time required for ADDR to stabilize in advance to the WE rising edge), Twp_setup (the time required for WE to stabilize in advance to the PROG rising edge), Tdp_setup (the time required for Datain to stabilize in advance to the PROG rising edge), Tdp_hold (the time required for Datain to be maintained after the PROG rising edge), Tp_widthl (the pulse width requirement of the PROG low level), and Tp_widthh (the pulse width requirement of the PROG high level); reuse the general timing parameter verification function library. The timing converter module 110 required by the virtual verification device 100 can be automatically generated.

[0048] Through the virtual verification device proposed in the present invention, operations on different memories are converted into events of a unified form. There is no need to modify the backdoor detection logic in the test case accordingly according to the content of the behavior model. The addition of the platform can automatically cover all test cases. It can check whether the timing of the storage controller in the device to be verified meets the design requirements. Automatic inspection reduces the possibility of omissions, improves the adequacy of verification, and ensures the correctness and reliability of the storage controller in the actual design.

[0049] In a specific embodiment of the present invention, for example, please refer to Figure 4 ,In the IP verification platform (IP verification involves ,verification of the designed functional modules), the sequence verification structure (i.e. the virtual ,verification device) can be used to convert the interface timing generated by the ,memory controller into result events through the timing converter (i.e. the ,timing conversion module), and the result events are stored in the result event queue (i.e. the second queue module).

[0050] Expected events can be generated in two ways. One is to generate events from incentive content, and the other is to use the result events generated after the previous verification as the later expected events. The expected events are stored in the expected event queue (i.e., the first queue module).

[0051] In the queue comparison module, the expected events in the expected event queue are compared with the result events in the result event queue one by one to verify whether the function of the memory controller meets the design expectations. At the same time, the timeout detection module detects whether the time for storing the result event in the result event queue has timed out. If a timeout occurs, the verification memory controller is turned off and a timeout detection error is output.

[0052] Please refer to Figure 5 , which is the IP verification process of the memory controller performed by the verification device proposed in the present invention (i.e., the process of verifying whether the hardware description language code of the memory controller is correct). Figure 6 As shown, it is the original IP verification process for verifying the memory controller. In the original verification process, if the memory changes, the test case needs to be modified accordingly for verification; in the verification process of the present invention, a verification method for comparing expected events with result events is provided to cover functional detection, and the form of events is unified, so there is no need to modify and adjust the test case accordingly each time. In addition, in the verification process of the present invention, since the interface timing of the memory controller will be responded to as an event, IP verification can be completed even without the participation of the behavioral model, which speeds up the verification time of the memory controller.

[0053] In a specific embodiment of the present invention, for example, please refer to Figure 7 In the SOC (system on chip) verification platform, the use of sequence verification structure (i.e. virtual verification device) can traverse various application scenarios in regression testing, automatically check whether the controller's command conversion is correct and whether the timing output is correct, so that the functional verification is fully covered and the error feedback is rapid during dynamic verification. In the Netlist (netlist, a text file that describes the connectivity of electronic circuits) verification platform, not only the timing can be fully checked, but also the result event text saved during SOC verification is used as the expected event queue during Netlist verification for formal verification to verify the consistency of SOC and Netlist functions under the same test case configuration. Since the interface timing of the memory controller is detected, the sequence verification structure used by SOC and Netlist is exactly the same as IP verification, without any modification.

[0054] Please refer to Figure 8 In SOC design, regression verification is required to ensure the correct function of the memory controller, but traditional functional verification cannot complete the detailed inspection of the memory being accessed. Therefore, the modification of the SOC design may cause the performance and efficiency of the actual memory access of the bus to decrease, and it cannot be discovered in time. When the verification device proposed by the present invention is used for verification, all memory access events can be retained during the regression verification of the SOC, and then it can be intuitively observed whether the code changes will affect the memory access efficiency of the storage controller.

[0055] In one embodiment of the present invention, please refer to Fig. 9 , which shows a flow chart of a storage controller verification method provided in some embodiments of the present disclosure. The verification method is executed by the above-mentioned verification device 100, and includes the following steps: When verifying the storage controller to be verified, S100 generates a corresponding interface timing after inputting the stimulus content of the operation to be verified into the storage controller to be verified.

[0056] S200 generates a result event after monitoring that the interface timing of the operation to be verified is consistent with the interface timing specification of the corresponding operation of the memory; and stores the result event in a result queue.

[0057] S300 compares and analyzes the result queue with the expected queue to identify whether the storage controller to be verified has passed the verification; the expected queue stores the expected event corresponding to the stimulus content.

[0058] Specifically, during the dynamic verification process of the storage controller, it is first necessary to input a series of stimulus contents of the operations to be verified. The stimulus contents should cover all functional points of the storage controller, usually including various read and write commands, address signals, data signals, and control signals.

[0059] After inputting the stimulus content of the operation to be verified, the storage controller will generate the corresponding interface timing according to its internal logic and design specifications. These timing signals include the start and end time of data transmission, synchronous or asynchronous control of read and write operations, and various clock and delay signals required when interacting with the on-chip system or memory.

[0060] In order to verify that the storage controller can operate correctly, the verification process also needs to closely monitor the timing of these interfaces to check whether they meet the expected specifications and standards. During the digital circuit and chip verification process, the storage controller or any digital interface needs to meet the timing requirements of the data sheet under all expected operating conditions to ensure the performance and reliability of the storage controller.

[0061] During the interface timing detection process of the storage controller, it is necessary to verify that each interface timing can accurately meet the interface timing specifications required in the data sheet of the corresponding memory. For example, when the storage controller generates a specific timing response. Once it is detected that the interface timing matches the interface timing specification of the corresponding operation, a result event will be automatically generated. The generated result event is stored in a special result queue, which is a dynamic data structure used to temporarily store the result events generated during a verification process.

[0062] The result queue includes the result events after the interface timing conversion of the storage controller in response to various stimulus contents during the actual verification process. The expected queue is an ordered set of expected events. The expected event is the event corresponding to the interface timing that the stimulus content is expected to generate through the storage controller. It represents the behavior and performance that the storage controller should exhibit in response to the stimulus content. When the storage controller determines whether it can produce the expected response and behavior after receiving the stimulus content, it is necessary to compare and analyze the result queue obtained from the actual verification with the expected queue corresponding to the stimulus content.

[0063] In this embodiment, the storage controller to be verified may be a logic circuit generated by a hardware description language code file, and the storage controller to be verified also includes an instance of storage controller verification, an instance of SOC verification, and an instance of Netlist verification.

[0064] Before the above step S300, an expectation queue needs to be generated in advance, including: using an expectation generation module to generate an expected event according to the incentive content and storing it in the expectation queue; or, using the result queue generated after the operation to be verified passes the previous verification as the expectation queue for the later verification.

[0065] Specifically, the expectation queue is generated dynamically, and the result event is generated dynamically with the injection of stimulus. The memory controller can be operated in the test case, and the expectation generation module stores the event corresponding to the operation in the result queue. Dynamic configuration can be used to unify the code logic of automated verification in the verification test case, and improve the readability and reusability of the test case in different project verifications.

[0066] In addition, another method in the verification process is to generate the expected queue in a static way, use the result queue of the previous verification as the expected queue for the later verification, and load the result queue after the previous verification into the verification environment by importing text. This method is based on the assumption that if the storage controller exhibits correct behavior in the previous verification, then these behaviors can be used as reference standards for subsequent verification. For example, the result event queue saved by the SoC verification instance can be used as the expected event queue of the Netlist verification instance to verify the consistency of the SOC and Netlist functions under the same test case configuration. In this way, an equivalent verification process can be constructed, in which the verification of each stage is based on the verification results of the previous stage, with high information content and strong reusability.

[0067] Before the above step S300, the method further includes the following steps: detecting whether the storage update time of the result queue has timed out, and if timed out, shutting down the verification storage controller and printing out the timeout detection error.

[0068] Specifically, monitoring the result queue's deposit update time is a critical real-time check that verifies whether the storage controller can respond to stimulus content and generate result events within the specified time, thereby verifying whether its performance meets the design specifications. If the result queue's update time times out, it means that the storage controller has failed to complete the operation within the expected time, which may indicate a performance problem or potential failure of the storage controller.

[0069] Once a timeout is detected, immediate action is taken to respond to the abnormal situation. First, the process of verifying the memory controller executed by the test case is automatically shut down, and a timeout error is printed out to prevent memory controller design errors, such as internal deadlocks that prevent verification from continuing to run normally. The timeout detection error message printed out can contain detailed information about the timeout event, such as the time point when the timeout occurred, the related stimulus content, and possible cause analysis.

[0070] Through the storage controller verification method proposed in the present invention, it is possible to directly check whether the functions of the storage controller are correct without relying on the memory behavior model, and it is possible to systematically verify whether the interface timing of the storage controller meets the design specifications, and to discover and correct problems in a timely manner, thereby greatly improving the observability of the storage controller.

[0071] In one embodiment of the present invention, before verifying the storage controller to be verified, it is necessary to extract the timing parameters in the interface timing specification and their corresponding timing parameter relationships, including the following steps: extracting a number of first timing parameters and a number of first timing parameter relationships from the interface timing specification; the first timing parameters and the first timing parameter relationships are the conditions that need to be met for the item to be verified to perform any operation.

[0072] Specifically, in this embodiment, the first timing parameter and the first timing parameter relationship of the interface timing specification are extracted to form the timing conversion module in the above embodiment, which is consistent with the working mechanism described in the timing conversion module in the above embodiment and will not be repeated here.

[0073] In one embodiment of the present invention, after detecting that the interface timing meets the interface timing specification of the corresponding operation of the memory, a result event is generated. Please refer to Fig.10 The above step S200 further includes: S210 acquires second timing parameters of the interface timing to be detected from the interface timing, and detects whether the second timing parameters correspond to the first timing parameters respectively.

[0074] S220: When the second timing parameter corresponds to the first timing parameter, obtain a second timing parameter relationship of the interface timing to be detected, and detect whether the second timing parameter relationship is consistent with the corresponding first timing parameter relationship.

[0075] S230: When the second timing parameter relationship corresponds to the first timing parameter relationship, a result event is generated; otherwise, an error prompt message is generated.

[0076] Specifically, during the monitoring process, when an interface signal with a timing relationship changes, the assertion will be triggered and the start time will be recorded; it will continue until another interface signal with the timing relationship changes, at which time the assertion ends and the end time is recorded. The assertion will then call a function to check whether the interval between the start and end times meets the timing parameter requirements of the memory, and retain the judgment result returned by the function.

[0077] After monitoring that the level combination of the interface timing is one of any operations of the memory, the judgment result saved by the assertion corresponding to the timing relationship related to the operation is triggered. When all the judgment results are free of errors, a result event will be generated. If it is found during the detection process that the correspondence between the second timing parameter relationship and the first timing parameter relationship is inconsistent, an error prompt message will be generated. The error prompt message can explain which timing relationships fail to meet the timing parameter requirements, which is convenient for analyzing the results and diagnosing the problem. After the storage controller is redesigned and modified, verification is performed again to verify whether the problem has been resolved.

[0078] Please refer to Figure 3 Each monitoring assertion has a corresponding trigger condition. For example, the start and end of the monitoring assertion a_ce_we_setup is: CE rising edge -> WE rising edge; the start and end of the monitoring assertion a_prog_widthl is: PROG falling edge -> PROG rising edge. At the end, the function in the timing parameter verification function library will be called to determine whether the timing parameter requirements are met, and the judgment result returned by the function will be saved.

[0079] When the timing interface is monitored to have a level combination: CE=1, WE=1, PROG=1, it is determined that the current operation is a memory programming operation, and the judgment results of the monitoring assertions a_ce_we_setup, a_ad_we_setup, a_we_pr_setup, a_da_pr_setup, a_da_pr_hold, a_prog_widthl, and a_prog_widthh are checked. When the judgment results saved by the monitoring assertions are all correct, the event is output (i.e., the event shown in the figure). The output form of the result event is a data structure, which can be in the form of: programming operation-programming address-programming data.

[0080] The storage controller verification method proposed in the present invention can check whether the interface timing of the storage controller meets the expected performance standard in design and implementation, thereby improving the verification quality and the speed of finding errors.

[0081] In one embodiment of the present invention, there are multiple situations when identifying whether the storage controller to be verified has passed the verification. Herein, one of the situations is described. The above step S300 includes: S310 compares the result events stored in the result queue with the expected events stored in the expected queue one by one to see if they are consistent; if they are consistent, the storage controller to be verified passes the verification; otherwise, the storage controller to be verified fails the verification.

[0082] Specifically, by comparing each result event in the result queue with the corresponding expected event in the expected queue one by one, the result event corresponding to the current interface timing of the storage controller in the test case and all the timings can be dynamically obtained to verify the correctness. If the events in the result queue are completely consistent with the events in the expected queue, it means that the storage controller to be verified has exhibited the expected behavior in the test scenario, and thus the verification has passed. If any inconsistent event is found during the comparison process, the storage controller to be verified fails the verification, and a detailed comparison result is generated, indicating the specific differences and possible causes.

[0083] Another example of verifying the storage controller function is described below. Fig.11 , the above step S300 further includes: S320 compares and analyzes whether the number of occurrences of the same result event in the result queue exceeds a preset number.

[0084] If the number of times does not exceed the preset number in S330, the storage controller to be verified has passed the verification; otherwise, the storage controller to be verified has failed the verification.

[0085] Specifically, for example, when verifying the function of the prefetch control module of the storage controller, if the data corresponding to a certain address is always prefetched, multiple identical result events are generated. This may simply be a performance or efficiency issue. For example, an abnormally high occurrence frequency indicates that there are repeated operations that may be invalid.

[0086] For example, during SOC verification, regression verification is used to ensure that the functions of the memory controller are correct, but the performance and efficiency of bus memory access cannot be fed back in time, and the modification of requirements may also lead to a decrease in the performance and efficiency of bus memory access. However, through the verification method proposed by the present invention, when SOC performs regression verification, all memory access events can be retained, and then it can be intuitively observed whether changes in other codes will affect the memory access efficiency of the storage controller.

[0087] Through the storage controller verification method proposed in the present invention, by comparing the events in the result queue and the expected queue, it is possible to effectively discover what kind of unexpected operation errors the memory controller has generated, and monitor all memory operations that have occurred, fully exposing the problems of insufficient efficiency and performance, and improving the coverage and adequacy of verifying the storage controller.

[0088] In one embodiment of the present invention, the verification device of the storage controller is generated by hardware description language code, and includes a processor and a storage unit, wherein the storage unit is used to store a computer program; the processor is used to execute the computer program stored in the storage unit to implement the verification method of the storage controller in the above-mentioned corresponding method embodiment.

[0089] The storage unit may be an internal storage unit of the terminal device, such as a hard disk or memory of the terminal device. The storage unit may also be an external storage device of the terminal device, such as a plug-in hard disk equipped on the smart device, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. Further, the storage unit may also include both an internal storage unit of the device terminal and an external storage device. The storage unit is used to store the computer program and other programs and data required by the terminal device. The storage unit may also be used to temporarily store data that has been output or is to be output.

[0090] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0091] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented with electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed with hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0092] It should be noted that the above embodiments can be freely combined as needed. The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered as the protection scope of the present invention.

Claims

1. A storage controller verification method, characterized in that: include: When verifying the storage controller to be verified, after inputting the stimulus content of the operation to be verified into the storage controller to be verified, a corresponding interface timing is generated; After monitoring that the interface timing of the operation to be verified complies with the interface timing specification of the corresponding operation of the memory, a result event is generated; Storing the result event in a result queue; The result queue is compared and analyzed with the expected queue to identify whether the storage controller to be verified has passed the verification; the expected queue stores the expected events corresponding to the stimulus content.

2. The storage controller verification method according to claim 1, characterized in that: The comparing and analyzing the result queue with the expected queue to identify whether the storage controller to be verified has passed the verification includes: Compare the result events stored in the result queue with the expected events stored in the expected queue one by one to see if they are consistent; if they are consistent, the storage controller to be verified passes the verification; otherwise, the storage controller to be verified fails the verification; the storage controller to be verified includes an instance of storage controller verification, an instance of SOC verification, and an instance of Netlist verification.

3. The storage controller verification method according to claim 1, characterized in that: The comparing and analyzing the result queue with the expected queue to identify whether the storage controller to be verified has passed the verification further includes: Analyzing whether the number of occurrences of the same result event in the result queue exceeds a preset number; If the number of times does not exceed the preset number, the verification of the storage controller to be verified is passed; otherwise, the verification of the storage controller to be verified is failed.

4. The storage controller verification method according to claim 1, characterized in that: Before verifying the storage controller to be verified, the method includes: A plurality of first timing parameters and a plurality of first timing parameter relationships are extracted from the interface timing specification; the first timing parameters and the first timing parameter relationships are conditions that need to be satisfied for the item to be verified to perform any operation.

5. The storage controller verification method according to claim 1, characterized in that: After the interface timing of the operation to be verified is monitored to be consistent with the interface timing specification of the corresponding operation of the memory, a result event is generated, including: Acquire second timing parameters of the interface timing to be detected from the interface timing, and detect whether the second timing parameters correspond to the first timing parameters respectively; When the second timing parameter corresponds to the first timing parameter, obtaining a second timing parameter relationship of the interface timing to be detected, and detecting whether the second timing parameter relationship is consistent with the corresponding first timing parameter relationship; When the second timing parameter relationship corresponds to and is consistent with the first timing parameter relationship, the result event is generated; otherwise, an error prompt message is generated.

6. The storage controller verification method according to claim 1, characterized in that: Before comparing and analyzing the result queue with the expected queue, the expected queue includes: Using an expectation generation module to generate an expected event according to the incentive content, and storing the expected event in the expectation queue; Or, the result queue generated after the operation to be verified passes the preliminary verification is used as the expected queue for the subsequent verification.

7. The storage controller verification method according to claim 1, characterized in that: When comparing and analyzing the result events in the result queue with the expected events in the expected queue, the method further includes: Detect whether the storage update time of the result queue has timed out. If timeout occurs, close and verify the storage controller, and print out the timeout detection error.

8. A verification device for a storage controller, characterized in that: The verification device of the storage controller is generated by a hardware description language code file, and includes a processor and a storage unit, which is used to call instructions stored in the storage unit. When the instructions are executed, they are executed to implement the operations performed by the verification method of the storage controller as described in any one of claims 1-7.

9. A virtual verification device for a storage controller, characterized in that: include: The first queue module is used to store the expected events generated according to the incentive content; A timing conversion module, used for converting the interface timing generated by the storage controller to be verified according to the stimulus content into a result event; A second queue module, used for storing the result event generated by the timing conversion module; The queue comparison module is used to compare and analyze the expected event with the result event one by one to identify whether the storage controller to be verified has passed the verification.

10. The virtual verification device of the storage controller according to claim 9, characterized in that: Also includes: The first queue module is further used to store the result event generated after the previous verification, and use the result event as the expected event for the later verification; And / or, a timeout detection module, used to detect whether the storage update time of the result event of the second queue module has timed out.

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