An offload memory transaction acceleration device, system, method, and storage medium

Abstract

Embodiments of the present application provide an offload memory transaction acceleration device, system, method and storage medium, which belong to the technical field of data processing. The device comprises: an acceleration unit configured to receive a write transaction sent by a processor core, and the acceleration unit is provided with a cache interface and a non-cache interface; an acceleration interconnection component adopts a target shared access mode, and the acceleration interconnection component processes one write transaction at a time in the target shared access mode; when the acceleration interconnection component is currently processing a write transaction of cache data sent by the cache interface, the acceleration interconnection component initiates a write transaction operation of the cache data to the cache consistency control component to write the cache data into the cache; and when the acceleration interconnection component is currently processing a write transaction of non-cache data sent by the non-cache interface, the acceleration interconnection component initiates a write transaction operation of the cache data to the controller memory interconnection component to write the non-cache data into the memory. Embodiments of the present application aim to avoid the deadlock problem occurring in the memory transaction processing process.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of data processing, in particular, relate to an offloading memory transaction acceleration device, system, method and storage medium. BACKGROUND

[0002] With the development of data processing technology, the storage demand of data is gradually increasing. At present, multi-core architecture is adopted to increase the concurrent processing capability of the system, such as using multiple central processing units (CPUs) to improve the energy utilization rate of the storage system. When the CPU performs memory operation on the memory, if the traditional direct memory read or write operation is adopted, a large blocking and time delay will be generated, thereby reducing the computing power of the CPU. At present, a hardware acceleration unit is used to offload the read and write transaction operations of the memory, which can reduce the waiting time and burden of the CPU, and can accelerate the data processing and transmission process.

[0003] In order to solve the problem of maintaining cache consistency in multi-core processing applications, ARM proposes AXI4 bus protocol and ACE bus protocol and corresponding cache consistency controller components to realize cache consistency. However, when the hardware acceleration unit is used at the same time, the cache consistency controller and the hardware acceleration unit may access the memory resource through the AXI bus component at the same time, which causes the operations of the two to conflict with each other and easily causes the problem of deadlock. SUMMARY

[0004] Embodiments of the present application provide an offloading memory transaction acceleration device, system, method and storage medium, which aims to avoid the problem of deadlock in the memory transaction processing process.

[0005] In a first aspect, an offloading memory transaction acceleration device is provided, which is applied to a system on chip. The system on chip includes a processor core, a cache consistency control component and a controller memory interconnection component. The device includes an acceleration unit and an acceleration interconnection component, wherein:

[0006] The acceleration unit is configured to receive a write transaction sent by the processor core. The acceleration unit is provided with a cache interface and a non-cache interface. The cache interface is configured to receive a write transaction of cache data sent by the processor core. The non-cache interface is configured to receive a write transaction of non-cache data sent by the processor core.

[0007] The acceleration interconnection component adopts a target shared access mode. In the target shared access mode, the acceleration interconnection component processes one write transaction at a time.

[0008] initiating, by the acceleration interconnect component, a write transaction operation of the cache data to the cache coherency control component to write the cache data to cache when the acceleration interconnect component is currently processing a write transaction of the cache data sent by the cache interface;

[0009] initiating, by the acceleration interconnect component, a write transaction operation of the cache data to the cache coherency control component to write the cache data to cache when the acceleration interconnect component is currently processing a write transaction of the cache data sent by the cache interface;

[0010] Optionally, when the acceleration interconnect component initiates the write transaction operation of the cache data to the cache coherency control component, if the cache is full, the cache coherency control component initiates a memory coherency operation and sends pause information to the acceleration interconnect component;

[0011] The acceleration interconnect component is configured to pause processing any write transaction in response to the pause information.

[0012] When the memory coherency operation is performed, the cache coherency control component is configured to send evicted data in the cache to the controller memory interconnect component and write the evicted data to memory.

[0013] Optionally, the acceleration interconnect component is provided with a cache data queue and a non-cache data queue, both of which are first-in-first-out queues, the cache data queue is configured to store write transactions of cache data sent by the cache interface, and the non-cache data queue is configured to store write transactions of non-cache data sent by the non-cache interface.

[0014] The acceleration interconnect component is configured to select one write transaction in the cache data queue or the non-cache data queue for processing each time.

[0015] Optionally, the acceleration interconnect component is configured to poll and select a write transaction in the cache data queue or the non-cache data queue for processing each time.

[0016] Optionally, different priorities are set for the cache data queue and the non-cache data queue, the acceleration interconnect component is configured to obtain a write transaction from the queue with a higher priority for processing each time, and when the queue with a higher priority does not contain a write transaction, obtain a write transaction from the queue with a lower priority for processing.

[0017] Optionally, any write transaction of cache data or non-cache data includes a write address transaction and a write data transaction.

[0018] The acceleration interconnect component includes a write address transaction processor and a write data transaction processor.

[0019] When the write address transaction processor and the write data transaction processor determine that the current transaction is a write transaction of non-cache data, the acceleration interconnection component is configured to send the address information and the data information of the non-cache data to the controller memory interconnection component, and the controller memory interconnection component is configured to write the data information of the non-cache data into the memory at a position corresponding to the address of the non-cache data.

[0020] When the write address transaction processor and the write data transaction processor determine that the current transaction is a write transaction of cache data, the acceleration interconnection component is configured to send the address information and the data information of the cache data to the cache coherence control component.

[0021] If the target cache in the multi-level cache corresponding to the address information of the cache data is not full, the cache controller in the cache coherence control component is configured to write the data information of the cache data into a position corresponding to the address information of the cache data.

[0022] If the target cache in the multi-level cache corresponding to the address information of the cache data is full, the cache controller in the cache coherence control component is configured to determine evicted data in the target cache, send the evicted data to the controller memory interconnection component, write the evicted data into the memory, and send pause information to the acceleration interconnection component.

[0023] The acceleration interconnection component is configured to pause processing of any write transaction in response to the pause information.

[0024] Optionally, when the acceleration interconnection component pauses processing of any write transaction, if the acceleration interconnection component receives continue processing information sent by the cache coherence control component, the acceleration interconnection component is configured to continue processing of any write transaction in response to the continue processing information.

[0025] In a second aspect, an embodiment of the present application provides an on-chip system, which includes a processor core, a cache coherence control component, and a controller memory interconnection component, and further includes the offload memory transaction acceleration device of the first aspect.

[0026] In a third aspect, an embodiment of the present application provides a memory transaction processing method, which is applied to the on-chip system of the second aspect, and further includes:

[0027] In response to a write transaction processing instruction of any processor, according to a data type corresponding to the write transaction, determining whether to send the write transaction to a cache interface or a non-cache interface of an acceleration unit.

[0028] The acceleration interconnection component determines a current processing write transaction, initiates a cache data write transaction operation to the cache coherence control component when the current processing write transaction is a cache data write transaction, and initiates a cache data write transaction operation to the controller memory interconnection component to write the non-cache data into the memory when the current processing write transaction is a non-cache data write transaction.

[0029] When the cache of the system on chip is full, the cache coherence control component initiates a memory coherence operation and sends a pause information to the acceleration interconnection component.

[0030] The acceleration interconnection component pauses processing any write transaction in response to the pause information.

[0031] In a fourth aspect, an embodiment of the present application provides a non-volatile readable storage medium, which stores a computer program, wherein the computer program is executed by a processor to perform the memory transaction processing method in the third aspect.

[0032] Advantages:

[0033] The unloading memory transaction acceleration device provided in the embodiment is applied to a system on chip, the system on chip includes a processor core, a cache coherence control component and a controller memory interconnection component, and the device includes an acceleration unit and an acceleration interconnection component.

[0034] The acceleration unit includes a cache interface and a non-cache interface, the cache interface is used to receive a cache data write transaction sent by the processor core, and the non-cache interface is used to receive a non-cache data write transaction sent by the processor core; and the acceleration interconnection component adopts a target shared access mode, in which the acceleration interconnection component processes one write transaction at a time.

[0035] When the acceleration interconnection component currently processes a cache data write transaction sent by the cache interface, the cache coherence control component is initiated to perform a cache data write transaction operation to write the cache data into the cache; and when the acceleration interconnection component currently processes a non-cache data write transaction sent by the non-cache interface, the controller memory interconnection component is initiated to perform a cache data write transaction operation to write the non-cache data into the memory.

[0036] Further, the data that needs to be written into the cache or does not need to be written into the cache is classified and then processed in a write transaction, and the acceleration interconnection component can only process one unfinished write transaction at a time in the target shared access mode, so that the write transaction processing processes of the cache data and the non-cache data do not conflict, and the deadlock problem in the memory transaction processing process is avoided. BRIEF DESCRIPTION OF DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or prior art description will be briefly introduced.

[0038] Figure 1 A functional module diagram of the offload memory transaction acceleration device provided by the embodiments of the present application is shown;

[0039] Figure 2 An architecture schematic diagram of the system on chip provided by the embodiments of the present application is shown;

[0040] Figure 3 A step flowchart of the memory transaction processing method provided by the embodiments of the present application is shown;

[0041] Figure 4 A schematic diagram of the non-volatile readable storage medium provided by the embodiments of the present application is shown. DETAILED DESCRIPTION

[0042] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

[0043] In order to make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the embodiments of the present application will be described in detail below with reference to the drawings. However, those skilled in the art can understand that, in the embodiments of the present application, many technical details are presented in order to make the readers better understand the present application. However, the technical solutions claimed by the present application can be implemented even without these technical details and based on various changes and modifications of the following embodiments. The division of the following embodiments is for the convenience of description, and should not constitute any limitation on the specific implementation of the present application, and the embodiments can be combined and referenced with each other without contradiction.

[0044] SSD: Solid State Disk, solid state disk;

[0045] CPU: Central Processing Unit, central processor;

[0046] SOC: System on Chip, system on chip;

[0047] AXI: Advanced Xtensible Interface, Advanced Xtensible Interface, is a high-level extensible on-chip bus with high performance, high bandwidth and low latency;

[0048] ACE: AXI Coherency Extensions, AXI Coherency Extensions;

[0049] CCI: Cache Coherent Interconnect, cache coherent interconnect component

[0050] CMUIC: Controller Memory Unit Interconnect Controller, controller memory unit interconnect controller

[0051] DDR / SRAM: Double Data Rate, Synchronous Dynamic Random Access Memory, double data rate, synchronous dynamic random access memory

[0052] ME: MoveEngine, acceleration unit

[0053] ACC: Acceleration Module, offload memory transaction acceleration device

[0054] With the development of data processing technology, the storage demand of data is gradually increasing. At present, multi-core architecture is adopted to increase the concurrent processing capability of the system. For example, multiple CPUs are used to improve the energy utilization rate of the storage system. When the CPU performs memory operations on the memory, if the traditional direct memory read or write operation is used, a large blocking and time delay will be generated, thereby reducing the computing power of the CPU. The hardware acceleration unit offloads the read and write transaction operations of the memory, reduces the waiting time and burden of the CPU, and can accelerate the data processing and transmission process.

[0055] The hardware acceleration unit can perform memory coherent and non-coherent operations on the memory at the same time. When the hardware acceleration unit performs memory coherent operation, it will pass through the cache. The cache is managed and maintained by the cache controller. When the cache is full, the cache will perform data invalidation operation at the same time, flush part of the data in the cache to the memory, and complete the action of deleting the part of the data in the cache.

[0056] At present, in the multi-core processing scene of the system on chip application, in order to solve the problem of maintaining cache coherence, ARM proposes AXI4 bus protocol and ACE bus protocol and corresponding cache coherence controller components to realize the method of cache coherence. However, if the hardware acceleration unit is continued to be applied in the scene of realizing cache coherence based on the cache coherence controller components, there may be a problem that the cache coherence controller and the hardware acceleration unit use AXI bus components to access the memory at the same time, the operations of the two conflict with each other, and the problem of deadlock is easy to occur.

[0057] Therefore, in order to avoid the deadlock problem in the memory transaction process, the embodiment of the present application provides an offload memory transaction acceleration device.

[0058] Referring to Figure 1 , a functional module diagram of an offload memory transaction acceleration device provided by the embodiment of the present application is shown, the device includes an acceleration unit and an acceleration interconnection component, the acceleration unit is denoted as ME, the acceleration unit is used to receive the write transaction sent by the processor core, the acceleration unit is provided with a cache interface and a non-cache interface, the cache interface is used to receive the write transaction of the cache data sent by the processor core, and the non-cache interface is used to receive the write transaction of the non-cache data sent by the processor core.

[0059] In a feasible implementation manner, the acceleration interconnection component can be an ACE-Lite interconnection component based on the ACE-Lite protocol, the ACE-Lite interconnection component adopts a target shared access mode, which can be an N-to-M shared access mode, in the N-to-M shared access mode, the acceleration interconnection component, i.e., the ACE-Lite interconnection component, processes one write transaction at a time.

[0060] The offload memory transaction acceleration device described in the embodiment is applied to a system on chip (SOC), the system on chip includes a plurality of processor cores, a cache coherence control component, a controller memory interconnection component, and a memory DDR.

[0061] Referring to Figure 2 , a schematic diagram of the architecture of a system on chip provided by the embodiment of the present application is shown, the SOC includes a plurality of processor cores, such as CPU-0 …… CPU-x, CPU-N, the plurality of CPU cores can improve the concurrent processing capability of the system on chip; the ARM system of the SOC includes a cache and a cache coherence control component, the cache coherence control component is used to connect the CPU core, the ME, and the memory DDR, and is used to ensure the cache coherence across different components, the cache coherence control component further includes a cache controller, the cache controller is used to perform the read, write, and invalidation processes of data of the cache; the controller memory interconnection component is used to write the data sent by the cache controller and the non-cache data sent by the acceleration interconnection component into the memory, and the controller memory interconnection component includes an AXI connection component.

[0062] AXI is a high-level, scalable, on-chip bus defined by ARM Company, which is high performance, high bandwidth and low latency. AXI defines five independent channels between master and slave: write address channel, write data channel, write response channel, read address channel and read data channel. The address channel is used to send address and control information between master and slave during basic handshake. The data channel is used for master to write data to slave and slave to read data from master. The write response information has a dedicated channel so that the master can verify whether the write transaction is completed. Each data exchange is called a transaction, which includes address and control information, transmitted data and any response information.

[0063] The device sets two API interfaces: non-cache interface API1 and cache interface API2 in the acceleration unit, and uses the two API interfaces as AXI master. When receiving a write transaction of data sent by any CPU core, the device sends the data to the corresponding API interface according to whether the data is cache data that needs to be written into cache or non-cache data that needs to be written into memory directly. The non-cache interface API1 and the cache interface API2 send the write transaction of data to the acceleration interconnection component.

[0064] In this embodiment, the acceleration interconnection component is an ACE-Lite interconnection component based on N-to-M shared access mode. In the N-to-M shared access mode, the ACE-Lite interconnection component processes one write transaction at a time. For each connected master (non-cache interface API1 and cache interface API2), the arbiter of the ACE-Lite interconnection component selects one write transaction from the requesting master for processing. After the data transmission is completed, arbitration of the next request is performed, and the next write transaction is executed.

[0065] In a possible implementation, in order to store the write transactions sent by the two interfaces of the acceleration unit, the acceleration interconnection component is provided with a cache data queue and a non-cache data queue. The cache data queue and the non-cache data queue are both first-in-first-out queues. The cache data queue is used to store the write transaction of cache data sent by the cache interface, and the non-cache data queue is used to store the write transaction of non-cache data sent by the non-cache interface. The acceleration interconnection component is used to select one write transaction in the cache data queue or the non-cache data queue for processing at a time.

[0066] For example, the acceleration interconnection component can poll and select a write transaction in the cache data queue or the non-cache data queue for processing at a time, that is, one write transaction in the cache data queue is obtained for processing, and then one write transaction in the non-cache data queue is obtained for processing, and the two types of write transactions are processed in this way.

[0067] In actual implementation, different priorities can be set for the cache data queue and the non-cache data queue, and the acceleration interconnection component is configured to process a write transaction from a queue with a higher priority each time until no write transaction is contained in the queue with the higher priority, and then process a write transaction from a queue with a lower priority.

[0068] For example, the data in the cache is data with a higher processing frequency, and thus the write transaction entering the cache can be processed preferentially, and the cache data queue can be set to have a high priority. The data written into the memory can be slightly delayed compared with the data written into the cache, and thus the non-cache data queue can be set to have a low priority.

[0069] When the cache data queue contains a write transaction to be processed, the acceleration interconnection component processes the write transaction in the cache data queue in sequence and individually until no write transaction is contained in the cache data queue, and then processes a write transaction from the non-cache data queue in sequence and individually. When a new write transaction is added to the cache data queue, the acceleration interconnection component can jump to processing the new write transaction in the cache data queue.

[0070] In another possible implementation, a continuous processing times threshold can also be set. When the number of times that the acceleration interconnection component processes the write transaction in the cache data queue continuously is greater than a first continuous processing times threshold, the write transaction in the non-cache data queue can be processed. When the number of times that the acceleration interconnection component processes the write transaction in the non-cache data queue continuously is greater than a second continuous processing times threshold, the write transaction in the cache data queue is continuously processed, thereby avoiding a problem that the write transaction in any data queue waits for a long time.

[0071] In actual application, the arbitration manner in which the acceleration interconnection component processes the write transaction in the cache data queue or the non-cache data queue can also be customized according to actual application requirements.

[0072] When the acceleration interconnection component currently processes the write transaction of the cache data sent by the cache interface, the write transaction operation of the cache data is initiated to the cache consistency control component, so as to write the cache data into the cache.

[0073] When the acceleration interconnection component currently processes the write transaction of the non-cache data sent by the non-cache interface, the write transaction operation of the cache data is initiated to the controller memory interconnection component, so as to write the non-cache data into the memory.

[0074] Specifically, any write transaction of cache data or non-cache data includes a write address transaction (Write Address) and a write data transaction (Write Data); the acceleration interconnection component includes a write address transaction processor and a write data transaction processor.

[0075] When the acceleration interconnection component obtains a write transaction from any data queue for processing, including the write address transaction Write Address and the write data transaction Write Data of the write transaction, and then through the address transaction processor and the write data transaction processor, the slave device corresponding to the write transaction is determined.

[0076] When the write address transaction processor and the write data transaction processor determine that the current transaction being processed is a write transaction of non-cache data, the ACE-AXI component is taken as a slave device, and the address information and data information of the non-cache data are sent to the AXI connection component in the controller memory interconnection component through the ACE-AXI component after protocol conversion, and the AXI interface is used to send the non-cache data to the controller memory interconnection component, which is used to write the data information of the non-cache data into the memory at the position corresponding to the address of the non-cache data.

[0077] When the write address transaction processor and the write data transaction processor determine that the current transaction being processed is a write transaction of cache data, the ACE-LS interface of the ARM system is taken as a slave device, and the address information and data information of the cache data are sent to the cache coherence control component to write the cache data into the cache.

[0078] When the acceleration interconnection component initiates a write transaction operation of cache data to the cache coherence control component, if the cache is full, the cache needs to remove part of the evicted data from itself to release space to store the data information of the write transaction sent by the acceleration interconnection component. The cache determines the way of evicting data, which can be customized according to the actual application requirements, such as taking the data with the minimum access frequency as the evicted data.

[0079] After determining the evicted data, the cache coherence control component needs to initiate a memory coherence operation, that is, to write the evicted data in the memory. At this time, the cache controller in the cache coherence control component occupies the interface of the controller memory interconnection component through the AXI-M, writes the evicted data into the memory, and after the writing is completed, stores the data information of the cache data sent by the acceleration interconnection component in the cache at the position corresponding to the address information of the cache data.

[0080] Because the cache controller is occupying the interface of the controller memory interconnection component in the process of writing the evicted data into the memory, the pause information can be sent to the acceleration interconnection component at this time; the acceleration interconnection component is configured to pause processing any write transaction in response to the pause information, so as to further avoid the problem of deadlock.

[0081] In a feasible implementation, the cache can also be a multi-level cache, such as a level one cache L1, a level two cache L2, and a level three cache L3. If the target cache in the multi-level cache corresponding to the address information of the cache data is not full, the cache controller in the cache coherence control component is configured to write the data information of the cache data into the position corresponding to the address information of the cache data.

[0082] If the target cache in the multi-level cache corresponding to the address information of the cache data is full, the cache controller in the cache coherence control component is configured to determine the evicted data in the target cache, send the evicted data to the controller memory interconnection component, write the evicted data into the memory, and send pause information to the acceleration interconnection component; the acceleration interconnection component is configured to pause processing any write transaction in response to the pause information.

[0083] When the acceleration interconnection component pauses processing any write transaction, if the acceleration interconnection component receives the continue processing information sent by the cache coherence control component, the acceleration interconnection component is configured to continue processing any write transaction in response to the continue processing information.

[0084] To illustrate the deadlock problem of the existing cache coherence controller and hardware acceleration unit, specifically, there is only one master device in the existing acceleration unit to perform the write transaction of cache data and non-cache data, that is, the acceleration unit with one master device simultaneously performs the write transaction of cache data and non-cache data.

[0085] Suppose that at this time, the write transaction processing in the first-in-first-out queue should be write transaction 1 (Write Address1 and Write Data1), write transaction 2 (Write Address2 and Write Data2), and write transaction 3 (Write Address3 and Write Data3) in turn, and write transaction 1 and write transaction 2 are for cache data, and write transaction 3 is for non-cache data.

[0086] At this time, the acceleration unit initiates the write transaction 1 and the write transaction 2 of the cache data, and first writes the Write Address 1 and the Write Address 2 into the full cache. Since the speed of writing the non-cache data into the memory is faster than the speed of writing the evicted data in the cache into the memory, at this time, the acceleration unit initiates the write transaction 3 of the non-cache data, that is, the address of the Write Address 3 has been written into the AXI connection component, and only the Write Data 3 corresponding to the write transaction 3 is waited for.

[0087] The cache needs to perform a data invalidation operation, and after the evicted data is written into the memory, the process needs to occupy the interface of the AXI connection component in the controller memory interconnection component of the write memory. Since the address of the Write Address 3 has been written into the AXI connection component at this time, the Write Data 3 corresponding to the write transaction 3 is being waited for, that is, because the acceleration unit of the write transaction 3 always occupies the AXI interconnect, the evicted data cannot occupy the interface of the AXI connection component to complete the write memory process.

[0088] As for the Write Data 3 of the write transaction 3, since based on the first-in-first-out queue, only after the data of the write transaction 1 and the write transaction 2, that is, the Write Data 1 and the Write Data 2, are written into the cache, the data transmission process of sending the Write Data 3 to the AXI connection component can be performed. However, the precondition of writing the Write Data 1 and the Write Data 2 into the cache is that the evicted data in the cache is written into the memory, and because the AXI connection component is occupied by the write transaction 3 in progress, the evicted data cannot complete the write memory operation, and thus the Write Data 1 and the Write Data 2 cannot complete the write cache. In the case that the Write Data 1 and the Write Data 2 cannot complete the write cache, the Write Data 3 also cannot be processed, thereby forming a deadlock.

[0089] In the device, the cache interface and the non-cache interface are set as two master devices of the AXI in the acceleration unit, the acceleration interconnection component adopts an N-to-M shared access mode, when the two write transactions of writing into the cache and writing into the memory are initiated at the same time, the arbitrator of the acceleration interconnection component selects the cache interface or the non-cache interface as the master device, and enables the transaction transmission operation to the target slave device, and only one memory transaction request is processed at a time. When the write transaction being processed is completed, the next write transaction processing can be performed, that is, after the Write Address and the Write Data of any write transaction are completed, the next write transaction is executed, so that the deadlock problem of the above-mentioned acceleration unit with only one master device does not occur.

[0090] When the non-cache interface is arbitrated as the current master, the write transaction of the non-cache data is sent to the target slave ACE-AXI conversion component, and then to the controller memory interconnection controller, to complete the process of writing the non-cache data into the memory.

[0091] When the cache interface is arbitrated as the current master, the write transaction of the cache data is sent to the target slave ACE-LS interface of the ARM system, and then to the cache coherence control component, to write the cache data into the cache.

[0092] When the cache is full, to avoid the conflict between the process of writing the non-cache data into the memory and the process of writing the evicted data in the cache into the memory, the controller memory interconnection component sends a pause information to the acceleration interconnection component, so that the acceleration interconnection component pauses processing any write transaction in response to the pause information, and then does not continue to write the cache data into the full cache, and does not execute the process of writing the non-cache data into the memory, further avoiding the problem of deadlock.

[0093] Referring to Figure 3 , a step flowchart of a memory transaction processing method provided by an embodiment of the application is shown, which is applied to the system on chip described in the embodiment, and the method comprises the following steps:

[0094] S101: In response to a write transaction processing instruction of any processor, according to the data type corresponding to the write transaction, it is determined whether to send the write transaction to the cache interface or the non-cache interface of the acceleration unit.

[0095] The cache interface stores the write transaction corresponding to the received cache data in the cache data queue; and the non-cache interface stores the write transaction corresponding to the received non-cache data in the cache data queue.

[0096] S102: The acceleration interconnection component determines the current processing write transaction, and when the current processing write transaction is the write transaction of the cache data, initiates the write transaction operation of the cache data to the cache coherence control component; and when the current processing write transaction is the write transaction of the non-cache data, initiates the write transaction operation of the cache data to the controller memory interconnection component, to write the non-cache data into the memory.

[0097] The interface currently serving as the master in the acceleration interconnection component acquires the current processing write transaction from the corresponding queue, and according to the data type, sends the write transaction to the corresponding target slave.

[0098] S103: When the cache of the system on chip is full, the cache coherence control component initiates the memory coherence operation, and sends a pause information to the acceleration interconnection component.

[0099] S104: The acceleration interconnection component suspends processing any write transaction in response to the suspension information.

[0100] When the cache is full, the evicted data in the cache needs to be written into the memory, thus at this time, the suspension information can be sent to the acceleration interconnection component, that is, the acceleration interconnection component can be prevented from continuing to write cache data into the full cache, and the acceleration interconnection component can also be prevented from processing non-cache data writing into the memory, further avoiding the deadlock.

[0101] Referring to Figure 4 , a schematic diagram of a non-volatile readable storage medium provided by an embodiment of the present application is shown, the non-volatile readable storage medium 400 stores a computer program 401, wherein the computer program is executed by a processor to execute the memory transaction processing method provided by the embodiment.

[0102] Each of the embodiments in the specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same and similar parts of each embodiment can be referred to each other.

[0103] Those skilled in the art should understand that the embodiments of the embodiments of the present application can be provided as a method, device, or computer program product. Therefore, the embodiments of the present application can adopt a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Moreover, the embodiments of the present application can adopt the form of a computer program product implemented on one or more computer usable storage media (including but not limited to disk memory, CD-ROM, optical memory, etc.) containing computer usable program code.

[0104] The embodiments of the present application are described with reference to the flowcharts and / or block diagrams according to the method, terminal device (system), and computer program product of the embodiments of the present application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and the combination of the flows and / or blocks in the flowcharts and / or block diagrams can be realized by computer program instructions. These computer program instructions can be provided to a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to produce a machine, so that the instructions executed by the computer or other programmable data processing terminal device produce a device for implementing the functions specified in the flowcharts and / or block diagrams. Figure 1 The device for implementing the functions specified in one flow or multiple flows and / or blocks Figure 1 The device for implementing the functions specified in one flow or multiple flows and / or blocks

[0105] These computer program instructions can also be stored in a computer readable memory capable of guiding a computer or other programmable data processing terminal device to work in a specific manner, so that the instructions stored in the computer readable memory produce a product including instruction devices, which implement the functions specified in the flowcharts and / or block diagrams.Figure 1 one or more processes and / or blocks Figure 1 the function(s) specified in the block or blocks.

[0106] These computer program instructions can also be loaded into computer or other programmable data processing terminal devices, so that a series of operation steps are performed on the computer or other programmable terminal devices to generate computer-implemented processes, thus the instructions executed on the computer or other programmable terminal devices provide a process for implementing the functions specified in the flowchart Figure 1 one or more processes and / or blocks Figure 1 the function(s) specified in the block or blocks.

[0107] Although the preferred embodiments of the present application have been described, those skilled in the art can make additional changes and modifications to these embodiments once they get the basic inventive concept. Therefore, the appended claims are intended to cover all the changes and modifications falling within the scope of the embodiments of the present application.

[0108] Finally, it should be noted that, in the present text, the relational terms such as first and second and the like are used merely to distinguish one entity or operation from another entity or operation, without necessarily requiring or implying any such actual relationship or order between such entities or operations. Moreover, the terms "comprising", "including" or any other variant thereof are intended to cover non-exclusive inclusion, so that processes, methods, articles or terminal devices including a series of elements not only include those elements, but also include other elements not explicitly listed or other elements inherent to such processes, methods, articles or terminal devices. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of additional identical elements in the process, method, article or terminal device including the said element.

[0109] The principles and implementation manners of the present application are described herein by applying specific examples; the above descriptions of the examples are only used to help understand the method of the present application and its core idea; meanwhile, for those skilled in the art, according to the idea of the present application, there will be changes in the specific implementation manners and application scopes; in conclusion, the content of the present description should not be understood as a limitation to the present application.

Claims

1. An offload memory transaction acceleration device, comprising: The application is applied to a system on chip, which comprises a processor core, a cache consistency control component and a controller memory interconnection component, and the device comprises an acceleration unit and an acceleration interconnection component, wherein: The acceleration unit is configured to receive a write transaction sent by the processor core, and the acceleration unit is provided with a cache interface and a non-cache interface, the cache interface is configured to receive a write transaction of cache data sent by the processor core, and the non-cache interface is configured to receive a write transaction of non-cache data sent by the processor core; The acceleration interconnection component adopts a target shared access mode, in which the acceleration interconnection component processes one write transaction at a time; When the acceleration interconnection component is currently processing a write transaction of cache data sent by the cache interface, a write transaction operation of cache data is initiated to the cache consistency control component to write the cache data into the cache; When the acceleration interconnection component is currently processing a write transaction of non-cache data sent by the non-cache interface, a write transaction operation of cache data is initiated to the controller memory interconnection component to write the non-cache data into the memory.

2. The device according to claim 1, wherein When the acceleration interconnection component initiates a write transaction operation of cache data to the cache consistency control component, if the cache is full, the cache consistency control component initiates a memory consistency operation and sends a pause information to the acceleration interconnection component; The acceleration interconnection component is configured to pause processing any write transaction in response to the pause information; When the memory consistency operation is performed, the cache consistency control component is configured to send evicted data in the cache to the controller memory interconnection component and write the evicted data into the memory.

3. The device according to claim 1, wherein The acceleration interconnection component is provided with a cache data queue and a non-cache data queue, both of which are first-in-first-out queues, the cache data queue is configured to store a write transaction of cache data sent by the cache interface, and the non-cache data queue is configured to store a write transaction of non-cache data sent by the non-cache interface; The acceleration interconnection component is configured to select one write transaction in the cache data queue or the non-cache data queue for processing at a time.

4. The apparatus of claim 3, wherein, The acceleration interconnection component is configured to poll and select a write transaction in the cache data queue or the non-cache data queue for processing at a time.

5. The apparatus of claim 3, wherein, Different priorities are set for the cache data queue and the non-cache data queue, the acceleration interconnection component is configured to obtain one write transaction from a queue with a higher priority for processing at a time, and when the queue with the higher priority does not contain a write transaction, obtain one write transaction from a queue with a lower priority for processing.

6. The apparatus of claim 1, wherein, Any write transaction of cache data or non-cache data comprises a write address transaction and a write data transaction; The acceleration interconnection component comprises a write address transaction processor and a write data transaction processor. When the write address transaction processor and the write data transaction processor determine that the current transaction is a write transaction of non-cache data, the acceleration interconnection component is configured to send the address information and the data information of the non-cache data to the controller memory interconnection component, and the controller memory interconnection component is configured to write the data information of the non-cache data into the memory at a position corresponding to the address of the non-cache data. When the write address transaction processor and the write data transaction processor determine that the current transaction is a write transaction of cache data, the acceleration interconnection component is configured to send the address information and the data information of the cache data to the cache coherence control component. If the target cache in the multi-level cache corresponding to the address information of the cache data is not full, the cache controller in the cache coherence control component is configured to write the data information of the cache data into a position corresponding to the address information of the cache data. If the target cache in the multi-level cache corresponding to the address information of the cache data is full, the cache controller in the cache coherence control component is configured to determine evicted data in the target cache, send the evicted data to the controller memory interconnection component, write the evicted data into the memory, and send pause information to the acceleration interconnection component. The acceleration interconnection component is configured to pause processing of any write transaction in response to the pause information.

7. The apparatus of claim 6, wherein When the acceleration interconnection component pauses processing of any write transaction, if the acceleration interconnection component receives continue processing information sent by the cache coherence control component, the acceleration interconnection component is configured to continue processing of any write transaction in response to the continue processing information.

8. A system on chip, characterized by The system on chip includes a processor core, a cache coherence control component, and a controller memory interconnection component, and further includes the offload memory transaction acceleration apparatus of any one of claims 1-7.

9. A memory transaction method, characterized by, The method applied to the system on chip of claim 8 further includes: In response to a write transaction processing instruction of any processor, determining whether to send the write transaction to a cache interface or a non-cache interface of an acceleration unit according to a data type corresponding to the write transaction; The acceleration interconnection component determines a current write transaction, and initiates a cache data write transaction operation to the cache coherence control component when the current write transaction is a write transaction of cache data, or initiates a cache data write transaction operation to the controller memory interconnection component when the current write transaction is a write transaction of non-cache data, to write the non-cache data into the memory; When the cache of the system on chip is full, the cache coherence control component initiates a memory coherence operation and sends pause information to the acceleration interconnection component; The acceleration interconnection component pauses processing of any write transaction in response to the pause information.

10. A non-volatile readable storage medium, characterized by The non-volatile readable storage medium stores a computer program, and the computer program is executed by a processor to perform the memory transaction processing method of claim 9.

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