Display device, method of driving the same, and electronic device including the same

Abstract

A display device, a method of driving the same, and an electronic device including the same are disclosed. The display device includes: a display panel including sub-pixels; a gate driver supplying a gate signal to the sub-pixels; a data driver supplying a data voltage to the sub-pixels; a driving voltage generator that supplies a gamma reference voltage including a black data voltage to the data driver; and a driving controller determining an offset voltage of the black data voltage based on at least one selected from a driving frequency, a dimming level, and a temperature.

Description

[0001] This application claims priority to and all benefits derived from Korean Patent Application No. 10-2023-0073787, filed on Jun. 8, 2023, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] The present disclosure relates to a display device, a method of driving the display device, and an electronic device including the display device. Background Art

[0003] Typically, a display device includes a display panel, a gate driver, a data driver, and a drive controller. The display panel may include a plurality of gate lines, a plurality of data lines, and a plurality of sub-pixels electrically connected to the plurality of gate lines and the plurality of data lines. The gate driver may provide a gate signal to the gate line, the data driver may provide a data voltage to the data line, and the drive controller may control the gate driver and the data driver.

[0004] In a display device supporting (or operable in) variable frequency driving, a time (duration or period) in which a data voltage is not written in one frame may vary according to a driving frequency. Summary of the invention

[0005] In a display device supporting variable frequency driving, as the time in which a data voltage is not written in one frame increases, the amount of current leaked through a switching transistor of a subpixel may increase, and a brightness difference may be caused due to the leakage current.

[0006] Embodiments of the present disclosure will provide a display device in which a black data voltage is adjusted.

[0007] Another embodiment of the present disclosure is to provide a method of driving a display device in which a black data voltage is adjusted.

[0008] Yet another embodiment of the present disclosure is to provide an electronic device including a display device in which a black data voltage is adjusted.

[0009] According to an embodiment of the present disclosure, a display device may include: a display panel including sub-pixels; a gate driver providing a gate signal to the sub-pixels; a data driver providing a data voltage to the sub-pixels; a driving voltage generator providing a gamma reference voltage including a black data voltage to the data driver; and a driving controller determining an offset voltage of the black data voltage based on at least one selected from a driving frequency, a dimming level, and a temperature.

[0010] In an embodiment, the driving controller may determine the black data set voltage based on the driving frequency, and determine the black data voltage by adding an offset voltage of the black data voltage to the black data set voltage.

[0011] In an embodiment, the black data setting voltage may decrease as the driving frequency increases.

[0012] In an embodiment, with respect to the same driving frequency and the same temperature, the offset voltage of the black data voltage may be smaller at the second dimming level greater than the first dimming level than at the first dimming level.

[0013] In an embodiment, with respect to the same dimming level and the same temperature, the offset voltage of the black data voltage may be smaller at a second driving frequency greater than the first driving frequency than at the first driving frequency.

[0014] In an embodiment, with respect to the same dimming level and the same driving frequency, the offset voltage of the black data voltage may be smaller at a second temperature less than the first temperature than at the first temperature.

[0015] In an embodiment, the subpixels may include a first color subpixel displaying a first color and a second color subpixel displaying a second color, and with respect to the same dimming level, the same driving frequency, and the same temperature, the offset voltage of the black data voltage for the first color subpixel may be smaller than the offset voltage of the black data voltage for the second color subpixel.

[0016] In an embodiment, the driving controller may determine an offset voltage of an anode initialization voltage for initializing a light emitting element of a sub-pixel based on the black data voltage.

[0017] In an embodiment, the offset voltage of the anode initialization voltage may increase as the offset voltage of the black data voltage increases.

[0018] In an embodiment, the driving voltage generator may include a first regulator generating a black data voltage by receiving a gray scale expressing voltage, and the driving controller may determine an offset voltage of the gray scale expressing voltage based on the black data voltage.

[0019] In an embodiment, the gray scale expressing voltage may be determined as a sum of the black data voltage and a headroom margin of the first regulator.

[0020] In an embodiment, the driving voltage generator may include a first regulator generating a black data voltage by receiving a grayscale expressing voltage, the driving voltage generator may provide a gate high voltage to the gate driver, and the driving controller may determine an offset voltage of the gate high voltage based on the grayscale expressing voltage.

[0021] In an embodiment, the sub-pixel may include a switching transistor, and the gate high voltage may be determined as the sum of a grayscale expressing voltage and a threshold voltage of the switching transistor.

[0022] In an embodiment, the display device may further include: a power supply that provides a source voltage to a driving voltage generator, the driving voltage generator may provide a gate high voltage to a gate driver and include a second regulator that generates the gate high voltage by receiving the source voltage, and the driving controller may determine an offset voltage of the source voltage based on the gate high voltage.

[0023] In an embodiment, the source voltage may be determined as the sum of the gate high voltage and the headroom of the second regulator.

[0024] In an embodiment, the display device may further include: a power supply that provides a source voltage to a driving voltage generator, the driving voltage generator may include a third regulator that generates a gate low voltage by receiving a reference voltage, and a reference voltage generator that generates a reference voltage based on the source voltage in a first mode and generates a reference voltage based on the source voltage and a first external voltage in a second mode, and the driving controller may select one of the first mode and the second mode based on the gate low voltage.

[0025] In an embodiment, the reference voltage in the first mode is a voltage corresponding to the source voltage, the reference voltage in the second mode is a voltage corresponding to the sum of the source voltage and the first external voltage, and when the absolute value of the gate low voltage and the sum of the clearance margin of the third regulator is greater than the absolute value of the voltage corresponding to the source voltage, the driving controller can select the second mode between the first mode and the second mode.

[0026] In an embodiment, the driving controller may determine a first offset voltage of the black data voltage based on the driving frequency and the dimming level, calculate a first corrected black data voltage by adding the first offset voltage of the black data voltage to the black data set voltage, determine a second offset voltage of the black data voltage based on the dimming level and the temperature, calculate a second corrected black data voltage by adding the second offset voltage of the black data voltage to the first corrected black data voltage, and determine the second corrected black data voltage as the black data voltage.

[0027] In an embodiment, the driving controller may determine a first offset voltage of an anode initialization voltage of a light-emitting element for initializing a sub-pixel based on a first corrected black data voltage, calculate a first corrected anode initialization voltage by adding the first offset voltage of the anode initialization voltage to an anode initialization set voltage, determine a second offset voltage of the anode initialization voltage based on a second corrected black data voltage, calculate a second corrected anode initialization voltage by adding the second offset voltage of the anode initialization voltage to the first corrected anode initialization voltage, and determine the second corrected anode initialization voltage as the anode initialization voltage.

[0028] In an embodiment, the driving voltage generator may generate a black data voltage by receiving a grayscale expression voltage, and the driving controller may determine a first offset voltage of the grayscale expression voltage based on a black data setting voltage, calculate a first corrected grayscale expression voltage by adding the first offset voltage of the grayscale expression voltage to the grayscale expression setting voltage, determine a second offset voltage of the grayscale expression voltage based on the first corrected black data voltage, calculate a second corrected grayscale expression voltage by adding the second offset voltage of the grayscale expression voltage to the first corrected grayscale expression voltage, determine a third offset voltage of the grayscale expression voltage based on the second corrected black data voltage, calculate a third corrected grayscale expression voltage by adding the third offset voltage of the grayscale expression voltage to the second corrected grayscale expression voltage, and determine the third corrected grayscale expression voltage as the grayscale expression voltage.

[0029] In an embodiment, the driving voltage generator may provide a gate high voltage to the gate driver, and the driving controller may determine a first offset voltage of the gate high voltage based on a first corrected grayscale expression voltage, calculate the first corrected gate high voltage by adding the first offset voltage of the gate high voltage to a gate high set voltage, determine a second offset voltage of the gate high voltage based on a second corrected grayscale expression voltage, calculate the second corrected gate high voltage by adding the second offset voltage of the gate high voltage to the first corrected gate high voltage, determine a third offset voltage of the gate high voltage based on temperature, calculate the third corrected gate high voltage by adding the third offset voltage of the gate high voltage to the second corrected gate high voltage, and determine the third corrected gate high voltage as the gate high voltage.

[0030] In an embodiment, the display device may further include: a power supply, which provides a source voltage to a driving voltage generator, the driving voltage generator can generate a gate high voltage by receiving the source voltage, and the driving controller can determine a first offset voltage of the source voltage based on the first corrected gate high voltage, calculate the first corrected source voltage by adding the first offset voltage of the source voltage to the source voltage setting voltage, determine the second offset voltage of the source voltage based on the second corrected gate high voltage, calculate the second corrected source voltage by adding the second offset voltage of the source voltage to the first corrected source voltage, determine the third offset voltage of the source voltage based on the third corrected gate high voltage, calculate the third corrected source voltage by adding the third offset voltage of the source voltage to the second corrected source voltage, and determine the third corrected source voltage as the source voltage.

[0031] In an embodiment, the driving voltage generator may provide the gate low voltage to the gate driver, and the driving controller may determine an offset voltage of the gate low voltage based on an initialization voltage of the sub-pixel.

[0032] In an embodiment, the driving voltage generator may provide a gate low voltage to the gate driver, and the driving controller may determine a first offset voltage of the gate low voltage based on an initialization voltage of the sub-pixel, calculate a first correction gate low voltage by adding the first offset voltage of the gate low voltage to the gate low set voltage, determine a second offset voltage of the gate low voltage based on temperature, calculate a second correction gate low voltage by adding the second offset voltage of the gate low voltage to the first correction gate low voltage, and determine the second correction gate low voltage as the gate low voltage.

[0033] According to an embodiment of the present disclosure, a method for driving a display device may include: determining an offset voltage of a black data voltage based on at least one selected from a driving frequency, a dimming level, and a temperature; determining an offset voltage of a grayscale expression voltage based on the black data voltage; determining an offset voltage of a gate high voltage based on the grayscale expression voltage; determining an offset voltage of a source voltage based on the gate high voltage; and selecting a mode for generating a reference voltage based on a gate low voltage.

[0034] According to an embodiment of the present disclosure, the electronic device may include: a processor that provides input image data to the display device; the display device that displays an image based on the input image data; and a power supply that supplies power to the display device.

[0035] The display device according to an embodiment of the present disclosure may determine an offset voltage of a black data voltage based on a driving frequency, a dimming level and / or a temperature to set an optimal black data voltage corresponding to the driving frequency, the dimming level and / or the temperature.

[0036] However, the effects of the present disclosure are not limited to the above-described effects, and various extensions can be made within a range not departing from the spirit and scope of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The above and other features of the present disclosure will become more apparent by describing the embodiments of the present disclosure in more detail with reference to the accompanying drawings, in which:

[0038] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure;

[0039] Figure 2 It is a graphic Figure 1 A circuit diagram of an embodiment of a sub-pixel of a display device;

[0040] Figure 3 It is a diagram of Figure 1 A signal timing diagram of an example in which a display device of FIG. 1 is operated at a driving frequency of 120 Hz;

[0041] Figure 4 It is a diagram of Figure 1 A signal timing diagram of an example in which a display device of FIG. 1 is operated at a driving frequency of 60 Hz;

[0042] Figure 5 It is a diagram of Figure 1 A graph showing an example of a display device determining a black data setting voltage based on a driving frequency;

[0043] Figure 6 It is a graphic Figure 1 A block diagram of an embodiment of a driving voltage generator for a display device;

[0044] Figure 7 It is a diagram of Figure 1 FIG. 1 is a diagram showing an example of a driving controller of a display device determining a black data voltage;

[0045] Figure 8 It is a diagram of Figure 1 FIG. 1 is a diagram showing an example of a drive controller of a display device determining an anode initialization voltage;

[0046] Fig. 9 and Fig.10 It is a graphic Figure 1 An example graph of an offset voltage of a black data voltage of a display device with respect to a driving frequency;

[0047] Fig.11 and Fig.12 It is a graphic Figure 1 An example graph of an offset voltage of an anode initialization voltage of a display device with respect to a driving frequency;

[0048] Fig.13 and Fig.14 It is a graphic Figure 1 An example graph of an offset voltage of a black data voltage of a display device with respect to temperature;

[0049] Fig.15 and Fig.16 It is a graphic Figure 1 An example graph of an offset voltage of an anode initialization voltage of a display device relative to temperature;

[0050] Fig.17 is a graph illustrating that a display device according to an embodiment of the present disclosure determines a black data voltage for each sub-pixel;

[0051] Fig.18 It is a diagram of Fig.17 A graph showing an example of determining an anode initialization voltage for each sub-pixel by a display device according to an embodiment of the present invention;

[0052] Fig.19 It is a diagram of Figure 1 FIG. 1 is a diagram showing an example of a driving controller of a display device determining a gray scale expression voltage;

[0053] Fig. 20 It is a diagram of Figure 1 FIG. 1 is a diagram showing an example of a driving controller of a display device determining a gate high voltage;

[0054] Fig.21 It is a diagram of Figure 1 FIG. 1 is a diagram showing an example of a driving controller of a display device determining a source voltage;

[0055] Fig. 22 It is a diagram of Figure 1 FIG. 1 is a diagram showing an example in which a driving controller of a display device determines a mode for generating a reference voltage;

[0056] Fig.23 is a diagram illustrating an example in which a driving controller of a display device according to an embodiment of the present disclosure determines a black data voltage;

[0057] Fig.24 It is a diagram of Fig.23 FIG. 1 is a diagram showing an example of a drive controller of a display device determining an anode initialization voltage;

[0058] Fig.25 It is a diagram of Fig.23 FIG. 1 is a diagram showing an example of a driving controller of a display device determining a gray scale expression voltage;

[0059] Fig.26 It is a diagram of Fig.23 FIG. 1 is a diagram showing an example of a driving controller of a display device determining a gate high voltage;

[0060] Fig. 27 It is a diagram of Fig.23 FIG. 1 is a diagram showing an example of a driving controller of a display device determining a source voltage;

[0061] Fig.28 It is a diagram of Fig.23 FIG. 1 is a diagram showing an example of a driving controller of a display device determining a gate low voltage;

[0062] Fig.29 is a flowchart illustrating a method of driving a display device according to an embodiment of the present disclosure; and

[0063] Fig.30 is a block diagram illustrating an electronic device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0064] The present invention will now be more fully described hereinafter with reference to the accompanying drawings in which various embodiments are shown. However, the present invention can be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. The same reference numerals always refer to the same elements.

[0065] Throughout the specification, when a part is "connected" to another part, this case includes not only a case where the parts are "directly connected" but also a case where the parts are "indirectly connected" with another element interposed therebetween. The terms used herein are used to describe specific embodiments and are not intended to limit the present disclosure.

[0066] The term used in this article is only used to describe the purpose of specific embodiments, and is not intended to be limited. As used in this article, "one", "the (described)" and "at least one" do not represent the limitation of quantity, and unless the context clearly indicates otherwise, it is intended to include both singular and plural. Therefore, the reference to "one" element in the claim (followed by the reference to "the (described)" element) includes the (described) element and multiple (described) elements. For example, unless the context clearly indicates otherwise, "element" has the same meaning as "at least one element". "At least one" should not be interpreted as being limited to "one". "Or" means "and / or". As used in this article, the term "and / or" includes any combination and all combinations of one or more related listed items. "At least any one of X, Y and Z" and "selected from at least any one of X, Y and Z" can be interpreted as any combination (for example, XYZ, XY, YZ and XZ) of two or more of X, Y and Z. It will be further understood that when used in this specification, the terms “comprises” or “includes” and / or variations thereof indicate the presence of stated features, regions, integers, steps, operations, elements and / or parts, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, parts and / or groups.

[0067] Here, terms such as "first" and "second" can be used to describe various components, but the components are not limited to these terms. These terms are used to distinguish one component from another component. Therefore, a first component can refer to a second component within a range without departing from the scope disclosed herein.

[0068] Spatially relative terms such as "under" and "on" may be used for descriptive purposes to describe the relationship between one element or feature and another (other) element or feature as shown in the drawings. In addition to the directions depicted in the drawings, spatially relative terms are intended to include other directions in use, operation and / or manufacture. For example, when the device shown in the drawings is reversed, the element depicted as being positioned "under" other elements or features is positioned along the direction "on" the other elements or features. Therefore, in an embodiment, the term "under" may include both the upper and lower directions. In addition, the device may face other directions (e.g., rotated 90 degrees or in other directions), and the spatially relative terms used herein are therefore interpreted accordingly.

[0069] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless so explicitly defined herein.

[0070] Various embodiments are described with reference to the accompanying drawings that schematically illustrate ideal embodiments. Accordingly, it is expected that shapes may vary, for example, depending on tolerances and / or manufacturing techniques. Therefore, the embodiments disclosed herein should not be interpreted as limited to the specific shapes shown, but should be interpreted as including changes in shape that occur, for example, due to manufacturing. As described above, the shapes shown in the drawings may not show the actual shape of an area of ​​the device, and the present embodiments are not limited to this.

[0071] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0072] Reference Figure 1 , an embodiment of a display device may include a display panel 100, a drive controller 200, a gate driver 300, a data driver 400, an emission driver 500, a drive voltage generator 600, and a power supply 700. In an embodiment, the drive controller 200 and the data driver 400 may be integrated into one chip. In an embodiment, the drive controller 200, the data driver 400, and the drive voltage generator 600 may be integrated into one chip.

[0073] The display panel 100 may include a display area DA for displaying an image and a non-display area NDA disposed adjacent to the display area DA. In an embodiment, the gate driver 300 and the emission driver 500 may be installed in the non-display area NDA.

[0074] The display panel 100 may include a plurality of gate lines GL, a plurality of data lines DL, a plurality of emission lines EL, and a plurality of sub-pixels SP electrically connected to the gate lines GL, the data lines DL, and the emission lines EL. The gate lines GL and the emission lines EL may extend in a first direction D1, and the data lines DL may extend in a second direction D2 crossing the first direction D1.

[0075] The drive controller 200 may receive input image data IMG and an input control signal CONT from a processor (e.g., a graphics processing unit (GPU), etc.). In an embodiment, for example, the input image data IMG may include red image data, green image data, and blue image data. In an embodiment, the input image data IMG may further include white image data. In an alternative embodiment, for example, the input image data IMG may include magenta image data, yellow image data, and cyan image data. The input control signal CONT may include a master clock signal and a data enable signal. The input control signal CONT may further include a vertical synchronization signal and a horizontal synchronization signal.

[0076] The driving controller 200 may generate a first control signal CONT1 , a second control signal CONT2 , a third control signal CONT3 , a fourth control signal CONT4 , a fifth control signal CONT5 , and a data signal DATA based on input image data IMG and an input control signal CONT.

[0077] The driving controller 200 may generate a first control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signal CONT, and output the first control signal CONT1 to the gate driver 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0078] The driving controller 200 may generate a second control signal CONT2 for controlling the operation of the data driver 400 based on the input control signal CONT, and output the second control signal CONT2 to the data driver 400. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0079] The driving controller 200 may generate a data signal DATA by receiving input image data IMG and an input control signal CONT. The driving controller 200 may output the data signal DATA to the data driver 400.

[0080] The driving controller 200 may generate a third control signal CONT3 for controlling the operation of the emission driver 500 based on the input control signal CONT, and output the third control signal CONT3 to the emission driver 500. The third control signal CONT3 may include a vertical start signal and an emission clock signal.

[0081] The driving controller 200 may generate a fourth control signal CONT4 for controlling the operation of the driving voltage generator 600 based on the input control signal CONT, and output the fourth control signal CONT4 to the driving voltage generator 600. The driving voltage generator 600 may output driving voltages VGH, VGL, VINT, and VAINT having voltage values ​​(or levels) determined by the driving controller 200.

[0082] The driving controller 200 may generate a fifth control signal CONT5 for controlling the operation of the power supply 700 based on the input control signal CONT and output the fifth control signal CONT5 to the power supply 700. The power supply 700 may output the source voltage VLIN1 having a voltage value determined by the driving controller 200.

[0083] The gate driver 300 may generate a gate signal for driving the gate line GL in response to the first control signal CONT1 received from the driving controller 200. The gate driver 300 may output the gate signal to the gate line GL. In an embodiment, for example, the gate driver 300 may sequentially output the gate signal to the gate line GL.

[0084] The data driver 400 may receive the second control signal CONT2 and the data signal DATA from the driving controller 200. The data driver 400 may generate a data voltage obtained by converting the data signal DATA into an analog voltage. The data driver 400 may output the data voltage to the data line DL.

[0085] The emission driver 500 may generate emission signals for driving the emission lines EL in response to the third control signal CONT3 received from the driving controller 200. The emission driver 500 may output the emission signals to the emission lines EL. In an embodiment, for example, the emission driver 500 may sequentially output the emission signals to the emission lines EL.

[0086] The driving voltage generator 600 may provide a gate high voltage VGH and a gate low voltage VGL to the gate driver 300 and the emission driver 500 in response to a fourth control signal CONT4 received from the driving controller 200. The gate high voltage VGH may be a voltage corresponding to a high voltage level of a gate signal, and the gate low voltage VGL may be a voltage corresponding to a low voltage level of a gate signal.

[0087] The driving voltage generator 600 may apply the first initialization voltage VINT and the second initialization voltage VAINT to the display panel 100 in response to the fourth control signal CONT4 received from the driving controller 200. Detailed features of the first initialization voltage VINT and the second initialization voltage VAINT will be described later.

[0088] The driving voltage generator 600 may provide the gamma reference voltage VGREF to the data driver 400 in response to the fourth control signal CONT4 received from the driving controller 200. The gamma reference voltage VGREF may include a data voltage V0 (i.e., a black data voltage) of 0 gray to a data voltage V255 of 255 gray. The data driver 400 may output a data voltage of each gray using the gamma reference voltage VGREF.

[0089] The driving voltage generator 600 may receive a first external voltage VCI (at Figure 6 ) and generates a reference voltage VLOUT3 (in Figure 6 Detailed features of this will be described later.

[0090] The power supply 700 may increase the source voltage VLIN1 (also at Figure 6 ) is provided to the driving voltage generator 600. The power supply 700 may generate the source voltage VLIN1 by receiving the second external voltage VBAT. In an embodiment, for example, the power supply 700 may be a power management integrated circuit (PMIC).

[0091] Figure 2 It is a graphic Figure 1 A circuit diagram of an embodiment of a sub-pixel of a display device.

[0092] Reference Figure 2 In an embodiment, each of the sub-pixels SP may include a driving transistor T1, switching transistors T2 to T7 (or second to seventh transistors), and a light emitting element EE.

[0093] In an embodiment, for example, each of the sub-pixels SP may include: a first transistor T1 (i.e., a driving transistor), including a control electrode (or a gate electrode) connected to a first node N1, a first electrode connected to a second node N2, and a second electrode connected to a third node N3; a second transistor T2, including a control electrode receiving a gate signal SCAN[N], a first electrode receiving a data voltage VDATA, and a second electrode connected to the second node N2; a third transistor T3, including a control electrode receiving a gate signal SCAN[N], a first electrode connected to the third node N3, and a second electrode connected to the first node N1; a fourth transistor T4, including a control electrode receiving a gate signal SCAN[N-1] of a previous pixel row, a first electrode receiving a first initialization voltage VINT, and a second electrode connected to the first node N1; a fifth transistor T5, including The first electrode of the first transistor T6 includes a control electrode receiving an emission signal EM[N], a first electrode receiving a first power voltage ELVDD (e.g., a high power voltage), and a second electrode connected to a second node N2; a sixth transistor T6 includes a control electrode receiving an emission signal EM[N], a first electrode connected to a third node N3, and a second electrode connected to a fourth node N4; a seventh transistor T7 includes a control electrode receiving a gate signal SCAN[N], a first electrode receiving a second initialization voltage VAINT, and a second electrode connected to a fourth node N4; a storage capacitor CST includes a first electrode receiving a first power voltage ELVDD and a second electrode connected to a first node N1; and a light emitting element EE includes a first electrode (i.e., an anode electrode) connected to a fourth node N4 and a second electrode receiving a second power voltage ELVSS (e.g., a low power voltage). However, the present disclosure is not limited thereto. In alternative embodiments, for example, each of the sub-pixels SP may have a 3T1C structure including three transistors and one capacitor, a 5T2C structure including five transistors and two capacitors, a 7T1C structure including seven transistors and one capacitor, or a 9T1C structure including nine transistors and one capacitor, etc.

[0094] In an embodiment, the first to seventh transistors T1, T2, T3, T4, T5, T6 and T7 can be implemented as p-channel metal oxide semiconductor (PMOS) transistors. In such an embodiment, the low voltage level can be an activation level, and the high voltage level can be a deactivation level. For example, when the signal applied to the control electrode of the PMOS transistor has a low voltage level, the PMOS transistor can be turned on. For example, when the signal applied to the control electrode of the PMOS transistor has a high voltage level, the PMOS transistor can be turned off.

[0095] However, the present disclosure is not limited thereto. In an alternative embodiment, for example, the first to seventh transistors T1, T2, T3, T4, T5, T6 and T7 can be implemented as n-channel metal oxide semiconductor (NMOS) transistors. In such an embodiment, the low voltage level can be a deactivation level, and the high voltage level can be an activation level. For example, when the signal applied to the control electrode of the NMOS transistor has a low voltage level, the NMOS transistor can be turned off. For example, when the signal applied to the control electrode of the NMOS transistor has a high voltage level, the NMOS transistor can be turned on. That is, the activation level and the deactivation level can be determined according to the type of transistor.

[0096] For example, in the initialization period, the gate signal SCAN[N-1] of the previous pixel row may have an activation level, and the fourth transistor T4 may be turned on. Accordingly, a first initialization voltage VINT (hereinafter, referred to as a gate initialization voltage) may be applied to the first node N1 (i.e., a gate initialization operation). That is, the control electrode (or storage capacitor CST) of the first transistor T1 may be initialized.

[0097] For example, in the data writing and anode initialization period, the gate signal SCAN[N] may have an activation level, and the second transistor T2, the third transistor T3, and the seventh transistor T7 may be turned on. Accordingly, the data voltage VDATA may be written to the storage capacitor CST, and the second initialization voltage VAINT (hereinafter, referred to as the anode initialization voltage) may be applied to the first electrode (i.e., the anode electrode) of the light emitting element EE.

[0098] For example, in the emission period, the emission signal EM[N] may have an activation level, and the fifth transistor T5 and the sixth transistor T6 may be turned on. Accordingly, the first power voltage ELVDD may be applied to the first transistor T1 to generate a drive current, and the drive current may be applied to the light emitting element EE. That is, the light emitting element EE may emit light having a brightness corresponding to the drive current.

[0099] Figure 3 It is a diagram of Figure 1 A signal timing diagram of an example in which a display device operates at a driving frequency of 120 Hz, and Figure 4 It is a diagram of Figure 1 FIG. 4 is a signal timing diagram of an example in which a display device operates at a driving frequency of 60 Hz.

[0100] Reference Figures 1 to 4 In an embodiment, the input control signal CONT may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a data enable signal DE.

[0101] The vertical synchronization signal Vsync may include a plurality of pulses, and may indicate the end of the previous frame and the start of the current frame based on the time point at which each of the pulses is generated. The interval between adjacent pulses of the vertical synchronization signal Vsync may correspond to one frame. The horizontal synchronization signal Hsync may include a plurality of pulses, and may indicate the end of the previous horizontal period and the start of a new horizontal period based on the time point at which each of the pulses is generated. The data enable signal DE may indicate the supply of input image data IMG in the horizontal period. The input image data IMG may be supplied in the form of a data voltage VDATA in units of pixel rows in the horizontal period corresponding to the data enable signal DE.

[0102] In an embodiment, Figure 3 and Figure 4 As shown in , when the driving frequency decreases, the length of one frame may increase. In addition, the data enable signal DE may not have a pulse in the period in which the length of one frame is increased. In the period in which the data enable signal DE does not have a pulse, the data voltage VDATA may not be written. While the data voltage VDATA is not written, the voltage stored in the storage capacitor CST may leak through the third transistor T3 and the fourth transistor T4. That is, when the same data voltage VDATA is written even if the driving frequency is different, a brightness difference may be caused due to leakage current. In an embodiment, the drive controller 200 can minimize the brightness difference by determining the offset voltage of the black data voltage or the black data set voltage based on the driving frequency. A detailed description of this will be given later.

[0103] Figure 5 It is a diagram of Figure 1 FIG. 1 is a graph showing an example in which a display device determines a black data setting voltage based on a driving frequency.

[0104] Reference Figure 1 and Figure 5 In an embodiment, the driving controller 200 may determine the black data set voltage V0_SET based on the driving frequency. The driving controller 200 may determine the black data voltage V0 by adding an offset voltage of the black data voltage V0 to the black data set voltage V0_SET.

[0105] The black data voltage may be the maximum value among the data voltages. Figure 2 As shown in , the driving transistor may be implemented as a PMOS transistor. In such an embodiment, as the gate voltage of the driving transistor increases, the driving current may decrease. Accordingly, the data voltage may have a maximum value in the black grayscale (ie, 0 grayscale).

[0106] like Figure 5As shown in , the black data setting voltage V0_SET may decrease as the dimming level ML decreases. In an embodiment, in a partial interval of the high dimming level ML, as the dimming level ML decreases, the black data setting voltage V0_SET may increase. In an embodiment, in a partial interval of the low dimming level ML, the black data setting voltage V0_SET may be constant regardless of the dimming level ML.

[0107] As the dimming level ML decreases, the driving controller 200 can reduce the data range of the data voltage at the low dimming level ML by reducing the black data setting voltage V0_SET. In addition, as the data range of the data voltage decreases, the instantaneous afterimage caused by the hysteresis characteristics of the driving transistor at low brightness (e.g., low dimming level ML) can be minimized.

[0108] In an embodiment, the gamma curve of the display device may be adjusted by adjusting the dimming level ML. For example, the dimming level ML may be set by a user. For example, as the dimming level ML decreases, the maximum brightness displayed by the display device may decrease. For example, as the dimming level ML decreases, the brightness displayed by the display device may generally decrease.

[0109] In an embodiment, the black data setting voltage V0_SET may decrease as the driving frequency increases. As described above, when the same data voltage is written while the driving frequency is changed, a brightness difference may be caused due to leakage current. The driving controller 200 may minimize the brightness difference by determining the black data setting voltage V0_SET based on the driving frequency.

[0110] Figure 6 It is a graphic Figure 1 A block diagram of an embodiment of a driving voltage generator for a display device.

[0111] Reference Figure 6 , an embodiment of the driving voltage generator 600 may include a first regulator 610 , a second regulator 620 , a third regulator 630 , a fourth regulator 640 , and a reference voltage generator 650 .

[0112] The first regulator 610 may generate the black data voltage V0 by receiving the gray scale expressing voltage VREG. The first regulator 610 may generate the black data voltage V0 having a voltage value determined by the driving controller 200 by receiving the gray scale expressing voltage VREG.

[0113] In an embodiment, for example, when the driving transistor is implemented as an NMOS transistor, the first regulator 610 may generate a white data voltage (eg, a 255 grayscale data voltage) having a voltage value determined by the driving controller 200 by receiving the grayscale representation voltage VREG.

[0114] In an embodiment, the first regulator 610 may generate the black data voltage V0 using the grayscale representation voltage VREG as a top voltage. In an embodiment, for example, the black data voltage V0 may be less than the grayscale representation voltage VREG. For example, the black data voltage V0 may have a voltage value within a range less than or equal to a voltage obtained by subtracting a headroom margin of the first regulator 610 from the grayscale representation voltage VREG.

[0115] The second regulator 620 may generate the gate high voltage VGH by receiving the source voltage VLIN1. The second regulator 620 may generate the gate high voltage VGH having a voltage value determined by the driving controller 200 by receiving the source voltage VLIN1.

[0116] In an embodiment, the second regulator 620 may generate a gate high voltage VGH using the source voltage VLIN1 as a top voltage. In an embodiment, for example, the gate high voltage VGH may be less than the source voltage VLIN1. For example, the gate high voltage VGH may have a voltage value within a range less than or equal to a voltage obtained by subtracting a headroom margin of the second regulator 620 from the source voltage VLIN1.

[0117] The third regulator 630 may generate the gate low voltage VGL by receiving the reference voltage VLOUT3 The third regulator 630 may generate the gate low voltage VGL having a voltage value determined by the driving controller 200 by receiving the reference voltage VLOUT3.

[0118] In an embodiment, the third regulator 630 may generate a gate low voltage VGL using the reference voltage VLOUT3 as a bottom voltage. In an embodiment, for example, the gate low voltage VGL may be greater than the reference voltage VLOUT3. For example, the gate low voltage VGL may have a voltage value within a range greater than or equal to a voltage value obtained by adding the headroom of the third regulator 630 to the reference voltage VLOUT3.

[0119] The fourth regulator 640 may generate the gray scale expressing voltage VREG by receiving the source voltage VLIN1. The fourth regulator 640 may generate the gray scale expressing voltage VREG having a voltage value determined by the driving controller 200 by receiving the source voltage VLIN1.

[0120] In an embodiment, the fourth regulator 640 may generate a grayscale expression voltage VREG using the source voltage VLIN1 as a top voltage. In an embodiment, for example, the grayscale expression voltage VREG may be less than the source voltage VLIN1. For example, the grayscale expression voltage VREG may have a voltage value within a range less than or equal to a voltage obtained by subtracting a headroom margin of the fourth regulator 640 from the source voltage VLIN1.

[0121] The reference voltage generator 650 may generate a reference voltage VLOUT3 by receiving the source voltage VLIN1 or the first external voltage VCI and the source voltage VLIN1 . Detailed features of this will be described later.

[0122] Figure 7 It is a diagram of Figure 1 FIG. 1 is a diagram of an example of a driving controller of a display device determining a black data voltage, Figure 8 It is a diagram of Figure 1 FIG. 1 is a diagram showing an example of a drive controller of a display device determining an anode initialization voltage, Fig. 9 and Fig.10 It is a graphic Figure 1 is a graph of an example of an offset voltage of a black data voltage of a display device relative to a driving frequency, Fig.11 and Fig.12 It is a graphic Figure 1 An example graph of an offset voltage of an anode initialization voltage of a display device relative to a driving frequency, Fig.13 and Fig.14 It is a graphic Figure 1 An example graph of an offset voltage of a black data voltage of a display device relative to temperature is shown, and Fig.15 and Fig.16 It is a graphic Figure 1 FIG. 1 is a graph of an example of an offset voltage of an anode initialization voltage versus temperature of a display device.

[0123] Figure 7 The V0 of the black data voltage V0 only indicates information about the voltage value of the black data voltage V0, and does not instruct the driving controller 200 to generate the black data voltage V0. That is, the driving controller 200 determines the voltage value of the black data voltage V0. This is for Figure 7 The V0_SET and V0_OS are the same.

[0124] Figure 8 The VAINT of the anode initialization voltage VAINT only indicates information about the voltage value of the anode initialization voltage VAINT, and does not instruct the drive controller 200 to generate the anode initialization voltage VAINT. That is, the drive controller 200 determines the voltage value of the anode initialization voltage VAINT. This is for Figure 8 The VAINT_SET and VAINT_OS are the same.

[0125] Reference Figure 1 and Figure 7, an embodiment of the driving controller 200 may include a black data voltage offset determiner 210. The black data voltage offset determiner 210 may determine an offset voltage V0_OS of the black data voltage V0 based on at least one selected from the driving frequency FR, the dimming level ML, and the temperature T. Here, the temperature T may be the temperature of the display panel 100. In an embodiment, for example, the display device may further include a thermometer for measuring the temperature of the display panel 100.

[0126] The black data voltage V0 may be determined as the sum of an offset voltage V0_OS of the black data voltage V0 and a black data set voltage V0_SET. The black data set voltage V0_SET may be the black data voltage before the offset voltage V0_OS of the black data voltage V0 is applied.

[0127] In an embodiment, when the dimming level ML is greater than or equal to a preset reference level, the offset voltage V0_OS of the black data voltage V0 may have a value of 0. In an embodiment, when the dimming level ML is less than the preset reference level, the offset voltage V0_OS of the black data voltage V0 may be applied, and when the dimming level ML is greater than or equal to the preset reference level, the black data set voltage V0_SET may be determined as the black data voltage V0. At low brightness (e.g., low dimming level ML), a brightness difference due to leakage current may appear obviously or be easily recognized. Therefore, the offset voltage V0_OS of the black data voltage V0 may be applied at the low dimming level ML.

[0128] In an embodiment, the black data voltage offset determiner 210 may determine the offset voltage V0_OS of the black data voltage V0 using a lookup table including voltage values ​​of the offset voltage V0_OS of the black data voltage V0. In an embodiment, for example, the lookup table may include voltage values ​​of the offset voltage V0_OS of the black data voltage V0 corresponding to the driving frequency FR, the dimming level ML, and / or the temperature T. In an embodiment, although not shown, the display device may further include a memory device storing the lookup table.

[0129] In an embodiment, the black data voltage offset determiner 210 may determine a voltage value of the offset voltage V0_OS of the black data voltage V0 through an operation expression including the driving frequency FR, the dimming level ML, and / or the temperature T.

[0130] Reference Figure 1 , Figure 2 , Figure 7 and Figure 8, an embodiment of the driving controller 200 may include an anode initialization voltage offset determiner 220. The anode initialization voltage offset determiner 220 may determine an offset voltage VAINT_OS of the anode initialization voltage VAINT based on the black data voltage V0. In an embodiment, the offset voltage VAINT_OS of the anode initialization voltage VAINT may increase as the offset voltage V0_OS of the black data voltage V0 increases.

[0131] As the black data voltage V0 decreases, the driving current at the black grayscale (e.g., 0 grayscale) may increase. In addition, as the driving current increases, the voltage charged in the internal capacitor of the light-emitting element EE may increase. Accordingly, as the black data voltage V0 decreases, the anode initialization voltage VAINT may be determined to have a smaller value. That is, when the black data voltage V0 increases, the anode initialization voltage VAINT may have a margin by the increase of the black data voltage V0, and even if the anode initialization voltage VAINT increases by the margin, the anode electrode may be fully initialized.

[0132] The anode initialization voltage VAINT may be determined as the sum of an offset voltage VAINT_OS of the anode initialization voltage VAINT and an anode initialization setting voltage VAINT_SET. Before applying the offset voltage VAINT_OS of the anode initialization voltage VAINT, the anode initialization setting voltage VAINT_SET may be the anode initialization voltage. In an embodiment, the anode initialization setting voltage VAINT_SET may be determined based on the black data setting voltage V0_SET.

[0133] In an embodiment, the anode initialization setting voltage VAINT_SET can be set to a low voltage value at a low grayscale (e.g., a low dimming level ML) to prevent the brightness at a low grayscale (e.g., a low dimming level ML) from increasing. When the offset voltage VAINT_OS of the anode initialization voltage VAINT is not applied, a reverse bias may be applied to the light-emitting element EE, and color drag may occur due to the reverse bias. The drive controller 200 can ensure the margin of the anode initialization voltage VAINT by applying the offset voltage V0_OS of the black data voltage V0 at a low grayscale (e.g., a low dimming level ML). The drive controller 200 can increase the anode initialization voltage VAINT by applying the offset voltage VAINT_OS of the anode initialization voltage VAINT corresponding to the margin of the anode initialization voltage VAINT. Accordingly, a forward bias can be applied to the light-emitting element EE, and color drag can be minimized.

[0134] In an embodiment, the anode initialization voltage offset determiner 220 determines the offset voltage VAINT_OS of the anode initialization voltage VAINT based on the black data voltage V0, but the present disclosure is not limited thereto. In an alternative embodiment, for example, the anode initialization voltage offset determiner 220 may determine the offset voltage VAINT_OS of the anode initialization voltage VAINT based on the offset voltage V0_OS of the black data voltage V0.

[0135] In an embodiment, the anode initialization voltage offset determiner 220 may determine the offset voltage VAINT_OS of the anode initialization voltage VAINT using a lookup table including voltage values ​​of the offset voltage VAINT_OS of the anode initialization voltage VAINT. For example, the lookup table may include a voltage value of the offset voltage VAINT_OS of the anode initialization voltage VAINT corresponding to the black data voltage V0 (or the offset voltage V0_OS of the black data voltage V0).

[0136] In an embodiment, the anode initialization voltage offset determiner 220 may determine a voltage value of the offset voltage VAINT_OS of the anode initialization voltage VAINT through an operation expression including the black data voltage V0 (or an offset voltage V0_OS of the black data voltage V0 ).

[0137] Reference Figures 7 to 12 , with respect to the same driving frequency and the same temperature, the offset voltage V0_OS of the black data voltage V0 may be smaller at the second dimming level ML2 that is greater than the first dimming level ML1 than at the first dimming level ML1. That is, with respect to the same driving frequency and temperature (i.e., when the driving frequency and temperature do not change), the offset voltage V0_OS of the black data voltage V0 at the second dimming level ML2 may be smaller than the offset voltage V0_OS of the black data voltage V0 at the first dimming level ML1. Similarly, with respect to the same driving frequency and temperature, the offset voltage VAINT_OS of the anode initialization voltage VAINT may be smaller at the second dimming level ML2 than at the first dimming level ML1. That is, with respect to the same driving frequency and temperature, the offset voltage VAINT_OS of the anode initialization voltage VAINT at the second dimming level ML2 may be smaller than the offset voltage VAINT_OS of the anode initialization voltage VAINT at the first dimming level ML1.

[0138] In an embodiment, Fig. 9 and Fig.11 As shown in , as the dimming level ML increases, the offset voltage V0_OS of the black data voltage V0 can be gradually reduced. Similarly, as the dimming level ML increases, the offset voltage VAINT_OS of the anode initialization voltage VAINT can also be gradually reduced. In an alternative embodiment, as Fig.10 and Fig.12 As shown in , the offset voltage V0_OS of the black data voltage V0 can continuously decrease as the dimming level ML increases within the preset range of the dimming level, and can have a constant value within another preset range of the dimming level. Similarly, the offset voltage VAINT_OS of the anode initialization voltage VAINT can also continuously decrease as the dimming level ML increases within the preset range of the dimming level, and can have a constant value within another preset range of the dimming level.

[0139] With respect to the same dimming level and the same temperature, the offset voltage V0_OS of the black data voltage V0 may be smaller at the second driving frequency FR2 that is greater than the first driving frequency FR1 than at the first driving frequency FR1. That is, with respect to the same dimming level and temperature (i.e., when the dimming level and the temperature do not change), the offset voltage V0_OS of the black data voltage V0 at the second driving frequency FR2 may be smaller than the offset voltage V0_OS of the black data voltage V0 at the first driving frequency FR1. Similarly, with respect to the same dimming level and the same temperature, the offset voltage VAINT_OS of the anode initialization voltage VAINT may be smaller at the second driving frequency FR2 than at the first driving frequency FR1. That is, with respect to the same dimming level and temperature, the offset voltage VAINT_OS of the anode initialization voltage VAINT at the second driving frequency FR2 may be smaller than the offset voltage VAINT_OS of the anode initialization voltage VAINT at the first driving frequency FR1.

[0140] As described above, as the driving frequency FR decreases, the amount of leakage current may increase. Therefore, as the driving frequency FR decreases, the brightness difference due to the reduced driving frequency FR may be minimized by using the black data voltage V0 of a higher voltage.

[0141] In an embodiment, the difference between the black data voltages V0 at different driving frequencies (e.g., the first driving frequency FR1 and the second driving frequency FR2) may be greater at the first dimming level ML1 than at the second dimming level ML2. That is, the difference between the black data voltages V0 at different driving frequencies (e.g., the first driving frequency FR1 and the second driving frequency FR2) may decrease as the dimming level ML increases.

[0142] Reference Figure 7 , Figure 8 as well as Figures 13 to 16, with respect to the same dimming level and the same driving frequency, the offset voltage V0_OS of the black data voltage V0 may be smaller at the second temperature TT2 less than the first temperature TT1 than at the first temperature TT1. That is, with respect to the same dimming level and driving frequency (i.e., when the dimming level and the driving frequency do not change), the offset voltage V0_OS of the black data voltage V0 at the second temperature TT2 may be smaller than the offset voltage V0_OS of the black data voltage V0 at the first temperature TT1. Similarly, at the second temperature TT2 less than the first temperature TT1, the offset voltage VAINT_OS of the anode initialization voltage VAINT may be smaller. That is, with respect to the same dimming level and driving frequency, the offset voltage VAINT_OS of the anode initialization voltage VAINT at the second temperature TT2 may be smaller than the offset voltage VAINT_OS of the anode initialization voltage VAINT at the first temperature TT1. Due to the characteristics of the switching transistor, the amount of current leaked at high temperature may increase. Accordingly, as the temperature T increases, the brightness difference due to the increased temperature T may be minimized by using a higher voltage black data voltage V0.

[0143] Fig.17 is a graph illustrating that a display device according to an embodiment of the present disclosure determines a black data voltage for each sub-pixel, and Fig.18 It is a diagram of Fig.17 FIG. 1 is a graph showing an example of determining an anode initialization voltage for each sub-pixel in a display device of the present invention.

[0144] Since the display device according to the embodiment is different from the display device according to the embodiment, in addition to determining the offset voltage V0_OS of the black data voltage V0 for each sub-pixel based on the type of the sub-pixel, Figure 1 The configurations of the display devices are substantially the same, and thus the same figure numerals and reference symbols are used for the same or similar components, and any repeated detailed description thereof will be omitted.

[0145] Reference Figure 1 , Figure 2 , Figure 7 , Figure 8 , Fig.17 and Fig.18 , the subpixels SP may include a first color subpixel R displaying a first color, a second color subpixel G displaying a second color, and a third color subpixel B displaying a third color. For example, the first color may be red, the second color may be green, and the third color may be blue.

[0146] In an embodiment, with respect to the same dimming level, the same driving frequency, and the same temperature, the offset voltage V0_OS of the black data voltage V0 for the first color sub-pixel R may be smaller than the offset voltage V0_OS of the black data voltage V0 for the second color sub-pixel G. In an embodiment, with respect to the same dimming level, the same driving frequency, and the same temperature, the offset voltage V0_OS of the black data voltage V0 for the third color sub-pixel B may be smaller than the offset voltage V0_OS of the black data voltage V0 for the second color sub-pixel G.

[0147] The light efficiency of the sub-pixel SP may be different depending on the color displayed by the sub-pixel SP. For example, the light efficiency of the second color sub-pixel G may be better than the light efficiency of the first color sub-pixel R and the third color sub-pixel B. In this case, with respect to the same brightness (or dimming level), the second color sub-pixel G may use a driving current that is smaller than the driving current of the first color sub-pixel R and the third color sub-pixel B. That is, the second color sub-pixel G may use a driving current that is smaller than the driving current of the first color sub-pixel R and the third color sub-pixel B, and due to the smaller driving current, the internal capacitor of the light-emitting element EE of the second color sub-pixel G may not be fully charged. Accordingly, the second color sub-pixel G may use an anode initialization voltage VAINT that is smaller than the anode initialization voltage VAINT of the first color sub-pixel R and the third color sub-pixel B. In addition, the second color sub-pixel G may use a low voltage black data voltage V0 by using a low voltage anode initialization voltage VAINT.

[0148] In an embodiment, Fig.17 As shown in , the offset voltage V0_OS of the black data voltage V0 for the first color subpixel R and the offset voltage V0_OS of the black data voltage V0 for the third color subpixel B may be identical to each other, but the present disclosure is not limited thereto.

[0149] In an embodiment, the offset voltage V0_OS of the black data voltage V0 for the first color sub-pixel R may be different from the offset voltage V0_OS of the black data voltage V0 for the third color sub-pixel B. For example, when the light efficiency of the first color sub-pixel R is better than that of the third color sub-pixel B, the offset voltage V0_OS of the black data voltage V0 for the first color sub-pixel R may be greater than the offset voltage V0_OS of the black data voltage V0 for the third color sub-pixel B. For example, when the light efficiency of the third color sub-pixel B is better than that of the first color sub-pixel R, the offset voltage V0_OS of the black data voltage V0 for the first color sub-pixel R may be less than the offset voltage V0_OS of the black data voltage V0 for the third color sub-pixel B.

[0150] Fig.19 It is a diagram of Figure 1 FIG. 1 is a diagram showing an example in which a driving controller of a display device determines a grayscale expressing voltage.

[0151] Fig.19 The VREG of FIG. 1 only indicates information about the voltage value of the grayscale expression voltage VREG, and does not instruct the driving controller 200 to generate the grayscale expression voltage VREG. That is, the driving controller 200 determines the voltage value of the grayscale expression voltage VREG. This is for Fig.19 The VREG_SET and VREG_OS are the same.

[0152] Reference Figure 1 , Figure 6 and Fig.19 , an embodiment of the driving controller 200 may include a grayscale expression voltage offset determiner 230. The grayscale expression voltage offset determiner 230 may determine an offset voltage VREG_OS of the grayscale expression voltage VREG based on the black data voltage V0. In an embodiment, the grayscale expression voltage VREG may be determined as the sum of the black data voltage V0 and the headroom of the first regulator 610.

[0153] The grayscale expression voltage VREG may be determined as the sum of an offset voltage VREG_OS of the grayscale expression voltage VREG and a grayscale expression setting voltage VREG_SET. The grayscale expression setting voltage VREG_SET may be the grayscale expression voltage before the offset voltage VREG_OS of the grayscale expression voltage VREG is applied. In an embodiment, the grayscale expression setting voltage VREG_SET may be determined based on the black data setting voltage V0_SET. In an embodiment, for example, the grayscale expression setting voltage VREG_SET may be determined as the sum of the black data setting voltage V0_SET and the headroom of the first regulator 610.

[0154] In the present embodiment, the grayscale voltage offset determiner 230 determines the offset voltage VREG_OS of the grayscale voltage VREG based on the black data voltage V0, but the present disclosure is not limited thereto. In an embodiment, for example, the grayscale voltage offset determiner 230 may determine the offset voltage VREG_OS of the grayscale voltage VREG based on the offset voltage V0_OS of the black data voltage V0.

[0155] In an embodiment, the grayscale expression voltage offset determiner 230 may determine the offset voltage VREG_OS of the grayscale expression voltage VREG by using a lookup table including voltage values ​​of the offset voltage VREG_OS of the grayscale expression voltage VREG. In an embodiment, for example, the lookup table may include voltage values ​​of the offset voltage VREG_OS of the grayscale expression voltage VREG corresponding to the black data voltage V0 (or the offset voltage V0_OS of the black data voltage V0).

[0156] In an embodiment, the grayscale expressing voltage offset determiner 230 may determine the voltage value of the offset voltage VREG_OS of the grayscale expressing voltage VREG through an operation expression including the black data voltage V0 (or the offset voltage V0_OS of the black data voltage V0 ).

[0157] Fig. 20 It is a diagram of Figure 1 FIG. 1 is a diagram of an example in which a driving controller of a display device determines a gate high voltage.

[0158] Fig. 20 The VGH of the gate high voltage VGH only indicates information about the voltage value of the gate high voltage VGH, and does not indicate that the drive controller 200 generates the gate high voltage VGH. That is, the drive controller 200 determines the voltage value of the gate high voltage VGH. This is for Fig. 20 The VGH_SET and VGH_OS are the same.

[0159] Reference Figure 1 , Figure 2 and Fig. 20 , an embodiment of the driving controller 200 may include a gate high voltage offset determiner 240. The gate high voltage offset determiner 240 may determine an offset voltage VGH_OS of the gate high voltage VGH based on the grayscale expression voltage VREG. In an embodiment, the gate high voltage VGH may be determined as the sum of the grayscale expression voltage VREG and the threshold voltages of the switching transistors T2 to T7.

[0160] The gate high voltage VGH may be determined as the sum of an offset voltage VGH_OS of the gate high voltage VGH and a gate high setting voltage VGH_SET. The gate high setting voltage VGH_SET may be a gate high voltage before applying the offset voltage VGH_OS of the gate high voltage VGH. In an embodiment, the gate high setting voltage VGH_SET may be determined based on a grayscale representation setting voltage VREG_SET. In an embodiment, for example, the gate high setting voltage VGH_SET may be determined as the sum of the grayscale representation setting voltage VREG_SET and the threshold voltages of the switching transistors T2 to T7.

[0161] In the present embodiment, the gate high voltage offset determiner 240 determines the offset voltage VGH_OS of the gate high voltage VGH based on the grayscale expression voltage VREG, but the present disclosure is not limited thereto. In an embodiment, for example, the gate high voltage offset determiner 240 may determine the offset voltage VGH_OS of the gate high voltage VGH based on the offset voltage VREG_OS of the grayscale expression voltage VREG.

[0162] In an embodiment, the gate high voltage offset determiner 240 may determine the offset voltage VGH_OS of the gate high voltage VGH by using a lookup table including voltage values ​​of the offset voltage VGH_OS of the gate high voltage VGH. In an embodiment, for example, the lookup table may include voltage values ​​of the offset voltage VGH_OS of the gate high voltage VGH corresponding to the grayscale expression voltage VREG (or the offset voltage VREG_OS of the grayscale expression voltage VREG).

[0163] In an embodiment, the gate high voltage offset determiner 240 may determine the voltage value of the offset voltage VGH_OS of the gate high voltage VGH through an operation expression including the grayscale expressing voltage VREG (or the offset voltage VREG_OS of the grayscale expressing voltage VREG).

[0164] Fig.21 It is a diagram of Figure 1 FIG. 1 is a diagram of an example in which a driving controller of a display device determines a source voltage.

[0165] Fig.21 The VLIN1 of the source voltage VLIN1 only indicates information about the voltage value of the source voltage VLIN1, and does not instruct the drive controller 200 to generate the source voltage VLIN1. That is, the drive controller 200 determines the voltage value of the source voltage VLIN1. This is for Fig.21 The VLIN1_SET and VLIN1_OS are the same.

[0166] Reference Figure 1 , Figure 6 and Fig.21 , an embodiment of the driving controller 200 may include a source voltage offset determiner 250. The source voltage offset determiner 250 may determine an offset voltage VLIN1_OS of the source voltage VLIN1 based on the gate high voltage VGH. In an embodiment, the source voltage VLIN1 may be determined as the sum of the gate high voltage VGH and the headroom of the second regulator 620.

[0167] The source voltage VLIN1 may be determined as the sum of an offset voltage VLIN1_OS of the source voltage VLIN1 and a source voltage setting voltage VLIN1_SET. The source voltage setting voltage VLIN1_SET may be the source voltage before the offset voltage VLIN1_OS of the source voltage VLIN1 is applied. In an embodiment, the source voltage setting voltage VLIN1_SET may be determined based on the gate high setting voltage VGH_SET. In an embodiment, for example, the source voltage setting voltage VLIN1_SET may be determined as the sum of the gate high setting voltage VGH_SET and the headroom of the second regulator 620.

[0168] In this embodiment, the source voltage offset determiner 250 determines the offset voltage VLIN1_OS of the source voltage VLIN1 based on the gate high voltage VGH, but the present disclosure is not limited thereto. In an embodiment, for example, the source voltage offset determiner 250 may determine the offset voltage VLIN1_OS of the source voltage VLIN1 based on the offset voltage VGH_OS of the gate high voltage VGH.

[0169] In an embodiment, the source voltage offset determiner 250 may determine the offset voltage VLIN1_OS of the source voltage VLIN1 using a lookup table including voltage values ​​of the offset voltage VLIN1_OS of the source voltage VLIN1. In an embodiment, for example, the lookup table may include voltage values ​​of the offset voltage VLIN1_OS of the source voltage VLIN1 corresponding to the gate high voltage VGH (or the offset voltage VGH_OS of the gate high voltage VGH).

[0170] In an embodiment, the source voltage offset determiner 250 may determine the voltage value of the offset voltage VLIN1_OS of the source voltage VLIN1 through an operation expression including the gate high voltage VGH (or the offset voltage VGH_OS of the gate high voltage VGH).

[0171] Fig. 22 It is a diagram of Figure 1 FIG. 1 is a diagram of an example in which a driving controller of a display device determines a mode for generating a reference voltage.

[0172] Reference Figure 1 , Figure 6 and Fig. 22 , an embodiment of the driving controller 200 may include a reference voltage mode determiner 270. The reference voltage mode determiner 270 may select one of the first mode M1 and the second mode M2 ​​based on the gate low voltage VGL.

[0173] The reference voltage generator 650 may generate a reference voltage VLOUT3 based on the source voltage VLIN1 in the first mode M1, and may generate the reference voltage VLOUT3 based on the source voltage VLIN1 and the first external voltage VCI in the second mode M2. In an embodiment, the reference voltage VLOUT3 in the first mode M1 may be a voltage corresponding to the source voltage VLIN1, and the reference voltage VLOUT3 in the second mode M2 ​​may be a voltage corresponding to the sum of the source voltage VLIN1 and the first external voltage VCI. That is, the absolute value of the reference voltage VLOUT3 in the second mode M2 ​​may be greater than the absolute value of the reference voltage VLOUT3 in the first mode M1.

[0174] In an embodiment, when the sum of the absolute value of the gate low voltage VGL and the headroom of the third regulator 630 is greater than the absolute value of the voltage corresponding to the source voltage VLIN1 , the reference voltage mode determiner 270 may select the second mode M2 ​​among the first and second modes M1 and M2 .

[0175] As described above, the display device can reduce undesirable power loss by optimizing different driving voltages (eg, the grayscale expressing voltage VREG, the gate high voltage VGH, the source voltage VLIN1, and the reference voltage VLOUT3) based on the black data voltage V0.

[0176] Fig.23 is a diagram illustrating an example in which a driving controller of a display device according to an embodiment of the present disclosure determines a black data voltage, Fig.24 It is a diagram of Fig.23 FIG. 1 is a diagram showing an example of a drive controller of a display device determining an anode initialization voltage, Fig.25 It is a diagram of Fig.23 FIG. 1 is an example of a driving controller of a display device determining a gray scale expression voltage, Fig.26 It is a diagram of Fig.23 FIG. 1 is a diagram showing an example of a driving controller of a display device determining a gate high voltage, Fig. 27 It is a diagram of Fig.23 FIG. 1 is an example of a driving controller of a display device determining a source voltage, and Fig.28 It is a diagram of Fig.23 FIG. 1 is a diagram of an example in which a driving controller of a display device determines a gate low voltage.

[0177] Since in addition to using multiple offset voltages, according to Figure 23 to Figure 28 The display device of the embodiment shown in Figure 1 The embodiments of the display device are substantially the same, and thus the same figure numerals and reference symbols are used for the same or similar components, and any repeated detailed description thereof will be omitted.

[0178] Reference Figure 1 and Fig.23 , an embodiment of the driving controller 200 may include a first black data voltage shift determiner 211 and a second black data voltage shift determiner 212 .

[0179] The first black data voltage offset determiner 211 may determine a first offset voltage V0_OS1 of the black data voltage V0 based on the driving frequency FR and the dimming level ML. In an embodiment, for example, the first offset voltage V0_OS1 of the black data voltage V0 may be Fig. 9 or Fig.10 The offset voltage V0_OS of the black data voltage V0 has the same form.

[0180] The second black data voltage offset determiner 212 may determine a second offset voltage V0_OS2 of the black data voltage V0 based on the temperature T and the dimming level ML. In an embodiment, for example, the second offset voltage V0_OS2 of the black data voltage V0 may be Fig.13 or Fig.14 The offset voltage V0_OS of the black data voltage V0 has the same form.

[0181] The driving controller 200 may calculate a first corrected black data voltage V0_C1 by adding a first offset voltage V0_OS1 of the black data voltage V0 to the black data set voltage V0_SET, calculate a second corrected black data voltage V0_C2 by adding a second offset voltage V0_OS2 of the black data voltage V0 to the first corrected black data voltage V0_C1, and determine the second corrected black data voltage V0_C2 as the black data voltage V0.

[0182] In an embodiment, the second offset voltage V0_OS2 of the black data voltage V0 may be determined based on the gate high voltage and the gate low voltage. As the temperature T increases, the gate high voltage may increase and the gate low voltage may decrease. In addition, the source voltage may be increased to increase the gate high voltage and decrease the gate low voltage. As the source voltage increases, a margin for increasing the grayscale expression voltage and the black data voltage V0 may be ensured. The drive controller 200 may increase the black data voltage V0 by applying the second offset voltage V0_OS2 of the black data voltage V0 corresponding to the margin.

[0183] Reference Figure 1 and Fig.24 , an embodiment of the driving controller 200 may include a first anode initialization voltage offset determiner 221 and a second anode initialization voltage offset determiner 222 .

[0184] The first anode initialization voltage offset determiner 221 may determine a first offset voltage VAINT_OS1 of the anode initialization voltage VAINT based on the first corrected black data voltage V0_C1. In an embodiment, for example, the first offset voltage VAINT_OS1 of the anode initialization voltage VAINT may be Fig.11 or Fig.12 The anode initialization voltage VAINT and the offset voltage VAINT_OS have the same form.

[0185] The second anode initialization voltage offset determiner 222 may determine a second offset voltage VAINT_OS2 of the anode initialization voltage VAINT based on the second corrected black data voltage V0_C2. In an embodiment, for example, the second offset voltage VAINT_OS2 of the anode initialization voltage VAINT may be Fig.15 or Fig.16The anode initialization voltage VAINT and the offset voltage VAINT_OS have the same form.

[0186] The driving controller 200 can calculate a first corrected anode initialization voltage VAINT_C1 by adding a first offset voltage VAINT_OS1 of the anode initialization voltage VAINT to the anode initialization set voltage VAINT_SET, calculate a second corrected anode initialization voltage VAINT_C2 by adding a second offset voltage VAINT_OS2 of the anode initialization voltage VAINT to the first corrected anode initialization voltage VAINT_C1, and determine the second corrected anode initialization voltage VAINT_C2 as the anode initialization voltage VAINT.

[0187] As described above, the embodiment of the driving controller 200 can reflect the change of the black data voltage V0 according to the application of the offset voltage to the anode initialization voltage VAINT. For example, when only the first offset voltage V0_OS1 is applied to the black data voltage V0, the first corrected anode initialization voltage VAINT_C1 can be determined as the anode initialization voltage VAINT.

[0188] Reference Figure 1 and Fig.25 , an embodiment of the driving controller 200 may include a first grayscale representation voltage shift determiner 231 , a second grayscale representation voltage shift determiner 232 , and a third grayscale representation voltage shift determiner 233 .

[0189] The first grayscale expression voltage offset determiner 231 may determine a first offset voltage VREG_OS1 of the grayscale expression voltage VREG based on the black data setting voltage V0_SET. The second grayscale expression voltage offset determiner 232 may determine a second offset voltage VREG_OS2 of the grayscale expression voltage VREG based on the first corrected black data voltage V0_C1. The third grayscale expression voltage offset determiner 233 may determine a third offset voltage VREG_OS3 of the grayscale expression voltage VREG based on the second corrected black data voltage V0_C2.

[0190] The driving controller 200 can calculate the first corrected grayscale expression voltage VREG_C1 by adding the first offset voltage VREG_OS1 of the grayscale expression voltage VREG to the grayscale expression setting voltage VREG_SET, calculate the second corrected grayscale expression voltage VREG_C2 by adding the second offset voltage VREG_OS2 of the grayscale expression voltage VREG to the first corrected grayscale expression voltage VREG_C1, calculate the third corrected grayscale expression voltage VREG_C3 by adding the third offset voltage VREG_OS3 of the grayscale expression voltage VREG to the second corrected grayscale expression voltage VREG_C2, and determine the third corrected grayscale expression voltage VREG_C3 as the grayscale expression voltage VREG.

[0191] As described above, the embodiment of the driving controller 200 can reflect the change of the black data voltage V0 according to the application of the offset voltage to the grayscale expression voltage VREG. For example, when only the first offset voltage V0_OS1 is applied to the black data voltage V0, the second corrected grayscale expression voltage VREG_C2 can be determined as the grayscale expression voltage VREG.

[0192] Reference Figure 1 and Fig.26 , an embodiment of the driving controller 200 may include a first gate high voltage offset determiner 241 , a second gate high voltage offset determiner 242 , and a third gate high voltage offset determiner 243 .

[0193] The first gate high voltage offset determiner 241 may determine a first offset voltage VGH_OS1 of the gate high voltage VGH based on the first corrected grayscale expression voltage VREG_C1. The second gate high voltage offset determiner 242 may determine a second offset voltage VGH_OS2 of the gate high voltage VGH based on the second corrected grayscale expression voltage VREG_C2. The third gate high voltage offset determiner 243 may determine a third offset voltage VGH_OS3 of the gate high voltage VGH based on the temperature T.

[0194] The driving controller 200 can calculate the first correction gate high voltage VGH_C1 by adding the first offset voltage VGH_OS1 of the gate high voltage VGH to the gate high set voltage VGH_SET, calculate the second correction gate high voltage VGH_C2 by adding the second offset voltage VGH_OS2 of the gate high voltage VGH to the first correction gate high voltage VGH_C1, calculate the third correction gate high voltage VGH_C3 by adding the third offset voltage VGH_OS3 of the gate high voltage VGH to the second correction gate high voltage VGH_C2, and determine the third correction gate high voltage VGH_C3 as the gate high voltage VGH.

[0195] Due to the characteristics of the switching transistor, the amount of current leaked at high temperature may increase. In addition, as the gate high voltage VGH increases, the current leaked through the switching transistor may decrease. Accordingly, the driving controller 200 may increase the gate high voltage VGH by applying a third offset voltage VGH_OS3 of the gate high voltage VGH based on the temperature T.

[0196] In an embodiment, the third offset voltage VGH_OS3 of the gate high voltage VGH may increase as the temperature T increases. In an embodiment, when the temperature T is greater than or equal to a preset reference temperature, the third offset voltage VGH_OS3 of the gate high voltage VGH may be applied.

[0197] As described above, the embodiment of the driving controller 200 can reflect the change of the grayscale expression voltage VREG due to the application of the offset voltage (i.e., the change of the black data voltage V0 according to the application of the offset voltage) and the change of the characteristics of the switching transistor due to the temperature T to the gate high voltage VGH. For example, when only the first offset voltage VREG_OS1 is applied to the grayscale expression voltage VREG, the first correction gate high voltage VGH_C1 can be determined as the gate high voltage VGH.

[0198] However, the present disclosure is not limited to the order of applying the offset voltages. For example, when only the first offset voltage VREG_OS1 is applied to the grayscale expressing voltage VREG, a voltage obtained by adding the third offset voltage VGH_OS3 of the gate high voltage VGH to the first correction gate high voltage VGH_C1 may be determined as the gate high voltage VGH.

[0199] Reference Figure 1 and Fig. 27 , an embodiment of the driving controller 200 may include a first source voltage offset determiner 251 , a second source voltage offset determiner 252 , and a third source voltage offset determiner 253 .

[0200] The first source voltage offset determiner 251 may determine a first offset voltage VLIN1_OS1 of the source voltage VLIN1 based on the first correction gate high voltage VGH_C1. The second source voltage offset determiner 252 may determine a second offset voltage VLIN1_OS2 of the source voltage VLIN1 based on the second correction gate high voltage VGH_C2. The third source voltage offset determiner 253 may determine a third offset voltage VLIN1_OS3 of the source voltage VLIN1 based on the third correction gate high voltage VGH_C3.

[0201] The driving controller 200 may calculate a first corrected source voltage VLIN1_C1 by adding a first offset voltage VLIN1_OS1 of the source voltage VLIN1 to the source voltage set voltage VLIN1_SET, calculate a second corrected source voltage VLIN1_C2 by adding a second offset voltage VLIN1_OS2 of the source voltage VLIN1 to the first corrected source voltage VLIN1_C1, calculate a third corrected source voltage VLIN1_C3 by adding a third offset voltage VLIN1_OS3 of the source voltage VLIN1 to the second corrected source voltage VLIN1_C2, and determine the third corrected source voltage VLIN1_C3 as the source voltage VLIN1.

[0202] As described above, the embodiment of the driving controller 200 can reflect the change of the gate high voltage VGH according to the application of the offset voltage (ie, the change of the black data voltage V0) to the source voltage VLIN1. For example, when only the first offset voltage VGH_OS1 is applied to the gate high voltage VGH, the first corrected source voltage VLIN1_C1 can be determined as the source voltage VLIN1.

[0203] In an embodiment, the third source voltage offset determiner 253 may determine a third offset voltage VLIN1_OS3 of the source voltage VLIN1 based on the third correction gate high voltage VGH_C3 and a third correction gate low voltage described later. In an embodiment, the drive controller 200 may reduce a reference voltage that is a basis for the gate low voltage and reduce the source voltage VLIN1 that is a basis for the reference voltage to reduce the gate low voltage based on the temperature T. That is, the drive controller 200 may reflect a change in the gate high voltage VGH (i.e., a change in the black data voltage V0) and a change in the gate low voltage due to application of the offset voltage to the source voltage VLIN1.

[0204] Reference Figure 1 and Fig.28 , the embodiment of the driving controller 200 may determine the offset voltage of the gate low voltage VGL based on the initialization voltage VINT or VAINT of the sub-pixel SP.

[0205] In an embodiment, the driving controller 200 may determine an offset voltage of the gate low voltage VGL based on the gate initialization voltage VINT. In an embodiment, the driving controller 200 may determine an offset voltage of the gate low voltage VGL based on the anode initialization voltage VAINT.

[0206] An embodiment of the driving controller 200 may include a first gate low voltage offset determiner 261 and a second gate low voltage offset determiner 262 .

[0207] The first gate low voltage offset determiner 261 may determine a first offset voltage VGL_OS1 of the gate low voltage VGL based on the initialization voltage VINT or VAINT. The second gate low voltage offset determiner 262 may determine a second offset voltage VGL_OS2 of the gate low voltage VGL based on the temperature T.

[0208] The driving controller 200 may calculate a first correction gate low voltage VGL_C1 by adding a first offset voltage VGL_OS1 of the gate low voltage VGL to the gate low set voltage VGL_SET, calculate a second correction gate low voltage VGL_C2 by adding a second offset voltage VGL_OS2 of the gate low voltage VGL to the first correction gate low voltage VGL_C1, and determine the second correction gate low voltage VGL_C2 as the gate low voltage VGL.

[0209] In an embodiment, the first gate low voltage offset determiner 261 may determine the first offset voltage VGL_OS1 of the gate low voltage VGL based on the gate initialization voltage VINT. In addition, the first offset voltage VGL_OS1 of the gate low voltage VGL may increase as the gate initialization voltage VINT increases.

[0210] In an embodiment, the first gate low voltage offset determiner 261 may determine the first offset voltage VGL_OS1 of the gate low voltage VGL based on the anode initialization voltage VAINT. In addition, the first offset voltage VGL_OS1 of the gate low voltage VGL may increase as the anode initialization voltage VAINT increases.

[0211] In an embodiment, the second offset voltage VGL_OS2 of the gate low voltage VGL may have a negative value and may decrease as the temperature T increases. That is, the gate low voltage VGL may decrease as the temperature T increases.

[0212] Fig.29 is a flowchart illustrating a method of driving a display device according to an embodiment of the present disclosure.

[0213] Reference Fig.29 , Fig.29 An embodiment of a method for driving a display device may include: determining an offset voltage of a black data voltage based on at least one selected from a driving frequency, a dimming level, and a temperature (processing S100); determining an offset voltage of a grayscale expression voltage based on the black data voltage (processing S200); determining an offset voltage of a gate high voltage based on the grayscale expression voltage (processing S300); determining an offset voltage of a source voltage based on the gate high voltage (processing S400); and selecting a mode for generating a reference voltage based on a gate low voltage (processing S500). According to Fig.29 The process S100 to S500 of the method of driving a display device may be performed by Figure 1 display device to achieve (or by Figure 1 (executed by a display device).

[0214] Fig.30 is a block diagram illustrating an electronic device according to an embodiment of the present disclosure.

[0215] Reference Fig.30 , an embodiment of the electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. At this time, the display device 1060 may be Figure 1 In addition, the electronic device 1000 may further include several ports capable of communicating with a video card, a sound card, a memory card, a USB device, or the like, or communicating with other systems. In an embodiment, the electronic device 1000 may be implemented as a smart phone. However, this is merely an example, and the electronic device 1000 is not limited thereto. For example, the electronic device 1000 may be implemented as a mobile phone, a television, a video phone, a smart tablet, a smart watch, a tablet personal computer (PC), a vehicle navigation device, a computer monitor, a notebook computer, or a head-mounted display device, etc.

[0216] The processor 1010 may perform specific calculations or tasks. According to an embodiment, the processor 1010 may be a microprocessor, a central processing unit, an application processor, etc. The processor 1010 may be connected to other components via an address bus, a control bus, or a data bus, etc. According to an embodiment, the processor 1010 may also be connected to an expansion bus such as a peripheral component interconnect (PCI) bus.

[0217] The memory device 1020 may store data to be used for the operation of the electronic device 1000. For example, the memory device 1020 may include a nonvolatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, and a ferroelectric random access memory (FRAM) device, and / or a volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, and a mobile DRAM device, etc.

[0218] The storage device 1030 may include a solid state drive (SSD), a hard disk drive (HDD), a CD-ROM, and the like.

[0219] The input / output device 1040 may include input devices such as a keyboard, a keypad, a touch pad, a touch screen, and a mouse, and output devices such as a speaker and a printer. According to an embodiment, the display device 1060 may be included in the input / output device 1040.

[0220] The power supply 1050 may supply power required for the operation of the electronic device 1000. For example, the power supply 1050 may be a power management integrated circuit (PMIC).

[0221] The display device 1060 may display an image corresponding to the visual information of the electronic device 1000. In an embodiment, the display device 1060 may be an organic light emitting display device or a quantum dot light emitting display device, but is not limited thereto. The display device 1060 may be connected to other components via a bus or other communication links.

[0222] The present disclosure may be applied to a display device and an electronic device including the display device. For example, the present disclosure may be applied to a digital television (TV), a three-dimensional (3D) TV, a mobile phone, a smart phone, a virtual reality (VR) device, a PC (e.g., a tablet computer or a notebook computer), a home electronic device, a personal digital assistant (PDA), a portable media player (PMP), a digital camera, a music player, a portable game console or a navigation system, etc.

[0223] The present invention should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the present invention to those skilled in the art.

[0224] While the invention has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit or scope of the invention as defined by the claims.

Claims

1. A display device, include: A display panel including sub-pixels; A gate driver, providing a gate signal to the sub-pixel; a data driver, providing a data voltage to the sub-pixel; a driving voltage generator to provide a gamma reference voltage including a black data voltage to the data driver; as well as The driving controller determines an offset voltage of the black data voltage based on at least one selected from a driving frequency, a dimming level, and a temperature.

2. The display device according to claim 1, in, The driving controller determines a black data setting voltage based on the driving frequency, and determines the black data voltage by adding the offset voltage of the black data voltage to the black data setting voltage.

3. The display device according to claim 2, in, The black data setting voltage decreases as the driving frequency increases.

4. The display device according to claim 1, in, With respect to the same driving frequency and the same temperature, the offset voltage of the black data voltage is smaller at a second dimming level greater than the first dimming level than at the first dimming level.

5. The display device according to claim 1, in, With respect to the same dimming level and the same temperature, the offset voltage of the black data voltage is smaller at a second driving frequency greater than the first driving frequency than at the first driving frequency.

6. The display device according to claim 1, in, With respect to the same dimming level and the same driving frequency, the offset voltage of the black data voltage is smaller at a second temperature less than a first temperature than at the first temperature.

7. The display device according to claim 1, in, The sub-pixels include a first color sub-pixel displaying a first color and a second color sub-pixel displaying a second color, and With respect to the same dimming level, the same driving frequency, and the same temperature, the offset voltage of the black data voltage for the first color sub-pixel is smaller than the offset voltage of the black data voltage for the second color sub-pixel.

8. The display device according to any one of claims 1 to 7, in, The driving controller determines an offset voltage of an anode initialization voltage for initializing a light emitting element of the sub-pixel based on the black data voltage.

9. The display device according to claim 8, in, The offset voltage of the anode initialization voltage increases as the offset voltage of the black data voltage increases.

10. The display device according to claim 1, in, The driving voltage generator includes a first regulator generating the black data voltage by receiving a gray scale expressing voltage, and The driving controller determines an offset voltage of the gray scale expressing voltage based on the black data voltage.

11. The display device according to claim 10, in, The gray scale expressing voltage is determined as a sum of the black data voltage and a headroom margin of the first regulator.

12. The display device according to claim 1, in, The driving voltage generator includes a first regulator generating the black data voltage by receiving a gray scale expressing voltage, The driving voltage generator provides a gate high voltage to the gate driver, and The driving controller determines an offset voltage of the gate high voltage based on the grayscale expressing voltage.

13. The display device according to claim 12, in, The sub-pixel includes a switching transistor, and The gate high voltage is determined as the sum of the grayscale expressing voltage and a threshold voltage of the switching transistor.

14. The display device according to claim 1, further comprising: include: a power supply, providing a source voltage to the driving voltage generator, wherein the driving voltage generator provides a gate high voltage to the gate driver and includes a second regulator for generating the gate high voltage by receiving the source voltage, and The driving controller determines an offset voltage of the source voltage based on the gate high voltage.

15. The display device according to claim 14, in, The source voltage is determined as a sum of the gate high voltage and a headroom margin of the second regulator.

16. The display device according to claim 1, further comprising: include: a power supply, providing a source voltage to the driving voltage generator, wherein the driving voltage generator comprises a third regulator generating a gate low voltage by receiving a reference voltage and a reference voltage generator generating the reference voltage based on the source voltage in a first mode and generating the reference voltage based on the source voltage and a first external voltage in a second mode, and The driving controller selects one of the first mode and the second mode based on the gate low voltage.

17. The display device according to claim 16, in, The reference voltage in the first mode is a voltage corresponding to the source voltage, The reference voltage in the second mode is a voltage corresponding to a sum of the source voltage and the first external voltage, and When a sum of an absolute value of the gate low voltage and a headroom of the third regulator is greater than an absolute value of the voltage corresponding to the source voltage, the driving controller selects the second mode among the first mode and the second mode.

18. The display device according to claim 1, in, The driving controller determines a first offset voltage of the black data voltage based on the driving frequency and the dimming level, calculates a first corrected black data voltage by adding the first offset voltage of the black data voltage to a black data set voltage, determines a second offset voltage of the black data voltage based on the dimming level and the temperature, calculates a second corrected black data voltage by adding the second offset voltage of the black data voltage to the first corrected black data voltage, and determines the second corrected black data voltage as the black data voltage.

19. The display device according to claim 18, in, The driving controller determines a first offset voltage of an anode initialization voltage for initializing the light-emitting element of the sub-pixel based on the first corrected black data voltage, calculates a first corrected anode initialization voltage by adding the first offset voltage of the anode initialization voltage to an anode initialization set voltage, determines a second offset voltage of the anode initialization voltage based on the second corrected black data voltage, calculates a second corrected anode initialization voltage by adding the second offset voltage of the anode initialization voltage to the first corrected anode initialization voltage, and determines the second corrected anode initialization voltage as the anode initialization voltage.

20. The display device according to claim 18, in, The driving voltage generator generates the black data voltage by receiving a gray scale expressing voltage, and The driving controller determines a first offset voltage of the grayscale expression voltage based on the black data setting voltage, calculates a first corrected grayscale expression voltage by adding the first offset voltage of the grayscale expression voltage to the grayscale expression setting voltage, determines a second offset voltage of the grayscale expression voltage based on the first corrected black data voltage, calculates a second corrected grayscale expression voltage by adding the second offset voltage of the grayscale expression voltage to the first corrected grayscale expression voltage, determines a third offset voltage of the grayscale expression voltage based on the second corrected black data voltage, calculates a third corrected grayscale expression voltage by adding the third offset voltage of the grayscale expression voltage to the second corrected grayscale expression voltage, and determines the third corrected grayscale expression voltage as the grayscale expression voltage.

21. The display device according to claim 20, in, The driving voltage generator provides a gate high voltage to the gate driver, and The driving controller determines a first offset voltage of the gate high voltage based on the first correction grayscale expression voltage, calculates a first correction gate high voltage by adding the first offset voltage of the gate high voltage to a gate high setting voltage, determines a second offset voltage of the gate high voltage based on the second correction grayscale expression voltage, calculates a second correction gate high voltage by adding the second offset voltage of the gate high voltage to the first correction gate high voltage, determines a third offset voltage of the gate high voltage based on the temperature, calculates a third correction gate high voltage by adding the third offset voltage of the gate high voltage to the second correction gate high voltage, and determines the third correction gate high voltage as the gate high voltage.

22. The display device according to claim 21, further comprising: include: a power supply, providing a source voltage to the driving voltage generator, wherein the driving voltage generator generates the gate high voltage by receiving the source voltage, and The drive controller determines a first offset voltage of the source voltage based on the first correction gate high voltage, calculates a first correction source voltage by adding the first offset voltage of the source voltage to a source voltage setting voltage, determines a second offset voltage of the source voltage based on the second correction gate high voltage, calculates a second correction source voltage by adding the second offset voltage of the source voltage to the first correction source voltage, determines a third offset voltage of the source voltage based on the third correction gate high voltage, calculates a third correction source voltage by adding the third offset voltage of the source voltage to the second correction source voltage, and determines the third correction source voltage as the source voltage.

23. The display device according to claim 1, in, The driving voltage generator provides a gate low voltage to the gate driver, and The driving controller determines an offset voltage of the gate low voltage based on an initialization voltage of the sub-pixel.

24. The display device according to claim 1, in, The driving voltage generator provides a gate low voltage to the gate driver, and The driving controller determines a first offset voltage of the gate low voltage based on an initialization voltage of the sub-pixel, calculates a first correction gate low voltage by adding the first offset voltage of the gate low voltage to a gate low set voltage, determines a second offset voltage of the gate low voltage based on the temperature, calculates a second correction gate low voltage by adding the second offset voltage of the gate low voltage to the first correction gate low voltage, and determines the second correction gate low voltage as the gate low voltage.

25. A method for driving a display device, the method include: determining an offset voltage of a black data voltage based on at least one selected from a driving frequency, a dimming level, and a temperature; determining an offset voltage of a grayscale expressing voltage based on the black data voltage; Determining an offset voltage of a gate high voltage based on the grayscale expression voltage; determining an offset voltage of a source voltage based on the gate high voltage; as well as A mode for generating a reference voltage is selected based on the gate low voltage.

26. An electronic device, include: a processor that provides input image data to a display device according to any one of claims 1 to 24; The display device displays an image based on the input image data; as well as A power supply supplies power to the display device.

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