Sequential activation of memory components

Abstract

The invention relates to sequential activation of memory components. In one embodiment, a method includes providing a first activation power to a first memory component of a plurality of memory components for a first time period according to a memory component activation sequence, the first activation power is provided without providing activation power to at least one other memory component of the plurality of memory components. The method includes providing a second activation power to a second memory component for a second time period according to the memory component activation sequence.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to memory systems, and more particularly, to sequential activation of memory components. Background Art

[0002] A memory system may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. In general, a host system may utilize a memory system to store data at the memory devices and retrieve data from the memory devices. Summary of the invention

[0003] In one aspect, the present disclosure provides a method for sequential activation of memory components, comprising: providing a first activation power to a first memory component among a plurality of memory components within a first time period according to a memory component activation sequence, wherein during the first time period, the first activation power is provided without providing activation power to at least one other memory component among the plurality of memory components; and providing a second activation power to a second memory component within a second time period according to the memory component activation sequence.

[0004] In another aspect, the present disclosure further provides an apparatus for sequential activation of memory components, comprising: a first memory component; a second memory component; a voltage regulator coupled to the first memory component and the second memory component; and an activation sequence circuit system configured to activate the first memory component and the second memory component according to a memory component activation sequence by: providing a first activation power to the first memory component via the voltage regulator to activate the first memory component during a first time period without providing activation power to at least one other memory component of the plurality of memory components during the first time period; and providing a second activation power to the second memory component via the voltage regulator to activate the second memory component during a second time period.

[0005] In yet another aspect, the present disclosure further provides a system for sequential activation of memory components, comprising: a plurality of packages including a plurality of stacked memory components, the plurality of stacked memory components including a first memory component, a second memory component, and a third memory component; a voltage regulator coupled to a memory component in the plurality of memory components; and an activation sequence circuit system configured to: provide corresponding activation power to each package in the plurality of packages according to a memory component activation sequence without providing activation power to at least one other package in the plurality of packages; and provide corresponding activation power to each memory component in the plurality of memory components in the corresponding package according to the memory component activation sequence without providing activation power to at least one other memory component of the corresponding package. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments of the present disclosure.

[0007] Figure 1 An example memory system configured according to some embodiments of the present disclosure is described.

[0008] Figure 2A An example configuration of a memory die suitable for sequential activation of memory components according to some embodiments of the present disclosure is described.

[0009] Figure 2B Another example configuration of a memory die suitable for sequential activation of memory components according to some embodiments of the present disclosure is illustrated.

[0010] Figure 2C Yet another example configuration of a memory die suitable for sequential activation of memory components according to some embodiments of the present disclosure is illustrated.

[0011] Figure 3A An example configuration of a package suitable for sequential activation of memory components according to some embodiments of the present disclosure is described.

[0012] Figure 3B Another example configuration of a package suitable for sequential activation of memory components according to some embodiments of the present disclosure is described.

[0013] Figure 4 is a flow chart of a method corresponding to sequential activation of memory components according to some embodiments of the present disclosure.

[0014] Figure 5 is a block diagram of an example computer system including a memory device according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0015] Aspects of the present disclosure relate to sequential activation of memory components, and in particular to memory systems (e.g., memory subsystems) configured to employ sequential activation of memory components. Memory components may be included in a memory system. A memory system (e.g., a memory subsystem) may be a storage system, a storage device, a memory module, or a combination of the like. An example of a memory subsystem is a storage system such as a solid-state drive (SSD). Figure 1 and other figures describe examples of storage devices and memory modules.

[0016] A memory device, such as a dynamic random access memory (DRAM) or a solid state drive (SSD), may be activated (powered on) by power provided from a power source. For example, when power is supplied to the memory device, the power management circuitry of the memory device may detect the voltage and begin regulating the voltage to a stable voltage level suitable for operating the memory device. This voltage regulation may involve ramping up the voltage and current to a desired operating level for the memory device (or a portion of the memory device) in a controlled manner during a power-on ramp phase.

[0017] The power-on ramp phase refers to the initial period of time after the memory device is powered on, during which the voltage applied to the memory components in the memory device is gradually ramped up to the full operating voltage. The ramped voltage may be referred to as the ramped activation power. The ramped activation power may be the device core power (V dd ), device I / O power (V ddq ) and / or reference voltage (V ref ), and other types of voltages that are ramped up over a period of time. The ramp-up process is intended to prevent damage to the memory cells and other components of the device that may occur when the full operating voltage is suddenly applied. During the power-up ramp-up phase, the memory device may initially be in a state where it is not fully operational, and some operations, such as write or read operations, may be impossible. That is, the memory components of the memory device have not yet been "initialized". However, after the power-up ramp-up phase is completed, a given memory component is "initialized", and thereby allows the memory component to be accessed by the host system and allows data to be read and / or written to the memory component.

[0018] Some previous approaches may estimate the size of the voltage regulator in an attempt to account for the presence of a "worst case" of ramping up all memory components simultaneously during memory device activation. Such approaches may employ a high power voltage regulator with high voltage and / or current delivery capabilities to ensure that a sufficient amount of voltage / current is available to provide activation power (e.g., ramp up activation power) to each memory component in the memory device substantially simultaneously. That is, previous approaches may provide respective activation power to each memory component in the memory device simultaneously.

[0019] However, such methods may be inefficient (e.g., consuming relatively large amounts of power during normal memory device operation) and / or may be expensive. Inefficient operation of high-power voltage regulators may be particularly unacceptable in mobile devices or other types of devices that may operate on limited battery power. In addition, such methods may occupy a disproportionate amount of physical space, thereby reducing the amount of space available for other circuit systems such as memory components. Therefore, this inefficient use of space may reduce the overall performance of the memory system in which such methods are employed. In addition, due at least to the presence of the high-power voltage regulator, such methods may generate a large amount of heat (e.g., which may be detrimental to the operating life and / or performance of the memory components). In addition, some previous methods may allow an end user, administrator, or other individual to configure memory device power usage during operation (e.g., adjust the operating envelope of the memory device). However, such methods may not allow for limiting peak power consumption during activation (e.g., may not allow different memory components in the memory device to be activated at different times).

[0020] To address the above and other deficiencies, the methods herein employ sequential activation of memory components. For example, memory components may be activated according to a memory component activation sequence. As used herein, a memory component activation sequence refers to a specified activation order of multiple memory components, such as multiple memory dies, multiple packages (memory packages containing multiple memory dies), or both. It is noteworthy that the memory component activation sequence herein may allow some but not all memory components to be activated substantially at the same time. For example, some but not all memory dies may be activated at a given time, and / or some but not all packages may be activated at a particular time.

[0021] Thus, the methods herein may have lower peak power consumption (lower maximum instantaneous voltage and / or lower maximum instantaneous current) during activation of memory components compared to other methods, such as activating all memory devices and all packages simultaneously. Unlike previous methods (such as the methods described above), sequential activation of memory components (e.g., memory dies, packages, or both) may exhibit relatively low peak power consumption during activation of each memory component. For example, the peak power consumption (peak current and / or voltage) of the memory components in the methods herein may be a fraction of the peak power consumption associated with other methods, such as methods that activate all memory dies and packages substantially simultaneously. Furthermore, due at least to the relatively low peak power consumption during activation, the methods herein may allow for the use of relatively smaller voltage regulators, and thus may be more efficient (e.g., consume less power during normal memory device operation), less costly, and / or may occupy less physical space than previous methods, thus resulting in enhanced overall performance of computing systems and / or memory devices in which such methods are employed.

[0022] For clarity, embodiments herein will be generally described with respect to circuit systems having a given number of memory dies and packages, however, it should be understood that embodiments with different numbers of memory dies and / or packages are contemplated within the scope of the present disclosure. For clarity, embodiments herein will be generally described with respect to memory devices, however, it should be understood that embodiments utilizing caches are contemplated within the scope of the present disclosure.

[0023] Figure 1 1 is a block diagram of a system 101 having a memory device 100 configured according to some embodiments of the present disclosure. As shown, the memory device 100 includes a main memory 102 (e.g., NAND flash memory, NOR flash memory, chalcogenide PCM, etc.) and a controller 106 that operably couples the main memory 102 to a host device 108 (e.g., an upstream central processing unit (CPU)).

[0024] The main memory 102 includes a plurality of memory regions or memory units 120, each of which includes a plurality of memory cells 122. The memory units 120 may be individual memory dies, memory planes in a single memory die, a stack of memory dies vertically connected with through silicon vias (TSVs) (vertical stack), or the like. For example, in one embodiment, each of the memory units 120 may be formed from a semiconductor die and arranged with the other memory unit dies within a single device package (package 138). In other embodiments, a plurality of memory units 120 may be co-located on a single die and / or distributed across a plurality of device packages (e.g., a package 138 coupled to a substrate such as a PCB). That is, although Figure 1 The main memory 102 illustrated in includes an individual package (package 138), but in various instances, the main memory 102 may include multiple packages (eg, multiple packages, each package including vertically stacked memory dies).

[0025] The memory cells 122 may include, for example, floating gate, charge trap, phase change, ferroelectric, magnetoresistive, and / or other suitable storage elements configured to store data permanently or semi-permanently. The main memory 102 and / or the individual memory units 120 may also include other circuit components (not shown) for accessing and / or programming (e.g., writing) the memory cells 122 and other functionalities, such as for processing information and / or communicating with the controller 106, such as multiplexers, decoders, buffers, read / write drivers, address registers, data output / input registers, etc.

[0026] The memory cells 122 may be arranged into rows 124 (e.g., each corresponding to a word line) and columns 126 (e.g., each corresponding to a bit line). Each word line may include one or more memory pages, depending on the number of data states that the memory cells 122 of that word line are configured to store. For example, a single word line of memory cells 122 in which each memory cell 122 is configured to store one of two data states (e.g., SLC memory cells configured to each store one bit) may include a single memory page. Alternatively, a single word line of memory cells 122 in which each memory cell 122 is configured to store one of four data states (e.g., MLC memory cells configured to each store two bits) may include two memory pages. Furthermore, memory pages can be interleaved such that a word line including memory cells 122 in which each memory cell 122 is configured to store one of two data states (e.g., SLC memory cells) can span two memory pages in an "even-odd bit line architecture," where all of the memory cells 122 in odd columns 126 of a single word line are grouped as a first memory page, and all of the memory cells 122 in even columns 126 of the same word line are grouped as a second memory page. The number of memory pages per word line can be even higher (e.g., 4, 6, 8, etc.) when the even-odd bit line architecture is used in word lines of memory cells 122 in which each memory cell 122 is configured to store a larger number of data states (e.g., memory cells configured as MLC, TLC, QLC, etc.).

[0027] Each column 126 may include a string of series-coupled memory cells 122 connected to a common source. The memory cells 122 of each string may be connected in series between a source select transistor (e.g., a field effect transistor) and a drain select transistor (e.g., a field effect transistor). The source select transistors may be commonly coupled to a source select line, and the drain select transistors may be commonly coupled to a drain select line.

[0028] In other embodiments, the memory cells 122 may be arranged in a hierarchy and / or group of a different type than that shown in the illustrated embodiment. For example, in some embodiments, the memory cells 122 may be configured as or include a FinFET having a semiconductor fin covered by a gate. The channel region of the FinFET is formed within the fin at the intersection between the gate conductor and the fin. For example, the FinFET may be an n-type FinFET or a p-type FinFET.

[0029] Furthermore, although shown in the illustrated embodiments as having a particular number of memory cells, rows, columns, blocks, and memory units for illustrative purposes, the number of memory cells, rows, columns, blocks, and memory units may vary, and in other embodiments, the dimensions may be larger or smaller than shown in the illustrated examples. For example, in some embodiments, the memory device 100 may include only one memory unit 120. Alternatively, the memory device 100 may include 2, 3, 4, 8, 10, or more (e.g., 16, 32, 64, or more) memory units 120. Although in the illustrated embodiments, the number of memory cells, rows, columns, blocks, and memory units may vary, and in other embodiments, the dimensions may be larger or smaller than shown in the illustrated examples. For example, in some embodiments, the memory device 100 may include only one memory unit 120. Alternatively, the memory device 100 may include 2, 3, 4, 8, 10, or more (e.g., 16, 32, 64, or more) memory units 120. Figure 1 1 and 2. In the embodiment of the present invention, the memory units 120 are shown as each including two memory blocks 128, but in other embodiments, each memory unit 120 may include one, three, four, eight, or more (e.g., 16, 32, 64, 100, 128, 256, or more) memory blocks. In some embodiments, each memory block 128 may include, for example, two 15 memory pages, and each memory page in a block may include, for example, 2 12 memory cells 122 (eg, a "4k" page).

[0030] The controller 106 may be a microcontroller, a dedicated logic circuit system (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other type of suitable processor. The controller 106 may include a processor 130 that is configured to execute instructions stored in the memory. The controller 106 may reside on the main memory 102 and / or may be located elsewhere on the memory device 100. For example, some or all elements of the controller 106 may be located in one or more packages and / or one or more memory dies in the main memory 102.

[0031] In the illustrated example, the memory of the controller 106 includes an embedded memory 132 configured to execute various processes, logic flows, and routines for controlling the operation of the memory device 100, including managing the main memory 102 and handling communications between the memory device 100 and the host device 108. In some embodiments, the embedded memory 132 may include memory registers that store, for example, memory pointers, fetched data, etc. The embedded memory 132 may include volatile and / or non-volatile memory (e.g., DRAM, SRAM, NAND, NOR, PCM) for storing memory registers, and may also include read-only memory (ROM) (e.g., for storing microcode). Although in Figure 1In the example set forth in , the memory device 100 has been illustrated as including a controller 106, but in another embodiment of the present technology, the memory device may not include a controller and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory device).

[0032] In operation, the controller 106 may directly write or otherwise program (e.g., erase) various memory areas of the main memory 102, such as by writing to groups of memory pages and / or memory blocks 128. In NAND-based memories, a write operation typically includes programming the memory cells 122 in a selected memory page with a particular data value (e.g., a string of data bits having a logical 0 or logical 1 value). An erase operation is similar to a write operation, except that an erase operation reprograms an entire memory block 128 or multiple memory blocks 128 to the same data state (e.g., a logical 1).

[0033] The controller 106 and / or the main memory 102 may be coupled to a power supply circuit 140 configured to provide power used during operation and activation of the main memory 102. The power supply circuit 140 may provide lower voltages (e.g., lower than 5V) and / or higher voltages (e.g., higher than 5V) to different circuits / domains. For example, the power supply circuit 140 may include circuits that provide lower voltages for reading memory regions and / or for performing internal operations. Also, the power supply circuit 140 may include a high voltage source 142 configured to provide higher voltages for programming memory regions. Additionally, the power supply circuit 140 may be configured to provide power for activation of the main memory 102, as described herein.

[0034] The controller 106 communicates with the host device 108 through the host device interface 110. In some embodiments, the host device 108 and the controller 106 can communicate through a serial interface such as a serial attached SCSI (SAS), a serial AT attachment (SATA) interface, a peripheral component interconnect express (PCIe), an I2C / I3C interface, and / or other suitable interfaces (e.g., a parallel interface). The host device 108 can send various requests (in the form of, for example, packets or packet streams) to the controller 106. The request can include commands for writing, erasing, returning information, and / or for performing specific operations (e.g., TRIM operations). The request can also include an interrupt or another command indicating a change in a condition (e.g., a power loss event), which can trigger the implementation of the power loss algorithm.

[0035] The host device 108 may be any of a number of electronic devices or components thereof that are capable of utilizing memory to temporarily or permanently store information. For example, the host device 108 may be a computing device, such as a desktop or portable computer, a server, a handheld device (such as a mobile phone, a tablet computer, a digital reader, a digital media player), or a component thereof (such as a central processing unit, a coprocessor, a dedicated memory controller, etc.). The host device 108 may be a networking device (such as a switch, a router, etc.) or any of a digital image recorder, audio and / or video, a vehicle, an appliance, a toy, or many other products. In one embodiment, the host device 108 may be directly connected to the memory device 100, although in other embodiments, the host device 108 may be indirectly connected to the memory device 100 (e.g., through a networking connection or through an intermediary device).

[0036] The controller 106 may include an activation sequence circuit system 134. Although not shown in the figure to avoid obscuring the figure, Figure 1 1, but activation sequence circuitry 134 may include various circuitry to facilitate aspects of the disclosure described herein. In some embodiments, according to the disclosure, activation sequence circuitry 134 may include specialized circuitry in the form of an ASIC, FPGA, load switch, state machine, hardware processing device, and / or other logic circuitry that may allow activation sequence circuitry 134 to orchestrate and / or perform operations such as sequential activation of memory components, particularly with respect to systems on a chip. For example, activation sequence circuitry 134 may include load switches and / or other circuitry (e.g., data calibration (DQ) circuitry) that is configured to distribute activation power to some, but not all, memory components at a given time according to a memory component activation sequence, as described herein.

[0037] In some embodiments, the controller 106 includes at least a portion of the activation sequence circuitry 134. For example, the controller 106 may include a processor 130 (processing device) configured to execute instructions stored in a local memory 132 for performing the operations described herein. In some embodiments, the activation sequence circuitry 134 is part of a host system 108, an application, or an operating system. The activation sequence circuitry 134 may reside on the main memory 102 and / or the controller (memory controller) 106. As used herein, the term "resides on" refers to something that is physically located on a particular component. For example, the activation sequence circuitry 134 "resides on the main memory 102" refers, for example, to a condition in which the hardware circuitry in which the activation sequence circuitry 134 is included is physically located on the main memory 102. The term "resides on" may be used interchangeably with other terms such as "deployed on" or "located on".

[0038] The activation sequence circuitry 134 may be configured to detect a power-on event associated with the main memory 102. The power-on event may be detected based on a change in an indicator / flag or other mechanism and / or based on a change in voltage / current in the main memory 102, among other possibilities. In some embodiments, components of the main memory 102 may detect the power-on event before and / or without receiving a main memory start command originating from the host 108. Thus, in some embodiments, components of the main memory 102 may detect the power-on event before the host 108 propagates a signal or assertion command across the main memory 102 that invokes a memory cell of a memory component (e.g., package and / or memory die) in the main memory 102.

[0039] Detection of a power-on event may allow or facilitate activation sequence circuitry 134 to perform operations described herein. For example, activation sequence circuitry 134 may be configured to determine a memory component activation sequence in response to the occurrence of a power-on event associated with the system, and may subsequently cause the memory components to be sequentially activated, as described herein.

[0040] For example, memory components may be daisy-chained together, e.g. Figure 2A and Figure 3B . In such embodiments, the activation sequence circuit system 134 may be configured to provide activation power to a first memory component in a chain of memory components based on a memory component activation sequence. For example, a trigger signal may be transmitted to a first memory component in the chain (as indicated by the memory component activation sequence) to cause the first memory component to be activated. Once activated, the first memory component may transmit a signal indicating its activation state to the activation sequence circuit system 134 and / or a certain amount of delay may be applied to ensure that the first memory component is activated. In response to the activation of the first memory component (e.g., receiving a signal indicating an activation state) and / or the lapse of a delay, the activation sequence circuit system 134 may transmit a trigger signal to a second memory component in the chain to cause the second memory component to be activated, and so on, until all memory components are sequentially activated (e.g., where a certain amount of intentional delay (e.g., delay due to a resistor and capacitor (RC) delay circuit) is introduced between the activation of at least some of the memory components).

[0041] In some embodiments, the activation sequence or an indicator of the activation sequence may be stored in memory 132 or other locations in main memory 102, among other possibilities. For example, activation sequence circuitry 134 may include fuse circuitry (not illustrated). Alternatively or in addition, the fuse circuitry may be included in a given package and / or a given die. For example, each package may include a corresponding fuse circuitry, among other possibilities.

[0042] The fuse circuitry may include an indicator of the activation sequence. The indicator may be data or other indicators that allow the activation sequence circuitry 134 to determine the memory component activation sequence based on the data. For example, the data may indicate a respective time period associated with each memory component in the memory component activation sequence, and the activation sequence circuitry 134 may be configured to determine the respective time period associated with each memory component in the memory component activation sequence based on the value of the data (e.g., where a certain amount of delay is introduced between activation of at least some of the different memory components).

[0043] In some embodiments, the activation sequence circuitry 134 may allow an end user, administrator, or other individual to set or change the memory component activation sequence. That is, unlike previous methods that do not allow an end user or other individual to change the memory component activation sequence, the methods herein may allow the activation order of memory components in the memory component activation sequence to be changed, e.g., depending on the preferences of the end user, and still ensure that the memory components are activated sequentially.

[0044] Figure 2A An example configuration 221 of a memory die suitable for sequential activation of memory components according to some embodiments of the present disclosure is illustrated. Figure 2A As illustrated, example configuration 221 may include a first memory die 220-1, a second memory die 220-2, ..., a third memory die 220-D (collectively referred to as memory die 220). Although example configuration 221 includes three memory dies, any number of memory dies may be used (e.g., 4 memory dies, 8 memory dies, 16 memory dies, etc.). Memory die 220 may be similar to or similar to Figure 1 In some embodiments, each memory die 220 may be included in an individual package (in the same individual package), as well as other possibilities.

[0045] The memory dies 220 may be configured (e.g., wired) in a cascade or daisy-chain manner. Power 226 may be provided to the memory dies 220. Power 226 may be power provided from a voltage regulator 229 (e.g., a power supply including the voltage regulator 229) coupled to each memory die 220. The voltage regulator may include or form a circuit diagram of a power supply circuit. Figure 1 A portion of power supply circuit 140 is depicted. In some embodiments, the voltage regulator is an individual voltage regulator coupled to each package in the package, each memory die of the plurality of memory die 220, or both.

[0046] The activation voltage may be provided in a sequential manner to each memory die configured in a cascade or daisy-chain manner. For example, each memory die 220 may be provided with power from the voltage regulator 229 concurrently, but may be provided with corresponding activation power (e.g., a ramped activation power (e.g., a ramped current and / or voltage) that is higher than the normal operating power) at different times according to the memory component activation sequence. For example, the first memory die 220-1 may be activated at a different time than at least one of the other memory dies 220. In other words, the first memory die 220-1 may be activated without at least one other memory die of the memory dies 220 being activated. Similarly, each other memory die may be activated without at least one other memory die of the memory dies 220 being activated.

[0047] For example, a delay (e.g., an RC delay due to a resistor and capacitor (RC) delay circuit) may be intentionally applied between activations of different memory components. The duration of the delay (e.g., RC delay) between providing activation power to different memory dies may be the same or different. For example, in some embodiments, the delay between providing activation power to each memory die 220 may be the same. For example, activation power may be provided to a first memory die for a first time period, and then a first amount of delay (e.g., RC delay) may be applied before providing activation power to a second memory die 220-2 for a second time period. Similarly, a second amount of delay may be applied before providing activation power to a third memory die 220-D for a third time period. Thus, the activation power provided to each memory die 220 (e.g., consumed by each memory die 220) may be staggered.

[0048] For example, without providing (e.g., concurrently providing) activation power to at least one other memory die (e.g., the second memory die 220-2, the third memory die 220-D, etc.), activation power may be provided to the first memory die 220-1 via the first CA link 227-1 for a first time period according to the memory component activation sequence. That is, without providing activation power to at least one other memory die (at the same time as the first activation power is provided to the first memory die 220-1), a portion of the power 226 may be provided to the memory cells or other components in the first memory die 220-1 as activation power (the first activation power) to activate the first memory die 220-1.

[0049] Subsequently (e.g., once the first memory die 220-1 is activated), a portion of the power 226 may be provided to the second memory die 220-2 as activation power for a second period of time (second activation power) via the second CA link 227-2 according to the memory component activation sequence. Without providing activation power to at least one other memory die (e.g., without providing activation power to memory cells in the first memory die 220-1 and / or the third memory die 220-D, etc.), activation power (second activation power) may be provided to memory cells or other components in the second memory die 220-2.

[0050] In addition, a portion of the power 226 may subsequently (e.g., once the first memory die 220-1 and the second memory die 220-2 are activated) be provided to the third memory die 220-D as activation power (third activation power) via the third CA link 227-C according to the memory component activation sequence to activate the memory cells or other components in the third memory die 220-D. The third activation power may be provided to the memory cells or other components in the third memory die 220-D without providing (e.g., concurrently providing) activation power to at least one other memory die (e.g., without providing activation power to the memory cells in the first memory die 220-1 and / or the second memory die 220-2, etc.).

[0051] Once the memory die 220 are activated, power 226 can continue to be provided at normal operating levels to each memory die 220. For example, power 226 can continue to be provided to the memory die to allow the host to invoke memory operations involving the memory die 220.

[0052] Figure 2B Another example configuration 222 of memory dies suitable for sequential activation of memory components according to some embodiments of the present disclosure is illustrated. Figure 2B Similar to Figure 2A , with the proviso that there may be signals (e.g., represented as external signals 251-1, 251-2, and 251-C) to activate the memory die according to an activation sequence (e.g., rather than based on Figure 2A Alternatively or additionally, one or more of signals 251-1, 251-2, and / or 251-C may be internal signals, such as signals provided by a die and / or package to another component (eg, to another die and / or package).

[0053] like Figure 2BAs illustrated, portions of power 226 may be provided to each memory die 220 from voltage regulator 229 via power rail 235 at different respective time periods according to a memory component activation sequence to activate each memory die 220. In some embodiments, memory die 220 may be electrically coupled to power rail 235 via interface circuitry. Examples of interface circuitry include traces, buses, and / or other types of interface circuitry that may be configured to electrically couple memory die 220 to power rail 235. For example, as described herein, memory die 220 may be coupled to power rail 235 via CA link 227, among other possibilities.

[0054] In some embodiments, a controller (e.g. Figure 1 The controller 106 in the embodiment may be configured to cause activation power to be provided to different memory dies via power rail 235 at different corresponding time periods according to the memory component activation sequence. For example, the controller may cause various switches, buses, CA circuit systems, and / or other interface circuit systems to selectively provide a portion of power 226 as activation power to one or more corresponding memory dies (but not all memory dies) via power rail 235 at different corresponding time periods according to the memory component activation sequence.

[0055] continue Figure 2B As a non-limiting example, a portion of the power 226 may be provided to the first memory die 220-1 via the power rail 235 and via the first CA link 227-1 as activation power. In response to receiving the first activation signal 251-1 at the first memory die, the activation power may be provided to the first memory die 220-1. The first activation signal 251-1 (and similarly other activation signals described herein) may be an external signal transmitted by a controller such as those described herein, or may be an internal signal (e.g., inside the die and / or package). In the absence of providing activation power to at least one other memory die (e.g., the second memory die 220-2 and / or the third memory die 220-D), the activation voltage may be provided to the first memory die in a first time period according to the memory component activation sequence. The activation power (the first activation power) may be a ramped activation power that is ramped up (e.g., increased) during the first time period to activate the first memory die 220-1.

[0056] Subsequently, activation power may be provided to the next memory die in the memory component activation sequence. In response to receiving the second activation signal 251-2 at the second memory die, activation power may be provided to the second memory die 220-2. For example, continuing Figure 2BIn the illustrated non-limiting example, without providing activation power to at least one other memory die (e.g., the first memory die 220-1 and / or the third memory die 220-D), a portion of the power 226 can be provided to the second memory die 220-2 as a second activation power for a second time period via the power rail 235 and via the second CA link 227-2 according to the memory component activation sequence. The second activation power can be a ramped activation power that is ramped up.

[0057] continue Figure 2B In the illustrated non-limiting example, a portion of the power 226 may be provided to the third memory die 220-D via the power rail 235 and via the third CA link 227-C. In response to receiving the third activation signal 251-C at the third memory die, the activation power may be provided to the third memory die 220-D. Without providing activation power to at least one other memory die (e.g., the first memory die 220-1 and / or the second memory die 220-2), the third activation power may be provided to the third memory die 220-D in a third time period according to the memory component activation sequence. The third activation power may be a ramped activation power that is ramped up (e.g., increased) during the third time period to activate the third memory die 220-D. That is, each memory die 220 may be activated by the corresponding ramped activation power provided thereto according to the memory component activation sequence.

[0058] Figure 2C Yet another example configuration 231 of a memory die suitable for sequential activation of memory components according to some embodiments of the present disclosure is illustrated. Figure 2C Similar to Figure 2B , with the proviso that the controlling memory die are configured to arbitrate when to provide activation power to the respective memory die, rather than Figure 2B An external activation signal associated with each memory die is employed as described.

[0059] For example, the control memory die (in Figure 2C ) may be the first memory die (die 1) 220-1, such as Figure 2CAs described. That is, individual memory dies of the plurality of memory dies may be control memories. However, any one or more memory dies may be control memory dies. The control memory die may include logic or other circuitry configured to arbitrate when each auxiliary memory die (represented by "auxiliary"), such as the second memory die 220-2 and / or the third memory die 220-D, is provided with corresponding activation power according to the memory component activation sequence. For example, arbitration signals (represented as 233-1, 233-2) may be transmitted between the control memory die and each auxiliary memory die via circuitry (e.g., via a CA link, etc.) to allow the control memory die to arbitrate the provision of activation power (via track 235) to each memory die 220 according to the memory component activation sequence. The first memory die (control die) may initiate activation of the memory component, among other possibilities, in response to receiving an activation signal 251-1 (e.g., an activation signal transmitted by a controller such as the controller described herein). Although signal 251 is illustrated as an external signal, in some embodiments, signal 251 may be an internal signal initiated from the die (eg, the first package).

[0060] Figure 3A An example configuration 333 of a package suitable for sequential activation of memory components according to some embodiments of the present disclosure is illustrated. Figure 3A Similar to Figure 2B , with the proviso that the package exists as a replacement for the memory die. Figure 3A As illustrated, configuration 333 may include a first package ("package 1") 338-1, a second package ("package 2") 338-2, ..., a third package ("package X") 338-P (collectively referred to as packages 338). Although configuration 333 includes three packages, any number of packages may be employed. Package 338 may be similar to or similar to Figure 1 Package 138 is illustrated.

[0061] like Figure 3A As illustrated, power 326 may be provided from voltage regulator 329 to each package 338 via power rail 335. Notably, a portion of power 326 may be provided via power rail 335 as a plurality of activation powers that are provided at different respective time periods according to a memory component activation sequence to activate each package 338. In some embodiments, package 338 may be electrically coupled to power rail 335 via interface circuitry. Examples of interface circuitry include traces, buses, and / or other types of interface circuitry that may be configured to electrically couple package 338 to power rail 335. For example, as described herein, package 338 may be coupled to power rail 335 via CA links 327-1, 327-2, ..., 327-C, among other possibilities.

[0062] In some embodiments, a controller (e.g., Figure 1 The controller 106 described herein may be configured to cause portions of the power 326 to be provided to different packages as activation power via the power rail 335 at different respective time periods according to the memory component activation sequence. For example, the controller may cause various switches, buses, CA circuitry, and / or other interface circuitry to selectively enable activation power to one or more respective packages (but not all packages) at different respective time periods according to the memory component activation sequence, similar to the configuration described above with respect to FIG. Figure 2B For example, activation power may be provided to the first package 338-1 in response to receiving the first activation signal 351-1 at the first package. Activation power may also be provided to the second package 338-2 in response to receiving the second activation signal 351-2 at the second package 338-2. Activation power may also be provided to the third package 338-P in response to receiving the third activation signal 351-C at the third package 338-P.

[0063] Figure 3B Another example configuration 336 of a package suitable for sequential activation of memory components according to some embodiments of the present disclosure is illustrated. Figure 3B Similar to Figure 2A , with the proviso that the package exists as a replacement for the memory die.

[0064] In some embodiments, in combination Figures 3A to 3B The sequential activation of packages described in either of the above may be combined with Figures 2A to 2C . For example, in some embodiments, each respective package may be activated in a sequential manner according to a memory component activation sequence, and each respective memory die contained in a package may also be activated in a sequential manner according to a memory component activation sequence. For example, each respective memory die in a first package may be activated in a sequential manner before each respective memory die in a second package is activated in a sequential manner. The sequential activation of each package in a package and the sequential activation of each memory die of the respective memory die contained in each package may achieve a further reduction in peak power consumption associated with activation of a memory device including multiple packages, each package having multiple memory dies.

[0065] Figure 4 4 is a flow chart of a method 460 corresponding to sequential activation of memory components according to some embodiments of the present disclosure. The method 460 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, the method 460 is performed by Figure 1 The controller 106 of the embodiment of the present invention is executed. Although shown in a specific sequence or order, unless otherwise specified, the order of the process can be modified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes can be performed in different orders, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0066] As mentioned, the methods herein provide activation power to a given memory component (e.g., a memory die and / or package) in a memory device according to a memory component activation sequence without providing activation power to at least one other memory component in the memory device. In other words, activation power may be provided to one or more memory components in a memory device without providing activation power to one or more other memory components in the memory device.

[0067] For example, activation power may be provided to a given memory component (e.g., a given memory die, a given package containing a memory die, or both) without simultaneously providing activation power to most other memory components, as well as other possibilities described herein. Thus, the methods herein may achieve a reduction in peak power consumption during activation of a memory component. The reduction in peak power may allow the use of a smaller voltage regulator, enhance memory device performance, reduce heat generation, and / or provide other benefits, as described herein.

[0068] Additionally, in some embodiments, activation power may be provided to an individual memory component (e.g., a first memory die included in an individual package) according to a memory component activation sequence without providing activation power to any other memory component at the same time. In such embodiments, after activation of a memory component (e.g., a first memory die), subsequent activation power may be provided to another individual memory component (e.g., a second memory die in an individual package) according to a memory component activation sequence without providing activation power to another other memory die. In this manner, each individual memory component (e.g., an individual memory die) may be activated without simultaneously activating any other memory component to achieve further reductions in peak power consumption during activation of the memory component.

[0069] At operation 462, method 460 includes enabling a first activation power (e.g., a first memory die activation power) to a first memory component of a plurality of memory components within a first time period according to a memory component activation sequence. As mentioned, during the first time period, the first activation power to the first memory die may be enabled (e.g., provided) without enabling activation power to at least one other memory die of the plurality of memory dies. For example, for a given package having sixteen memory dies, activation power may be enabled for memory dies in the package without enabling activation power to at least one, at least two, at least three, at least four, at least five, at least six, at least seven, at least eight, at least nine, at least ten, at least eleven, at least twelve, at least thirteen, at least fourteen, or fifteen other memory dies at the same time (e.g., during the first time period). In some embodiments, activation power may be enabled for a memory die (one or more memory dies) in a memory device without enabling activation power to at least half of the other memory dies in the memory device. For example, continuing with the above example, activation power may be enabled for a memory die at a given time without enabling activation power to at least eight other memory dies included in the package of the memory device at the given time. Further, in some embodiments, activation power may be enabled to an individual memory die at a given time without enabling activation power to any other memory die in the memory device at the given time.

[0070] In some embodiments, method 460 includes enabling a first activation power (e.g., package activation power) to a first package included in a plurality of packages during a first time period according to a memory component activation sequence. As mentioned, during the same time period (e.g., first time period), the first activation power to the first package may be enabled without enabling activation power to at least one other package in the plurality of packages. In other words, peak power consumption associated with activation of a package (memory package) may be reduced by activating the first package without activating at least one other package, as compared to other methods of activating each package substantially simultaneously. In some embodiments, activation power may be enabled for a package (one or more packages) in a memory device without enabling activation power to at least half of the other packages in the memory device. For example, continuing with the above example, activation power to a package may be enabled at a given time without providing activation power to at least two other packages in the memory device at the given time. Furthermore, in some embodiments, activation power may be provided to an individual memory die at a given time without providing activation power to any other package in the memory device at the given time.

[0071] Additionally, in some embodiments, method 460 includes enabling activation power to a memory die contained in the package during a time period according to a memory component activation sequence without enabling activation power to at least one other memory die contained in the package and without enabling activation power to at least one other package of the plurality of packages during the time period. Enabling activation power to the memory die without enabling activation power to at least one other memory die contained in the package and without enabling activation power to at least one other package during the same time period may achieve further reduction in peak power consumption during activation of the package containing the memory device. For example, activation power may be enabled for the memory die without enabling activation power to any other memory die contained in the package and without enabling activation power to any other package to achieve maximum reduction in power consumption associated with activation of the memory component.

[0072] For example, in a memory device including 8 packages (X=8) with 16 dies per package (Y=16) and a corresponding activation time of 25 microseconds for each activation power applied to the memory dies, the total duration of activating each package and memory device (assuming no overlap of activation signals) may be equal to 3.2 milliseconds, among other possible values, depending on the number of packages, memory dies, activation duration, etc. The above total duration of the memory component activation sequence (3.2 milliseconds) may be slightly longer than the time associated with other methods of enabling (providing) activation power to all memory components in the memory device substantially simultaneously (e.g., about 25 microseconds). Notably, the time difference between the different methods may be imperceptible to an end user, however, as described herein, the maximum reduction in peak power consumption associated with memory component activation may be achieved.

[0073] However, some embodiments herein may activate two or more memory dies (but not all memory dies) simultaneously and / or activate two or more packages (but not all packages) simultaneously. Such embodiments may achieve a reduction in the total duration of activation of each memory component (e.g., relative to activating each package and memory die individually) and still achieve a reduction in peak power consumption during activation, compared to other approaches that activate all memory components in the memory dies substantially simultaneously and still achieve a reduction in peak power consumption during activation.

[0074] For example, at 464, method 460 includes enabling a second activation power to a second memory component during a second time period according to the memory component activation sequence. During the second time period, the second activation power to the second memory component may be enabled without enabling activation power to at least one other memory component. For example, the second activation power to the second memory component may be enabled without enabling activation power to at least one other memory component (other than the first memory component that has been activated). In some instances, the second activation power to the second memory component may be enabled without enabling activation power to at least half of the other memory components. In some instances, the second activation power may be enabled for the second memory component without enabling activation power to any other memory component.

[0075] Although described above primarily with respect to a first memory component and a second memory component, it should be understood that sequential activation of memory components may be employed for each memory component in a memory device. For example, each memory component (e.g., a memory die or package) in a memory device may be sequentially activated without at least one other memory component, as described herein.

[0076] The second time period may or may not overlap with the first time period. In some embodiments, the second time period may be offset from the first time period (have a different start and / or end time). For example, the start of the second time period may be after (follows) the start of the first time period, and the end time of the second time period may be after the end time of the first time period.

[0077] The first time period and the second time period may have the same or different respective durations. For example, when each time period is associated with the same type of memory component (e.g., a memory die or package), the first time period and the second time period may be substantially the same (have the same duration). Similarly, the first activation power and the second activation power may have the same or different magnitudes. For example, each activation power applied to each memory die may have the same magnitude and duration, but at least a portion of the activation power may be enabled for different memory dies at different time periods. For example, the first activation power may be a ramp-up activation power having a given magnitude at a given time point during the first time period, the given magnitude being equal to the magnitude at a corresponding (same) time point during the second time period. Similarly, each activation power applied to each package may have the same magnitude and duration, but at least a portion of the activation power may be enabled for different packages at different time periods.

[0078] In some embodiments, a portion of the second time period may overlap with a portion of the first time period. Thus, during the time period in which the first time period overlaps with the second time period, activation power (e.g., the first activation power) may be enabled for the first memory component, while activation power (e.g., the second activation power) may be enabled for the second memory component. In some embodiments, the second time period may overlap with some but not all of the first time period. For example, the second time period may overlap with a given percentage or a portion of the first time period but not all of the first time period. For example, the second time period may overlap with less than half of the first time period (less than half of the total duration of the first time period), less than one-third of the first time period, less than one-fifth of the first time period, less than one-tenth of the first time period, and the like. Overlapping a portion of the second time period with a portion of the first time period can reduce the total amount of time that each memory component is activated and still achieve a reduction in the peak power consumption of the memory component during activation of the memory component.

[0079] However, in some embodiments, the second time period may not overlap with the first time period. When the second time period does not overlap with a portion of the first time period, the maximum reduction in peak power consumption associated with the activation of each memory component can be achieved (e.g., activating each respective memory component at a different non-overlapping time period). For example, the start time of the second time period may be after the end time of the first time period. In some embodiments, the second time period may begin substantially immediately after the end of the first time period. Having the second time period begin substantially immediately after the end of the first time period can ensure that the time periods do not overlap while still facilitating timely activation of each memory component.

[0080] In some embodiments, the memory components, such as the first memory component and the second memory component, are non-volatile memory components contained in a non-volatile memory device, such as described herein. For example, the non-volatile memory device can be a solid state drive (SSD), among other possibilities. However, in some embodiments, the memory components, such as the first memory component and the second memory component, are volatile memory components contained in a volatile memory device. For example, the volatile memory device can be a dynamic random access memory (DRAM), among other possibilities.

[0081] As mentioned, in some embodiments, a memory component may be a memory die, a package (including a memory die), or both. For example, in some embodiments, a memory component may include multiple memory dies in one or more packages. For example, the first memory component and the second memory component mentioned above may be a first memory die and a second memory die included in one or more packages. However, in some embodiments, the first memory component and the second memory component may be a first package and a second package, respectively, as described herein. Likewise, when reference is made to a first memory component and a second memory component, it should be understood that the sequential activation of the memory components described herein is applicable to any number of memory components.

[0082] In some embodiments, the total duration of the memory activation sequence is equal to the sum of the durations of the respective activation times of each memory component. For example, the total duration of the memory activation sequence may be equal to the sum of the respective activation times of each memory die contained in one or more packages in the memory device. That is, the total duration of the memory activation sequence may be equal to the amount of time used to activate each memory component in the memory device (e.g., each memory die contained in each package).

[0083] Figure 5 is a block diagram of an example computer system 580 including a memory device 500 according to some embodiments of the present disclosure. Figures 1 to 4 Any of the foregoing memory devices and the configurations of memory dies and / or packages described may be incorporated into any of a myriad of larger and / or more complex systems, representative examples of which are Figure 5 Schematically shown in FIG. System 580 may include memory device 500, power supply 582, driver 584, processor 586, and / or other subsystems or components 588.

[0084] The memory device 500 may include the Figures 1 to 4 The features of the memory devices described herein and the configuration of the memory die and / or the configuration of the package are generally similar, and therefore may include various features for sequential activation of memory components. The resulting system 580 may perform any of a variety of functions, such as memory storage, data processing, and / or other suitable functions. Thus, the representative system 580 may include (without limitation) handheld devices (e.g., mobile phones, tablet computers, digital readers, and digital audio players), computers, vehicles, appliances, and other products. The components of the system 580 may be housed in a single unit or distributed among multiple, interconnected units (e.g., via a communication network). The components of the system 580 may also include any of a remote device and a variety of computer-readable media.

[0085] It should be noted that the methods described above describe possible implementations, and operations and steps may be rearranged or otherwise modified, and other implementations are possible. In addition, embodiments from two or more of the methods may be combined. The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof. Some of the accompanying drawings may illustrate the signal as a single signal; however, a person of ordinary skill in the art will understand that the signal may represent a signal bus, where the bus may have a variety of bit widths.

[0086] The devices discussed herein, including memory devices, may be formed on a semiconductor substrate or die, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping with various chemical species, including but not limited to phosphorus, boron, or arsenic. Doping may be performed by ion implantation during the initial formation or growth of the substrate or by any other doping method.

[0087] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. Other examples and implementations are within the scope of the present disclosure and the appended claims. Features that implement the functions may also be physically located at various locations, including portions that are distributed so that the functions are implemented at different physical locations.

[0088] As used herein, "or" as used in a list of items (e.g., a list of items beginning with a phrase such as "at least one" or "one or more"), including as used in the claims, indicates an inclusive list, such that a list of at least one of, for example, A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Moreover, as used herein, the phrase "based on" should not be interpreted as a reference to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on".

[0089] From the foregoing, it should be understood that specific embodiments of the present invention have been described herein for illustrative purposes, but various modifications may be made without departing from the scope of the present invention. In fact, in the foregoing description, numerous specific details are discussed to provide a thorough and detailed description of embodiments of the present technology. However, those skilled in the relevant art will recognize that the present disclosure may be practiced without one or more of the specific details. In other examples, well-known structures or operations typically associated with memory systems and devices are not shown or described in detail to avoid making other aspects of the present technology unclear. In general, it should be understood that in addition to the specific embodiments disclosed herein, various other devices, systems and methods may also be within the scope of the present technology.

Claims

1. A method for sequential activation of a memory component, comprising: providing a first activation power to a first memory component of a plurality of memory components for a first time period according to a memory component activation sequence, wherein the first activation power is provided without providing activation power to at least one other memory component of the plurality of memory components during the first time period; and According to the memory component activation sequence, second activation power is supplied to a second memory component for a second period of time.

2. The method of claim 1, further comprising providing the first activation power to the first memory component without providing activation power to at least half of the other memory components during the first time period.

3. The method of claim 1, further comprising providing the first activation power to the first memory component during the first time period without providing activation power to any of the other memory components.

4. The method according to any one of claims 1 to 3, wherein the first activation power is a first ramp-up activation power, and wherein the second activation power is a second ramp-up activation power.

5. The method of any one of claims 1 to 3, wherein a portion of the second time period overlaps a portion of the first time period.

6. The method of any one of claims 1 to 3, wherein the second time period does not overlap with the first time period, wherein the second time period begins substantially immediately after the end of the first time period.

7. An apparatus for sequential activation of memory components, comprising: a first memory component; a second memory component; a voltage regulator coupled to the first memory component and the second memory component; and an activation sequence circuitry configured to activate the first memory component and the second memory component according to a memory component activation sequence by: supplying first activation power to the first memory component via the voltage regulator for a first time period to activate the first memory component without supplying activation power to at least one other memory component of the plurality of memory components during the first time period; and A second activation power is supplied to the second memory component via the voltage regulator for a second time period to activate the second memory component.

8. The apparatus of claim 7, wherein the first memory component and the second memory component are stacked memory components.

9. The apparatus of claim 8, wherein the first memory component and the second memory component are stacked non-volatile memory components included in a non-volatile memory device.

10. The apparatus of claim 8, wherein the first memory component and the second memory component are stacked volatile memory components included in a volatile memory device.

11. The apparatus of claim 7, wherein the first memory component and the second memory component further comprise first and second packages, respectively.

12. A system for sequential activation of memory components, comprising: a plurality of packages comprising a plurality of stacked memory components, the plurality of stacked memory components comprising a first memory component, a second memory component, and a third memory component; a voltage regulator coupled to a memory component of the plurality of memory components; and activating a sequence circuit system configured to: providing respective activation power to each of the plurality of packages according to a memory component activation sequence without providing activation power to at least one other package of the plurality of packages; and Respective activation power is provided to each of the plurality of memory components in the respective package according to the memory component activation sequence without providing activation power to at least one other memory component of the respective package.

13. The system of claim 12, wherein the voltage regulator is an individual voltage regulator coupled to each package of the plurality of packages, each memory component of the plurality of memory components, or both.

14. The system of claim 12, wherein: The activation sequence circuitry includes fuse circuitry; An indicator of the memory component activation sequence is stored in the fuse circuitry; and The activation sequence circuitry is configured to determine the memory component activation sequence based on the indicator.

15. The system of claim 12, wherein: at least one package of the plurality of packages having a respective power output coupled to a respective power input of another package of the plurality of packages; at least one memory die of the plurality of memory die has a power output coupled to a power input of another memory die of the plurality of memory die; or Both.

16. The system of claim 12, wherein the activation sequence circuitry is configured to: providing respective activation power to each individual package of the plurality of packages according to the memory component activation sequence without providing activation power to any other package of the plurality of packages; providing respective activation power to each individual memory component of the plurality of memory components in the respective package according to the memory component activation sequence without providing activation power to any other memory component of the plurality of packages in the respective package; or Both.

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